Instruction Leaflet 40-201.7 All possible contingencies which may arise during installation, operation or maintenance, and all details and variations of this equipment do not purport to be covered by these instructions. If further information is desired by purchaser regarding this particular installation, operation or maintenance of this equipment, the local ABB Power T&D Company Inc. representative should be contacted. ABB Power T&D Company Inc. Relay Division Coral Springs, FL 33065 NEW INFORMATION Effective: March 1994 1. INTRODUCTION The G.703 Interface Adapter interfaces CCITT G.703 compliant Data Communication System to 64 kbs Fiber Optic or RS 422 port operating at 64 k baud. 2. FEATURES The G.703 interface complies with CCITT G.703 co- directional, 64 kbps specifications. There is a five ter- minal, screw terminal block with two terminals for the transmit line, two for the receive line and one for earth ground. The fiber optic and RS 422 ports operate at 64 kbps. Data rate clock signals are not needed or provided by the adapter. NOTE: Only the transmit and receive data signals are available. Therefore a self clocking code like NRZI must be used. The fiber optic port has a separate transmitter and detector connectors (separate transmit and receive fibers are required). Wavelength is 850 nm and ST type connectors are used. The transmitter is HFBR- 14XX series and the receiver is HFBR-24XX series. The RS 422 interface has transmit and receive differ- ential pairs that comply with RS 422 electrical specifi- cations. The connector and pins (chassis and signal grounds, transmit and receive pairs) comply with RS 530 specifications. 3. SPECIFICATIONS 3.1. Power Requirements Input Voltage: 48 Vdc nominal (42 to 60 V range) or 125 Vdc nominal (100 to 200 V range) Power Consumption: 5W 3.2. Temperature Range Operating: 0C to 65C Storage: -20C to 80C 3.3. Physical Data Height: 5.30 (134.6 mm) Width: 3.43 (87.1 mm) Depth: 4.25 (108 mm) Weight: 2.0 lbs (0.9 kg) 3.4. Communication Ports 3.4.1. G.703 Port CCITT G.703 co-directional 64 kbs compliant, trans- former coupled. 3.4.2. Fiber Optic, 64 kbs Port Transmit and receive lines 850 nm, ST connector, multi-mode cable, 10 dB optical power budget. 3.4.3. RS 422, 64 kbs Port Transmit and receive lines are RS 422 (electrical) and RS 530 (mechanical, connector and pin num- bers) compliant. G.703 Adapter X R R X CCITT G.703 64 kbs 256 k baud RS 422 or Fiber Optic 64 kbs 64 k baud
Figure 1. G.703 Block Diagram
I.L. 40-201.7 2 The female (receptacle) DB25 connector is used in adherence to Data Communication Equipment (DCE) definition. 4. INDICATORS The four LEDs indicate: Transmitted signal activity (transitions) Received signal activity (transitions) Presence of G.703 received signal carrier and sync. power 5. INSTALLATION 5.1. Power Connect 48 Vdc or 125 Vdc nominal to DC Power Input terminals. 5.2. G.703 Port Connect transmit and receive ports to G.703 TX OUT and G.703 RX IN terminals respectively. Use of shielded twisted pairs is strongly recommended. Connect earth ground to terminal Chassis GND. 5.3. 64 kbs Port 5.3.1. RS 422 / RS 530 Option The G.703 Interface Adapter is equipped with DB25 female (Receptacle) connector. Therefore the inter- connecting cable must use DB25 male connector. Connect transmit pair (data from Interface Adapter) to pins 3 and 16. (Pin 3 positive and pin 14 negative). Connect receive pair to pins 2 (positive) and 14 (neg- ative). Connect pin 7 (signal common) to corresponding sig- nal common pin at the other end of the cable. 5.3.2. Fiber Optic Option Connect transmit data cable to XMT fiber optic transmitter. Connect receive data cable to RCV fiber optic receiver. NOTE: ST connectors and multi-mode fiber optic cables are required. 6. DETAILED DESCRIPTION 6.1. G.703 Fundamentals The following describes 64 kbit/s G.703 co-direc- tional interface in which the information and its asso- ciated timing signal are transmitted in the same direction. Code conversion rules Step 1 A 64-kbit/s bit period is divided into four unit intervals. Step 2 A binary one is coded as a block of the following four bits: 1 1 0 0 Step 3 A binary zero is coded as a block of the following four bits: 1 0 1 0 Step 4 The binary signal is converted into a three-level signal by alternating the polarity of consecutive blocks. Step 5 The alternation in polarity of the blocks is violated every 8th block. The violation block marks the last bit in an Octet. These conversion rules are illustrated in Figure 2. 6.2. Circuit Description Both G.703 line pairs (refer to Internal Schematic Dwg. 1617C21) are coupled to U1 via transformers T1 and T2. U1 converts the received analog signal at secondary of T1, to digital form and monitors received signal level. U1 also has level interface devices and output transistors that drive the transmit line pair via the pri- mary of T2. Co-directional Digital Data Processor U2 decodes the received G.703, 256 k baud signal and extracts the 64 kbps received data. It also converts 64 kbps data into a 256 k baud G.03 transit signal and moni- tors the received signal for correct sync. U2 does not output and input 64 kbps data directly. It communicates in bursts of 8 bits at a time, at a 2.048 MHz clock rate, 8,000 times per second. This is because this particular IC is designed for equipment that processes T-1, CEPT or ISDN signals. I.L. 40-201.7 3 EPLD U3 contains shift registers, counters, clock dividers and other logic that interfaces binary, syn- chronous, 64 kbps data to the bursts of data used by U2. The EPLD also detects transmit and receive data transitions and will pulse the data activity LEDs. The EPLD divides clock from crystal oscillator U5, or 2.048 MHz and 256 kHz for U2. It also switches from fiber optic port to the RS 530 port as determined by position of Jumper J1. The EPLD monitors carrier detector and sync signals from U1 and U2 and if these are all good, it will light the received signal OK LED. When the fiber port is enabled, then transmitter LE1 and receiver LE2 are active. Q1 is an emitter follower which when conducting (EPLD drives its base low), will turn off the LED transmitter by absorbing all the R5 current. when Q1 is turned off by the EPLD driv- ing its base high, then all current goes to LED trans- mitter LE1. When the RS 422 port is enabled, than the signal path between U4 and the EPLD is active. U4 con- verts standard CMOS / TTL logic level to the differen- tial RS 422 levels used for the data transmit and receive paths. The only internal voltage is +5 Vdc (Power Supply Module schematic #1617C22). This is supplied by an internal Vicor power supply PS1. A different Vicor supply and input filter capacitor is required for 48 V, or 125 Vdc input voltage. DC input is applied to P5.1 and P5.22. this is fused by F1 and F2 before being applied to bridge rectifier BR1 and then to the Vicor dc input. BR1 always directs the right polarity to the power supply regardless of supply voltage polarity. 7. ORDERING INFORMATION 7.1. Catalog Number Typical Catalog Number G.703 1 R Input Voltage 1 - 48 Vdc 2 - 125 Vdc Interface Type R - RS 422/RS 530 H - Fiber Optic 850 nm ST Connector 7 1 Bit number 64 kbit/s data Steps 1 - 3 Step 4 Step 5 Octet Timing 8 0 1 0 2 1 3 0 4 0 5 1 6 1 7 1 8 0 1 1 Violation Violation Figure 2. Code Conversions I . L .
4 0 - 2 0 1 . 7 4 Figure 3. Internal Schematic (Main Module) 1617C21 Sub 1 I.L. 40-201.7 5 Figure 4. Internal Schematic (Power Supply) 1617C22 Sub 1 I.L. 40-201.7 6 Figure 5. Assembly Drawing (Main Module) 1617C20 Sub 1 I.L. 40-201.7 7 Figure 6. Assembly Drawing (Power Supply) 1617C23 Sub 1 I . L .
4 0 - 2 0 1 . 7 8 Figure 7. Outline Drawing 1617C34 Sub 1 I . L .
4 0 - 2 0 1 . 7 9 Figure 8. General Assembly 1617C33 Sub 1