Offset Reduction in CMOS Current Feedback

Amplifier
Sarang H.Upadhyay1 , Mohammedzuber P. Malek2 , , Amisha P.Naik3
1,2
PG Students of Nirma University

3
Assistant Professor of NIrma University

Institute of Technology, Nirma University, Ahmedabad-382481

[email protected],[email protected],
[email protected],[email protected]

Abstract:- the needs of the analog signal processing

circuitry but by that of the digital circuitry.
The current feedback amplifier structures gained Also because CMOS CFAs are typically
popularity among analog designers due to its wide composed of a CMOS current conveyor
bandwidth, high slew rate and low distortion. But the followed by a buffer stage, a low-voltage
Presently available CFOA architectures are facing a CMOS current conveyor would enable CFA
problem of poor offset performance. Proposed offset
compensation technique reduces the offset about 100%. based circuits to be implemented in
This is supported by a eldo-spice simulation results submicron CMOS IC technologies with
carried out using TSMC 0.35u technology. Simulation reduced supply voltages. Examples of low
results indicate an overall bandwidth in excess of 20 voltage CMOS current
MHz and 15 MHz for each circuit at a gain of −10 and conveyors that could be used to build low
with a 3.3 V supply. Experimental results from a chip
voltage CFAs, But with several devices
fabricated in a 0.35 μm CMOS technology agree closely
with the simulation results. stacked between its rails, operation at low
voltages may become an issue.
Keywords : CFOA, CCII , Offset compensation In this paper we report on CMOS
implementations that are suitable for low
I. Introduction supply voltage applications. In circuit-1,
low voltage high-swing current mirrors are
Current feedback amplifiers (CFA) are employed in a unique configuration. The
noted for their high swing, low voltage current mirror
potential for high bandwidth, high slew offers the advantage of improved Z
rate, and a closed-loop bandwidth which is terminal impedance while allowing low
almost independent of the closed loop supply operation. In circuits, the Z
gain . Bipolar implementations are popular terminal circuit is formed by copying the
due to their high speed and the ease with output of the amplifier used to form the
which the low impedance current sensing buffer. Like a conventional CFA, the
node can be implemented . The lower current feedback occurs externally
transconductance of MOS transistors through a feedback. In this we proposed
typically makes CMOS current feedback the offset compensation circuit in order to
amplifiers inferior to bipolar further reduce the offset of circuit-1,
implementations. A CMOS CFA is, section II discuses the circuit description ,
however, desirable for mixed-signal IC section III discuses the proposed offset
applications. In such applications, the compensation circuit and section IV describes
choice of IC technology is dictated not by simulation of the circuit.
II. Circuit Description Transistors W(um)/L(um)

In the circuit proposed B.J. Maundy shown in fig-1 is MC1=MA,MC2 10/1

a (uncompensated) CCII based CFOA which is
cascaded stage formed using CCII followed by MC3 3/1
voltage follower. In this circuit, low voltage high-
swing cascode current mirrors are employed in a MC4=MB,MC5 35/4
unique configuration. The high swing, low voltage
current mirror offers the advantage of improved Z
Table-I
terminal impedance while allowing low supply
operation. In this, the Z terminal circuit is formed by
copying the output of the amplifier used to form the
buffer. Like a conventional CFA, the current
feedback occurs externally through a feedback Kc3 Vc1 - Keff Vc2 =Kc3 (VDD -|
resistor. The CFA property of constant-bandwidth VTp|) - Keff (VDD -|Veff|)
relatively independent of closed loop gain is
maintained in this design. The above circuit gives a Keff =Kc1 Kc2 Kc1 +Kc2
offset of 30mV,which can be further reduced by
employing compensation circuit made up of
Veff = VTN + |VTP|
transistors MC1,MC2,MC3,MC4,MC5 as shown in
fig-2. The proposed compensation circuit gives offset
reduction by 100% . Transistors M1 through M4 achieved by making the voltage at the gate of M25
form the differential input buffer stage of the (Vc) equal to the difference between Va and Vb;
amplifier. The node labeled a acts as a high multiplied by a very large gain. Hence, when Vc is
impedance node whose gain g1ro1 depends on the set to a finite value, the difference between Va and
product of the transconductance of M1/M3 and the Vb will be approximately equal to zero and
output impedance seen at node a. Here g1 represents independent of IX.For proper operation, Vc1 and Vc2
the transconductance of M1 and M3 and ro1 is the must be chosen so that Va is equal to Vb and
reciprocal of the total conductance seen at node a. according to the following equation: The
Hence the output resistance of a gain stage is compensation circuit in (fig-2) made up of transistors
represented by the ro terms. MC1,MC2,MC3,MC4 and ,MC5. the aspect ratio are
given in table 2
Transistors M5-M22 forms a second stage which
provides required gain which is a non-inverting
amplifier using wide-swing cascade mirror. The
operation of the wide-swing cascode mirror is well M1-M2,M23-M24 35/3
documented and is increasingly becoming popular in
many analog low voltage designs. To ensure M3-M4,M25-M26 49/1
maximum input dynamic range, complementary
transistors M5–M14 and M27–M37 are used at the M5-M6,M27-M28 100/1
input of the second stage gain in Fig. 3.2. The
remaining transistors M7– M20, M10–M18, M28– M8-M9,M19-M21,M20,M22 270/1
M38, and M34–M36 form the high-swing cascode
mirrors. In this circuit the gates of transistors M2 and M30-M31,M38-M39
M24 form the voltage following nodes.
M11,M14,M29,M40 27.1/1
III. The Proposed Offset Compensation Circuit
M10,M34 72/1
The reason of poor offset performance of a above
circuit is due to voltage difference between the A and M12,M13,M15,M16,M17,M1 480/1
the B terminals of the voltage buffer stage which 8
results due to current transfer error of current mirror
formed by M14-M15 which is mainly due to channel
M32,M33,M35,M36
length modulation. A solution to this problem is to
make Va equal to Vb for any value of IX. This is
M7,M28 40.5/1

Table-II

Fig.1 Circuit diagram (Without Offset compensation)

Fig.2Circuit
diagram (With
Offset
compensation)

IV. Simulation

Eldo Spiece
simulations were
carried out with
model parameters
of 0.35um CMOS
process provided by
MOSIS (TSMC).
The supply voltages
were equal to Open loop AC Analysis
3.3V.The transistors offset(circuit-2 (circuit-2 With
aspect ratios of the Without offset offset
compensation) AC Analysis compensation)
Circuit and the
(circuit-2 Without
modification
offset
circuits are given in compensation)
Table I and Table
II. Simulation
results are given in
Table III.

Analysis Circuit Close loop offset

(circuit-2 Without
offset
compensation)
Offset 30mv offset
Analysis(circuit-2 Layout of circuit-
voltage(input)
With offset 1
compensation)
-3db bandwidth 8meg

UGB 16meg

Gain 10db

Phase-margin 65(degree)

Power dissipation 74.477mW

 Voltage Low- integrated circuit Guerrini.”Low-
Power CMOS design.”John voltage,low-
Current Wiley & Sons, power CMOS
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Peter [6] Giuseppe Ferri
Aronhime,” and Nicole C.
Alternative
Layout of Realizations of
Modified Circuit CMOS Current
Feedback
Conclusion Amplifiers”for
Low Voltage
The proposed offset Applications”
compensated circuit
Analog Integrated
reduces the offset to
Circuits and Signal
0mv (100%), when
Processing, 32,
the circuit is used in
157–168, 2002_C
closed loop mode.
2002 Kluwer
This is achieved by
Academic
just increasing the
Publishers.
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Manufactured in
five The -3db
The Netherlands
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compensated [3] I. A. Awad and
amplifier is 8MHz A. M. Soliman,”
with phase margin New CMOS
of 65 degree. The Realization of the
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compensated and
uncompensated
Transactions On
amplifier is Circuits And
74.7Watt.The Systems—Ii:
layout area is 0.129 Analog And
mm2 Digital Signal
Processing, Vol.
46, No. 4, April
1999
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