XV SBMicro Intl.

Conference on Microelectronics & Packaging, Manaus (Brazil), September 2000

A CMOS/SOI Continuous-Time Low-Pass gm-C Filter

C. Cavalcanti1,2, J. A. De Lima1 & M. Verleysen3

1
Electrical Engineering Department, Universidade Estadual Paulista
12516-410 Guaratingueta – SP, Brazil
[email protected]
[email protected]

2
Microelectronics and Electronics Department, Universidade Estadual de Campinas
13081-970 Campinas – SP, Brazil
3
Microelectronics Laboratory, Université Catholique de Louvain
B-1348 Louvain-la-Neuve, Belgium

Abstract Continuous-time filters successfully process high-

speed signals in applications where distortion and noise
This paper describes a preliminary comparative performance are not too demanding such as many data
analysis between continuous-time gm-C filters based on communications and video circuits. Their lower
a specific transcondutor but designed according to consumption with respect to switched-capacitor filters
CMOS/bulk (conventional) and CMOS/SOI fabrication makes them thus attractive to low-power applications.
processes. A compensation technique to minimize the Transconductance-C filters can readily be implemented
phase-error (lead-phase) of the basic integrator owing in fully-integrated form, compatible with the remaining,
to the relatively high output-conductance of the often digital, system in most desired technologies.
adopted transconductor is examined. Such a technique Besides, electronic-tuning against environmental or
consists of moving the RHP zero frequency closer to processing variations can be made by adjusting the gm
the non-dominant LHP pole by adding an extra parameter through its dependence on some dc bias
capacitance along the signal feedforward path. voltage or current [2-5]. Owing to smaller stray
A 3rd-order low-pass, ladder-type elliptic-filter capacitances, CMOS/SOI filters are expected to feature
was designed and integrated on a 2µm CMOS/SOI better performances concerning frequency-range and
fabrication process. At nominal bias and VDD=5V, the linearity than their counterparts integrated on
filter experimental parameters are fp=4.1MHz, conventional CMOS/bulk processes.
fs=12MHz, Amax<2.47dB and Amin>39dB. As no This paper is organized as follows. In Section II, a
meaningful gain-peaking around the roll-off frequency comparison between the frequency characteristic of
was found, small phase-error associated with basic CMOS/SOI and CMOS/bulk integrators, built around
integrators can be assumed. The filter linearity is the transconductor-cell proposed by Krummenacher
described by a THD of 0.25% for a differential output [6], is carried out. By employing a macromodeling of
voltage Vout=200mVpp. the integrator, the phase-lead at the unity-gain
frequency, caused by the transconductor relatively low
output-resistance, is compensated by properly adjusting
the frequency of the positive zero associated with the
I. Introduction
signal feedforward path. In Section III, the design of a
CMOS/SOI low-pass, 3rd-order Cauer filter is
With the perspective of providing quasi-ideal
presented. Experimental results of the CMOS/SOI filter
three-terminal transistors, the CMOS Silicon-on-
are presented in Section IV. Conclusions and final
Insulator technology has increasingly become more
remarks are summarized in Section V.
attractive as compared to its bulk counterpart on
designing integrated circuits with superior performance
on temperature and radiation hardness, packing density, II. Integrator Modeling and Design
frequency operation, power consumption, latch-up
hazards and others [1]. Very-low leakage currents make The simplified small-signal model of an inverting
CMOS/SOI suitable for micropower applications such gm-C integrator is shown in Figure 1. Low-frequency
as battery-powered and human-implanted devices. transconductance and the finite output-conductance are
 XV SBMicro Intl. Conference on Microelectronics & Packaging, Manaus (Brazil), September 2000

represented by gmo and go, respectively. Ci and Co are decreases from 4.44º to 3.34º for the CMOS/bulk
the stray-capacitances at input and output nodes, integrator. Nonetheless, a further improvement occurs
respectively, and Cp the coupling capacitance. for the CMOS/SOI version where the phase-error is
Assuming Ci>>Cp and defining CT = CL + Cp + Co, the lowered from 1.00º to –0.01º (excess phase). As the
integrator transfer-function turns out compensation technique is affected by process random-
variations as well as modeling-uncertainties of output-
gmo conductances and stray-capacitances, an optimal Cex
s−
Vo( s) Cp Cp that would exactly cancel out the phase-error is not
= (1) therefore proposed. By means of careful layout-
Vs ( s) RsCiCT  1  go 
s +  s +  extraction and simulation, a range of Cex capacitances
 RsCi  CT  can however be found to lower the phase-error (lead or
excess) close to one-degree values.
with a low-frequency gain -gmo/go. Dominant and
secondary poles are respectively p1=go/CT and CMOS /SOI CMOS /Bulk
p2=1/(RsCi). As expected, the feedforward capacitance Transistor µm]
W [µ µm]
L [µ µm] L [µ
W [µ µm]
Cp gives rise to a zero z1=gmo/Cp on positive real-axis. M1-M1A 264 6 44 1.6
A previously-reported transconductor stage [6] M2-M2A 15 2 7.6 1.6
was considered for a comparative analysis between
M3-M3A 40 10 44 1.6
circuits of same functionality integrated on CMOS/bulk
M4-M4A 26 12 120 1.6
and CMOS/SOI. Figure 2 displays the schematic of the
M5-M5A 46 2 21 1.6
adopted fully-differential transconductor. It basically
corresponds to a differential-pair, whose linear range is
Table 1. Drawn-sizing of transconductor-transistors
extended by voltage-controlled source-degeneration,
and active loads with an embedded common-mode
feedback (CMFB) loop. Nominal parameters are gm =
150µS, go = 2µS, Ci = 0.42pF, Co = 0.22pF and Cp = III. Filter Design
20fF. In order to compare the integrator performance in
different fabrication processes, an identical gm was The block diagram and specifications of a
assumed as design specification for the CMOS/SOI balanced 3rd-order low-pass, RLC ladder elliptic-filter
version. Transconductor-sizing for both versions is with resistive termination using a gyrator-capacitor
listed in Table 1, for a nominal bias current Iref = 50µA. combination is shown in Figure 6. Filter specifications
Simulation of CMOS/bulk and CMOS/SOI correspond to a nominal 3dB-cuttof frequency
circuits was carried out with PSPICE and ELDO, fp=4.0MHz, a stopband-frequency fs=12MHz, a
respectively. Design and process parameters passband-attenuation Amax<1.0dB and a stopband-
correspond to a standard 0.8µm CMOS and a 2µm attenuation Amin>23dB. On-chip capacitors are
CMOS/SOI fabrication processes. A single supply- C1=2.88pF, C2=0.7375pF, C3=2.88pF and C=2.675pF.
voltage VDD is assumed. Figure 3 overlays the resulting The simulated frequency characteristic of the
frequency characteristic of both integrators, for CMOS/SOI filter is displayed in Figure 7, for VDD=
CL=5pF. The CMOS/bulk version revealed a unity-gain 5V, resulting fp=5.75MHz, fs=19MHz, Amax<1.5dB and
frequency ft=446kHz, a low-frequency voltage-gain AV Amin>25.7dB.
=19dB and a phase-error of 4.5o, whereas its
CMOS/SOI counterpart presented fp=110kHz, AV
=28.1dB and a phase-error of 1.0o. Lead-phase is IV. Experimental Results
mainly associated with dominant-pole p1 due to the
transconductor relatively high output-conductance on The CMOS/SOI version of the designed filter was
both versions although the CMOS/SOI one exhibits a integrated at the Microelectronics Laboratory, Catholic
lower go. As an excessive phase-error may cause gain- University of Louvain, Louvain-la-Neuve, Belgium.
peaking in the filter-passband near the roll-off Effective area is 2mm2 and its microphotograph is
frequency, and consequently distortion [7], its displayed in Figure 8. The measured frequency
reduction by moving the zero z1 to frequencies close to response of the filter @VDD=5V is illustrated in Figure
p1 is thus proposed. Such a technique tends to 9. As it can be seen, no meaningful gain-peaking near
compensate for the original phase-lead since a zero on roll-off frequency is found which suggests occurrence
the RHP acts as a LHP pole, as far as phase-shifting is of a small phase-error associated with building-part
concerned. In practice, compensation is achieved by integrators. The filter experimental parameters are
adding an extra capacitance Cex along the feedforward fp=4.1MHz, fs=12MHz, Amax<2.47dB and Amin>39dB,
path, as depicted in Figure 4. As go/CT << (1/RsCi), the which are in good agreement with simulation. The 3dB-
secondary pole shouldn’t affect the Cex value. cutoff frequency as function of VDD is illustrated in
The compensation effect on the phase-error is Figure 10. The meaningful difference between
shown in Figure 5. For Cex = 200fF, the phase error simulated and measured data could mostly be attributed
 XV SBMicro Intl. Conference on Microelectronics & Packaging, Manaus (Brazil), September 2000

to inaccuracies of the pseudo SOI-transistor model fellow of the FNRS (Belgian National Fund for
embedded in ELDO that is simply adapted from a Scientific Research).
standard MOSFET modeling. Moreover, non-ideal
effects in metal/poly-Silicon floating and grounded VII. References
capacitors may also contribute to such deviations.
The filter 3dB-cutoff frequency can be tuned by [1] Colinge, J. P. - Silicon-on-Insulator Technology:
the bias current Iref, as shown in Figure 11, variations of Materials to VLSI, Kluwer Academic Publishers, 1997.
the bandwidth with the supply voltage could be [2] Pennock, J. L. - “CMOS Triode Transconductor for
compensated by adjusting Iref through on-chip auto- Continuos-Time Active Integrated Filters”, Electronic
tuning systems [8]. The filter linearity corresponds to a Letters, Vol. 21, No. 18, August 1985.
total harmonic distortion (THD) of 0.25% for a [3] Gatti, U., Maloberti, F. & Torelli, G. –“CMOS Triode-
differential output-voltage Vout=200mVpp. The Transistor Transconductor for High-Frequency Continuous-
measured THD as function of signal level (peak Time Filters”, Proc. IEE Circuits, Devices and Systems, vol.
141, No. 6, Dec 1994.
amplitude) @VDD=4V is shown in Figure 12.
[4] Low-Voltage/Low-Power Integrated Circuits and
Systems, Edited by Sánchez-Sinencio, E. & Andreou, A.,
IEEE Press, 1999.
V. Conclusion [5] De Lima, J. A & Dualibe, C. – “On Designing Linearly-
Tunable Ultra-Low Voltage CMOS gm-C Filters”, proc. of
A comparative analysis between continuous-time IEEE ISCAS, Geneva, Switzerland, 2000.
gm-C filters based on a specific transcondutor but [6] Krummenacher, F. & Joehl, N. - “A 4-MHz CMOS
Continuos-Time Filter with On-Chip Automatic Tuning”,
designed according to different fabrication processes
IEEE JSSC, Vol. 23, No. 3, June 1988.
was carried out. Simulated data from the frequency [7] Khorramabadi, H. & Gray, P. - “High-Frequency CMOS
response of CMOS/bulk and CMOS/SOI basic Continuos-Time Filters”, ibid, vol. SC-19, No. 6, December
integrators confirm a better performance of latter 1984.
version with respect to low-frequency gain and phase [8] Schaumann, R., Ghausi, M. & Laker, K. – “Design of
error. In addition, this work proposes a compensation Analog Filters - Passive, Active RC and Switched
method to cope with the lead-phase due to the Capacitors”, Prentice Hall, 1990.
relatively high output-conductance of the adopted
transconductor. Based on the integrator small-signal
macromodeling, the resulting RHP zero is moved
towards the non-dominant LHP pole by adding an extra
capacitor along the signal feedthrough-path.
A balanced 3rd-order low-pass, RLC ladder-type
elliptic-filter was designed and integrated on a 2µm
CMOS/SOI fabrication process. At nominal bias and
VDD=5V, the filter experimental parameters are
fp=4.1MHz, fs=12MHz, Amax<2.47dB and Amin>39dB,
which are on good agreement with simulated data. As
no meaningful gain-peaking around the roll-off
frequency was found, small phase-errors related to
building-part integrators are suggested. The filter
presents a THD of 0.25% for a differential output
voltage Vout=200mVpp@VDD=4V. Lack of accurate
modeling for SOI transistors in circuit simulators, such
as ELDO and PSPICE, precludes from obtaining a
closer fitting between simulated and experimental
results as observed, for instance, on the filter frequency
response as function of the power-supply voltage.

VI. Acknowledgements
The authors would like to express their
thankfulness to FAPESP (process 97/09613-0) and
CAPES in Brazil, for financial assistance and
continuous support on integrated circuits research and
to the MIVIP Esprit project LTR22527, funded by the
European Commission. Dr. M. Verleysen is a research
 XV SBMicro Intl. Conference on Microelectronics & Packaging, Manaus (Brazil), September 2000

Figure 1. Equivalent small-signal model of gm-C integrator Figure 2. Fully-differential transconductor [6]

(a) (b)

Figure 3. Simulated frequency response of integrators: (a) gain and (b) phase

Figure 4. Integrator with compensation capacitors (Cex) Figure 5. Simulated phase-error of integrators.
 XV SBMicro Intl. Conference on Microelectronics & Packaging, Manaus (Brazil), September 2000

C2

R fp = 4 MHz
fs = 12 MHz
L2
C1 C3 Amax < 1dB
Vin R Vout Amin > 23dB

2C 2

gm1 gm2 gm3 gm4 gm5 gm6 gm7

+ - + + - - -
Vin + - + + - gm - - gm Vout
2gm gm 2gm gm 2C 2gm
- + C1 - - + + C3 +
- + - - + + +

VTUNE

2C 2

Figure 6. Block diagram of a 3rd-order low-pass Cauer gm-C filter (inset: filter specification)

(a) (b)

Figure 7. Simulated frequency response of SOI filter : (a) gain and (b) phase

Figure 8. Microphotograph of the SOI filter Figure 9. Measured frequency response of the SOI filter
 XV SBMicro Intl. Conference on Microelectronics & Packaging, Manaus (Brazil), September 2000

Figure 10. SOI filter characteristic against supply-voltage Figure 11. SOI filter bandwidth as function of bias current

Figure 12. Measured total harmonic distortion of SOI filter

@VDD = 4V