Sl No Theory 1 2 3 & ( )

Subject Code P1MAC03 P1VLC01 P1VLC02 P1VLC03 P1VLC0& P1VLC0(

M.TECH. VLSI DESIGN SEMESTER I Subject

Mathematical Foundations of Electronics Engineering VLSI asic ! Conce"ts Ad#anced $igital S%stem $esign VLSI 'echnolog% Verilog Programming Analog Integrated Circuit $esign VLSI $esign La+ SEMESTER II Subject

3 3 3 3 3 3 0

0 0 1 0 1 1 0

0 0 0 0 0 0 2

3 3 & 3 & & 2 23 C

Practical * P1VLC0) Total Credits Sl No Theory 1 2 3 & ( ) Practical * Subject Code P2VLC0* P2VLC0P2VLC0/ P2VLC10 P2VLC11 11111 P2VLC12

$igital CM,S VLSI $esign 'esting of VLSI Circuits. est academic elec VLSI Signal Processing ASIC $esign. #lsi cdac VLSI for 0ireless communication Electi#e 2 I. est cdac Em+edded s%stem and ad#anced VLSI $esign La+ SEMESTER III Subject

3 3 3 3 3 3 0

1 1 0 1 0 0 0

0 0 0 0 0 0 2

& & 3 & 3 3 2 23

Total Credits Sl Subject No Code Theory 1 11111 2 11111 3 11111 Practical & P3VLC13 Total Credits Sl No Practical 1 Total Credits Subject Code P&VLC1& L T P

Electi#e 2 II Electi#e 2 III Electi#e 2 IV Pro3ect Phase I SEMESTER IV Subject

3 3 3 0

0 0 0 0

0 0 0 12

3 3 3 ) 1( C

Pro3ect Phase II

2&

12 12

!er all Total Credits " #$ L % Lecture& T % Tutorial& P % Practical& C % Credit LIST ' ELECTIVES ' R SEM II %ELECTIVE(I 1

Sl No 1 2 3 & (

Subject Code PEVLC1( PEVLC1) PEVLC1* PEVLC1PEVLC1/

Subject VLSI S%stem $esign Solid State $e#ice Modeling and Simulation Em+edded S%stem $esign $SP Processor Architecture and Programming cdac est electi#e ii FP4A ased Signal Processing LIST ' ELECTIVES ' R SEM III %ELECTIVE(II Subject Com"uter Aided $esign for VLSI Ph%sical $esign of VLSI Circuits 5igh S"eed S0itching Architecture $esign of VLSI in Em+edded S%stem Ad#anced Micro Processor and Microcontrollers ' ELECTIVES ' R SEM III %ELECTIVE(III Subject 5ard0are soft0are co6design 7ano technolog% Introduction to MEMS S%stem $esign 8ireless Sensor 7et0or9s Control S%stem on Chi"

L 3 3 3 3 3

T 0 0 0 0 0

P 0 0 0 0 0

C 3 3 3 3 3

Sl No 1 2 3 & (

Subject Code PEVLC20 PEVLC21 PEVLC22 PEVLC23 PEVLC2&

L 3 3 3 3 3

T 0 0 0 0 0

P 0 0 0 0 0

C 3 3 3 3 3

LIST Sl No 1 2 3 & ( Subject Code PEVLC2( PEVLC2) PEVLC2* PEVLC2PEVLC2/

L 3 3 3 3 3

T 0 0 0 0 0

P 0 0 0 0 0

C 3 3 3 3 3

LIST Sl No 1 2 3 & ( Subject Code PEVLC30 PEVLC31 PEVLC32 PEVLC33 PEVLC3&

' ELECTIVES ' R SEM III %ELECTIVE(IV Subject L 3 3 3 3 3 T 0 0 0 0 0 P 0 0 0 0 0 C 3 3 3 3 3

Lo0 Po0er VLSI $esign Semiconductor memor% design ! Processing Com"uter architecture and Parallel Processing $ata Con#erters 7et0or9 on Chi"

L % Lecture& T % Tutorial& P % Practical& C % Credit

SEMESTER I P)M*C+$ M*THEM*TIC*L ' ,ND*TI NS ' ELECTR NICS ENGINEERING L T P C : VLSI; $++$ *i-. 'o gi#e e<"osure to different a""lied mathematics techni=ues> this 0ill +e useful for designing efficient :area.s"eed; electronic automation tools for VLSI design? bjecti!e. 'o im"art 9no0ledge on Fu@@% Logic/ $ifferential E=uations/ 4ra"h 'heor% and Algorithms? ,NIT I 'u00y Lo1ic 23$ asic conce"ts of fu@@% logic 2 fu@@% sets 2 o"erations of fu@@% sets 2 "ro"erties of fu@@% sets 2 fu@@% relations 2 com"osition of fu@@% relations 2 fu@@% "ro"ositions 2 fu@@% =uantifiers> fu@@% "rocessor? ,NIT II 4ueui51 Models 23$ asics of =ueuing models 2Poisson =ueue s%stems 2 transient state "ro+a+ilit% 2 stead% state "ro+a+ilities 2 single and multi6ser#er models 0ith finite and infinite ca"acit% 2 LittleAs formula 6 :M6461; =ueueing model 2 Pollac@e96Bhinchine formula ,NIT III Di66ere5tial E7uatio5s 23$ Solution of first6order differential e=uations using numerical methods? Solution of "h%sical situations that can +e modeled +% first6order differential e=uations? Solution of higher order homogeneous differential e=uations 0ith constant coefficients? Solution of non6homogeneous higher6order differential e=uations using the method of Cndetermined Coefficients> Solution of non6homogeneous higher6order differential e=uations using the method of Variation of Parameters ,NIT IV Gra8h Theory 23$ 4ra"hs 2 Introduction 2 Isomor"hism 2 Su+ gra"hs 2 8al9s> Paths> Circuits 2 Connectedness 2 Com"onents 2 Euler 4ra"hs 2 5amiltonian Paths and Circuits 2 'rees 2 Pro"erties of trees 2 $istance and Centers in 'ree 2 Dooted and inar% 'rees? ,NIT V *l1orith-s 23$ AlgorithmsE Connectedness and Com"onents 2 S"anning tree 2 Finding all S"anning 'rees of a 4ra"h 2 Set of Fundamental Circuits 2 Cut Vertices and se"ara+ilit%? Shortest Path Algorithm 2 $FS 2 Planarit% 'esting 2 Isomor"hism T T*L. 9:3):";+ Periods RE'ERENCES. 1? 4?F? Blir and ? Guan> HFu@@% Sets and Fu@@% LogicE 'heor% and A""licationsI> P5I Learning Pri#ate Limited> 7e0 $elhi> 1//*? 2? 5? A? 'aha> H,"erations DesearchE An IntroductionI> se#enth edition> Pearson Education> 7e0 $elhi> 2002? 3? 4?5? 4olu+ and C?5? Van Loan> HMatri< Com"utationsI> third edition> Fohns 5o"9ins Cni#ersit% Press> London> 1//)? &? 7arsingh $eo> H4ra"h 'heor%E 8ith A""lication to Engineering and Com"uter ScienceI> P5I> 2003? (? D?F? 8ilson> HIntroduction to 4ra"h 'heor%I> Fourth Edition> Pearson Education> 2003? )? $ifferential E=uations 0ith oundar%6Value Pro+lems> *th ed? Jill ! Cullen> 'homson. roo9s Cole> 200/ *? V? Sundara"andian> HPro+a+ilit%> Statistics and Kueuing 'heor%I> P5I Learning> 7e0 $elhi> 200/?

CDLE https://noppa.lut.fi/noppa/opintojakso/bm20a3101/.../lecture_1_2.pdf htt"E..en?0i9i"edia?org.0i9i.Fu@@%Lset htt"E..000?doc?ic?ac?u9.Mnd.sur"riseL/).3ournal.#ol&.s+aa.re"ort?fu@@%sets?html htt"E..000?dia?fi?u"m?es.Mmgremesal.MID.slides.LessonN202N20:Fu@@%N20Pro"ositions;?"df itlab.ee.nsysu.edu.tw/course/97a !/part/ppt/"art0#_$%.1&'(.ppt en?0i9i"edia?org.0i9i.=ueueingLtheor% 000?cs?ute<as?edu.M+ro0ne.???."a"ers.sim"le=ueuingmodels"df?"df 0e+?"d<?edu.Msti"a9+.???.=ueuingmodelsingleser#erformulas?html 000?slideshare?net.amitc%rus.=ueuing6theor% htt"E..000?efunda?com.math.ode.linearodeLconsthomo?cfm htt"E..000?cliffsnotes?com.stud%Lguide.Constant6Coefficients?to"icArticleId61/*3)>articleId61/*20?html htt"E..000?+techguru?com."roLone.9e%0ordLe#elMElectronicsN20andN20CommunicationM$ifferential N20e=uationN20M5igherN20orderN20linearN20differentialN20e=uationsN200ithN20constant N20coefficientsM&13&d())a)(0233cM0+f2d3)/&(f-1+(cM/2)2&1ff)1(3f10+Mlist?html htt"E..oc0?mit?edu.courses.mathematics.1-6036differential6e=uations6s"ring62010.#ideo6lectures.lecture6*6 first6order6linear60ith6constant6coefficients. htt"E..000?math?neu?edu.Mmasse%.Masse%.Masse%Ldocs.class.1st,rderLa"lace?"df htt"E..math?info.$ifferentialLE=uations.La"laceLLinearL$iffE=nLConstCoef. htt"E..000?academicearth?org.lectures.la"lace6transform6to6sol#e6linear6odes htt"E..000?sosmath?com.diffe=.second.#ariation.#ariation?html htt"E..tutorial?math?lamar?edu.Classes.$E.VariationofParameters?as"< htt"E..tutorial?math?lamar?edu.Classes.$E.CndeterminedCoefficients?as"< htt"E..000?cliffsnotes?com.stud%Lguide.'he6Method6of6Cndetermined6Coefficients?to"icArticleId6 1/*3)>articleId61/*21?html n"tel?iitm?ac?in.courses.8e+course6contents.II'???2.node*-?html htt"E..000?efunda?com.math.ode.linearodeLundeterminedcoeff?cfm htt"E..000?csd?uoc?gr.Mh%(-3.re#ie0edLnotes.euler?"df htt"E..0e+s"ace?shi"?edu.deensle%.discretemath.flash.ch*.sec*L*.hamiltongra"hs?html htt"E..en?0i9i"edia?org.0i9i.DootedL+inar%Ltree www.cis.upenn.edu/)matus*ek/cit'9+&2012/.../09&binary&trees.ppt www.math.northwestern.edu/)mlerma/courses/cs310.../dm&bin trees.pdf htt"E..en?0i9i"edia?org.0i9i.4ra"hLisomor"hism www.uow.edu.au/)bmaloney/wuct121/Graphs,eek10-ecture2.pdf htt"E..math0orld?0olfram?com.Isomor"hic4ra"hs?html htt"E..000?cs?"rinceton?edu.Mrs.Algs$S0*.1(ShortestPaths?"df htt"E..en?0i9i"edia?org.0i9i.$i39straOsLalgorithm htt"E..en?0i9i"edia?org.0i9i.ShortestL"athL"ro+lem <eyo5d the syllabusE 7ormalit%As> con#e<it% and conca#it% of Fu@@% sets? ,"en and closed 3ac9son net0or9s in Kueueing theor%? Coloring of gra"hs> ellman6Ford algorithm for shortest "ath ?

P)VLC+) VLSI <*SICS = C NCEPTS

LTPC $++$

*IM 'o gi#e an introduction to +asic M,S transistor theor%> M,S "rocessing technologies and 5$L "rogramming <>ECTIVES 'o im"art 9no0ledge on CM,S circuits and #arious factors to +e considered for CM,S circuit design? $ifferent "rocessing technologies :n60ell> "60ell> t0in tu+ ; 5$L "rogramming methods for se=uential and com+inational circuits ,NIT I VLSI <*SICS/ CM S CIRC,IT *ND L GIC DESIGN 2 asics of VLSI> VLSI $esign flo0> Front end and +ac9 end VLSI design> M,S transistor> transistor as a s0itch >CM,S M,S logic gate design> "h%sical design of +asics logic gates >CM,S in#erters and its Characteristics> Po0er dissi"ation Estimation of resistance> ca"acitance> inductance >CM,S logic structures design? ,NIT II VLSI CIRC,IT CH*R*CTERI?*TI N *ND PER' RM*NCE 2

Secondar% order effects> CM,S gate transistor si@ing> si@ing routing conductors> charge sharing> $esign margin> %ield> relia+ilit%> Scaling of M,S transistor dimensions and La%out design rules ,NIT III CM S CIRC,IT ESTIM*TI N *ND L GIC DESIGN 2 Po0er dissi"ation Estimation of resistance> ca"acitance> and inductance ?CM,S logic structures design> Cloc9ing strategies? ,NIT IV CM S PR CESSING TECHN L G@ 2

Cr%stal gro0th "rocess> CM,S technologies6 "60ell "rocess> n60ell "rocess> t0in tu+ "rocess and silicon on insulator "rocess? ,NIT V <*SICS ' 'PG* *ND *SIC 2

*SIC desi15 6loA/ ty8es o6 *SICs/ <asic testi51 -ethods 6or *SICs/ 'PG* 6loA/ De!ice 8ro1ra--i51/ Di66ere5t 'PG* structures. T T*L " 9: 8eriods <E@ ND THE S@LL*<,S E"ita<%> $e"osition> Ion6im"lantation> and $iffusion

RE'ERENCES. 1? 8este> Eshraghian> HPrinci"les of CM,S VLSI designI> 2nd Edition Addison 8esle%> 1//&? 2? $ouglas A Puc9nell and Bamaran Eshragian> H asic VLSI design H> 3 rd edition> P5I> 1//&? 3?Samir Palnit9ar > Verilog 5$L 2 4uide to digital design and s%nthesis > III edition > Pearson Eduaction &? S?IMAM ! M?PE$DAM> HLogic s%nthesis for Lo0 2 Po0er VLSI $esignsI> Blu0er Academic "u+lishers> 1//-? ,RLs 1? htt"E..000?n"tel?iitm?ac?in.courses.10)10(03 2? htt"E..000?aicdesign?org.scnotes.2002notes.Cha"ter0262CP:-L13L02;?"df

P)VLC+B *DV*NCED DIGIT*L S@STEM DESIGN *IM 'o e<"ose the students to the fundamentals of digital logic +ased s%stem design?

LTPC $)+9

<>ECTIVES 'o im"art 9no0ledge on asics on S%nchronous ! As%nc digital s0itching design? $esign ! realisation of error free functional +loc9s for digital s%stems ,NIT I 2 De#ie0 of se=uential circuits> Meal% ! Moore Models> Anal%sis ! S%nthesis of S%nchronous se=uential circuits> Introduction to V5$L> design units> data o+3ects> signal dri#ers> inertial and trans"ort dela%s> delta dela%> V5$L data t%"es> concurrent and se=uential statements? ,NIT II 2 $igital s%stem design 5ierach%> ASM charts> 5ard0are descri"tion language> Control logic $esign Deduction of state ta+les> State Assignments> Su+"rograms 2 Functions> Procedures> attri+utes> generio> generate> "ac9age> IEEE standard logic li+rar%> file I.,> test +ench> com"onent declaration> instantiation> configuration ,NIT III 2 Anal%sis and s%nthesis of As%nchronous se=uential circuits> critical and non6critical races> Essential 5a@ard ,NIT IV 2 Com+inational and se=uential circuit design 0ith PL$As > Introduction to CPL$As ! FP4AAs> Com+inational logic circuit design and V5$L im"lementation of follo0ing circuits 2 first adder> Su+tractor> decoder> encoder> multi"le<er> ALC> +arrel shifter> &P& 9e% +oard encoder> multi"lier> di#ider> 5amming code encoder and correction circuits ,NIT V 2 'ault Modeli51 Fault classes and models 2 Stuc9 at faults> ridging faults> 'ransition and Intermittent faults? Fault $iagnosis of com+ination circuits +% con#entional methods6 Path sensiti@ation techni=ue> oolean different method and Boha#i algorithm? T T*L. 9:3):CTutorialD ";+ Periods TEET < F. 1? $igital "rinci"les and design 2 % $onald $?4i#one 'ata Mc4ra0 5ill 2? $igital $esign 2 % Morris Mano6 3rd Edition> P5I <eyo5d the Syllabus CML +ased modeling> 8ireless sensor net0or9s> Automatic test "attern genration RE'ERENCE < FS. 1? $igital circuits and logic design 2 % Samuel C?Lee> P5I? :Cnit6V onl%; 2? Logic $esign 'heor% 2 % 7?7? is0as> P5I? 3? S0itching and Finite Automata 'heor% 2 % Boha#i JVI> 2nd Edition> 'M5? CDLsE 1? htt"sE..000?cs?0ashington?edu.education.courses.()*.01au."ro3ect.sue$ocs.tutorial2?"df 2? htt"E..000?i"fn?ist?utl?"t.EC6Ph$.1stedition. ro0nFP4A/)?"df P)VLC+$ VLSI TECHN L G@ LTPC $ + + $ 7

*IM 'o ma9e the students to learn the com"lete flo0 of IC fa+rication> manufacturing and testing? <>ECTIVE 'o im"art 9no0ledge on Lithogra"h% techni=ues Cr%stal gro0th Com"lete flo0 of IC fa+rication ,NIT I 2 CR@ST*L GR GTH/ G*'ER PREP*R*TI N/ EPIT*E@ *ND EID*TI N Electronic 4rade Silicon> C@ochrals9i cr%stal gro0ing> Silicon Sha"ing> "rocessing consideration> Va"or "hase E"ita<%> Molecular eam E"ita<%> Silicon on Insulators> E"ita<ial E#aluation> 4ro0th Mechanism and 9inetics> 'hin ,<ides> ,<idation 'echni=ues and S%stems> ,<ide "ro"erties> Dedistridution of $o"ants at interface> ,<idation of Pol% Silicon> ,<idation inducted $efects? ,NIT II LITH GR*PH@ *ND REL*TIVE PL*SM* ETCHING 2

,"tical Lithogra"h%> Electron Lithogra"h%> P6Da% Lithogra"h%> Ion Lithogra"h%> Plasma "ro"erties> Feature Si@e control and Anisotro"ic Etch mechanism> relati#e Plasma Etching techni=ues and E=ui"ments> ,NIT III 2 DEP SITI N/ D,'',SI N/ I N IMPLEMENT*TI N *ND MET*LIS*TI N $e"osition "rocess> Pol%silicon> "lasma assisted $e"osition> Models of $iffusion in Solids> Flic9As one dimensional $iffusion E=uation 2 Atomic $iffusion Mechanism 2 Measurement techni=ues 6 Dange theor%6 Im"lant e=ui"ment? Annealing Shallo0 3unction 2 5igh energ% im"lantation 2 Ph%sical #a"our de"osition 2 Patterning? ,NIT IV PR CESS SIM,L*TI N *ND VLSI PR CESS INTEGR*TI N 2

Ion im"lantation 2 $iffusion and o<idation 2 E"ita<% 2 Lithogra"h% 2 Etching and $e"osition6 7M,S IC 'echnolog% 2 CM,S IC 'echnolog% 2 M,S Memor% IC technolog% 6 i"olar IC 'echnolog% 2 IC Fa+rication? ,NIT V *N*L@TIC*L/ *SSEM<L@ TECHNI4,ES *ND P*CF*GING 2 ' VLSI DEVICES

Anal%tical eams 2 eams S"ecimen interactions 6 Chemical methods 2 Pac9age t%"es 2 +an9ing design consideration 2 VLSI assem+l% technolog% 2 Pac9age fa+rication technolog% T T*L. " 9: 8eriods <E@ ND THE S@LL*<,S. iCM,S 'echnolog% Be% "rocess ste"s in $e#ice Fa+rication?

RE'ERENCES. 1? S?M?S@e> HVLSI 'echnolog%I> Mc?4ra0?5ill Second Edition? 1//-? 2?Amar mu9her3ee> HIntroduction to 7M,S and CM,S VLSI S%stem design Prentice 5all India?2000? 3?Fames $ Plummer> Michael $? $eal> Peter ?4riffin> HSilicon VLSI 'echnolog% fundamentals "ractice and ModelingI> Prentice 5all India?2000? &? 8ai Bai Chen>AVLSI 'echnolog%I CDC "ress> 2003 ,RLs 1? htt"E..000?n"tel?iitm?ac?in.#ideo?"h"Qsu+3ectIdR11*10)0/3 2. htt"E..000?authorstream?com.Presentation.7iteesh6-&)&06#lsi6technolog%6entertainment6""t6 "o0er"oint.

P)VLC+9 VERIL G PR GR*MMING *IM 'o ena+le the student to understand and 0rite the Verilog Programes <>ECTIVE 'o im"art 9no0ledge on $ifferent data t%"es $ifferent "rogramming methods Verilog s%nthesis ,5it I Di1ital desi15 Aith !erilo1 HDL = Hierarchical -odeli51 co5ce8ts $esign Flo0> 'rends in 5$L> $esign Methodologies> Modules> Instances> asic Conce"ts6 le<ical con#entions> $ata t%"es> S%stem tas9s and com"iler directi#es? ,5it B Modules a5d 8orts Module definitions> "ort declaration> connecting "orts> hierarchical name referencing?

LTPC $)+9

,5it $ Gate le!el a5d data6loA -odeli51 4ate le#elE Modeling using +asic> #erilog gate "rimiti#es> $ifferent timings6rise> fall> min> ma<> t%"ical $ataflo0E continuos assignments> dela% s"ecification> e<"ressions> o"erators and o"erands? ,5it 9 <eha!ioral Modeli51 Structured "rocedures> initial and al0a%s statements> +loc9ing and non +loc9ing statements> dela% control>e#ent control> conditional statement> multi0a% +ranching> loo"s> se=uential and "arrelel +loc9s ,5it : Lo1ic sy5thesis Aith !erilo1 HDL S%nthesis $esign flo0> #erilog s%nthesis> #erification 0ith gate le#el netlist> $esign "artition> se=uential circuit s%snthesis? T T*L. 9:3):CTutorialD ";+ PERI DS <E@ ND THE S@LL*<,S 4otchas from s%stem #erilog> D'L modeling of 4otchas> asics of 4otachas Programming RE'ERENCES. 1? HVerilog 5$LI +% Samir Palnit9ar> Sunmicro s%stems Press> Prentics 5all 2? 5dl Programming FundamentalsE Vhdl And Verilog: Series 6 $a#inci Engineering ; CHardco!er ( B++;H+)H+)D by 7a@eih M? otros ,RLs. 1? htt8.HHAAA.asic(Aorld.co-H!erilo1H!eritut.ht-l 2? htt8.HHAAA.ece.u-d.eduHcoursesHe5ee$:2aH!erilo1Itutorial.8d6

10

P)VLC+:*N*L G INTEGR*TED CIRC,IT DESIGN *IM 'o e<"ose the students to the fundamentals of Analog VLSI design <>ECTIVE 'o im"art 9no0ledge on asics of Analog VLSI Am"lifiers using M,S loads 7oise anal%sis in am"lifiers To u5dersta5d the *5alo1 VLSI

LTPC $)+9

,NIT I SINGLE ST*GE *MPLI'IERS 2 Common source stage> Source follo0er> Common gate stage> Cascode stage> Single ended and differential o"eration> asic differential "air> $ifferential "air 0ith M,S loads ,NIT II 'RE4,ENC@ RESP NSE *ND N ISE *N*L@SIS 2 Miller effect >Association of "oles 0ith nodes> fre=uenc% res"onse of common source stage> Source follo0ers> Common gate stage> Cascode stage> $ifferential "air> Statistical characteristics of noise> > noise in differential am"lifiers? ,NIT III PER*TI N*L *MPLI'IERS 2 Conce"t of negati#e feed+ac9> Effect of loading in feed+ac9 net0or9s> o"erational am"lifier "erformance "arameters> ,ne6stage ," Am"s> '0o6stage ," Am"s> In"ut range limitations> 4ain +oosting> sle0 rate> "o0er su""l% re3ection> noise in ," Am"s? ,NIT IV ST*<ILIT@ *ND 'RE4,ENC@ C MPENS*TI N 2 4eneral considerations> Multi"ole s%stems>Phase Margin> Fre=uenc% Com"ensation> Com"ensation of t0o stage ," Am"s> Sle0ing in t0o stage ," Am"s> ,ther com"ensation techni=ues? ,NIT V <I*SING CIRC,ITS 2 asic current mirrors> cascode current mirrors> acti#e current mirrors> #oltage references> su""l% inde"endent +iasing> tem"erature inde"endent references? <E@ ND THE S@LL*<,S. ). 7oise in single stage am"lifiers 2? P'A' current generation 3? Constant64m iasing RE'ERENCES. 1? eh@ad Da@a#i> H$esign of Analog CM,S Integrated CircuitsI> 'ata Mc4ra0 5ill> 2001 2? 8ille% M?C? Sansen> HAnalog design essentialsI> S"ringer> 200)? 3? 4re+ene> H i"olar and M,S Analog Integrated circuit designI> Fohn 8ile% ! sons>Inc?> 2003? &? Philli" E?Allen> $ouglasD?5ol+erg> HCM,S Analog Circuit $esignI> Second edition> ,<ford Cni#ersit% Press> 2002 ,RLs. 1? uha0e+?hartford?edu.ilumo9an0.Intro()*?""t 2? htt8.HHco(lear5.i5HsitesHde6aultH6ilesHcourses(8d6sHEE;)J(L).8d6 P)VLC+; VLSI DESIGN L*< LTPC + +B B 11

*IM 'o gi#e hands on e<"erience on Electronic $esign Automation 'ools for digital circuits? Also to learn Verilog "rogramming in detail <>ECTIVE At the end of this la+ session student 0ill understand 8riting 5$L codes 8or9ing on different Mentor 4ra"hics tools List o6 eK8eri-e5ts 1? 8rite 5$L code for half adder> full adder> MCP> $EMCP> encoder> decoder code and simulate and s%nthesis 2? 8rite 5$L code for s%nchronous and as%nchronous Fli" Flo"s and Counters and simulate and s%nthesis 3? Verif% the out"uts of a+o#e e<"eriment on SPAD'A7 9it &? $ra0 schematic for an in#erter and uni#ersal gates and simulate (? $ra0 la%out for a+o#e designs )? Perform $DC and LVS chec9 for the a+o#e designs using <E@ ND THE S@LL*<,S 1? Im"lementation of se=uence detection using FSM modeling? 2? Simulation of 7M,S and CM,S circuits for an% oolean e<"ression in SPICE?

12

SEMESTER II PBVLC+# DIGIT*L CM S VLSI DESIGN *IM. 'o ha#e the detail stud% of $igital CM,S design <>ECTIVE 'o im"art 9no0ledge on M,S de#ice modeling $iferente com+inational logic circuits Cloc9ing methods for se=uential circuits ,NIT I M S TR*NSIST R PRINCIPLES 2 M,S 'echnolog% and VLSI> Process "arameters and considerations for> M,S and CM,S> Electrical "ro"erties of CM,S circuits and $e#ice modeling? CM,S In#erter Scaling CM,S circuits> Scaling "rinci"les and fundamental limits? ,NIT II C M<IN*TI N*L L GIC CIRC,ITS 2 Pro"agation $ela%s> Stic9 diagram> La%out diagrams> E<am"les of com+inational logic design> ElmoreAs constant> $%namic Logic 4ates> Pass 'ransistor Logic> Po0er $issi"ation> Lo0 Po0er $esign "rinci"les? ,NIT III SE4,ENTI*L L GIC CIRC,ITS 2 Static and $%namic Latches and Degisters> 'iming Issues> Pi"elines> Cloc9ing strategies> Memor% Architectures> and Memor% control circuits> S%nchronous and As%nchronous $esign? ,NIT IV DESIGNING *RITHMETIC <,ILDING <L CFS $ata "ath circuits> Architectures for Adders> Accumulators> Multi"liers> 'radeoffs 2 arrel Shifters> S"eed and Area L T PC $ ) +9

,NIT V IMPLEMENT*TI N STR*TEGIES 2 Full Custom and Semicustom $esign> Standard Cell design and cell li+raries> FP4A +uilding +loc9 architectures> FP4A interconnect routing "rocedures> enchmar9 Circuits> Case Studies? T T*L. 9:3):CTutorialD" PERI DS <E@ ND THE S@LL*<,S. 'he Acti#e and Pol% la%ers Electrostatic $ischarge "rotection RE'ERENCES 1? Fan Da+ae%> Anantha Chandra9asan> 7i9olic> H $igital Integrated CircuitsE A $esign Pers"ecti#eI? Second Edition> Fe+ 2003> Prentice 5all of India? 2? 7?8este> B? Eshraghian> H Princi"les of CM,S VLSI $esignI? Second Edition> 1//3 Addision 8esle%> 3? &? M F Smith> HA""lication S"ecific Integrated CircuitsI> Addisson 8esle%> 1//* (? Anantha Chandra9asan> 8?F> o0hill and F?Fo<> H$esign of 5igh Performance Micro"rocessor CircuitsI> Fohn 8ile%> 2000? ,RLs. 1?htt"E..000?"d<?edu.nanogrou".sites.000?"d<?edu?nanogrou".files.2013LCom+inationalLandLSe=uenti alLLogicLCircuitsL0?"df 2? htt"E..000?ami?ac?u9.courses.ami&&0*Ldicdes.u03.

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PBVLC+J TESTING

' VLSI CIRC,ITS

LTPC $)+9

*IM 'o ma9e the student to understand the need for testing> difficult% in testing> and different methods of testing <>ECTIVES 'o im"art 9no0ledge on Various faults and fault models 'echni=ues for testing of com+inational circuits> se=uential circuits> memor% and em+edded DAMs ,NIT I 2

Introduction to 'esting 6 Faults in digital circuits 6 Modeling of faults 6 Logical Fault Models 6 Fault detection 6 Fault location 6 Fault dominance 6 Logic Simulation 6 '%"es of simulation 6 $ela% models 6 4ate le#el E#ent6dri#en simulation? ,NIT II 2

'est generation for com+inational logic circuits 6 'esta+le com+inational logic circuit design 6 'est generation for se=uential circuits 6 design of testa+le se=uential circuits? ,NIT III 2

$esign for 'esta+ilit% 6 Ad6hoc design 6 4eneric scan +ased design 6 Classical scan +ased design 6 S%stem le#el $F' a""roaches? ,NIT IV 2

uilt6In Self 'est 6 'est "attern generation for IS' 6 Circular IS' 6 IS' Architectures 6 'esta+le Memor% $esign 6 'est algorithms 6 'est generation for Em+edded DAMs ,NIT V 2

Logic Le#el $iagnosis 6 $iagnosis +% CC' reduction 6 Fault $iagnosis for Com+inational Circuits 6 Self6 chec9ing design 6 S%stem Le#el $iagnosis? T T*L. 9:3):CTutorialD " ;+ 8eriods <E@ ND THE S@LL*<,S. 'esting Em+edded A""lications RE'ERENCES. 1? M? A+ramo#ici> M?A? reuer and A?$? Friedman> S$igital S%stems and 'esta+le $esignS Faico Pu+lishing 5ouse> 2002? 2? P?B? Lala> S$igital Circuit 'esting and 'esta+ilit%S> Academic Press> 2002? 3? M?L? ushnell and V?$? Agra0al> SEssentials of Electronic 'esting for $igital> Memor% and Mi<ed6Signal VLSI CircuitsS> Blu0ar Academic Pu+lishers> 2002? &? A?L? Crouch> S$esign for 'est for $igital ICOs and Em+edded Core S%stemsS> Prentice 5all International> 2002? ,RLs. 1? htt"E..000?ece?uc?edu.M03one.Com+6'4?"df 2? 000?ece?mcgill?ca.M@@ilic.)&/.hh?""t

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PBVLC+2 VLSI SIGN*L PR CESSING *IM 'o stud% the signal "rocessing in VLSI "ros"ecti#e <>ECTIVE 'o im"art 9no0ledge on Programming "rocessor $ifferent con#olution techni=ues Arithmetic architectures

LTPC $+ + $

,NIT I INTR D,CTI N T DSP S@STEMS 2 Introduction 'o $SP S%stems 6'%"ical $SP algorithmsT Iteration ound 2 data flo0 gra"h re"resentations> loo" +ound and iteration +ound> Longest "ath Matri< algorithmT Pi"elining and "arallel "rocessing 2 Pi"elining of FID digital filters> "arallel "rocessing> "i"elining and "arallel "rocessing for lo0 "o0er? ,NIT II RETIMING 2 Detiming 6 definitions and "ro"ertiesT Cnfolding 2 an algorithm for Cnfolding> "ro"erties of unfolding> sam"le "eriod reduction and "arallel "rocessing a""licationT Algorithmic strength reduction in filters and transforms 2 26"arallel FID filter> 26"arallel fast FID filter> $C' algorithm architecture transformation> "arallel architectures for ran96order filters> ,dd6 E#en Merge6 Sort architecture> "arallel ran96order filters? ,NIT III '*ST C NV L,TI N 2 Fast con#olution 2 Coo96'oom algorithm> modified Coo96'oo9 algorithmT Pi"elined and "arallel recursi#e and ada"ti#e filters 2 inefficient.efficient single channel interlea#ing> Loo96 Ahead "i"elining in first6 order IID filters> Loo96Ahead "i"elining 0ith "o0er6of6t0o decom"osition> Clustered Loo96Ahead "i"elining> "arallel "rocessing of IID filters> com+ined "i"elining and "arallel "rocessing of IID filters> "i"elined ada"ti#e digital filters> rela<ed loo96ahead> "i"elined LMS ada"ti#e filter? ,NIT IV <IT(LEVEL *RITHMETIC *RCHITECT,RES 2 Scaling and roundoff noise6 scaling o"eration> roundoff noise> state #aria+le descri"tion of digital filters> scaling and roundoff noise com"utation> roundoff noise in "i"elined first6order filtersT it6Le#el Arithmetic Architectures6 "arallel multi"liers 0ith sign e<tension> "arallel carr%6ri""le arra% multi"liers> "arallel carr%6sa#e multi"lier> &< & +it augh68oole% carr%6sa#e multi"lication ta+ular form and im"lementation> design of L%onAs +it6serial multi"liers using 5ornerAs rule> +it6serial FID filter> CS$ re"resentation> CS$ multi"lication using 5ornerAs rule for "recision im"ro#ement? ,NIT V PR GR*MMING DIGIT*L SIGN*L PR CESS RS 2

7umerical Strength Deduction 2 su+e<"ression elimination> multi"le constant multi"lications> iterati#e matching? Linear transformationsT S%nchronous> 8a#e and as%nchronous "i"elining6 s%nchronous "i"elining and cloc9ing st%les> cloc9 s9e0 in edge6triggered single6"hase cloc9ing> t0o6"hase cloc9ing> 0a#e "i"elining> as%nchronous "i"elining +undled data #ersus dual rail "rotocolT Programming $igital Signal Processors 2 general architecture 0ith im"ortant featuresT Lo0 "o0er $esign 2 needs for lo0 "o0er VLSI chi"s> charging and discharging ca"acitance> short6circuit current of an in#erter> CM,S lea9age current> +asic "rinci"les of lo0 "o0er design? T T*L. 9: PERI DS <E@ ND THE S@LL*<,S Folding and unfolding> S%stolic architecture $esign> $igital lattice Filter Structures 15

RE'ERENCES ). Feshab F.Parhi/ L VLSI Di1ital Si15al Processi51 syste-s/ Desi15 a5d i-8le-e5tatio5 L/ Giley/ I5ter Scie5ce/ )222. 2? 4ar% Gea"> UPractical Lo0 Po0er $igital VLSI $esign>A Blu0er Academic Pu+lishers> 1//-? 3? Mohammed Ismail and 'erri Fie@> HAnalog VLSI Signal and Information Processing S> Mc 4ra065ill> 1//&? &? S.@. Fu51/ H.>. Ghite House/ T. Failath/ MVLSI a5d Moder5 Si15al Processi51 L/ Pre5tice Hall/ )2J:? (? Fose E? France> Gannis 'si#idis> S $esign of Analog 6 $igital VLSI Circuits for 'elecommunication and Signal Processing S> Prentice 5all> 1//&? ,RLs. 1? htt"E..000?ece?umn?edu.users."arhi.SLI$ES.cha"13?"df 2? 000?ece?umn?edu.grou"s.dd".inde<?html

16

PBVLC)+ *SIC DESIGN *IM 'o stud% the $esign of ASIC> logic cells of #arious su""liers

LTPC $)+9

<>ECTIVES 'o im"art 9no0ledge on CM,S and ASIC li+rar% design> 'he t%"es of "rogramming> architecture of logic cells and I., cells> $ifferent techni=ues of interconnection? 'o understand a+out "artitioning> floor "lanning> "lacement and routing techni=ues? ,NIT IINTR D,CTI N T *SICS/ CM S L GIC *ND *SIC LI<R*R@ DESIGN 2

'%"es of ASICs 6 $esign flo0 6 CM,S transistors CM,S $esign rules 6 Com+inational Logic Cell 2 Se=uential logic cell 6 $ata "ath logic cell 6 'ransistors as Desistors 6 'ransistor Parasitic Ca"acitance6 Logical effort 2Li+rar% cell design 6 Li+rar% architecture? ,NIT II PR GR*MM*<LE *SICS/ PR GR*MM*<LE *SIC L GIC CELLS *ND PR GR*MM*<LE *SIC IH CELLS 2 Anti fuse 6 static DAM 6 EPD,M and EEPD,M technolog% 6 PDEP +enchmar9s 6 Actel AC' 6 Pilin< LCA 2Altera FLEP 6 Altera MAP $C ! AC in"uts and out"uts 6 Cloc9 ! Po0er in"uts 6 Pilin< I., +loc9s? ,NIT III PR GR*MM*<LE *SIC INTERC NNECT/ PR GR*MM*<LE *SIC DESIGN S 'TG*RE *ND L G LEVEL DESIGN ENTR@ 2 Actel AC' 6Pilin< LCA 6 Pilin< EPL$> S"artran IIIE :architecture>interfacing; 6 Altera MAP (000 and *000 6 Altera MAP /000 6 Altera FLEP 2 Altera C%clone II:architecture > interfacing ; 2$esign s%stems 6 Logic S%nthesis 6 5alf gate ASIC 6Schematic entr% 6 Lo0 le#el design language 6 PLA tools 6E$IF6 CFI design re"resentation? ,NIT IV *SIC C NSTR,CTI N/ 'L R PL*NNING/ PL*CEMENT *ND R ,TING 2 S%stem "artition 6 FP4A "artitioning 6 "artitioning methods 6 floor "lanning 6 "lacement 6 "h%sical design flo0 2glo+al routing 6 detailed routing 2 s"ecial routing 6 circuit e<traction 6 $DC? ,NIT V L GIC S@NTHESIS/ SIM,L*TI N *ND TESTING 2 asic conce"ts6 identifiers6 gate "rimiti#es> gate dela%s> o"erators> timing controls> "rocedural assignments conditional statements> $ata flo0 and D'L> structural gate le#el s0itch le#el modeling> $esign hierarchies> eha#ioral and D'L modeling> 'est +enches> Structural gate le#el descri"tion of decoder> e=ualit% detector> com"arator> "riorit% encoder> half adder> full adder> Di""le carr% adder> $ latch and $ fli" flo"? $ifferent counters and FSM modeling T T*L. 9:3):CTutorialD " ;+ 8eriods <E@ ND THE S@LL*<,S. FP4A Fa+rics> Permanentl% "rogrammed FP4A

17

RE'ERENCES. 11 M?F?S ?Smith> SA""lication S"ecific Integrated Circuits> Addison 68esle% Longman Inc?> 1//*? 11 Far@ad 7e9oogar and Farana9 7e9oogar> From ASICs to S,CsE A Practical A""roach> Prentice 5all P'D> 2003?

11

8a%ne 8olf> 'PG*(<ased Syste- Desi15> Prentice 5all P'D> 200&? 11 D? Da3suman> S%stem6on6a6Chi" $esign and 'est? Santa Clara> CAE Artech 5ouse Pu+lishers> 2000? 11 F? 7e9oogar? 'iming Verification of A""lication6S"ecific Integrated . Circuits :ASICs;..Prentice 5all P'D> 1///? 11 Pilin<> Altera document should +e gi#en 11 F? has9erE Verilog 5$L "rimer> S "u+lication>2001 11 Ciletti Ad#anced $igital $esign 0ith the Verilog 5$L> Prentice 5all of India> 2003 CDLsE 1? htt"E..000?ece?ncsu?edu.asic.tutorials.tutor1.tutor1?"df 2? htt"E..000?asic60orld?com.

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PBVLC)) VLSI ' R GIRELESS C MM,NIC*TI N LTPC $++ $ *IM 'o stud% the 0ireless communication in VLSI "ers"ecti#e <>ECTIVE 'o im"art 9no0ledge on $ata con#erters Coding algorithms and techni=ues ,NIT I *N*L G T DIGIT*L C NVERSI N 2 Performance metrics for Analog6to6digital con#erters> sam"ling> +and6"ass sam"ling> =uanti@ation> '%"es of Analog6to6digital con#erters> Sigma $elta Analog6to6digital con#erters? ,NIT II C DING THE R@ *LG RITHMS *ND *RCHITECT,RE 2 Con#olution codes> trellis diagram> #iter+i algorithm> soft in"ut decoding> soft out"ut decoding> 'ur+o codes> L$PC coding> concatenated con#olution codes> 0eight distri+ution> S"ace6'ime codes> s"atial channels> "erformance measure> ,rthogonal s"ace6time +loc9 codes> s"atial multi"le<ing? ,NIT III TR*NSCIEVER *RCHITECT,RE *ND ISS,ES 2 Decei#er Architectures> Su"erheterod%ne recei#er> Image re3ection recei#er>65artle% and 8ea#er> Jero IF recei#er> Lo0 IF recei#er> 'ransmitter architecture> Su"erheterod%ne transmitter> $irect u" transmitter> '0o6ste"6u" transmitter> 'ransceie#er architectures for modern 0ireless s%stems> Case stud%? ,NIT IV 'DM S@S@TEM 2 Princi"le> "ro"agation characteristics>"rinci"le> mathematical model> ,F$M +ase+and signal "rocessing>Decei#er design> Automatic gain control and $C offset com"ensation> codesign of Automatic gain control and timing s%nchroni@ation> codesign of filtering and timing s%nchroni@ation> 'ransmit chain setu"? ,NIT V *N*L G IMP*IRMENT *ND ISS,ES 2 Decei#er sensiti#it% and noise figure> $C offsets> L, lea9age> Decei#er interferers and intermodulation distortion> Image re3ection> Kuadrature +alance and relation to Image re3ection> relation to EVM> Pea9 to a#erage "o0er ratio > Local oscillator "ulling in PLL> effect of "hase noise in PLL> Effect of "hase noise on ,F$M s%stems> Effect of fre=uenc% errors on ,F$M s%stems? T T*L. 9: PERI DS <E@ ND S@LL*<,S Lo0 7oise am"lifiers> acti#e ! "assi#e Mi<ers> Fre=uenc% s%nthesi@ers RE'ERENCES 11 Pui6In Ma9> Seng6Pan C> Dui Paulo Martins> HAnalog6+ase+and architectures and Circuits for multistandard and lo0 #oltage8ireless transcei#ersI> s"ringer> 200*? 11 Emad 7? Farag> Mohamed I? Elmasr%> HMi<ed signal VLSI 8ireless design Circuits and s%stemsI> Blu0er Academic Pu+lishers> 2002? 11 Andre 7eu+auer> Furgen Freuden+erger> Vol9er Buhn>I Coding theor%> Algorithms> Architectures and A""licationsI> Fohn 8ile% ! Sons>200*? 11 8olfgang E+erle> H8ireless 'ranscei#er S%stems $esignI>S"ringer> 200-? CDLsE 1? htt"E..000?scri+d?com.doc./0)/)22).Coding6'heor%6Algorithms6Architectures6And6A""lications6Andre6 7eu+auer6Et6Al6200* 2? htt"E..h%"er"h%sics?"h%6astr?gsu?edu.h+ase.electronic.adc?html

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PBVLC)B EM<EDDED S@STEMS *ND *DV*NCED VLSI CIRC,IT L*< *IM

LTPC + + B B

'o ma9e the students to 0or9 on different tools and to de#elo" a""lications on em+edded Micro controller? <>ECTIVES At the end of this la+ session student 0ill understand 8or9ing on Pilin< 8or9ing on 'anner E$A 8or9ing on PIC controller List o6 EK8eri-e5ts 1? Im"lementation of Ele#ator controller using PIC controller? 2? Im"lementation of Alarm cloc9 controller using PIC micro controller? 3? Im"lementation of tem"erature sensor using PIC controller &? 'iming simulation of an% se=uential circuit 0ith and 0ithout changing the user constraints? (? Po0er measurement> timing anal%sis for an% one adder and multi"lier )? Perform uilt in Self 'est : IS'; for a design? <E@ ND THE S@LL*<,S 1? $esign and Im"lementation of C,D$IC algorithm using FP4A 2? $esign of - +it sliced "rocessor

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ELECTIVE % I PEVLC): VLSI S@STEM DESIGN LTPC $ + +$ *IM 'o introduces #arious su+s%stems of a s%stem design> their control logic> #erification and testing? <>ECTIVES 'o im"art 9no0ledge on CM,S su+s%stem deign $ifferent t%"es of memor% structure asic of s%stem Verilog ,NIT I CM S S,<S@STEM DESIGN 2 inar%

Introduction 2 $ata "ath o"erations 2Parit% generator 2 Com"arators 2 Jero.one detectors6 counters 2 oolean o"erations 2 Multi"lication 2 Shifters? ,NIT II MEM R@ ELEMENTS 2

Dead.0rite memor%E 6 DAM6 Degister files 2 FIF,s> LIF,s> SIP,s6 Serial Access memor%? Dead onl% memor% 2 Content Addressa+le memor% 6 Finite 2 State Machine 2 FSM $esign "rocedure 2 Control Logic im"lementation E6 PLA Control im"lementation 2 D,M Control im"lementation 2 Multile#el logic 2 An e<am"le of control logic im"lementation? ,NIT III INTR D,CTI N T S@STEM VERIL G 2

S%stem Verilog origins> S%stem Verilog standards> enhancement for hard0are design> ad#antages of s%stem Verilog? ,NIT IV LITER*L V*L,ES *ND D*T* T@PES 2

Enhanced literal #alue assignments> e<ternal com"ilation unit declarations> simulation time units and "recision> s%stem Verilog data t%"es> t%"e casting? ,NIT V S@STEM VERIL G *RR*@S/ STR,CT,RES *ND ,NI NS 2

Assigning #alues to structures> "ac9ed and un"ac9ed structures> arra%s> structures and unions> asic "rogramming in S%stem Verilog T T*L. 9: 8eriods <E@ ND THE S@LL*<,S 1? CM,S chi" design o"tions 2? CM,S su+s%stem design6data "ath o"erations RE'ERENCES. 1? 7?5?E?8este and B?Eshraghian> H Princi"les of CM,S VLSI $esignI> 2 nd Edition 6 Addition 8esle%>1//3? 2? Fan ?M?Da+ae%> H$igital Integrated Circuits a design "ers"ecti#eI > P5I 1 st Editi 3? S%stem Verilog For $esign a 4uide % s%stem #erilog for hard0are modeling +% staurt southerland>Simon $a#idman>Peter Fla9e> Blu0er Academic Pu+lishers>200& ,RLs htt"E..000?9itece?com.0"6content.u"loads.2011.0/.CM,S6VLSI6Part6 1?"df htt"E..0e+?e0u?edu.grou"s.technolog%.Claudio.ee&30.Lectures.L16"rint?"df PEVLC); S LID ST*TE DEVICE M DELING *ND SIM,L*TI N LTPC $++$ 21

*IM 'o introduce a +asic 9no0ledge of semiconductor "h%sics> transistor modeling> o"to electronic de#ice modeling and de#ice "arameter measurement? <>ECTIVES 'o im"art 9no0ledge on VSemiconductor "h%sics> uni"olar and +i"olar de#ice modeling ,NIT I <*SIC SEMIC ND,CT R PH@SICS 2

Kuantum Mechanical Conce"ts> Carrier Concentration> 'rans"ort E=uation and6ga"> Mo+ilit% and Desisti#it%> Carrier 4eneration and Decom+ination> A#alanche Process> 7oise Sources? ,NIT II <IP L*R DEVICE M DELING 2

In3ection and 'rans"ort Model> Continuit% E=uation> $iode Small Signal and Large Signal :Change Control Model;> 'ransistor ModelsE E++er 2 Molls Model and 4ummel Port Model> Me<tram model> SPICE modeling tem"erature and area effects? ,NIT III M S'ET M DELING 2

Introduction Interior La%er> M,S 'ransistor Current> 'hreshold Voltage> 'em"erature Short Channel and 7arro0 8idth Effect> Models for Enhancement> $e"letion '%"e M,SFE'> CM,S Models in SPICE and stud% of 'anner tool? ,NIT IV P*R*METER ME*S,REMENT 2

4eneral Methods> S"ecific i"olar Measurement> $e"letion Ca"acitance> Series Desistances> Earl% Effect> 4ummel Plots> M,SFE'E Long and Short Channel Parameters> Statistical Modeling of io"olar and M,S 'ransistors? ,NIT V PT ELECTR NIC DEVICE M DELING 2

Static and $%namic Models> Date E=uations> 7umerical 'echni=ue> E=ui#alent Circuits> Modeling of LE$s> Laser $iode and Photo detectors> T T*L. 9: Periods <E@ ND THE S@LL*<,S M,SFE' CS small signal am"lifier> modeling of +od% effect> M,S FE' internal ca"acitance and high fre=uenc% model RE'ERENCES 1? Phili" E? Allen> $ouglas D?5o+erg> HCM,S Analog Circuit $esignI Second Edition> ,<ford Press 6 2002? 2? Biat Seng Geo> Samir S?Dofail> 8ang6Ling 4o+> HCM,S . iCM,S CLSI 6 Lo0 Voltage> lo0 Po0erI> Person education> Lo0 "rice edition> 2003? 3? S?M?S@e HSemiconductor $e#ices 6 Ph%sics and 'echnolog%I> Fohn 8ile% and sons> 1/-(? &? 4iuse""e Masso+rio and Paolo Antogentti> HSemiconductor $e#ice Modeling 0ith SPICEI Second Edition> Mc4ra065ill Inc> 7e0 Gor9> 1//3? ,RLs. 1? htt"E..000?electronics6tutorials?0s.diode.diodeL1?html 2? htt"E..ecee?colorado?edu.M+art.+oo9.+oo9.cha"ter&.ch&L)?htm PEVLC)# EM<EDDED S@STEM DESIGN LTPC $+ + $ *IM

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'o gi#e e<"osure to em+edded architecture> stud% of em+edded "rocessors> net0or9s of em+edded s%stems and real time characteristics of em+edded s%stems? <>ECTIVE 'o im"art 9no0ledge on Em+edded com"uters architecture CS structure organi@ation of different "rocessors ,NIT I EM<EDDED *RCHITECT,RE 2

Em+edded Com"uters> Characteristics of Em+edded Com"uting A""lications> Challenges in Em+edded Com"uting s%stem design> em+edded s%stem design "rocess6 De=uirements> S"ecification> Architectural $esign> $esigning 5ard0are and Soft0are Com"onents> S%stem Integration> Formalism for S%stem 6$esign6 Structural $escri"tion> eha#ioral $escri"tion> and $esign E<am"leE Model 'rain Controller ,NIT II EM<EDDED PR CESS R *ND C MP,TING PL*T' RM 2

ADM "rocessor6 "rocessor and memor% organi@ation> $ata o"erations> Flo0 of Control> S5ADC "rocessor6 Memor% organi@ation> $ata o"erations> Flo0 of Control> "arallelism 0ith instructions> CPC us configuration> ADM us> S5ADC us> Memor% de#ices> In"ut.out"ut de#ices> Com"onent interfacing> designing 0ith micro"rocessor de#elo"ment and de+ugging> $esign E<am"le E Alarm Cloc9? ,NIT III S@STEM DESIGN TECHNI4,ES 2

$esign Methodologies> De=uirement Anal%sis> S"ecification> S%stem Anal%sis and Architecture $esign> Kualit% Assurance> $esign E<am"leE 'ele"hone P P6 S%stem Architecture> In9 3et "rinter6 5ard0are $esign and Soft0are $esign> Personal $igital Assistants> Set6to" o<es? ,NIT IV PIC MICR (C NTR LLER *ND INTER'*CING 2

Introduction> CPC architecture> registers> instruction sets addressing modes loo" timing> timers interru"ts> interru"ts> timing I.o e<"ansion> I 2 C +us o"eration serial EPD,M> analog to digital con#erter> CAD'6 aud Date6$ata 5andling6initiali@ation> s"ecial features6 serial "rogramming 2 "arallel sla#e "ort? ,NIT V EM<EDDED MICR C MP,TER S@STEMS 2

Motorola MC)-511 famil% architecture registers> addressing modes "rograms> interfacing methods "arallel i.o interface> "arallel "ort interface> memor% interfacing? 5igh s"eed i.o interfacing> interru"ts 2 interru"t ser#ice routine6features of interru"ts 2 interru"t #ector and "riorit%> timing generation and measurements> in"ut ca"ture> out"ut com"are> fre=uenc% measurement> serial i.o de#ices Ds232> Ds&-(6 Analog interfacing> a""lications? T T*L. 9: 8eriods

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<E@ ND THE S@LL*<,S Micro"rocessor interfacing6I., addressing> memor% ma""ed I., and standard I., RE'ERENCES 1? 8a%ne 8olf/.Com"uters as Com"onentsE Princi"les of Em+edded Com"uting S%stem $esign> Morgan Baufman Pu+lishers> 2001 2. Fohn Peat man> H$esign 0ith micro6controllerI> Pearson education Asia> 1//-? 3? Fonarthan 8 Val#ano roo9s.code> HEm+edded micro com"uter s%stems> Deal time interfacingI> 'homson learning 2001? &? Fran9 Vahid and 'on% 4i#argi> Em+edded S%stem $esignE A Cnified 5ard0are.Soft0are Introduction>s> Fohn 8ile% ! Sons> 2000? (? PIC microcontrollerE an introduction to soft0are and hard0are interfacing % 5an68a% 5uang CDLsE 1? htt"E..000?unro+otica?com."u+lic.li+ro-?"df

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PEVLC)J DSP PR CESS R *RCHITECT,RE *ND PR GR*MMING *IM. 'o learn a+out "rogramma+le $SPs and architecture <>ECTIVES 'o im"art 9no0ledge on VLI8 architecture '%"ical stud% a+out C(P.C3P "rocessors> A$SP "rocessors and some ad#anced $SPs useful for real time a""lications? ,NIT I ',ND*MENT*LS ' PR GR*MM*<LE DSPS 2

LTPC $++ $

Multi"lier and Multi"lier accumulator 2 Modified us Structures and Memor% access in P6$SPs 2 Multi"le access memor% 2 Multi6"ort memor% 2 VLI8 architecture6 Pi"elining 2 S"ecial Addressing modes in P6 $SPs 2 ,n chi" Peri"herals? ,NIT II TMS$B+C:E PR CESS R 2

Architecture 2 Assem+l% language s%nta< 6 Addressing modes 2 Assem+l% language Instructions 6 Pi"eline structure> ,"eration 2 loc9 $iagram of $SP starter 9it 2 A""lication Programs for "rocessing real time signals? ,NIT III TMS$B+C$E PR CESS R 2

Architecture 2 $ata formats 6 Addressing modes 2 4rou"s of addressing modes6 Instruction sets 6 ,"eration 2 loc9 $iagram of $SP starter 9it 2 A""lication Programs for "rocessing real time signals 2 4enerating and finding the sum of series> Con#olution of t0o se=uences> Filter design ,NIT IV *DSP PR CESS RS Architecture of A$SP621PP and A$SP6210PP series of $SP "rocessors6 Addressing modes and assem+l% language instructions 2 A""lication "rograms 2Filter design> FF' calculation? ,NIT V *DV*NCED PR CESS RS 2 2

Architecture of 'MS320C(&PE Pi"e line o"eration> Code Com"oser studio 6 Architecture of 'MS320C)P 6 Architecture of Motorola $SP()3PP 2 Com"arison of the features of $SP famil% "rocessors? T T*L. 9: PERI DS <E@ ND THE S@LL*<,S Face reorgani@ation using SIM$> Im"lementation of s"eech reorgani@ation> 5armon% "rocessor> RE'ERENCES ?Ven9ataramani and M? has9ar> H$igital Signal Processors 2 Architecture> Programming and A""licationsI 2 'ata Mc4ra0 2 5ill Pu+lishing Com"an% Limited? 7e0 $elhi> 2003? 2? Cser guides 'e<as Instrumentation> Analog $e#ices> Motorola? CDLsE 1? htt"E..000?datasheetarchi#e?com.'MS320C(<W'C',DIALS6datasheet?html 2? htt"sE..000?dro"+o<?com.s.*0-u=3u3f33==t#.$SP6Processor?"df PEVLC)2 'PG* <*SED SIGN*L PR CESSING LTPC $++$ 25 1?

*IM 'o ena+le the students to learn the efiiceint hard0are architectures for #arious signal "rocessing a""lications? <>ECTIVES 'o im"art 9no0ledge on S"eech coding and standards Multirate signal "rocessing ,NIT I M,LTIR*TE SIGN*L PR CESSING 2 $ecimation and Inter"olation> S"ectrum of decimated and inter"olated signals> Pol%"hase decom"osition of FID filters and its a""lications to multi6rate $SP> Sam"ling rate con#erters Su+6+and encoder ,NIT II 'ILTER <*NFS 2 Cniform filter +an9? $irect and $F' a""roaches? Introduction to A$SL Modem> $iscrete multi6tone modulation and its reali@ation using $F'? KMF> Com"utation of $8' using filter +an9s ,NIT III DD'S 2 D,M LC' a""roach> S"urious signals 3itter? Com"utation of s"ecial functions using C,D$IC> Vector and rotation mode of C,D$IC> C,D$IC architectures ,NIT IV <L CF DI*GR*M ' * S 'TG*RE R*DI 2 $igital do0n con#erters and demodulators Cni#ersal modulator and demodulator using C,D$IC> Incoherent demodulation 6 digital a""roach for I and K generation> s"ecial sam"ling schemes? CIC filters? Desidue num+er s%stem and high s"eed filters using D7S? $o0n con#ersion using discrete 5il+ert transform? Cnder sam"ling recei#ers> Coherent demodulation schemes ,NIT V SPEECH C DING *ND ST*ND*RDS 2 Models of #ocal tract> S"eech coding using linear "rediction> CELP coder> an o#er#ie0 of 0a#eform coding> Vocoders> Vocoder attri+utes? loc9 diagrams of encoders and decoders of 4*23?1> 4*2)> 4*2*> 4*2- and 4*2/? T T*L. 9: 8eriods <E@ ND THE S@LL*<,S 1? $SP s%stem definitions 2? $SP transforms 3? $ifferent filter structures RE'ERENCES 1? Me%er?C?> aese> $igital Signal Processing 0ith FP4As> S"ringer> 2001? 2? Deed? F 5?> Soft0are Dadio> Pearson> 2002? 3? Mitra?S?B?> $igital Signal "rocessing> Mc4ra05ill> 1//-? &? Besha+ B?Parhi> HVLSI $igital Signal Processing s%stems> $esign and im"lementationI> 8ile%> Inter Science> 1/// ,RLs. 1? 000?cadence?com.rl.resources.0hiteL"a"ers.f"gaL0"?"df 2? htt"E..000?eee?h9u?h9.M0or93220.S"eechN20codingN206N20standards?"df

ELECTIVE II PEVLCB+ C MP,TER *IDED DESIGN ' R VLSI *IM

LTPC $++$

26

'o ma9e the students to understand the "h%sical design of a chi" <>ECTIVES 'o im"art 9no0ledge on $ifferent floor "lanning method $ifferent routing algorithms ,NIT I <*SIC *LG RITHMS *ND D*T* STR,CT,RES 2 $ata Structures and asic Algorithms 2 Algorithmic 4ra"h 'heor% and Com"utational com"le<it% 2 'racta+le and Intracta+le "ro+lems 6 4eneral Pur"ose Methods for Com+inational ,"timi@ation? ,NIT II P*RTITI NING % 'L R PL*NNING % PL*CEMENT = R ,TING *LG RITHMS 2 Partitioning 2 "ro+lem formulation 2 classification of "artitioning algorithms 2 grou" migration algorithms 2 simulated annealing and e#olution 2 "erformance dri#en "artitioning 6 floor "lanning and "in assignment 2 "ro+lem formulation 2 classification of floor "lanning algorithms 2 classification of "in assignment algorithms 2 "lacement 2 "ro+lem formulation 2 classification of "lacement algorithms 2 simulation +ased "lacement 2 "artitioning +ased "lacement 2 "erformance dri#en "lacement 2 routing 2 glo+al routing 2 "ro+lem formulation 2 classification of glo+al routing algorithms 2 detailed routing 2 "ro+lem formulation 2 classification of detailed routing algorithms? ,NIT III SIM,L*TI N/ L GIC S@NTHESIS = VERI'IC*TI N 2 Simulation 2 $ifferent le#els of simulation 6 Logic s%nthesis ! Verification 2 +asic issues in com+inational logic s%nthesis 2 +inar% decision diagrams 6 D, $$ "rinci"les 2 im"lementation and construction 2 mani"ulation 2 #aria+le ordering 2a""lications to #erification and com+inatorial o"timi@ation? ,NIT IV HIGH LEVEL S@NTHESIS = C MP*CTI N 2 5ard0are models for high le#el s%nthesis % internal re"resentation of the in"ut algorithm 2 allocation> assignment and scheduling 6 Com"action 2 "ro+lem formulation 2 classification of com"action algorithms 2 one dimensional com"action 2 one and a half dimensional com"action 2 t0o dimensional com"action 2 hierarchical com"action 2 recent trends in com"action? ,NIT V PH@SIC*L DESIGN *,T M*TI N ' 'PG*S = MCMS 2 Ph%sical $esign Automation of FP4As 2 FP4A technologies 2 "h%sical design c%cle for FP4As 2 "artitioning 2 routing 6 Ph%sical design automation of MCMS 2 MCM technologies 2 MCM Ph%sical design c%cle 2 "artitioning 2 "lacement 2 routing 6V5$L 6 Verilog 6 im"lementation of sim"le circuits using V5$L and Verilog? T T*L. 9: 8eriods <E@ ND S@SLL*<,S 1? Im"erati#e Programming 2? $eclarati#e Programming RE'ERENCES 1?7?A?Sher0ani> HAlgorithms for VLSI Ph%sical $esign AutomationI> 3 rd Edition> Blu0er Academic> 1///? 2? S?5?4ere@> HAlgorithms for VLSI $esign AutomationI> Fohn 8ile%> 1//-? CDLsE 1? htt"E..n"tel?iitm?ac?in.courses.II'6MA$DAS.CA$LforLVLSIL$esignLI.inde<?"h" 2? htt"E..000?ece?gatech?edu.research.%ohdl.Courses.ECE&-/&.lec.intro?"df PEVLCB) PH@SIC*L DESIGN ' VLSI CIRC,ITS LTPC $++$

*IM 'o stud% a+out different techni=ues for "lacement and routing in "h%sical design of VLSI circuits? <>ECTIVE 'o learn a+out "erformance issues in circuit la%out> cell generation and com"action? 27

,NIT I INTR D,CTI N T VLSI TECHN L G@ 2 La%out Dules6Circuit a+straction Cell generation using "rogramma+le logic arra% transistor chaining> 8ein erger arra%s and gate matrices6la%out of standard cells gate arra%s and sea of gates> field "rogramma+le gate arra%:FP4A;6la%out methodologies6Pac9aging6Com"utational Com"le<it%6Algorithmic Paradigms ,NIT II PL*CEMENT ,SING T P(D GN *PPR *CH 2 PartitioningE A""ro<imation of 5%"er 4ra"hs 0ith 4ra"hs> Bernighan6Lin 5euristic6 Datio cut6 "artition 0ith ca"acit% and i.o constraints? Floor "lanningE Dectangular dual floor "lanning6 hierarchical a""roach6 simulated annealing6 Floor "lan si@ing6 PlacementE Cost function6 force directed method6 "lacement +% simulated annealing6 "artitioning "lacement6 module "lacement on a resisti#e net0or9 2 regular "lacement6 linear "lacement? ,NIT III R ,TING ,SING T P D GN *PPR *CH 2 FundamentalsE Ma@e Dunning6 line searching6 Steiner trees 4lo+al DoutingE Se=uential A""roaches6 hierarchical a""roaches6 multi commodit% flo0 +ased techni=ues6 Dandomi@ed Douting6 ,ne Ste" a""roach6 Integer Linear Programming $etailed DoutingE Channel Douting6 S0itch +o< routing? Douting in FP4AE Arra% +ased FP4A6 Do0 +ased FP4As ,NIT IV PER' RM*NCE ISS,ES IN CIRC,IT L*@ ,T 2 $ela% ModelsE 4ate $ela% Models6 Models for interconnected $ela%6 $ela% in DC trees? 'iming 2 $ri#en PlacementE Jero Stac9 Algorithm6 8eight +ased "lacement6 Linear Programming A""roach 'iming $ri#ing DoutingE $ela% Minimi@ation6 Clic9 S9e0 Pro+lem6 uffered Cloc9 'rees? Minimi@ationE constrained #ia Minimi@ation6 unconstrained #ia Minimi@ation6 ,ther issues in minimi@ation ,NIT V SINGLE L*@ER R ,TING/ CELL GENER*TI N *ND C MP*CTI N 2 Planar su+set "ro+lem :PSP; 6 Single la%er glo+al routing6 Single La%er 4lo+al Douting6 Single La%er $etailed Douting6 8ire length and +end minimi@ation techni=ue 2 ,#er 'he Cell :,'C; Douting6 Multi"le chi" modules:MCM;6 Programma+le Logic Arra%s6 'ransistor chaining6 8ein urger Arra%s6 4ate matri< la%out6 1$ com"action6 2$ com"action T T*L. 9: 8eriods <E@ ND S@SLL*<,S 1? Di#er routing 2? Left Edge channel routing algorithm RE'ERENCES 1? Saraf@adeh> C?B? 8ong> HAn Introduction to VLSI Ph%sical $esignI> Mc 4ra0 5ill International Edition 1//( 2? 7a#eed A? Sher0ani HAlgorithm for VLSI Ph%sical $esign AutomationI> 3 rd Edition > S"ringer> 1//-? 3? Sadi= M? Sait> 5a+i+ Goussef HVLSI Ph%sical $esign Automation> 'heor% and PracticeI 8orld Scientific Pu+lishing Com"an%> 1st Edition>1///? ,RLs. 1? htt"E..000?ifte?de.mitar+eiter.lienig.ea+oo9?"df 2? htt"E..000?eecs?+er9ele%?edu.Mne0ton."resentations.Ar"a10L-/.tsld00-?htm PEVLCBB HIGH SPEED SGITCHING *RCHITECT,RE *IM 'o stud% a+out different 5igh s"eed s0itching circuits <>ECTIVE 'o im"art 9no0ledge on $ifferent s0itching technologies 28 LTPC $++$

$ifferent architectures Kues architecture

,NIT I L*N SGITCHING TECHN L G@ 2 S0itching Conce"ts> s0itch for0arding techni=ues> s0itch "ath control> LA7 S0itching> cut through for0arding> store and for0ard> #irtual LA7s? ,NIT II *TM SGITCHING *RCHITECT,RE 2 loc9ing net0or9s 6 +asic 6 and6 enhanced +an%an net0or9s> sorting net0or9s 6 merge sorting> re6 arranga+le net0or9s 6 full6and6 "artial connection net0or9s> non +loc9ing net0or9s 6 Decursi#e net0or9 construction> com"arison of non6+loc9ing net0or9> S0itching 0ith deflection routing 6 shuffle s0itch> tandem +an%an s0itch? ,NIT III 4,E,ES IN *TM SGITCHES 2 Internal Kueueing 6In"ut> out"ut and shared =ueueing> multi"le =ueueing net0or9s 2 com+ined In"ut> out"ut and shared =ueueing 6 "erformance anal%sis of Kueued s0itches? ,NIT IV P*CFET SGITCHING *RCHITECT,RES 2 Architectures of Internet S0itches and Douters6 ufferless and +uffered Cross+ar s0itches> Multi6stage s0itching> ,"tical Pac9et s0itchingT Internall% +uffered Cross+ars? ,NIT V IP SGITCHING 2 Addressing model> IP S0itching t%"es 6 flo0 dri#en and to"olog% dri#en solutions> IP o#er A'M address and ne<t ho" resolution> multicasting Total. 9: Periods <E@ ND THE S@LL*<,S ). S0itching fa+ric on a chi" 2? IP#) o#er A'M? RE'ERENCES 1? Achille Patta#ina> HS0itching 'heor%E Architectures and "erformance in road+and A'M net0or9s S> Fohn 8ile% ! Sons Ltd> 7e0 Gor9? 1//2? Elhanan% M? 5amdi> H5igh Performance Pac9et S0itching architecturesI> S"ringer Pu+lications> 200*? 3? Christo"her G Met@> HS0itching "rotocols ! ArchitecturesI> Mc4ra0 5ill Professional Pu+lishing> 7e0Gor9?1//-? &? Dainer 5andel> Manfred 7 5u+er> Stefan Schroder> HA'M 7et0or9s 6 Conce"ts Protocols> A""licationsI> 3rd Edition> Addison 8esle%> 7e0 Gor9? 1///? ,RLs. ). htt"E..000?niceindia?com.=+an9.dc1)21LhighLs"eedLs0itchingLarchitecture?"df 2? htt"E..9612?"isd?edu.currinst.net0or9.0)L-0(AL261LS4?"df

29

PEVLCB$ DESIGN

' VLSI IN EM<EDDED S@STEM $++$

LTPC

*IM 'o stud% the im"ortance of VLSI in em+edded s%stems? <>ECTIVES 'o learn a+out custom single "rocessor> multi"rocessor and different communications re=uired in the design of em+edded s%stems ,NIT I INTR D,CTI N 2

Em+edded s%stem o#er#ie0>$esign challengeE ,"timi@ing design metrics> Processor 'echnolog%> 4eneral"ur"ose Processors> Single"ur"ose Processors> and A""lication S"ecific Processors> IC 'echnolog%E Full custom.VLSI> Semicustom ASIC> PL$> 'rends> $esign 'echnolog%? ,NIT II C,ST M SINGLE P,RP SE PR CESS R 2

D' le#el com+inational com"onents> D' le#el se=uential com"onents > Custom Single "ur"ose Processor $esign> D' le#el Custom Single "ur"ose Processor $esign> ,"timi@ing Custom Single "ur"ose Processors > ,"timi@ing the original "rogram> ,"timi@ing the FSM$>,"timi@ing the data"ath> o"timi@ing the FSM? Ge5eral8ur8ose Processors asic architecture> $ata "ath> Control unit> Memor%> Pi"elining> Su"erscalar and VLI8 architectures> A""lication S"ecific instruction set Processors :ASIPAs;> Microcontrollers> $SP> Less 4eneral ASIP en#ironments> selecting a Micro"rocessor. 4eneral "ur"ose Processor $esign? ,NIT III *DV*NCED C MM,NIC*TI N PRINCIPLES 2

Parallel> serial and 0ireless Communications> Serial "rotocolsE 'he I2C us> 'he CA7 +us> Fire 0ire +us> CS ? Parallel "rotocolsE PCI +us> AM A +us> 0ireless "rotocolsE Ir$A> luetooth> IEEE -02?11? ,NIT IV DIGIT*L C*MER* EE*MPLE 2

CserAs "ers"ecti#e> $esignerA "ers"ecti#e> S"ecification> Informal functional s"ecification> 7onfunctional s"ecification ?E<ecuta+le s"ecification> $esign> Im"lementation 1E-0(1+ased design> Im"lementation 2E Fi<ed "oint F$C'> Im"lementation 3E 5ard0are F$C'? ,NIT V EM<EDDED S 'TG*RE DESIGN 2

Em+edded soft0are design> hard0are and soft0are interaction> mi<ed architecture.a""lication models> heterogeneous MPS,C> Virtual architecture model> #irtual architecture in s%stemC> a""lication e<am"les in #irtual architecture? T T*L. 9: 8eriods RE'ERENCES 1? Em+edded S%stem $esign6 A Cnified 5ard0are.Soft0are I ntroductionI>Fran9 Vahid and 'on% 4i#argis>Fohn 8ile% ! Sons>2002? 2? HEm+edded Soft0are design and "rogramming of multi"rocessor s%stem on chi"I> 9atalin "o"o#ici> ahmed 3eer%a>Maril%n 0olf>S"ringer "u+lications>2010? 3? HEm+edded S%stem $esignI Ste#e 5eath> utter0orth5einemann? &? HS"ecification and $esign of Em+edded s%stemsI> 4a3s9i and Vahid>Prentice 5all? PEVLCB9 *DV*NCED MICR PR CESS RS *ND MICR C NTR LLERS *IM 30 LTPC $ ++$

'o stud% a+out the ad#anced "rocessors in the VLSI industr% <>ECTIVE 'o im"art 9no0ledge on Pentium Processors architectures ADM Processors architectures Ad#anced micro controller architectures? ,NIT I MICR PR CESS R *RCHITECT,RE 2 Instruction Set 2 $ata formats 2Addressing modes 2 Memor% hierarch% 2register file 2 Cache 2 Virtual memor% and "aging 2 Segmentation6 "i"elining 2the instruction "i"eline 2 "i"eline ha@ards 2 instruction le#el "arallelism 2 reduced instruction set 2Com"uter "rinci"les 2 DISC #ersus CISC? ,NIT II HIGH PER' RM*NCE CISC *RCHITECT,RE % PENTI,M 2 CPC Architecture6 us ,"erations 2 Pi"elining 2 rach "redication 2 floating "oint unit6 ,"erating Modes 2Paging 2 Multitas9ing 2 E<ce"tion and Interru"ts 2 Instruction set 2 addressing modes? ,NIT III HIGH PER' RM*NCE RISC *RCHITECT,RE % *RM 2 ,rgani@ation of CPC 2 us architecture 2 Memor% management unit 6 ADM instruction set6 'hum+ Instruction set6 addressing modes 2 Programming the ADM "rocessor? ,NIT IV M T R L* ;JHC)) MICR C NTR LLERS 2 Instruction set addressing modes 2 o"erating modes6 Interru"t s%stem6 D'C6Serial Communication Interface ,NIT V PIC MICR C NTR LLER 2 CPC Architecture 2 Instruction set 2 interru"ts6 'imers6 I2C Interfacing 2CAD'6 A.$ Con#erter 2P8M and introduction to C6Com"ilers? Total. 9: Periods <E@ ND THE S@LL*<,S 1? Programming the Pentium "rocessor 2? A.$ Con#erter P8M and CAD' RE'ERENCES. 1? $aniel 'a+a9 > UA Ad#anced Micro"rocessorsI Mc4ra0 5ill?Inc?> 1//( 2? Fames L? Antona9os > H 'he Pentium Micro"rocessor UA Pearson Education > 1//*? 3? Ste#e Fur+er > UA ADM S%stem 2,n 2Chi" architecture HAddision 8esle% > 2000? &? 4ene ?5?Miller ?I Micro Com"uter Engineering >I Pearson Education > 2003? (? Fohn ? ?Peatman > H $esign 0ith PIC Microcontroller > Prentice hall> 1//*? )? Fames L?Antona9os >I An Introduction to the Intel famil% of Micro"rocessors UA Pearson Education 1///? *? arr%? ? reg>I 'he Intel Micro"rocessors Architecture > Programming and Interfacing H > P5I>2002? ,RLs. ). htt"E..000?cse?ohio6state?edu.M"anda.**(.slides.intelL"o0erL"erfL0)?"df 2? htt"E..home"ages?thm?de.Mhg10013.Lehre.MMS.8S030&LSS0&.Ioannis.P$F.arm?"df

ELECTIVE III PEVLCB: H*RDG*RE . S 'TG*RE C (DESIGN *IM 31 LT PC $ ++ $

'o ma9e the student to understand the 5ard0are . Soft0are Co6$esign <>ECTIVE 'o im"art 9no0ledge on Protot%"ing of S.8 !5.8 5ard0are.Soft0are Partitioning 5ard0are.Soft0are co s%nthesis ,NIT I S@STEM SPECI'IC*TI N *ND M DELLING 2 Em+edded S%stems > 5ard0are.Soft0are Co6$esign > Co6$esign for S%stem S"ecification and Modelling > Co6$esign for S%stem S"ecification and Modelling > Co6 $esign for 5eterogeneous Im"lementation 6 Processor S%nthesis > Single6Processor Architectures 0ith one ASIC > Single6Processor Architectures 0ith man% ASICs> Multi6Processor Architectures > Com"arison of Co6$esign A""roaches > Models of Com"utation >De=uirements for Em+edded S%stem S"ecification ? ,NIT II H*RDG*REHS 'TG*RE P*RTITI NING 2 'he 5ard0are.Soft0are Partitioning Pro+lem> 'he 5ard0are.Soft0are Partitioning Pro+lem> 5ard0are.Soft0are Cost Estimation> 4eneration of the Partitioning 4ra"h > Formulation of the 58.S8 Partitioning Pro+lem > ,"timi@ation > 58.S8 Partitioning +ased on 5euristic Scheduling> 58.S8 Partitioning +ased on 4enetic Algorithms ? ,NIT III H*RDG*REHS 'TG*RE C (S@NTHESIS 2 'he Co6S%nthesis Pro+lem> State6'ransition 4ra"h> Definement and Controller 4eneration> $istri+uted S%stem Co6S%nthesis ,NIT IV PR T T@PING *ND EM,L*TI N 2 Introduction> Protot%"ing and Emulation 'echni=ues >Protot%"ing and Emulation En#ironments >Future $e#elo"ments in Emulation and Protot%"ing >'arget Architecture6 Architecture S"eciali@ation 'echni=ues >S%stem Communication Infrastructure> 'arget Architectures and A""lication S%stem Classes> Architectures for Control6$ominated S%stems> Architectures for $ata6$ominated S%stems >Mi<ed S%stems and Less S"eciali@ed S%stems ,NIT V DESIGN SPECI'IC*TI N *ND VERI'IC*TI N 2 Concurrenc%> Coordinating Concurrent Com"utations> Interfacing Com"onents> Verification > Languages for S%stem6Le#el S"ecification and $esign S%stem6Le#el S"ecification >$esign De"resentation for S%stem Le#el S%nthesis> S%stem Le#el S"ecification Languages> 5eterogeneous S"ecification and Multi6Language Co6 simulation T T*L. 9: PERI DS

32

<E@ ND THE S@LL*<,S Interfacing an e<ternal 5.8 or S.8 and D',S> Da"id "roto t%"ing> Co simulation using 5$L RE'ERENCES 1? Dalf 7iemann > H5ard0are.Soft0are Co6$esign for $ata Flo0 $ominated Em+edded S%stemsI> Blu0er Academic Pu+> 1//-? 2? Forgen Staunstru" > 8a%ne 8olf >I5ard0are.Soft0are Co6$esignE Princi"les and PracticeI > Blu0er Academic Pu+>1//*? 3? 4io#anni $e Micheli > Dolf Ernst Morgon>I Deading in 5ard0are.Soft0are Co6 $esign H Baufmann Pu+lishers>2001? CDLsE 1? htt"[email protected](0/*.ref.0olf/&codesign?"df 2? htt"E..210?212?20(?2).sudarshan.Main.Courses.20126 2013.,ddSem.5scL12.lecses.refs.lec01.demicheli/*hard0aresoft0are?"df?

33

PEVLCB; N*N TECHN L G@ *IM 'o stud% a+out the nano machines and nano de#ices <>ECTIVE 'o Im"art 'he Bno0ledge ,n Solid state "h%sics $ifferent 7ano de#ices

LTPC $++$

,NIT() INTR D,CTI N T PH@SICS ' THE S LID ST*TE 2 Structure6si@e de"endence of "ro"erties6cr%stal structures6face centered cu+ic nano "articles6energ% +ands6insulators> semiconductors and conductors6reci"rocal s"ace6energ% +ands and ga"s of semiconductors6locali@ed "articlesX donors> acce"tors and dee" tra"s6mo+ilit% ,NIT(B METH DS ' ME*S,RING PR PERTIES 2 Structure6atomic structures6cr%stallogra"h%6"article si@e determination 2surface structure6microsco"%6 transmission electron microsco"%6field ion microsco"%6scanning microsco"%6s"ectrosco"%6infrared and raman s"ectrosco"%6"hotoemission and < ra% s"ectrosco"%6 ,NIT ($ PR PERTIES ' INDIVID,*L N*N P*RTICLES 2 Introduction6metal nanoclusters6magic num+ers6theoretical modeling of nano"articals6geometric structure6electronic structure6reacti#it%6fluctuations6semiconducting nano"articals6o"tical "articals6 "hotofragmentation 2rare gas and molecular clusters6inert gas clusters6su"erfluid clusters6molecular clusters6method of s%nthesis6DF "lasma6chemical methods6thermol%sis6"ulsed laser methods ,NIT (9 C*R< N N*N STR,CT,RES 2 Car+on molecules6car+on nanotu+es6fa+rication6structure6electrical "ro"erties6#i+rational "ro"erties6 mechanical "ro"erties6a""lication car+on nanotu+es6com"uters6fuel cells6chemical sensors6catal%sis6 mechanical reinforcement ,NIT (: N*N MECHINES *ND N*N DEVICES 2 Microelectromechanical s%stems :MEMSs;6nanoelectromechanical s%stems:7EMSs;6fa+rication6 nanode#ices and nanomechines6molecular and su"eramolecular s0itches Total. 9: Periods <E@ ND S@LL*<,S 7ano +iometric9s> a""lications of nano technolog% in solar energ% RE'ERENCES 1? Poole? C?P? Fr?> ,0ens? F? F?> Introduction to 7anotechnolog%> 8ile%> 2003 2? 8aser Danier> 7anoelectronics and Information 'echnolog% :Ad#anced Electronic Materials and 7o#el $e#ices;> 8ile%6VC5 2003 3? $re<ler? B?E?> 7anos%stems> 8ile% 1//2? ,RLs. 1? htt"E..snf?stanford?edu.Education.7anotechnolog%?S7F?0e+?"df 2? htt"E..000?nanotec?org?u9.finalDe"ort?htm

34

PEVLCB# INTR D,CTI N T

MEMS S@STEM DESIGN

LTPC $ + +$

*IM 'o gi#e introduction to micro electro mechanical details <>ECTIVE 'o im"art 9no0ledge on Introduction 'o MEMS Mechanism for MEMs $esign ,NIT I INTR D,CTI N T MEMS 2 MEMS and Micros%stems> Miniaturi@ation> '%"ical "roducts> Micro sensors> Micro actuation> MEMS 0ith micro actuators> Microaccelorometers and Micro fluidics> MEMS materials> Micro fa+rication ,NIT II MECH*NICS ' R MEMS DESIGN 2 Elasticit%> Stress> strain and material "ro"erties> ending of thin "lates> S"ring configurations> torsional deflection> Mechanical #i+ration> Desonance> 'hermo mechanics 2 actuators> force and res"onse time> Fracture and thin film mechanics? ,NIT III ELECTR ST*TIC DESIGN 2 ElectrostaticsE +asic theor%> electro static insta+ilit%? Surface tension> ga" and finger "ull u"> Electro static actuators> Com+ generators> ga" closers> rotar% motors> inch 0orms> Electromagnetic actuators? +ista+le actuators? ,NIT IV CIRC,IT *ND S@STEM ISS,ES 2 Electronic Interfaces> Feed+ac9 s%stems> 7oise> Circuit and s%stem issues> Case studies 2 Ca"aciti#e accelerometer> Pei@o electric "ressure sensor> Modeling of MEMS s%stems> CA$ for MEMS? ,NIT V INTR D,CTI N T PTIC*L *ND R' MEMS 2 ,"tical MEMS> 6 S%stem design +asics 2 4aussian o"tics> matri< o"erations> resolution?> Case studies> MEMS scanners and retinal scanning dis"la%> $igital Micro mirror de#ices? DF Memes 2 design +asics> case stud% 2 Ca"aciti#e DF MEMS s0itch> "erformance issues? T T*L. 9: PERI DS <E@ ND S@LL*<,S Materials for MEMs> Fa+rication "rocess of Micro s%stems> Micro s%stems "ac9aging?? RE'ERENCES 1? Ste"hen Santuria>I Micros%stems $esignI> Blu0er "u+lishers> 2000 2? ?7adim Maluf>I An introduction to Micro electro mechanical s%stem designI> Artech 5ouse> 2000 3? 2? Mohamed 4ad6el65a9> editor>I 'he MEMS 5and+oo9I> CDC "ress aco Daton> 2000? &? 3? 'ai Dan 5su>I MEMS ! Micro s%stems $esign and ManufactureI 'ata Mc4ra0 5ill> 7e0 $elhi> 2002? ,RLsE 1? htt"E..000?co#entor?com."roducts.mems. 2? htt"E..000?intellisense?com.u"load.0.20120(2/0310(1?"df

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PEVLCBJ GIRELESS SENS R NETG RFS *IM 'o gi#e introduction to the 0ireless sensor net0or9s <>ECTIVE 'o im"art 9no0ledge on Architectures of sensor net0or9s 7et0or9ing of sensors Infra structures

LTPC $ ++$

,NIT I VERVIEG ' GIRELESS SENS R NETG RFS 2 Challenges for 8ireless Sensor 7et0or9s6Characteristics re=uirements6re=uired mechanisms> $ifference +et0een mo+ile ad6hoc and sensor net0or9s> A""lications of sensor net0or9s6 Ena+ling 'echnologies for 8ireless Sensor 7et0or9s? ,NIT II *RCHITECT,RES 2 Single67ode Architecture 6 5ard0are Com"onents> Energ% Consum"tion of Sensor 7odes > ,"erating S%stems and E<ecution En#ironments> 7et0or9 Architecture 6 Sensor 7et0or9 Scenarios> ,"timi@ation 4oals and Figures of Merit>? ,NIT III NETG RFING ' SENS RS 2 Ph%sical La%er and 'ranscei#er $esign Considerations> MAC Protocols for 8ireless Sensor 7et0or9s> Lo0 $ut% C%cle Protocols And 8a9eu" Conce"ts 6 S6MAC > 'he Mediation $e#ice Protocol> 8a9eu" Dadio Conce"ts> Address and 7ame Management> Assignment of MAC Addresses> Douting Protocols ,NIT IV IN'R*STR,CT,RE EST*<LISHMENT 2 'o"olog% Control> Clustering> 'ime S%nchroni@ation> Locali@ation and Positioning> Sensor 'as9ing and Control? ,NIT V SENS R NETG RF PL*T' RMS *ND T LS 2 ,"erating S%stems for 8ireless Sensor 7et0or9s> Sensor 7ode 5ard0are 2 er9ele% Motes> Programming Challenges> 7ode6le#el soft0are "latforms> 7ode6le#el Simulators> State6centric "rogramming? Total. 9: Periods <E@ ND THE S@LL*<,S 1? 4ate0a% Conce"ts 2? Energ%6Efficient Douting 3? 4eogra"hic Douting RE'ERENCES 1? 5olger Barl ! Andreas 8illig> S Protocols And Architectures for 8ireless Sensor 7et0or9sS > Fohn 8ile%> 200(? 2? Feng Jhao ! Leonidas F? 4ui+as> H8ireless Sensor 7et0or9s6 An Information Processing A""roachS> Else#ier> 200*? 3? Ba@em Sohra+%> $aniel Minoli> ! 'aie+ Jnati> H8ireless Sensor 7et0or9s6 'echnolog%> Protocols> And A""licationsI> Fohn 8ile%> 200*? &? Anna 5ac> H8ireless Sensor 7et0or9 $esignsI> Fohn 8ile%> 2003? (? has9ar Brishnamachari> I7et0or9ing 8ireless SensorsI> Cam+ridge Press>200(? )? Mohammad Il%as And Imad Mahgao+>I5and+oo9 ,f Sensor 7et0or9sE Com"act 8ireless And 8ired Sensing S%stemsI> CDC Press>200(? *? 8a%ne 'omasi> HIntroduction 'o $ata Communication And 7et0or9ingI> Pearson Education> 200* ,RLs. ). htt"E..arri?uta?edu.acs.net0or9s.8irelessSensor7etCha"0&?"df 2? htt"E..000?sensor6net0or9s?org. PEVLCB2C NTR L S@STEM N CHIP LTPC 36

$++$ *IM 'o learn the modern IC +ased design for an% control a""lications <>ECTIVES 'o im"art 9no0ledge on control com"onents S,C design of fu@@% logic controller ,NIT I 2

Introduction to control s%stem conce"t6o"en loo" and closed loo"6control s%stem architecture6t%"es of control methodolog%6digital control s%stem6anal%sis of digital control s%stem6remote control conce"ts and a""lications ,NIT II 2

control com"onents and detailed stud%6o" am" 2 transmitter6 recei#ers6 standard cell arra% design64ate arra% design6full custom design6structured design6IP +ase design ,NIT III 2

Stud% of CC2(33 of 'e<as Instruments for Chi" solution to remote control a""lications ,NIT IV S%stem on Chi" design of a Fu@@% logic controller ,NIT V 2 2

Single chi" design of a tem"erature controller> Single chi" design of Engine control s%stem T T*L. 9: 8eriods <E@ ND THE S@LL*<,S S%stem on chi" test architectures> Delia+ilit% issues> 5igh S"eed I., interface? RE'ERENCES 1? Microcontroller +ased A""lied digital control +% $ogan I+rahim> Fohn 8ile%>200) 2? An o"timi@ed s%stem on chi" solution for 2?&45@ IEEE -02?1(?& remote control a""lication> 'e<as instrument> Fune 2010 and a""lication notes ,RLs. ). 000?isoi?in.Fournal. ac9Issues.#ol3B. 000?fu3itsu6ten?com.+usiness.technica

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ELECTIVE IV PEVLC$+ L G P GER VLSI DESIGN LTPC $++$ *IM 'o learn a+out "o0er dissi"ation in CM,S circuits> different "o0er o"timi@ation techni=ues <>ECTIVES 'o Im"art Bno0ledge ,n CM,S circuits for memor% cloc9 and interconnect? #arious techni=ues for Po0er estimation in circuits ,NIT I P GER DISSIP*TI N IN CM S 2

5ierarch% of limits of "o0er 2 Sources of "o0er consum"tion 2 Ph%sics of "o0er dissi"ation in CM,S FE' de#ices6 asic "rinci"le of lo0 "o0er design? ,NIT II P GER PTIMI?*TI N 2

Logical le#el "o0er o"timi@ation 2 Circuit le#el lo0 "o0er design 2 Circuit techni=ues for reducing "o0er consum"tion in adders and multi"liers ,NIT III DESIGN ' L G P GER CM S CIRC,ITS 2

Com"uter Arithmetic techni=ues for lo0 "o0er s%stems 2 Deducing "o0er consum"tion in memories 2 Lo0 "o0er cloc9> Interconnect and la%out design 2 Ad#anced techni=ues 2 S"ecial techni=ues ,NIT IV P GER ESTIM*TI N 2

Po0er estimation techni=ues 2 Logic le#el "o0er estimation 2 Simulation "o0er anal%sis 2 Pro+a+ilistic "o0er anal%sis? ,NIT V S@NTHESIS *ND S 'TG*RE DESIGN ' R L G P GER 2

S%nthesis for lo0 "o0er 2 eha#ioral le#el transforms6 Soft0are design for lo0 "o0er 6 T T*L. 9: 8eriods <E@ ND THE S@LL,<,S Lo0 #oltage6lo0 "o0er adder> multi"liers> RE'ERENCES 1? 2? B?Do% and S?C? Prasad > L,8 P,8ED CM,S VLSI circuit design> 8ile%>2000 $imitrios Soudris> Chirstian Pignet> Costas 4outis> $esigning CM,S Circuits For Lo0 Po0er> Blu0er>2002 3? F? ? Buo and F?5 Lou> Lo0 #oltage CM,S VLSI Circuits>8ile% 1///? &? A?P?Chandra9asan and D?8? roadersen> Lo0 "o0er digital CM,S design> Blu0er> 1//(? (? 4ar% Gea"> Practical lo0 "o0er digital VLSI design> Blu0er> 1//-? )? A+dellatif ellaouar>Mohamed?I? Elmasr%> Lo0 "o0er digital VLSI design>s Blu0er> 1//(? *? Fames ? Buo> Shin 2 chia Lin> Lo0 #oltage S,I CM,S VLSI $e#ices and Circuits? Fohn 8ile% and sons> inc 2001 CDLsE 1? 000?c"dee?ufmg?+r.Mfran9.lectures.Sill6Lo0Po0er2?""t 2? htt"E..000?cmos#lsi?com.lect1-?"df PEVLC$) SEMIC ND,CT R MEM R@ DESIGN = PR CESSING LTPC $++$ 38

*IM 'o stud% a+out +asic semiconductor memories> their t%"es and the faults in memories? <>ECTIVES 'esting and "ac9aging techni=ues of different memor% t%"es ,NIT I R*ND M *CCESS MEM RIES 2 SDAM Cell Structures6M,S SDAM Architecture6M,S SDAM Cell and Peri"heral Circuit ,"eration6 i"olar SDAM 'echnologies6Silicon ,n Insulator :S,l; 'echnolog%6Ad#anced SDAM Architectures and 'echnologies6A""lication S"ecific SDAMs? D@N*MIC R*ND M *CCESS MEM RIES CDR*MSD $DAM 'echnolog% $e#elo"ment6CM,S $DAMs6$DAMs Cell 'heor% and Ad#anced Cell Structures6 iCM,S> $DAMs6Soft Error Failures in $DAMs6Ad#anced $DAM $esigns and Architecture6A""lication S"ecific $DAMs? ,NIT II 2

N NV L*TILE MEM RIES Mas9ed Dead6,nl% Memories :D,Ms;65igh $ensit% D,Ms6Programma+le Dead6,nl% Memories :PD,Ms;6 i"olar PD,Ms6CM,S PD,Ms6Erasa+le :CV; 6 Programma+le Doad6,nl% Memories :EPD,Ms;6Floating64ate EPD,M Cell6,ne6'ime Programma+le :,'P; EPD,MS6Electricall% Erasa+le PD,Ms :EEPD,Ms;6EEPD,M 'echnolog% And Architecture67on#olatile SDAM6Flash Memories :EPD,Ms or EEPD,M;6Ad#anced Flash Memor% Architecture? ,NIT III 2 MEM R@ '*,LT M DELING/ TESTING/ *ND MEM R@ DESIGN ' R TEST*<ILIT@ *ND '*,LT T LER*NCE DAM Fault Modeling> Electrical 'esting> Pseudo Dandom 'esting6Mega+it $DAM 'esting67on#olatile Memor% Modeling and 'esting6I$$K Fault Modeling and 'esting6A""lication S"ecific Memor% 'esting ,NIT IV 2

SEMIC ND,CT R MEM R@ RELI*<ILIT@ *ND R*DI*TI N E''ECTS 4eneral Delia+ilit% Issues6DAM Failure Modes and Mechanism67on#olatile Memor% Delia+ilit%6Delia+ilit% Modeling and Failure Date Prediction6$esign for Delia+ilit%6Delia+ilit% 'est Structures6Delia+ilit% Screening and Kualification> DAM Fault Modeling> Electrical 'esting> Pseudo Dandom 'esting6Mega+it $DAM 'esting67on#olatile Memor% Modeling and 'esting6I$$K Fault Modeling and 'esting6A""lication S"ecific Memor% 'esting ,NIT V 2 P*CF*GING TECHN L GIES Dadiation Effects6Single E#ent Phenomenon :SEP;6Dadiation 5ardening 'echni=ues6Dadiation 5ardening Process and $esign Issues6Dadiation 5ardened Memor% Characteristics6Dadiation 5ardness Assurance and 'esting 6 Dadiation $osimetr%68ater Le#el Dadiation 'esting and 'est Structures? Ferroelectric Dandom Access Memories :FDAMs;64allium Arsenide :4aAs; FDAMs6Analog Memories6 Magnetoresisti#e Dandom Access Memories :MDAMs;6E<"erimental Memor% $e#ices? Memor% 5%+rids and MCMs :2$;6Memor% Stac9s and MCMs :3$;6Memor% MCM 'esting and Delia+ilit% Issues6Memor% Cards65igh $ensit% Memor% Pac9aging Future $irections? T T*L. 9: 8eriods <E@ ND THE S@LL*<,S CM,S memor% circuits> Gield im"ro#ement techni=ues> RE'ERENCES 39

1. Asho9 B? Sharma> Semiconductor MemoriesE 'echnolog%> 'esting> and Delia+ilit%> 8ile%6IEEE Press> 2002? 2. Asho9 B? Sharma > Semiconductor Memories> '0o6Volume Set/ 8ile%6IEEE Press> 2003? 3. Asho9 B? Sharma/ 4.

Semiconductor MemoriesE 'echnolog%> 'esting> and Delia+ilit%> Prentice 5all of India> 1//*?
rent Beeth> D? Faco+ a9er> $DAM Circuit $esignE A 'utorial> 8ile%6IEEE Press> 2000?

(? ett% Prince / 5igh

Performance MemoriesE 7e0 Architecture $DAMs and SDAMs 6 E#olution and Function> 8ile%> 1///?

,RLs. ). htt"E..highered?mcgra06hill?com.sites.dl.free.00*22-3)(3.10/3&2.hodgeLcha"t0-?"df B. htt"E..000?radio6electronics?com.info.data.semicond.memor%.different6t%"es6semiconductor6memor%?"h"

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PEVLC$B C MP,TER *RCHITET,RE *ND P*R*LLEL PR CESSING *IM 'o Stud% the Ad#anced Com"uter Architectures <>ECTIVE 'o im"art 9no0ledge on 7et0or9 "ro"erties of com"uters Su"erscalar techni=ues

LTPC $++$

,NIT() P*RELLEL C MP,TER PR GR*M *ND NETG RF PR PERTIES 2 Multi"rocessors and multicom"uters6multi#ector and SIM$ com"uters6PDAAM and VLSI M,$ELS6 architectural de#elo"ment trac9s6conditions of "arallelism6data and resources de"endences6hard0are and soft0are "arallelism6grain si@e and latenc%6grain "ac9ing and scheduling6static multi"rocessor scheduling6"rogram flo0 mechanisms6s%stem interconnect architecture6net0or9 "ro"erties and routing ,NIT(B PR CESS RS *ND MEM R@ 2 Ad#anced "rocessor technolog%6DISC scalar "rocessors6su"erscalar and #ector "rocessors6memor% hierarchical technolog%6#irtual memor% technolog%6cache memor% organi@ations6shared memor% organi@ations ,NIT($ PIPELINING *ND S,PERSC*L*R TECHNI4,ES 2 Linear "i"eline "rocessors6as%nchronous and s%nchronous models6cloc9ing and timing control 2 s"eedu">efficienc%>and through"ut6nonlinear "i"eline "rocessors6reser#ation and latenc% anal%sis6 Collison 2Free Scheduling6 Pi"eline Schedule ,"timi@ation6Instruction Pi"eline $esign6Instruction E<ecution Phases6 Mechanisms for Instruction Pi"elining6$%namic Instruction scheduling6 ranch 5andling 'echni=ues6Arithmetic Pi"eline $esign 2Com"uter Arithmetic Princi"les6Static Arithmetic Pi"elines6Multifunctional Arithmetic Pi"elines6Su"erscalar and su"er "i"eline design6Su"er "i"elined $esign ,NIT(9 M,LTIPR CESS R *ND M,LTIC MP,TERS 2 Multi"rocessor s%stem interconnects6cache coherence and s%nchroni@ation mechanisms6three generations of multicom"uters6message "assing mechanisms6#ector "rocessing "rinci"les 2#ector instruction t%"es6com"ound #ector "rocessing 2SIM$ com"uter organi@ations ,5it(: SC*L*<LE/ M,LTI THRE*DED *ND D*T*'L G *RCHITECT,RES 2 Latenc% hiding techni=ue6"rinci"les of multithreading6fine grain multicom"uters6scala+le and multithreaded architectures Total 9: 8eriods <E@ ND THE S@LLN,S Instruction le#el "arallel "rocessing> Memor% hierarchi technolog%> Shared memor% MIM$ architectures> RE'ERENCE. 1? $e@so Sima> 'erence Fountain> Peter Bacsu9> IAd#anced Com"uter architecture 2 A $esign S"ace A""roachI > Pearson education > 2003? 2? Bai 50ang> HAd#anced Com"uter Architecture S> Mc4ra0 5ill International> 1//3? 3? Fohn P?Shen> HModern "rocessor design 6 Fundamentals of su"er scalar "rocessorsI> 'ata Mc4ra0 5ill 2003? ,RLs. ). htt"E..000?niceindia?com.=+an9.A7L1)(2LC,MPC'EDLADC5I'EC'CDELLLLPADALLELLPD,CESSI 74?"df 2? htt"E.."eo"le?engr?ncsu?edu.efg.(0).sum//.001.lec16intro?"df PEVLC$$ D*T* C NVERTERS 41

L T P C $ + + $ *IM To study the di66ere5t data co5!erters <>ECTIVE 'o im"art the 9no0ledge on Sam"le And 5old Circuits A to $ and $ to A con#ersions ,NIT I <SICS ' D*T* C NVERTERS 2 Sam"ling s0itches> Con#entional o"en loo" and closed loo" sam"le and hold architecture> ,"en loo" architecture 0ith miller com"ensation> multi"le<ed in"ut architectures> rec%cling architecture s0itched ca"acitor architecture? ,NIT II SGITCH C*P*CIT R CIRC,ITS *ND C MP*R*T RS 2 S0itched6ca"acitor am"lifiers> s0itched ca"acitor integrator> s0itched ca"acitor common mode feed+ac9? Single stage am"lifier as com"arator> cascaded am"lifier stages as com"arator> latched com"arators? ,NIT III DIGIT*L T *N*L G C NVERSI N 2 Performance metrics> reference multi"lication and di#ision> s0itching and logic functions in $AC> resistor ladder $AC architecture> current steering> $AC architecture ,NIT IV *N*L G T DIGIT*L C NVERSI N 2 Performance metric> flash architecture> Pi"elined Architecture> Successi#e a""ro<imation architecture> 'ime interlea#ed architecture? ,NIT V PRECISI N TECHNI4,ES 2 Com"arator offset cancellationT ," Am" offset cancellation> Cali+ration techni=ues> range o#erla" and digital correction? T T*L"9: PERI DS <eyo5d the syllabus 7%=uist 2rate $.A con#erters> A . $ con#erters> 'esting of data con#erters RE'ERENCES 1? eh@ad Da@a#i> HPrinci"les of data con#ersion s%stem designI> IEEE "ress> 1//(? 2? Franco Malo+erti> H$ata Con#ertersI> S"ringer> 200*? 3? Dud% #an de Plassche> HCM,S Integrated Analog6to6$igital and $igital6to6Analog Con#ertersI Blu0er Acedamic Pu+lishers> oston> 2003? ,RLs. 1? htt"E..0006inst?eecs?+er9ele%?edu.Mee2&*.fa0&.fa0&.lectures.L11Lf0&?"df 2? htt"E..000?ee?ucla?edu.M+r0e+.director?html

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PEVLC$9 NETG RF

N CHIP

LTPC $++$

*IM 'o gi#e a +asic introduction on 7et0or9 on chi" <>ECTIVES To i-8art the N5oAled1e o5 Em+edded S,C A""lications 'esting strategies of 7,C Soft0are for Multi"rocessor 7et0or9s on Chi" ,NIT I 2 Em+edded S,C A""lications ! Platform Elements 7et0or9ing domain> multimedia domain> 0ireless communications> A""lication trends> First order a""lication "artitioning> Architecture> "rocessing elements> on chi" communication? ,NIT II 2 S%stem Le#el $esign Princi"les Platform +ased design "aradigm> design "hases> a+straction mechanics> models of com"utation> s%stem le#el design re=uirements> tradition 58.S8 co6design> and s%stem +ased transaction +ased modeling> current research on MPS,C design methodologies ,NIT III 2 'esting strategies of 7,C ,n "ac9et s0itched net0or9s for on chi" communication> 'esting Strategies for 7et0or9s on Chi" ,NIT IV Cloc9ing strategies on chi"> "arallel com"uter as 7,C region 2

,NIT V C*SE ST,D@ 2 Soft0are for Multi"rocessor 7et0or9s on Chi" IPV& format 0ith K,S su""ort> Intel IP2&00 reference 7PC> ,SCI 'LM standard> T T*L. 9: Periods <E@ ND THE S@LL*<,S Ph%sical 7et0or9 la%er> $ata6lin9 la%er in 7,C design> 7et0or9 interface architecture and design issues RE'ERENCES 1?Integrated s%stem le#el modeling of net0or9 on chi" ena+led multi "rocessor "latforms > 'im Bogel Visit Ama@onOs 'im Bogel Page search results Learn a+out Author Central > Dainer Leu"ers> 5einrich Me%r > S"ringer "u+lication? 2?7et0or9s on Chi"> A<el Fantsch and 5annu 'enhunen> Blu0er academic "u+lishers> 7e0%or9? CDLsE 1? htt"E..000?ida?liu?se.M"etel.7oC.lecture6notes.lect1"art1?"df 2? htt"E..000?d"s?ui+9?ac?at.Ms"ellegrini."u+.noc6slides0/?"df

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