TLC7628C

DUAL 8BIT MULTIPLYING

DIGITALTOANALOG CONVERTER
SLAS063B APRIL 1989 REVISED MARCH 2007

D Easy Microprocessor Interface

D On-Chip Data Latches
D Digital Inputs Are T TL-Compatible With
D
D
D

10.8-V to 15.75-V Power Supply

Monotonic Over the Entire A/D Conversion
Range
Fast Control Signaling for Digital Signal
Processor (DSP) Applications Including
Interface With TMS320
CMOS Technology
KEY PERFORMANCE SPECIFICATIONS
Resolution
Linearity Error
Power Dissipation
Settling Time
Propagation Delay Time

DW OR N PACKAGE
(TOP VIEW)

AGND
OUTA
RFBA
REFA
DGND
DACA/DACB
(MSB) DB7
DB6
DB5
DB4

20

19

18

17

16

15

14

13

12

10

11

OUTB
RFBB
REFB
VDD
WR
CS
DB0 (LSB)
DB1
DB2
DB3

8 bits
1/2 LSB
20 mW
100 ns
80 ns

description
The TLC7628C is a dual, 8-bit, digital-to-analog converter (DAC) designed with separate on-chip data latches
and featuring exceptionally close DAC-to-DAC matching. Data are transferred to either of the two DAC data
latches through a common, 8-bit input port. Control input DACA/DACB determines which DAC is loaded. The
load cycle of this device is similar to the write cycle of a random-access memory, allowing easy interface to most
popular microprocessor buses and output ports. Segmenting the high-order bits minimizes glitches during
changes in the most significant bits, where glitch impulse is typically the strongest.
The TLC7628C operates from a 10.8-V to 15.75-V power supply and is TTL-compatible over this range. 2- or
4-quadrant multiplying makes this device a sound choice for many microprocessor-controlled gain-setting and
signal-control applications.
The TLC7628C is characterized for operation from 0C to +70C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright 1995 2007, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

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TLC7628C
DUAL 8BIT MULTIPLYING
SLAS063B APRIL 1989 REVISED MARCH 2007

functional block diagram

DB0

14

REFA

13
12
11

Data
Inputs

10

Input
Buffer

9
8
DB7

DACA/DACB
WR
CS

Latch A

RFBA

4
2

OUTA

DACA

AGND

15

20

6
16

19

Logic
Control

Latch B

RFBB
OUTB

DACB

18
REFB

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VDD (to AGND or DGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 17 V
Voltage between AGND and DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD
Input voltage range, VI (to DGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to VDD + 0.3 V
Reference voltage range, VrefA or VrefB (to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V
Feedback voltage range, VRFBA or VRFBB (to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V
Output voltage range, VOA or VOB (to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V
Peak input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 A
Operating free-air temperature range, TA: TLC7628C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to +150C
Case temperature for 10 seconds, TC: FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +260C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package . . . . . . . . . . . . . +260C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

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TLC7628C
DUAL 8BIT MULTIPLYING
SLAS063B APRIL 1989 REVISED MARCH 2007

recommended operating conditions

MIN
Supply voltage, VDD

NOM

10.8

MAX

UNIT

15.75

10

Reference voltage, VrefA or VrefB

High-level input voltage, VIH

2.4

Low-level input voltage, VIL

0.8

CS setup time, tsu(CS)

CS hold time, th(CS) (see Figure 1)

50

ns

ns

DAC select setup time, tsu(DAC) (see Figure 1)

60

ns

DAC select hold time, th(DAC) (see Figure 1)

10

ns

Data bus input setup time tsu(D) (see Figure 1)

25

ns

Data bus input hold time th(D) (see Figure 1)

10

ns

Pulse duration, WR low, tw(WR) (see Figure 1)

50

ns

Operating free-air temperature, TA

TLC7628C

+70

electrical characteristics over recommended ranges of operating free-air temperature and VDD,
VrefA = Vref B = 10 V, VOA and VOB at 0 V (unless otherwise noted)
PARAMETER

TEST CONDITIONS

IIH

High-level input current

VI = VDD

IIL

Low-level input current

VI = 0

MIN

10

25C

Full range

10

25C

Reference input impedance REFA or REFB to

AGND

Ikg

5
DAC data latch loaded with 00000000,
VrefA = 10 V

Full range

200

25C

50

DAC data latch loaded with 00000000,

VrefB = 10 V

Full range

OUTB

200

Output leakage current

25C

Ci

Input capacitance

Co

Output capacitance (OUTA, OUTB)

UNIT
A
A
A
A
k

nA

50
1%

DC supply sensitivity gain/VDD

Supply current

20

OUTA

Input resistance match (REFA to REFB)

IDD

MAX

Full range

VDD = 5 %
Quiescent

All digital inputs at VIHmin or VILmax

Standby

All digital inputs at 0 V or VDD

Full range

0.02

25C

0.01
2

Full range

0.5

25C

0.1

DB0DB7

10

WR, CS,
DACA/DACB

15
DAC data latches loaded with 00000000

25

DAC data latches loaded with 11111111

60

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%/%

mA

pF

pF

TLC7628C
DUAL 8BIT MULTIPLYING
SLAS063B APRIL 1989 REVISED MARCH 2007

operating characteristics over recommended ranges of operating free-air temperature and VDD,
VrefA = VrefB = 10 V, VOA and VOB at 0 V (unless otherwise noted)
PARAMETER

TEST CONDITIONS

MIN

TYP

Linearity error
Settling time (to 1/2 LSB)

See Note 1

Gain error

See Note 2
REFA to OUTA

AC feedthrough

REFB to OUTB

See Note 3

UNIT

1/2

LSB

100

ns

Full range

25C

Full range

65

25C

75

LSB
dB

0.0035 %FSR/C

Temperature coefficient of gain

Propagation delay (from digital input to
90% of final analog output current)
Channel-to-channel
isolation

MAX

See Note 4

80

REFA to OUTB

See Note 5

25C

80

REFB to OUTA

See Note 6

25C

80

ns
dB

Digital-to-analog glitch impulse area

Measured for code transition from 00000000 to 11111111,

TA = 25C

330

nVs

Digital crosstalk

Measured for code transition from 00000000 to 11111111,

TA = 25C

60

nVs

Harmonic distortion
NOTES: 1.
2.
3.
4.
5.
6.

Vi = 6 V, f = 1 kHz, TA = 25C
85
dB
OUTA, OUTB load = 100 , Cext = 13 pF; WR and CS at 0 V; DB0DB7 at 0 V to VDD or VDD to 0 V.
Gain error is measured using an internal feedback resistor. Nominal full scale range (FSR) = Vref 1 LSB. Both DAC latches are
loaded with 11111111.
Vref = 20 V peak-to-peak, 10-kHz sine wave
VrefA = VrefB = 10 V; OUTA/OUTB load = 100 , Cext = 13 pF; WR and CS at 0 V; DB0DB7 at 0 V to VDD or VDD to 0 V.
VrefA = 20 V peak-to-peak, 10-kHz sine wave; VrefB = 0
VrefB = 20 V peak-to-peak, 10-kHz sine wave; VrefA = 0

th(CS)

tsu(CS)

CS

1.3 V

1.3 V

0.3 V

tsu(DAC)

DACA/DACB

1.3 V

3.5 V

th(DAC)
1.3 V

3.5 V
0.3 V

tw(WR)

WR

1.3 V

tsu(D)

DB0 DB7

1.3 V

3.5 V

1.3 V

Data In Stable

0.3 V
th(D)
3.5 V
1.3 V
0.3 V

For all input signals, tr = tf = 5 ns (10% to 90% points).

Figure 1. Setup and Hold Times

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TLC7628C
DUAL 8BIT MULTIPLYING
SLAS063B APRIL 1989 REVISED MARCH 2007

APPLICATION INFORMATION
This device is capable of performing 2-quadrant or full 4-quadrant multiplication. Circuit configurations for
2-quadrant and 4-quadrant multiplication are shown in Figures 2 and 3. Input coding for unipolar and bipolar
operation are summarized in Tables 2 and 3, respectively.
VI(A)
10 V
R1 (see Note A)
R2 (see Note A)
RFBA
REFA

DBO
Input
Buffer

DACA/
DACB

15

CS

16

WR

DACA

AGND

RFBB
Control
Logic

VOA

R4 (see Note A)
C2 (see Note B)

Latch

OUTB
DACB
REFB

DGND

A3
AGND

R3 (see Note A)

RECOMMENDED TRIM
RESISTOR VALUES
R1, R3
R2, R4

A1

VOB

DB7

8
Latch

C1 (see Note B)
OUTA

17
14

VDD

AGND

VI(B)
10 V

500
150

NOTES: A. R1, R2, R3, and R4 are used only if gain adjustment is required. See table for recommended values. Make gain adjustment with
digital input of 255.
B. C1 and C2 phase compensation capacitors (10 pF to 15 pF) are required when using high-speed amplifiers to prevent ringing or
oscillation.

Figure 2. Unipolar Operation (2-Quadrant Multiplication)

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TLC7628C
DUAL 8BIT MULTIPLYING
SLAS063B APRIL 1989 REVISED MARCH 2007

APPLICATION INFORMATION
VI(A)
10 V

DGND

Control
Logic

CS

WR

Latch

5 k

C2
(see Note C)

OUTB

DACB

R3 (see Note A)

VOA

R8

10 k

AGND

(see Note B)
R10

20 k
A4

VOB

R12
5 k

20 k

10 V
VI(B)

500
150

A2

(see
Note B)
R9

A3

REFB

RECOMMENDED TRIM
RESISTOR VALUES
R1, R3
R2, R4

R4 (see Note A)

15
16

RFBA

10 k
R11

20 k

DACA/
DACB

AGND

A1

R5

DB7

Latch

(see
Note B)
R7

C1(see Note C)

RFBA
OUTA
DACA

Input
Buffer

REFA

DBO

20 k

R1 (see Note A)
R2 (see Note A)

17
VDD
14

R6 (see Note B)

NOTES: A. R1, R2, R3, and R4 are used only if gain adjustment is required. See table for recommended values. Adjust R1 for VOA = 0 V with
code 10000000 in DACA latch. Adjust R3 for VOB = 0 V with 10000000 in DACB latch.
B. Matching and tracking are essential for resistor pairs R6, R7, R9, and R10.
C. C1 and C2 phase compensation capacitors (10 pF to 15 pF) may be required if A1 and A3 are high-speed amplifiers.

Figure 3. Bipolar Operation (4-Quadrant Operation)

Address Bus

A8A15

DACA/DACB
Address
Decode
Logic

A
CS
TLC7628
WR

A+1

CPU
8051

DB0
WR
DB7
ALE

AD0AD7

Latch

Data Bus

NOTE D: A = decoded address for TLC7628 DACA

A + 1 = decoded address for TLC7628 DACB

Figure 4. TLC7628 Intel 8051 Interface

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TLC7628C
DUAL 8BIT MULTIPLYING
SLAS063B APRIL 1989 REVISED MARCH 2007

APPLICATION INFORMATION

A8A15

Address Bus

DACA/DACB
Address
Decoder
Logic

VMA

A
CS
TLC7628
WR

A+1

CPU
6800

DB0
DB7

D0 D7

Data Bus

NOTE D: A = decoded address for TLC7628 DACA

A + 1 = decoded address for TLC7628 DACB

Figure 5. TLC7628 6800 Interface

voltage-mode operation
The current-multiplying DAC in the TLC7628C can be operated in a voltage mode. In the voltage mode, a fixed
voltage is placed on the current output terminal. The analog output voltage is then available at the reference
voltage terminal. An example of a current-multiplying DAC operating in voltage mode is shown in Figure 6. The
relationship between the fixed input voltage and the analog output voltage is given by the following equation:
Analog output voltage = fixed input voltage (D/256)
where D = the digital input. In voltage-mode operation, these devices meet the following specification:
LINEARITY ERROR

TEST CONDITIONS

Analog output voltage for REFA, REFB

REF
(Analog output voltage)

VDD = 12 V,

2R

OUTA or OUTB at 5 V,

MIN
TA = 25C

MAX

UNIT

LSB

2R

2R

2R

OUT (Fixed input voltage)

AGND

Figure 6. Current-Multiplying DAC Operating in Voltage Mode

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TLC7628C
DUAL 8BIT MULTIPLYING
SLAS063B APRIL 1989 REVISED MARCH 2007

PRINCIPLES OF OPERATION
This device contains two, identical, 8-bit, multiplying DACs: DACA and DACB. Each DAC consists of an inverted
R-2R ladder, analog switches, and input data latches. Binary-weighted currents are switched between the DAC
output and AGND, thus maintaining a constant current in each ladder leg independent of the switch state. Most
applications require only the addition of an external operational amplifier and voltage reference. A simplified D/A
circuit for DACA or DACB with all digital inputs low is shown in Figure 7.
Figure 8 shows the DACA or DACB equivalent circuit. Both DACs share the analog ground terminal 1 (AGND).
With all digital inputs high, the reference current flows to OUTA. A small leakage current (IIkg) flows across
internal junctions, and as with most semiconductor devices, doubles every 10C. The Co is caused by the
parallel combination of the NMOS switches and has a value that depends on the number of switches connected
to the output. The range of Co is 25 pF to 60 pF maximum. The equivalent output resistance (ro) varies with the
input code from 0.8R to 3R where R is the nominal value of the ladder resistor in the R-2R network.
The TLC7628C interfaces to a microprocessor through the data bus, CS, WR, and DACA/DACB control signals.
When CS and WR are both low, the analog output on this device, specified by the DACA/DACB control line,
responds to the activity on the DB0DB7 data bus inputs. In this mode, the input latches are transparent and
input data directly affects the analog output. When either the CS signal or WR signal goes high, the data on the
DB0DB7 inputs are latched until the CS and WR signals go low again. When CS is high, the data inputs are
disabled, regardless of the state of the WR signal.
The digital inputs of the TLC7628C provides TTL compatibility when operated from a supply voltage of 10.8 V
to 15.75 V.
R

REF
2R

2R

2R

2R

2R

RFB
S1

S2

S3

S8

R
OUT
AGND

DACA Data Latches and Drivers

Figure 7. Simplified Functional Circuit for DACA or DACB

RFB
R

R
REF

OUTA
1/256

COUT

Ilkg

AGND
Latch A or Latch B Loaded With 11111111

Figure 8. TLC7628 Equivalent Circuit for DACA or DACB

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TLC7628C
DUAL 8BIT MULTIPLYING
SLAS063B APRIL 1989 REVISED MARCH 2007

PRINCIPLES OF OPERATION
Table 1. Mode Selection Table
DACA/DACB

CS

WR

DACA

DACB

L
H
X
X

L
L
H
X

L
L
X
H

Write
Hold
Hold
Hold

Hold
Write
Hold
Hold

L = low level,

H = high level,

Table 2. Unipolar Binary Code

DAC LATCH CONTENTS
(see Note 7 )
MSB

ANALOG OUTPUT

LSB

11111111
10000001
10000000
01111111
00000001
00000000

X = dont care

Table 3. Bipolar (Offset Binary) Code

DAC LATCH CONTENTS
(see Note 8)
MSB

VI (255/256)
VI (129/256)
VI (128/256) = Vi /2
VI (127/256)
VI (1/256)
VI (0/256) = 0

ANALOG OUTPUT

LSB

11111111
10000001
10000000
01111111
00000001
00000000

VI (127/128)
VI (1/128)
0V
VI (1/128)
VI (127/128)
VI (128/128)

NOTES: 7. 1 LSB = (2 8)VI

8. 1 LSB = (2 7)VI

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PACKAGE OPTION ADDENDUM

www.ti.com

2-Feb-2007

PACKAGING INFORMATION
Orderable Device

Status (1)

Package
Type

Package
Drawing

Pins Package Eco Plan (2)

Qty

TLC7628CDW

ACTIVE

SOIC

DW

20

25

Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

TLC7628CDWG4

ACTIVE

SOIC

DW

20

25

Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

TLC7628CDWR

ACTIVE

SOIC

DW

20

2000 Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

TLC7628CDWRG4

ACTIVE

SOIC

DW

20

2000 Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

TLC7628CN

ACTIVE

PDIP

20

20

Pb-Free
(RoHS)

CU NIPDAU

N / A for Pkg Type

TLC7628CNE4

ACTIVE

PDIP

20

20

Pb-Free
(RoHS)

CU NIPDAU

N / A for Pkg Type

TLC7628IN

OBSOLETE

PDIP

20

TBD

Call TI

Lead/Ball Finish

MSL Peak Temp (3)

Call TI

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 1

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