Verilog for

Digital Design
Chapter 2:
Combinational Logic Design
Verilog for Digital Design
Copyright 2007
Frank Vahid and Roman Lysecky
1
AND/OR/NOT Gates AND/OR/NOT Gates
Verilog for Digital Design
Copyright 2007
Frank Vahid and Roman Lysecky
2
AND/OR/NOT Gates
Verilog Modules and Ports Verilog Modules and Ports
Y
X
F
Y
X
F
X F
module And2(X, Y, F);
input X, Y;
output F;
module Or2(X, Y, F);
input X, Y;
output F;
module Inv(X, F);
input X;
output F;
module Declares a newtype of component
p ;
...
p ;
...
p ;
...
module Declares a new type of component
Named And2" in first example above
Includes list of ports (module's inputs and outputs)
input List indicating which ports are inputs
output List indicating which ports are outputs
Each port is a bit can have value of 0, 1, or x (unknown value)
Note: Verilog already has built-in primitives for logic gates, but instructive to build them
Verilog for Digital Design
Copyright 2007
Frank Vahid and Roman Lysecky
3
vldd_ch2_And2.v vldd_ch2_Or2.v
vldd_ch2_Inv.v
AND/OR/NOT Gates
Modules and Ports Modules and Ports
Y
X
F
Y
X
F
X F
module And2(X, Y, F);
input X, Y;
output F;
module Or2(X, Y, F);
input X, Y;
output F;
module Inv(X, F);
input X;
output F;
Verilog has several dozen keywords
User cannot use keywords when naming items like modules or ports
module, input, and output are keywords above
Keywords must be lower case not UPPER CASE or a MixTure thereof
... ... ...
Keywords must be lower case, not UPPER CASE or a MixTure thereof
User-defined names Identifiers
Begin with letter or underscore (_), optionally followed by any sequence of letters, digits,
underscores, and dollar signs ($)
Valid identifiers: A, X, Hello, JXYZ, B14, Sig432, Wire 23, F1, F$2, Go $ $, , Input Valid identifiers: A, X, Hello, JXYZ, B14, Sig432, Wire_23, _F1, F$2, _Go_$_$, _, Input
Note: "_" and "Input" are valid, but unwise
Invalid identifiers: input (keyword), $ab (doesn't start with letter or underscore), 2A (doesn't start with
letter or underscore)
Note: Verilog is case sensitive. Sig432 differs from SIG432 and sig432
Verilog for Digital Design
Copyright 2007
Frank Vahid and Roman Lysecky
4
We'll initially capitalize identifiers (e.g., Sig432) to distinguish from keywords
vldd_ch2_And2.v vldd_ch2_Or2.v
vldd_ch2_Inv.v
AND/OR/NOT Gates
Modules and Ports Modules and Ports
Q: Begin a module definition for a 4x1 multiplexor
Inputs: I3, I2, I1, I0, S1, S0. Outputs: D
I0
Mux4
I0
I2
I1
I3
S1S0
D
d l M 4(I3 I2 I1 I0 S1 S0 D)
S1S0
4x1 mux
module Mux4(I3, I2, I1, I0, S1, S0, D);
input I3, I2, I1, I0;
input S1, S0;
output D;
... ...
Note that input ports above are separated into
two declarations for clarity f y
Verilog for Digital Design
Copyright 2007
Frank Vahid and Roman Lysecky
5
vldd_ch2_Mux4Beh.v
AND/OR/NOT Gates
Module Procedures always Module Proceduresalways
One way to describe a module's behavior
uses an "always" procedure
always Procedure that executes repetitively
x
F
always Procedure that executes repetitively
(infinite loop) from simulation start
@ event control indicating that statements
should only execute when values change
"(X,Y)" execute if X changes or Y changes
y
F
module And2(X, Y, F);
(X,Y) execute if X changes or Y changes
(change known as an event)
Sometimes called sensitivity list
Well say that procedure is sensitive to X and Y
"F <= X & Y;" Procedural statement that sets
wait until X or
Y changes
( , , )
input X, Y;
output F;
reg F;
l @( ) b i
F to AND of X, Y
&is built-in bit AND operator
<=assigns value to variable
reg Declares a variable data type, which
F <= x AND y
always @(X, Y) begin
F <= X & Y;
end
endmodule
holds its value between assignments
Needed for F to hold value between
assignments
Note: "reg", short for "register", is an unfortunate
name A regvariable may or may not
vldd_ch2_And2.v
Verilog for Digital Design
Copyright 2007
Frank Vahid and Roman Lysecky
6
name. A reg variable may or may not
correspond to an actual physical register. There
obviously is no register inside an AND gate.
AND/OR/NOT Gates
Module Procedures always Module Proceduresalways
Q: Given that "|" and "~" are built-in operators for OR and NOT, complete
the modules for a 2-input OR gate and a NOT gate
y
x
F
x F
module Or2(X, Y, F);
input X, Y;
output F;
module Inv(X, F);
input X;
output F;
reg F; reg F;
always @(X, Y) begin
F <= X | Y;
end
endmodule
always @(X) begin
F <= ~X;
end
endmodule endmodule endmodule
Verilog for Digital Design
Copyright 2007
Frank Vahid and Roman Lysecky
7
vldd_ch2_Or2.v
vldd_ch2_Inv.v
AND/OR/NOT Gates
Simulation and Testbenches A First Look Simulation and Testbenches A First Look
How does our new module behave?
Simulation Simulation
User provides input values, simulator
generates output values
Test vectors sequence of input values
Timescale directive is for
simulation. More later.
Waveform graphical depiction of sequence
`timescale 1 ns/1 ns
module And2(X, Y, F);
input X, Y;
t t F
1
0
X
User provides test
t
output F;
reg F;
always @(X, Y) begin
F <= X & Y;
end
Y
1
0
vectors
F
1
Simulator generates
output values based
end
endmodule
time
0
p
on HDL description
Si l t
Verilog for Digital Design
Copyright 2007
Frank Vahid and Roman Lysecky
8
Simulator
vldd_ch2_And2.v
AND/OR/NOT Gates
Simulation and Testbenches A First Look Simulation and Testbenches A First Look
Instead of drawing test vectors, user
can describe themwith HDL can describe them with HDL
`timescale 1 ns/1 ns
1
0
X
...
Y_s <= 0; X_s <= 0;
#10 0 1
module And2(X, Y, F);
input X, Y;
output F;
reg F;
0
Y
1
0
time
( )
10 20 30
#10 Y_s <= 0; X_s <= 1;
#10 Y_s <= 1; X_s <= 0;
#10 Y_s <= 1; X_s <= 1;
...
always @(X, Y) begin
F <= X & Y;
end
endmodule
F
1
0
(ns)
10 20 30
endmodule
"#10"
Tells simulator to keep present
values for 10 ns, before
executing the next statement
Verilog for Digital Design
Copyright 2007
Frank Vahid and Roman Lysecky
9
Simulator
vldd_ch2_And2.v
AND/OR/NOT Gates
Simulation and Testbenches
`timescale 1 ns/1 ns
Idea: Create new "Testbench" module that
provides test vectors to component's inputs
timescale 1 ns/1 ns
module Testbench();
reg X_s, Y_s;
wire F s;
Testbench
CompToTest
(A d2)
X
F
X_s
Y s
F_s
e
d
u
r
e
HDL testbench
wire F_s;
And2 CompToTest(X_s, Y_s, F_s);
initial begin
// Test all possible input combinations
(And2)
Y
F
Y_s
_
p
r
o
c
HDL testbench
Module with no ports
Declare reg variable for each input
port, wire for each output port
Y_s <= 0; X_s <= 0;
#10 Y_s <= 0; X_s <= 1;
#10 Y_s <= 1; X_s <= 0;
#10 Y_s <= 1; X_s <= 1;
end
Instantiate module, map variables
to ports (more in next section)
Set variable values at desired times
endmodule
More information
on next slides
Verilog for Digital Design
Copyright 2007
Frank Vahid and Roman Lysecky
10
vldd_ch2_And2TB.v
Note: CompToTest short for Component To Test
AND/OR/NOT Gates
Simulation and Testbenches
wire Declares a net data type, which
does not store its value
Vs. regdata type that stores value
`timescale 1 ns/1 ns
Vs. reg data type that stores value
Nets used for connections
Net's value determined by what it is
connected to
initial procedure that executes at
simulation start but executes only once
timescale 1 ns/1 ns
module Testbench();
reg X_s, Y_s;
wire F s;
simulation start, but executes only once
Vs. "always" procedure that also
executes at simulation start, but that
repeats
# Delay control number of time units
to delay this statement's execution
wire F_s;
And2 CompToTest(X_s, Y_s, F_s);
initial begin
// Test all possible input combinations
to delay this statements execution
relative to previous statement
`timescale compiler directive telling
compiler that from this point forward, 1
time unit means 1 ns
Validtime units s (seconds) ms
Y_s <= 0; X_s <= 0;
#10 Y_s <= 0; X_s <= 1;
#10 Y_s <= 1; X_s <= 0;
#10 Y_s <= 1; X_s <= 1;
end
Valid time units s (seconds), ms
(milliseconds), us (microseconds), ns
(nanoseconds), ps (picoseconds), and fs
(femtoseconds)
1 ns/1 ns time unit / time precision.
Precision is for internal rounding. For our
purposes, precision will be set same as
endmodule
Verilog for Digital Design
Copyright 2007
Frank Vahid and Roman Lysecky
11
p p p
time unit.
vldd_ch2_And2TB.v
Note: We appended "_s" to reg/wire identifiers to
distinguish them from ports, though not strictly necessary
AND/OR/NOT Gates
Simulation and Testbenches
P id t tb h fil t i l t Provide testbench file to simulator
Simulator generates waveforms
We can then check if behavior
looks correct
`timescale 1 ns/1 ns
module Testbench();
reg X_s, Y_s;
1
X s
wire F_s;
And2 CompToTest(X_s, Y_s, F_s);
initial begin
// Test all possible input combinations
1
0
X_s
Y_s
1
0
// Test all possible input combinations
Y_s <= 0; X_s <= 0;
#10 Y_s <= 0; X_s <= 1;
#10 Y_s <= 1; X_s <= 0;
#10 Y_s <= 1; X_s <= 1;
end
Simulator
F_s
1
0
time
(ns)
10 20 30
endmodule
Verilog for Digital Design
Copyright 2007
Frank Vahid and Roman Lysecky
12
vldd_ch2_And2TB.v
Combinational Circuits Combinational Circuits
Verilog for Digital Design
Copyright 2007
Frank Vahid and Roman Lysecky
13
Combinational Circuits
Component Instantiations Component Instantiations
Circuit A connection of modules
Also known as structure
X
F X F
A circuit is a second way to describe a
module
vs. using an always procedure, as earlier
I A f d l i
Y
Modules to be used
Instance An occurrence of a module in a
circuit
May be multiple instances of a module
e g Car's modules: tires engine windows
Module instances
K
e.g., Car's modules: tires, engine, windows,
etc., with 4 tire instances, 1 engine instance,
6 window instances, etc.
N2
N1
And2_1
Inv 1
K
P
S
W
And2_2
Inv_1
BeltWarn
Verilog for Digital Design
Copyright 2007
Frank Vahid and Roman Lysecky
14
Combinational Circuits
Module Instantiations Module Instantiations
Creating a circuit
1. Start definition of a new module
2 D l t f ti d l
`timescale 1 ns/1 ns
module BeltWarn(K, P, S, W);
2. Declare nets for connecting module
instances
N1, N2
Note: W is also a declared as a net.
input K, P, S;
output W;
wire N1, N2;
By defaults outputs are considered
wire nets unless explicitly declared as
a reg variable
3. Create module instances, create
i
And2 And2_1(K, P, N1);
Inv Inv_1(S, N2);
And2 And2_2(N1, N2, W);
endmodule
connections
Y
X
F X F
N1
And2 1
K
P
W
N2
And2_1
Inv_1
P
S
W
BeltWarn
And2_2
BeltWarn example: Turn on
warning light (w=1) if car key is
in ignition (k=1), person is
seated (p=1), and seatbelt is not
f t d ( 0)
Verilog for Digital Design
Copyright 2007
Frank Vahid and Roman Lysecky
15
BeltWarn
fastened (s=0)
vldd_ch2_BeltWarnStruct.v
Combinational Circuits
Module Instantiations
Module instantiation
statement
`timescale 1 ns/1 ns
module BeltWarn(K, P, S, W);
statement
And2 And2_1(K, P, N1);
( , , , );
input K, P, S;
output W;
wire N1, N2;
Note: Ports ordered
Connects instantiated module's
d i bl
And2 And2_1(K, P, N1);
Inv Inv_1(S, N2);
And2 And2_2(N1, N2, W);
endmodule
Note: Ports ordered
as in original And2
module definition
Name of new module instance
Must be distinct; hence And2_1 and And2_2
ports to nets and variables
endmodule
N1
And2_1
K
P
W
And2_2
Name of module to instantiate
N2
Inv_1
P
S
W
BeltWarn
Verilog for Digital Design
Copyright 2007
Frank Vahid and Roman Lysecky
16
vldd_ch2_BeltWarnStruct.v
Combinational Circuits
Module Instantiations
Q: Complete the 2x1 mux
circuit's module
`timescale 1 ns/1 ns
instantiations
module Mux2(I1, I0, S0, D);
input I1, I0;
input S0;
output D;
I0
Mux2
I1
S0
D
1. Start definition of a new
module(done)
p ;
D
I0
Inv Inv_1 (S0, N1);
And2 And2_1 (I0, N1, N2);
N1
N2
2 D l t
And2_1
Or2_1
wire N1, N2, N3;
(Draw desired circuit,
if not already done)
module (done)
D
I1
And2 And2_2 (I1, S0, N3);
Or2 Or2_1 (N2, N3, D);
endmodule
N1
N3
2. Declare nets
for internal wires
3. Create module instances
d t t
Inv 1
And2_2
S0
and connect ports
Inv_1
Verilog for Digital Design
Copyright 2007
Frank Vahid and Roman Lysecky
17
vldd_ch2_Mux2Struct.v
Combinational Circuit Structure
Simulating the Circuit g
Same testbench format for BeltWarn
module as for earlier And2 module
Testbench
CompToTest X
X_s
Y s
F s
e
d
u
r
e
`t i mescal e 1 ns/ 1 ns
modul e Test bench( ) ;
r eg X_s, Y_s;
`timescale 1 ns/1 ns
module Testbench();
reg K_s, P_s, S_s;
(And2)
Y
F
Y_s
F_s
p
r
o
c
e
b h
_ _
wi r e F_s;
And2 CompToTest ( X_s, Y_s, F_s) ;
i ni t i al begi n
/ / T t l l i bl i t bi t i
wire W_s;
BeltWarn CompToTest(K_s, P_s, S_s, W_s);
initial begin
K < 0 P < 0 S < 0
Testbench
CompToTest
(BeltWarn)
K
P
W
K_s
P_s
W_s
o
c
e
d
u
r
e
S s
/ / Test al l possi bl e i nput combi nat i ons
Y_s <= 0; X_s <= 0;
#10 Y_s <= 0; X_s <= 1;
#10 Y_s <= 1; X_s <= 0;
#10 Y_s <= 1; X_s <= 1;
end
K_s <= 0; P_s <= 0; S_s <= 0;
#10 K_s <= 0; P_s <= 1; S_s <= 0;
#10 K_s <= 1; P_s <= 1; S_s <= 0;
#10 K_s <= 1; P_s <= 1; S_s <= 1;
end
K BeltWarn
(BeltWarn)
p
r
o
S
S_s
end
endmodul e
endmodule
Verilog for Digital Design
Copyright 2007
Frank Vahid and Roman Lysecky
18
vldd_ch2_BeltWarnTB.v
P
S
W
Combinational Circuit Structure
Simulating the Circuit
`timescale 1 ns/1 ns
g
Si l t t tb h fil t bt i
timescale 1 ns/1 ns
module Testbench();
reg K_s, P_s, S_s;
wire W s;
Simulate testbench file to obtain
waveforms
_
BeltWarn CompToTest(K_s, P_s, S_s, W_s);
initial begin
K_s <= 0; P_s <= 0; S_s <= 0;
#10 0 1 S 0
1
1
0
K_s
#10 K_s <= 0; P_s <= 1; S_s <= 0;
#10 K_s <= 1; P_s <= 1; S_s <= 0;
#10 K_s <= 1; P_s <= 1; S_s <= 1;
end
endmodule
1
0
P_s
S_s
1
0
endmodule
Simulator
W_s
1
0
time (ns)
10 20
30
Verilog for Digital Design
Copyright 2007
Frank Vahid and Roman Lysecky
19
vldd_ch2_BeltWarnTB.v
Combinational Circuit Structure
Simulating the Circuit
`timescale 1 ns/1 ns
g
More on testbenches
module Testbench();
reg K_s, P_s, S_s;
wire W_s;
More on testbenches
Note that a single module instantiation
statement used
reg and wire declarations (K_s, P_s,
BeltWarn CompToTest(K_s, P_s, S_s, W_s);
initial begin
K_s <= 0; P_s <= 0; S_s <= 0;
#10 K s <= 0; P s <= 1; S s <= 0;
g ( _ _
S_s, W_s) used because procedure
cannot access instantiated module's
ports directly
I t d l d i
# _ ; _ ; _ ;
#10 K_s <= 1; P_s <= 1; S_s <= 0;
#10 K_s <= 1; P_s <= 1; S_s <= 1;
end
endmodule
Inputs declared as regs so can assign
values (which are held between
assignments)
Note module instantiation statement
and procedure can both appear in one
module
Verilog for Digital Design
Copyright 2007
Frank Vahid and Roman Lysecky
20
vldd_ch2_BeltWarnTB.v
Top-Down Design Combinational Behavior to
Structure Structure
Verilog for Digital Design
Copyright 2007
Frank Vahid and Roman Lysecky
21
Top-Down Design Combinational Behavior to Structure
Designer may initially know system behavior, but not structure
BeltWarn: W = KPS'
Top-down design
Capture behavior and simulate Capture behavior, and simulate
Capture structure (circuit), simulate again
Gets behavior right first, unfettered by complexity of creating structure
Capture
behavior
Simulate
W s
P_s
S_s
K_s
W_s
Capture
structure
Simulate
W s
P_s
S_s
K_s
Should be
the same
Verilog for Digital Design
Copyright 2007
Frank Vahid and Roman Lysecky
22
W_s
Top-Down Design Combinational Behavior to Structure
Always Procedures with Assignment Statements y g
How describe behavior? One way:
Use an always procedure
`timescale 1 ns/1 ns
module BeltWarn(K, P, S, W);
Sensitive to K, P, and S
Procedure executes only if change
occurs on any of those inputs
Simplest procedure uses one
input K, P, S;
output W;
reg W;
always @(K, P, S) begin
W < K & P & S Simplest procedure uses one
assignment statement
Simulate using testbench (same as
shown earlier) to get waveforms
W <= K & P & ~S;
end
endmodule
1
shown earlier) to get waveforms
Top-down design
Proceed to capture structure,
simulate again using same
1
0
P_s
S s
1
0
K_s
simulate again using same
testbench result should be the
same waveforms
W_s
1
0
S_s
0
time
(ns)
10 20 30 40
Verilog for Digital Design
Copyright 2007
Frank Vahid and Roman Lysecky
23
vldd_ch2_BeltWarnBeh.v
(ns)
Top-Down Design Combinational Behavior to Structure
Procedures with Assignment Statements
Procedural assignment statement
`timescale 1 ns/1 ns
Assigns value to variable
Right side may be expression of
operators
Built in bit operators include
module BeltWarn(K, P, S, W);
input K, P, S;
output W;
reg W;
Built-in bit operators include
& AND | OR ~ NOT
^ XOR ~^ XNOR
always @(K, P, S) begin
W <= K & P & ~S;
end
endmodule
Q: Create an always procedure to
compute:
F = C'H + CH'
vldd_ch2_BeltWarnBeh.v
Answer 1:
A 2
Answer 1:
al ways @( C, H) begi n
F <= ( ~C&H) | ( C&~H) ;
end
Answer 2:
al ways @( C, H)
begi n
F <= C ^ H;
end
Verilog for Digital Design
Copyright 2007
Frank Vahid and Roman Lysecky
24
Top-Down Design Combinational Behavior to Structure
Procedures with Assignment Statements
P d h lti l
` /
Procedure may have multiple
assignment statements
`timescale 1 ns/1 ns
module TwoOutputEx(A, B, C, F, G);
input A, B, C;
output F G; output F, G;
reg F, G;
always @(A, B, C) begin
F <= (B & B) | ~C;
G <= (A & B) | (B & C);
end
endmodule
vldd_ch2_TwoOutputBeh.v
Verilog for Digital Design
Copyright 2007
Frank Vahid and Roman Lysecky
25
Top-Down Design Combinational Behavior to Structure
Procedures with If-Else Statements
Process may use if-else statements Process may use if else statements
(a.k.a. conditional statements)
if (expression)
If expression is true (evaluates to
`timescale 1 ns/1 ns
module BeltWarn(K, P, S, W);
p (
nonzero value), execute
corresponding statement(s)
If false (evaluates to 0), execute
elses statement (else part is
input K, P, S;
output W;
reg W;
always @(K P S) begin
elses statement (else part is
optional)
Example shows use of operator ==
logical equality, returns true/false
(actually returns 1 or 0)
always @(K, P, S) begin
if ((K & P & ~S) == 1)
W <= 1;
else
W <= 0;
end
(actually, returns 1 or 0)
True is nonzero value, false is zero
vldd ch2 BeltWarnBehIf v
endmodule
Verilog for Digital Design
Copyright 2007
Frank Vahid and Roman Lysecky
26
vldd_ch2_BeltWarnBehIf.v
Top-Down Design Combinational Behavior to Structure
Procedures with If-Else Statements
More than two possibilities
Handled by stringing if-else
statements together
`timescale 1 ns/1 ns
module Mux4(I3, I2, I1, I0, S1, S0, D);
statements together
Known as if-else-if construct
Example: 4x1 mux behavior
Suppose S1S0 change to 01
( , , , , , , );
input I3, I2, I1, I0;
input S1, S0;
output D;
reg D;
Suppose S1S0 change to 01
ifs expression is false
else's statement executes,
which is an if statement
always @(I3, I2, I1, I0, S1, S0)
begin
if (S1==0 && S0==0)
D <= I0;
else if (S1==0 && S0==1)
Suppose
S1S0
change to
01
whose expression is true
else if (S1==0 && S0==1)
D <= I1;
else if (S1==1 && S0==0)
D <= I2;
else
D <= I3;
01
Note: The following indentation shows if
statement nesting, but is unconventional:
if (S1==0 && S0==0)
end
endmodule
if (S1==0 && S0==0)
D <= I0;
else
if (S1==0 && S0==1)
D <= I1;
else
&& logical AND
& : bit AND (operands are bits, returns bit)
&& : logical AND (operands are true/false
Verilog for Digital Design
Copyright 2007
Frank Vahid and Roman Lysecky
27
vldd_ch2_Mux4Beh.v
if (S1==1 && S0==0)
D <= I2;
else
D <= I3;
g ( p f
values, returns true/false)
Top-Down Design Combinational Behavior to Structure
Procedures with If-Else Statements
/
Q: Create procedure describing
behavior of a 2x4 decoder using if-
`timescale 1 ns/1 ns
module Dcd2x4(I1, I0, D3, D2, D1, D0);
input I1, I0;
output D3 D2 D1 D0;
behavior of a 2x4 decoder using if
else-if construct
output D3, D2, D1, D0;
I0
I1
D0
D1
D2
reg D3, D2, D1, D0;
always @(I1, I0)
begin
if (I1==0 && I0==0)
I1 D2
D3
2x4 decoder
( )
begin
D3 <= 0; D2 <= 0;
D1 <= 0; D0 <= 1;
end
else if (I1==0 && I0==1)
Order of assignment statementsdoes begin
D3 <= 0; D2 <= 0;
D1 <= 1; D0 <= 0;
end
else if (I1==1 && I0==0)
begin
Order of assignment statements does
not matter.
Placing two statements on one line
doesnot matter
begin
D3 <= 0; D2 <= 1;
D1 <= 0; D0 <= 0;
end
else
begin
does not matter.
To execute multiple statements if
expression is true, enclose them
between"begin" and"end"
Verilog for Digital Design
Copyright 2007
Frank Vahid and Roman Lysecky
28
vldd_ch2_Dcd2x4Beh.v
g
D3 <= 1; D2 <= 0;
D1 <= 0; D0 <= 0;
end
end
endmodule
between begin and end
Slide 28
F V1 Discuss how last else could have been "else if (I1==1 && I0==1)" ?
F V, 2/22/2007
Top-Down Design Combinational Behavior to Structure
Top-down design
`timescale 1 ns/1 ns
module BeltWarn(K, P, S, W);
input K, P, S;
t t W
p g
Capture behavior, and simulate
Capture structure using a second
module, and simulate
output W;
reg W;
always @(K, P, S) begin
W <= K & P & ~S;
end
`timescale 1 ns/1 ns
end
endmodule
Capture
behavior
Simulate
W
P_s
S_s
K_s
vldd_ch2_BeltWarnBeh.v
module BeltWarn(K, P, S, W);
input K, P, S;
output W;
W_s
Capture
structure
Simulate
W
P_s
S_s
K_s
Should be
the same
wire N1, N2;
And2 And2_1(K, P, N1);
Inv Inv_1(S, N2);
And2 And2_2(N1, N2, W);
W_s
Verilog for Digital Design
Copyright 2007
Frank Vahid and Roman Lysecky
29
vldd_ch2_BeltWarnStruct.v
_
endmodule
Top-Down Design Combinational Behavior to Structure
Common Pitfall Missing Inputs from Event Control Expression g p p
Pitfall Missing inputs from event
controls sensitivity list when describing
combinational behavior
Results in sequential behavior
Wrong 4x1 mux example
`timescale 1 ns/1 ns
module Mux4(I3, I2, I1, I0, S1, S0, D);
Missing I3-I0 from
sensitivitylist
Has memory
No compiler error
J ust not a mux
input I3, I2, I1, I0;
input S1, S0;
output D;
reg D;
always @(S1 S0)
sensitivity list
Recomputes D if S1
or S0 changes
Fails to recompute D if I3
always @(S1, S0)
begin
if (S1==0 && S0==0)
D <= I0;
else if (S1==0 && S0==1)
D <= I1;
I3
I1
(or I2, I1, I0) changes
Reminder
Combinational behavior: Output
value is purely a function of the
present input values
else if (S1==1 && S0==0)
D <= I2;
else
D <= I3;
end
d d l
S1
S0
3
present input values
Sequential behavior: Output
value is a function of present and
past input values, i.e., the system
has memory
Verilog for Digital Design
Copyright 2007
Frank Vahid and Roman Lysecky
30
vldd_ch2_Mux4Wrong.v
endmodule
D
Top-Down Design Combinational Behavior to Structure
Common Pitfall Missing Inputs from Event Control Expression g p p
Verilog provides mechanism to help avoid
this pitfall
@* implicit event control expression
Automatically adds all nets and variables
that are read by the controlled statement or
statement group
`timescale 1 ns/1 ns
module Mux4(I3, I2, I1, I0, S1, S0, D);
statement group
Thus, @* in example is equivalent to
@(S1,S0,I0,I1,I2,I3)
@(*) also equivalent
input I3, I2, I1, I0;
input S1, S0;
output D;
reg D;
always @* always @*
begin
if (S1==0 && S0==0)
D <= I0;
else if (S1==0 && S0==1)
D <= I1;
else if (S1==1 && S0==0)
D <= I2;
else
D <= I3;
end
d d l
Verilog for Digital Design
Copyright 2007
Frank Vahid and Roman Lysecky
31
endmodule
Top-Down Design Combinational Behavior
to Structure
Common Pitfall Output not Assigned on Every Pass
`timescale 1 ns/1 ns
module Dcd2x4(I1, I0, D3, D2, D1, D0);
i t I1 I0
p g y
Pitfall Failing to assign every output
on every pass through the procedure
for combinational behavior
input I1, I0;
output D3, D2, D1, D0;
reg D3, D2, D1, D0;
always @(I1, I0)
begin
for combinational behavior
Results in sequential behavior
Referred to as inferred latch (more later)
Wrong 2x4 decoder example
begin
if (I1==0 && I0==0)
begin
D3 <= 0; D2 <= 0;
D1 <= 0; D0 <= 1;
end
g p
Has memory
No compiler error
J ust not a decoder
else if (I1==0 && I0==1)
begin
D3 <= 0; D2 <= 0;
D1 <= 1; D0 <= 0;
end
l if (I1 1 && I0 0)
Missing assignments to
outputs D2, D1, D0
else if (I1==1 && I0==0)
begin
D3 <= 0; D2 <= 1;
D1 <= 0; D0 <= 0;
end
else if (I1==1 && I0==1)
I1I0=10 D2=1,
others=0
I1I0=11 D3=1,
but D2 stays same
else if (I1 1 && I0 1)
begin
D3 <= 1;
end
// Note: missing assignments
// to every output in last "else if"
D3
I0
I1
Verilog for Digital Design
Copyright 2007
Frank Vahid and Roman Lysecky
32
end
endmodule
vldd_ch2_Dcd2x4Wrong.v
D2
Top-Down Design Combinational Behavior to Structure
Common Pitfall Output not Assigned on Every Pass p g y
Same pitfall often occurs due to not considering all
possible input combinations
if (I1==0 && I0==0)
begin
D3 <= 0; D2 <= 0;
D1 < 0 D0 < 1 D1 <= 0; D0 <= 1;
end
else if (I1==0 && I0==1)
begin
D3 <= 0; D2 <= 0;
D1 <= 1; D0 <= 0; D1 < 1; D0 < 0;
end
else if (I1==1 && I0==0)
begin
D3 <= 0; D2 <= 1;
D1 <= 0; D0 <= 0;
Last "else" missing, so not all
input combinationsarecovered
end
input combinations are covered
(i.e., I1I0=11 not covered)
Verilog for Digital Design
Copyright 2007
Frank Vahid and Roman Lysecky
33
Hierarchical Circuits
Verilog for Digital Design
Copyright 2007
Frank Vahid and Roman Lysecky
34
Hierarchical Circuits
Using Modules Instances in Another Module Using Modules Instances in Another Module
Module can be used as instance in a new module
As seen earlier: And2 module used as instance in BeltWarn module
C ti B ltW d l b d i t i th Can continue: BeltWarn module can be used as instance in another
module
And so on
Hierarchy powerful mechanism for managing complexity e a c y po e u ec a s o a ag g co pe y
BeltWarn
WindowLock
Display
BeltWarn
Y
X
F
Verilog for Digital Design
Copyright 2007
Frank Vahid and Roman Lysecky
35
Hierarchical Circuits
Using Module Instances in Another Module g
4-bit 2x1 mux example
`timescale 1 ns/1 ns
module Mux2(I1 I0 S0 D);
D
I0
N1
N2
2x1 mux circuit from earlier
module Mux2(I1, I0, S0, D);
input I1, I0;
input S0;
output D;
I0
S0
I1
Mux2
D
D
I1
N1
N3
wire N1, N2, N3;
Inv Inv_1 (S0, N1);
And2 And2_1 (I0, N1, N2);
And2 And2_2 (I1, S0, N3);
O 2 O 2 1 (N2 N3 D)
Mux2
S0
Or2 Or2_1 (N2, N3, D);
endmodule
Verilog for Digital Design
Copyright 2007
Frank Vahid and Roman Lysecky
36
vldd_ch2_Mux2Struct.v
Hierarchical Circuits
Using Module Instances in Another Module g
4-bit 2x1 mux example
Createfour Mux2
`timescale 1 ns/1 ns
M 2 4b
A3 Create four Mux2
instances
module Mux2_4b(A3, A2, A1, A0,
B3, B2, B1, B0,
S0,
C3, C2, C1, C0);
I0
D
A3
Mux2
Mux2_4b
C3
A3
A2
A1
A0
B3
C3
C2
C1
C0
Mux2_4b
input A3, A2, A1, A0;
input B3, B2, B1, B0;
input S0;
output C3, C2, C1, C0;
M 2 M 2 3 (B3 A3 S0 C3)
0
S0
I1
D
I0
S0
I1
D
A3
B3
S0
A2
B2
Mux2
C3
C2
B2
B1
B0
Mux2 Mux2_3 (B3, A3, S0, C3);
Mux2 Mux2_2 (B2, A2, S0, C2);
Mux2 Mux2_1 (B1, A1, S0, C1);
Mux2 Mux2_0 (B0, A0, S0, C0);
endmodule
S0
I0
S0
I1
D
A1
B1
Mux2
C1
Can then use
Mux2_4b in
another modules
circuit andsoon
endmodule
I0
S0
I1
D
A0
B0
s0
Mux2
C0
circuit, and so on ...
Verilog for Digital Design
Copyright 2007
Frank Vahid and Roman Lysecky
37
vldd_ch2_Mux2_4bStruct.v
Built-In Gates Built In Gates
Verilog for Digital Design
Copyright 2007
Frank Vahid and Roman Lysecky
38
Built-In Gates
We previously defined AND, OR, and
NOT gates
Verilog has several built-in gates that
can be instantiated
and, or, nand, nor, xor, xor
One output, one or more inputs
The output is always the first in the list
of port connections
Example of 4-input AND:
`timescale 1 ns/1 ns
module BeltWarn(K, P, S, W);
input K, P, S;
Example of 4-input AND:
and a1 (out, in1, in2, in3, in4);
not is another built-in gate
Earlier BeltWarn example using built
output W;
wire N1, N2;
and And_1(N1, K, P);
not Inv 1(N2 S);
Earlier BeltWarn example using built-
in gates
Note that gate size is automatically
determinedby the port connection list
not Inv_1(N2, S);
and And_2(W, N1, N2);
endmodule
Verilog for Digital Design
Copyright 2007
Frank Vahid and Roman Lysecky
39
determined by the port connection list
vldd_ch2_BeltWarnGates.v