1 Power Integrity
1 Power Integrity
1 Power Integrity
Acknowledgement
Acknowledgement
Root Cause of PI
Lv V=LvdI/dt
Lv
Charge
Discharge
IN
OUT
Lg V
LgdI/dt
V=LgdI/dt
CPU/DSP/Switching chip are the class of
low-voltage high current applications
Lg
@ DC Open
Capacitive
behavior before
resonance
I
PWR
GND
@ HF Behave as capacitive
p
V f I f Z f
I Z DC I1Z PDN @ HF
Vdd
+/-5%Vdd
I1
ZPDN
PWR
Idisp
GND
Resonance/Anti-resonance
Anti resonance
Anti-resonance
Resonance
V
Z
I
I max
Vdd ripple
ZT
50% I max
Bypass/Decoupling Capacitors
Switching circuit requires current to charge the load
If the output impedance is too high, then VRM is unable to
respond well (VRM output impedance exceeds the desired
impedance)
External capacitors store charge. They bypass the VRM
and supply the current to the switching circuit
The bypass capacitors are also called decoupling
capacitors (decouple the VRM from the switching circuit)
ESR
ESL
Decap C
Equivalent circuit of
p g capacitor
p
decoupling
Capacitive
-20dB/decade
Shunt Model
T
Terminated
i t d w// 50
Series Model
Terminated w/
GND
Ideal Cap
Inductive
+20dB/decade
ESR
Decoupling Capacitors
Decouple the VRM from the switching circuit
Provides a low impedance path
VRM
Low frequency
Bulk
capacitors
Ceramic
decoupling
capacitors
PCB
planes
High frequency
1 S11
Z 0
Z
1 S11
2-Port Measurement
S12
Z11 25
1 S12
Example 1
Calculated Z-Profile
Bare board
5 cm
Area: A
d =10 mil
De-Cap: 1uF
At 300 kHz, Zc = 1/(C) = 0.5305
Measurement:
Board W/ Decap De-embedded
Example 2: DDR3-1600
U101
VRM
U201
U204
0.957
50% I max
0.5 0.21
Correlation
Ultra Low Impedance Measurement
S 21
2-Port measurement to capture the ultra low impedance Z 25
1 S 21
400 MHz
DQ1
VDD @ RAM
W/ Decap
VDD @ RAM
W/O Decap
VDD swing from 1.42 ~ 1.55, within the spec (1.5 +/- 6.67%)
VDD swing from 1.45~ 1.55, within the spec (1.5 +/- 6.67%)
Conclusions
Target impedance is the main parameter to design the
power plane
Ultra-low impedance measurement and proper embedded
technique should be applied to obtain the good correlation
Sigrity PowerSI and SystemSI provides an user-friendly
workflow to speed up the design flow
References
M. Swaminathan and A. E. Engin, Power integrity modeling
and design for semiconductors and systems, NJ: PrenticeHall 2007
Hall,
Agilent ultra-low impedance measurements using 2-port
meas rement application note
measurement,
note, 2007