ADXL375 Example
ADXL375 Example
ADXL375 Example
Data Sheet
FEATURES
GENERAL DESCRIPTION
APPLICATIONS
Concussion and head trauma detection
High force event detection
ADXL375
VDD I/O
POWER
MANAGEMENT
ADC
3-AXIS
SENSOR
DIGITAL
FILTER
32-LEVEL
FIFO
CONTROL
AND
INTERRUPT
LOGIC
INT1
INT2
SDA/SDI/SDIO
SERIAL I/O
SDO/ALT
ADDRESS
SCL/SCLK
CS
GND
11669-001
SENSE
ELECTRONICS
Figure 1.
Rev. B
Document Feedback
ADXL375
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
I2C Mode...................................................................................... 18
Specifications..................................................................................... 3
Self-Test........................................................................................ 12
Interrupts ......................................................................................... 13
REVISION HISTORY
4/14Rev. A to Rev. B
Changes to Figure 24 ...................................................................... 15
Changes to Register 0x1E, Register 0x1F, Register 0x20OFSX,
OFSY, OFSZ (Read/Write) Section .............................................. 21
9/13Rev. 0 to Rev. A
Added MEMS to Product Title ....................................................... 1
8/13Revision 0: Initial Version
Rev. B | Page 2 of 32
Data Sheet
ADXL375
SPECIFICATIONS
TA = 25C, VS = 2.5 V, VDD I/O = 2.5 V, acceleration = 0 g, CS = 10 F tantalum, CI/O = 0.1 F, output data rate (ODR) = 800 Hz, unless
otherwise noted.
Table 1.
Parameter
SENSOR INPUT
Measurement Range2
Nonlinearity
Cross-Axis Sensitivity3
SENSITIVITY
Sensitivity at XOUT, YOUT, ZOUT2, 4
Scale Factor at XOUT, YOUT, ZOUT2, 4
Sensitivity Change Due to Temperature
0 g OFFSET
0 g Output for XOUT, YOUT, ZOUT
0 g Offset vs. Temperature
NOISE
OUTPUT DATA RATE AND BANDWIDTH5
Output Data Rate (ODR)4, 6
SELF-TEST7
Output Change in Z-Axis
POWER SUPPLY
Operating Voltage Range (VS)
Interface Voltage Range (VDD I/O)
Supply Current
Measurement Mode
Standby Mode
Turn-On and Wake-Up Time8
TEMPERATURE
Operating Temperature Range
WEIGHT
Device Weight
Test Conditions/Comments
Each axis
Min
Typ1
180
200
0.25
2.5
18.4
44
20.5
49
0.02
22.6
54
LSB/g
mg/LSB
%/C
6000
400
10
5
+6000
mg
mg/C
mg/Hz
3200
Hz
Max
Unit
g
%
%
Each axis
6.4
2.0
1.7
ODR 100 Hz
ODR 3 Hz
2.5
1.8
3.6
VS
145
35
0.1
1.4
ODR = 3200 Hz
40
A
A
A
ms
+85
30
V
V
C
mg
Typical specifications are for at least 68% of the population of parts and are based on the worst case of mean 1 distribution, except for sensitivity, which represents
the target value.
2
Minimum and maximum specifications represent the worst case of mean 3 distribution and are not guaranteed in production.
3
Cross-axis sensitivity is defined as coupling between any two axes.
4
The output format for the 1600 Hz and 3200 Hz output data rates is different from the output format for the other output data rates. For more information, see the
Data Formatting at Output Data Rates of 3200 Hz and 1600 Hz section.
5
Bandwidth is the 3 dB frequency and is half the output data rate: bandwidth = ODR/2.
6
Output data rates < 6.25 Hz exhibit additional offset shift with increased temperature.
7
Self-test change is defined as the output (g) when the SELF_TEST bit = 1 (DATA_FORMAT register, Address 0x31) minus the output (g) when the SELF_TEST bit = 0.
Due to device filtering, the output reaches its final value after 4 when enabling or disabling self-test, where = 1/(data rate). For the self-test to operate correctly,
the part must be in normal power operation (LOW_POWER bit = 0 in the BW_RATE register, Address 0x2C).
8
Turn-on and wake-up times are determined by the user-defined bandwidth. At a 100 Hz data rate, the turn-on and wake-up times are each approximately 11.1 ms. For
other data rates, the turn-on and wake-up times are each approximately + 1.1 ms, where = 1/(data rate).
1
Rev. B | Page 3 of 32
ADXL375
Data Sheet
Table 2.
Parameter
Acceleration, Any Axis
Unpowered
Powered
VS
VDD I/O
Digital Pins
Output Short-Circuit Duration
(Any Pin to Ground)
Temperature Range
Powered
Storage
Rating
10,000 g
10,000 g
0.3 V to +3.9 V
0.3 V to +3.9 V
0.3 V to VDD I/O + 0.3 V or 3.9 V,
whichever is less
Indefinite
ESD CAUTION
40C to +105C
40C to +105C
Rev. B | Page 4 of 32
JA
150
JC
85
Unit
C/W
Data Sheet
ADXL375
SOLDERING PROFILE
Figure 2 and Table 4 provide information about the recommended soldering profile.
CRITICAL ZONE
TL TO TP
tP
TP
tL
TSMAX
TSMIN
tS
RAMP-DOWN
PREHEAT
11669-015
TEMPERATURE
RAMP-UP
TL
t25C TO PEAK
TIME
Sn63/Pb37
3C/sec maximum
Pb-Free
3C/sec maximum
100C
150C
60 sec to 120 sec
3C/sec maximum
183C
60 sec to 150 sec
240C +0C/5C
10 sec to 30 sec
6C/sec maximum
6 minutes maximum
150C
200C
60 sec to 180 sec
3C/sec maximum
217C
60 sec to 150 sec
260C +0C/5C
20 sec to 40 sec
6C/sec maximum
8 minutes maximum
Rev. B | Page 5 of 32
ADXL375
Data Sheet
GND
RESERVED
14
13
SDA/SDI/SDIO
12
SDO/ALT ADDRESS
11
RESERVED
10
NC
INT2
INT1
+X
GND
GND
VS
+Y
+Z
11669-002
CS
NOTES
1. NC = NOT INTERNALLY CONNECTED.
Mnemonic
VDD I/O
GND
RESERVED
GND
GND
VS
CS
INT1
INT2
NC
RESERVED
SDO/ALT ADDRESS
SDA/SDI/SDIO
SCL/SCLK
Description
Digital Interface Supply Voltage.
Ground. This pin must be connected to ground.
Reserved. This pin must be connected to VS or left open.
Ground. This pin must be connected to ground.
Ground. This pin must be connected to ground.
Supply Voltage.
Chip Select.
Interrupt 1 Output.
Interrupt 2 Output.
Not Internally Connected.
Reserved. This pin must be connected to ground or left open.
SPI 4-Wire Serial Data Output (SDO)/I2C Alternate Address Select (ALT ADDRESS).
I2C Serial Data (SDA)/SPI 4-Wire Serial Data Input (SDI)/SPI 3-Wire Serial Data Input and Output (SDIO).
I2C Serial Communications Clock (SCL)/SPI Serial Communications Clock (SCLK).
Rev. B | Page 6 of 32
Data Sheet
ADXL375
1.0
0.6
20
15
10
0.4
0.2
0
0.2
0.4
0.8
1.0
50
3.0
2.6
2.2
1.8
1.4
1.0
0.6
0.2
0.2
0.6
1.0
1.4
1.8
2.2
2.6
3.0
11669-203
0.6
5
11669-200
0.8
35
20
10
25
40
55
TEMPERATURE (C)
70
85
100
OFFSET (g)
25
1.0
0.6
15
10
0.4
0.2
0
0.2
0.4
0.8
1.0
50
3.0
2.6
2.2
1.8
1.4
1.0
0.6
0.2
0.2
0.6
1.0
1.4
1.8
2.2
2.6
3.0
11669-204
0.6
5
11669-201
0.8
20
35
20
10
25
40
55
TEMPERATURE (C)
70
85
100
OFFSET (g)
16
1.0
0.8
0.6
12
10
8
6
0.4
0.2
0
0.2
0.4
4
11669-202
0.8
1.0
50
3.0
2.6
2.2
1.8
1.4
1.0
0.6
0.2
0.2
0.6
1.0
1.4
1.8
2.2
2.6
11669-205
0.6
3.0
14
35
20
10
25
40
55
TEMPERATURE (C)
70
85
100
OFFSET (g)
Rev. B | Page 7 of 32
ADXL375
Data Sheet
25
23.0
SENSITIVITY (LSB/g)
22.0
15
10
21.5
21.0
20.5
20.0
19.5
18.5
18.0
50
18.0
18.2
18.4
18.6
18.8
19.0
19.2
19.4
19.6
19.8
20.0
20.2
20.4
20.6
20.8
21.0
21.2
21.4
21.6
21.8
22.0
22.2
22.4
22.6
22.8
23.0
11669-209
19.0
11669-206
22.5
20
35
20
10
25
40
55
70
85
100
TEMPERATURE (C)
SENSITIVITY (LSB/g)
25
23.0
20
SENSITIVITY (LSB/g)
22.0
15
10
21.5
21.0
20.5
20.0
19.5
18.5
18.0
50
18.0
18.2
18.4
18.6
18.8
19.0
19.2
19.4
19.6
19.8
20.0
20.2
20.4
20.6
20.8
21.0
21.2
21.4
21.6
21.8
22.0
22.2
22.4
22.6
22.8
23.0
11669-210
19.0
11669-207
22.5
35
20
10
25
40
55
70
85
100
TEMPERATURE (C)
SENSITIVITY (LSB/g)
23.0
16
22.5
22.0
SENSITIVITY (LSB/g)
12
10
8
6
21.5
21.0
20.5
20.0
19.5
4
11669-208
11669-211
19.0
18.5
18.0
50
18.0
18.2
18.4
18.6
18.8
19.0
19.2
19.4
19.6
19.8
20.0
20.2
20.4
20.6
20.8
21.0
21.2
21.4
21.6
21.8
22.0
22.2
22.4
22.6
22.8
23.0
14
35
20
10
25
40
55
70
85
100
TEMPERATURE (C)
SENSITIVITY (LSB/g)
Rev. B | Page 8 of 32
Data Sheet
ADXL375
200
20
15
10
150
100
50
5
11669-212
0
2.0
80
85
90
95
100
105
110
115
120
125
130
135
140
145
150
155
160
165
170
175
180
2.4
2.8
11669-215
25
3.6
3.2
200
X-AXIS, DUT1
X-AXIS, DUT2
Y-AXIS, DUT1
Y-AXIS, DUT2
Z-AXIS, DUT1
Z-AXIS, DUT2
20
150
OUTPUT (g)
15
10
100
0
100
110
120
130
140
150
160
170
180
190
11669-216
50
5
11669-213
25
200
50
100
150
200
Figure 17. Current Consumption at 25C, 100 Hz Output Data Rate, VS = 2.5 V
160
1.2
1.0
NORMALIZED SENSITIVITY
120
100
80
60
40
0.8
X-AXIS
Y-AXIS
Z-AXIS
0.6
0.4
0
10
1.60 3.12 6.25 12.50 25 50 100 200 400 800 1600 3200
OUTPUT DATA RATE (Hz)
11669-217
0.2
20
11669-214
140
100
FREQUENCY (Hz)
Rev. B | Page 9 of 32
1000
ADXL375
Data Sheet
THEORY OF OPERATION
The ADXL375 is a complete 3-axis acceleration measurement
system with a measurement range of 200 g. It measures both
dynamic acceleration resulting from motion or shock and static
acceleration, such as gravity.
Deflection of the structure is measured using differential capacitors that consist of independent fixed plates and plates attached
to the moving mass. Acceleration deflects the proof mass and
unbalances the differential capacitor, resulting in a sensor output
whose amplitude is proportional to acceleration. Phase sensitive
demodulation is used to determine the magnitude and polarity
of the acceleration.
POWER SEQUENCING
Power can be applied to VS or VDD I/O in any sequence without
damaging the ADXL375. Table 7 provides a description of all
the power modes. The interface voltage level is set using the
interface supply voltage, VDD I/O, which must be present to ensure
that the ADXL375 does not create a conflict on the communication bus. For single-supply operation, VDD I/O can be the same
as the main supply, VS. In a dual-supply application, however,
VDD I/O can differ from VS to accommodate the desired interface
voltage, as long as VS is greater than or equal to VDD I/O.
After VS is applied, the device enters standby mode. In standby
mode, power consumption is minimized; the device waits for
VDD I/O to be applied and for the command to enter measurement
mode. This command can be initiated by setting the measure bit
(Bit D3) in the POWER_CTL register (Address 0x2D).
Output Data
Rate (Hz)
3200
1600
800
400
200
100
50
25
12.5
6.25
3.13
1.56
0.78
0.39
0.20
0.10
Bandwidth
(Hz)
1600
800
400
200
100
50
25
12.5
6.25
3.13
1.56
0.78
0.39
0.20
0.10
0.05
IDD (A)
145
90
140
140
140
140
90
60
50
40
35
35
35
35
35
35
VS
Off
VDD I/O
Off
Bus Disabled
On
Off
Bus Enabled
Standby or Measurement
Off
On
On
On
Description
The device is completely off, but it is still possible for the device to create a conflict on the
communication bus.
The device is on in standby mode, but communication is unavailable and the device can create
a conflict on the communication bus. Minimize the duration of the bus disabled state during
power-up to prevent a conflict on the communication bus.
No functions are available, but the device does not create a conflict on the communication bus.
At power-up, the device is in standby mode, awaiting a command to enter measurement
mode, and all sensor functions are off. After the device is instructed to enter measurement
mode, all sensor functions are available.
Rev. B | Page 10 of 32
Data Sheet
ADXL375
FIFO BUFFER
Output Data
Rate (Hz)
400
200
100
50
25
12.5
Bandwidth
(Hz)
200
100
50
25
12.5
6.25
IDD (A)
90
60
50
45
40
35
FIFO
Mode
Bypass
FIFO
Stream
Trigger
Description
FIFO buffer is bypassed.
FIFO buffer collects up to 32 samples and
then stops collecting data, collecting new
data only when the buffer is not full.
FIFO buffer holds the last 32 samples.
When the buffer is full, the oldest data
is overwritten with newer data.
FIFO buffer holds the last samples before
the trigger event and continues to collect
data until full. New data is collected only
when the buffer is not full.
For data rates not shown in Table 8, the use of low power mode
does not provide any advantage over normal power mode. Therefore, it is recommended that low power mode be used only for
the data rates shown in Table 8.
Autosleep Mode
In bypass mode, the FIFO buffer is not operational and, therefore, remains empty.
2.
Standby Mode
For even lower power operation, standby mode can be used. In
standby mode, current consumption is reduced to 0.1 A (typical).
In this mode, no measurements are made, but the contents of the
FIFO buffer are preserved. To enter standby mode, clear the
measure bit (Bit D3) in the POWER_CTL register (Address 0x2D).
Bypass Mode
FIFO Mode
In FIFO mode, data from measurements of the x-, y-, and z-axes
is stored in the FIFO buffer. When the number of samples in the
FIFO buffer equals the level specified by the samples bits of the
FIFO_CTL register (Address 0x38), the watermark interrupt is
set (see the Watermark Bit section). The FIFO buffer continues
to accumulate samples until it is full (32 samples from measurements of the x-, y-, and z-axes) and then stops collecting data.
After the FIFO buffer stops collecting data, the device continues
to operate; therefore, features such as shock detection can be used
after the FIFO buffer is full. The watermark interrupt bit remains
set until the number of samples in the FIFO buffer is less than
the value stored in the samples bits of the FIFO_CTL register.
Stream Mode
In stream mode, data from measurements of the x-, y-, and z-axes
is stored in the FIFO buffer. When the number of samples in the
FIFO buffer equals the level specified by the samples bits of the
FIFO_CTL register (Address 0x38), the watermark interrupt is set
(see the Watermark Bit section). The FIFO buffer continues to
accumulate samples; the buffer stores the latest 32 samples from
measurements of the x-, y-, and z-axes, discarding older data as
new data arrives. The watermark interrupt bit remains set until
the number of samples in the FIFO buffer is less than the value
stored in the samples bits of the FIFO_CTL register.
Rev. B | Page 11 of 32
ADXL375
Data Sheet
Trigger Mode
In trigger mode, the FIFO buffer accumulates samples, storing
the latest 32 samples from measurements of the x-, y-, and z-axes.
After a trigger event occurs, an interrupt is sent to the INT1 or
INT2 pin (determined by the trigger bit in the FIFO_CTL register),
and the FIFO_TRIG bit (Bit D7) is set in the FIFO_STATUS
register (Address 0x39).
The FIFO buffer keeps the last n samples (n is the value specified
by the samples bits in the FIFO_CTL register) and then operates
in FIFO mode, collecting new samples only when the FIFO buffer
is not full. A delay of at least 5 s must elapse between the occurrence of the trigger event and the start of data readback from the
FIFO buffer to allow the buffer to discard and retain the necessary
samples.
Additional trigger events cannot be recognized until the part is
reset to trigger mode. To reset the part to trigger mode,
1.
2.
3.
If desired, read data from the FIFO buffer (see the Retrieving
Data from the FIFO Buffer section).
Before resetting the part to trigger mode, read back the
FIFO data; placing the device into bypass mode clears the
FIFO buffer.
Configure the device for bypass mode by setting Bits[D7:D6]
at Address 0x38 to 00.
Configure the device for trigger mode by setting Bits[D7:D6]
at Address 0x38 to 11.
SELF-TEST
The ADXL375 incorporates a self-test feature that effectively
tests its mechanical and electronic systems simultaneously. When
the self-test function is enabled (via the SELF_TEST bit in the
DATA_FORMAT register, Address 0x31), an electrostatic force
is exerted on the mechanical sensor.
This electrostatic force moves the mechanical sensing element in
the same manner as acceleration, and it is additive to the external
acceleration experienced by the device. This added electrostatic
force results in an output change in the x-, y-, and z-axes. Because
the electrostatic force is proportional to VS2, the output change
varies with VS.
The self-test response in the x- and y-axes exhibits bimodal
behavior and, therefore, is not always a reliable indicator of
sensor health or potential shift in device sensitivity. For this
reason, perform the self-test check in the z-axis.
Use of the self-test feature at data rates of less than 100 Hz or at
1600 Hz may yield values outside the limits shown in Figure 16.
For the self-test function to operate correctly, the part must be in
normal power operation (LOW_POWER bit = 0 in the BW_RATE
register, Address 0x2C) and be configured for a data rate from
100 Hz to 800 Hz, or for a data rate of 3200 Hz (see Table 6).
For more information about the self-test feature, see the Using
Self-Test section.
Rev. B | Page 12 of 32
Data Sheet
ADXL375
INTERRUPTS
The ADXL375 provides two output pins for driving interrupts:
INT1 and INT2. Both interrupt pins are push-pull, low impedance
pins (see Table 10 for output specifications). The default configuration of the interrupt pins is active high. The polarity can be
changed to active low by setting the INT_INVERT bit (Bit D5)
in the DATA_FORMAT register (Address 0x31). All interrupt
functions can be enabled simultaneously, but some functions
may need to share the same interrupt pin.
DATA_READY Bit
The DATA_READY bit is set when new data is available and
is cleared when no new data is available.
SINGLE_SHOCK Bit
1.
DOUBLE_SHOCK Bit
CLEARING INTERRUPTS
Activity Bit
1.
The activity bit is set when acceleration greater than the value
stored in the THRESH_ACT register (Address 0x24) is experienced on any participating axis. Participating axes are specified
by the ACT_INACT_CTL register (Address 0x27).
2.
3.
2.
Test Conditions/Comments
IOL = 300 A
IOH = 150 A
VOL = VOL, MAX
VOH = VOH, MIN
fIN = 1 MHz, VS = 2.5 V
CLOAD = 150 pF
Rev. B | Page 13 of 32
Min
Limit1
Max
0.2 VDD I/O
Unit
150
8
V
V
A
A
pF
210
150
ns
ns
ADXL375
Data Sheet
Inactivity Bit
Overrun Bit
The inactivity bit is set when acceleration less than the value stored
in the THRESH_INACT register (Address 0x25) is experienced
for more time than is specified by the TIME_INACT register
(Address 0x26) on all participating axes. Participating axes are
specified by the ACT_INACT_CTL register (Address 0x27). The
maximum value for TIME_INACT is 255 sec.
The overrun bit is set when new data replaces unread data. The
precise operation of the overrun function depends on the FIFO
mode (see the FIFO Buffer section).
Watermark Bit
The watermark bit is set when the number of samples in the FIFO
buffer equals the value stored in the samples bits (Bits[D4:D0])
of the FIFO_CTL register (Address 0x38). The watermark bit
is cleared automatically when the FIFO buffer is read and the
FIFO contents return to a value below the value specified by the
samples bits.
Rev. B | Page 14 of 32
Data Sheet
ADXL375
SERIAL COMMUNICATIONS
The ADXL375 supports I2C and SPI digital communications. In
both cases, the ADXL375 operates as a slave device. When the CS
pin is tied high to VDD I/O, I2C mode is enabled. The CS pin must
be tied high to VDD I/O or be driven by an external controller. If the
CS pin is left unconnected, the user may not be able to communicate with the part. In SPI mode, the CS pin is controlled by the
bus master. In both SPI and I2C modes of operation, ignore data
transmitted from the ADXL375 to the master device during writes
to the ADXL375.
SPI MODE
The ADXL375 can be configured for 3-wire SPI mode or 4-wire
SPI mode, as shown in Figure 22 and Figure 23. Clearing the SPI
bit (Bit D6) in the DATA_FORMAT register (Address 0x31) selects
4-wire mode; setting the SPI bit selects 3-wire mode. The maximum SPI clock speed is 5 MHz with 100 pF maximum loading.
The timing scheme requires clock polarity (CPOL) = 1 and clock
phase (CPHA) = 1. If power is applied to the ADXL375 before the
clock polarity and phase of the host processor are configured, take
the CS pin high before changing the clock polarity and phase.
When using 3-wire SPI mode, it is recommended that the SDO
pin be either pulled up to VDD I/O or pulled down to GND via a
10 k resistor.
SDIO
PROCESSOR
D OUT
SCLK
D OUT
CS
SDI
SDO
SCLK
PROCESSOR
D OUT
D OUT
D IN
D OUT
11669-003
ADXL375
Use of the 3200 Hz and 1600 Hz output data rates is recommended only with SPI communication speeds greater than or
equal to 2 MHz. The 800 Hz output data rate is recommended
only with communication speeds greater than or equal to 400 kHz,
and the remaining data rates scale proportionally. For example,
the minimum recommended communication speed for a 200 Hz
output data rate is 100 kHz. Operation at an output data rate above
the recommended maximum value may result in undesirable
effects on the acceleration data, including missing samples or
additional noise.
D IN/OUT
SDO
CS is the serial port enable line and is controlled by the SPI master.
This line must go low at the start of a transmission and high at the
end of a transmission, as shown in Figure 25 to Figure 27. SCLK
is the serial port clock and is supplied by the SPI master. SCLK
should idle high during a period of no transmission. In 4-wire
SPI mode, SDI and SDO are the serial data input and output,
respectively. In 3-wire SPI mode, SDIO functions as both the
serial data input and output. Data is updated on the falling edge
of SCLK and should be sampled on the rising edge of SCLK.
Rev. B | Page 15 of 32
ADXL375
CS
SDA/SDI/SDIO
SDO
SCLK
PROCESSOR
D OUT
D IN/OUT
D IN
D OUT
11669-104
CS
11669-004
ADXL375
ADXL375
Data Sheet
CS
tM
tSCLK
tDELAY
tS
tQUIET
tCS, DIS
SCLK
tHOLD
MB
SDI
A5
tSDO
X
SDO
A0
D7
ADDRESS BITS
X
D0
tDIS
DATA BITS
11669-017
tSETUP
CS
tM
tSCLK
tDELAY
tS
tCS, DIS
tQUIET
SCLK
tHOLD
R
SDI
MB
A5
tSDO
X
SDO
A0
tDIS
ADDRESS BITS
X
D7
D0
11669-018
tSETUP
DATA BITS
CS
tDELAY
tM
tSCLK
tS
tQUIET
tCS, DIS
SCLK
tSETUP
SDIO
tHOLD
R/W
tSDO
MB
A5
A0
D0
DATA BITS
11669-019
ADDRESS BITS
D7
NOTES
1. tSDO IS ONLY PRESENT DURING READS.
Rev. B | Page 16 of 32
Data Sheet
ADXL375
Test Conditions/Comments
Min
Limit1
Max
0.3 VDD I/O
0.1
0.1
IOL = 10 mA
IOH = 4 mA
VOL = VOL, MAX
VOH = VOH, MIN
fIN = 1 MHz, VS = 2.5 V
Unit
V
V
A
A
V
V
mA
mA
pF
Table 12. SPI Timing (TA = 25C, VS = 2.5 V, VDD I/O = 1.8 V)1
Parameter
fSCLK
tSCLK
tDELAY
tQUIET
tDIS
tCS, DIS
tS
tM
tSETUP
tHOLD
tSDO
tR4
tF4
Min
Limit2, 3
Max
5
200
5
5
10
150
0.3 tSCLK
0.3 tSCLK
5
5
40
20
20
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
SPI clock frequency
Mark-space ratio (1/(SPI clock frequency)) for the SCLK input is 40/60 to 60/40
CS falling edge to SCLK falling edge
SCLK rising edge to CS rising edge
CS rising edge to SDO/SDIO disabled
CS deassertion between SPI communications
SCLK low pulse width (space)
SCLK high pulse width (mark)
SDI/SDIO valid before SCLK rising edge
SDI/SDIO valid after SCLK rising edge
SCLK falling edge to SDO/SDIO output transition
SDO/SDIO output high to output low transition
SDO/SDIO output low to output high transition
The CS, SCLK, SDI, and SDO pins are not internally pulled up or down; they must be driven for proper operation.
Limits based on characterization results, with fSCLK = 5 MHz and bus load capacitance of 100 pF; not production tested.
3
The timing values are referred to the input thresholds (VIL and VIH) given in Table 11.
4
Output rise and fall times measured with capacitive load of 150 pF. tR and tF are not shown in Figure 25 to Figure 27.
1
2
Rev. B | Page 17 of 32
ADXL375
Data Sheet
I2C MODE
VDD I/O
ADXL375
RP
RP
PROCESSOR
CS
SDA
D IN/OUT
ALT ADDRESS
SCL
11669-008
D OUT
If other devices are connected to the same I2C bus, the nominal
operating voltage level of the other devices cannot exceed VDD I/O
by more than 0.3 V. External pull-up resistors, RP, are necessary
for proper I2C operation (see Figure 28). To ensure proper operation, refer to the UM10204 I2C-Bus Specification and User Manual,
Rev. 0319 June 2007, when selecting pull-up resistor values.
SINGLE-BYTE WRITE
MASTER START
SLAVE
DATA
REGISTER ADDRESS
ACK
ACK
STOP
ACK
MULTIPLE-BYTE WRITE
MASTER START
DATA
DATA
REGISTER ADDRESS
ACK
SLAVE
ACK
STOP
ACK
ACK
SINGLE-BYTE READ
MASTER START
SLAVE
START1
REGISTER ADDRESS
ACK
ACK
NACK
ACK
DATA
ACK
DATA
STOP
MULTIPLE-BYTE READ
MASTER START
SLAVE
ACK
ACK
NACK
NOTES
1. THE SHADED AREAS REPRESENT WHEN THE DEVICE IS LISTENING.
STOP
DATA
11669-033
1THIS
START1
REGISTER ADDRESS
ACK
Test Conditions/Comments
Min
Limit1
Max
0.3 VDD I/O
0.1
0.1
Rev. B | Page 18 of 32
Unit
V
V
A
A
V
mV
mA
pF
Data Sheet
ADXL375
Table 14. I2C Timing (TA = 25C, VS = 2.5 V, VDD I/O = 1.8 V)
Parameter
fSCL
t1
t2
t3
t4
t5
t63, 4, 5
t7
t8
t9
t10
Min
Limit1, 2
Max
400
2.5
0.6
1.3
0.6
100
0
0.6
0.6
1.3
0.9
300
0
t11
300
250
400
Cb
Unit
kHz
s
s
s
s
ns
s
s
s
s
ns
ns
ns
ns
pF
Description
SCL clock frequency
SCL cycle time
SCL high time
SCL low time
Hold time for start/repeated start condition
Data setup time
Data hold time
Setup time for repeated start condition
Setup time for stop condition
Bus-free time between a stop condition and a start condition
Rise time of SCL and SDA when receiving
Rise time of SCL and SDA when receiving or transmitting
Fall time of SCL and SDA when receiving
Fall time of SCL and SDA when transmitting
Capacitive load for each bus line
Limits based on characterization results, with fSCL = 400 kHz and a 3 mA sink current; not production tested.
The timing values are referred to the input thresholds (VIL and VIH) given in Table 13.
3
t6 is the data hold time that is measured from the falling edge of SCL. It applies to data during the transmission and acknowledge phases.
4
To bridge the undefined region of the falling edge of SCL, a transmitting device must internally provide an output hold time of at least 300 ns for the SDA signal (with
respect to VIH, MIN of the SCL signal).
5
The maximum value for t6 must be met only if the device does not stretch the low period (t3) of the SCL signal. The maximum value for t6 is a function of the clock low
time (t3), the clock rise time (t10), and the minimum data setup time (t5(MIN)). This value is calculated as t6(MAX) = t3 t10 t5(MIN).
2
SDA
t3
t9
t10
t4
t11
SCL
t6
t2
t5
t7
REPEATED
START
CONDITION
Rev. B | Page 19 of 32
t1
t8
STOP
CONDITION
11669-034
t4
START
CONDITION
ADXL375
Data Sheet
REGISTER MAP
All registers in the ADXL375 are eight bits in length.
Table 15. Register Map
Address
Hex
Decimal
0x00
0
0x01 to 0x1C 1 to 28
0x1D
29
0x1E
30
0x1F
31
0x20
32
0x21
33
0x22
34
0x23
35
0x24
36
0x25
37
0x26
38
0x27
39
0x2A
42
0x2B
43
0x2C
44
0x2D
45
0x2E
46
0x2F
47
0x30
48
0x31
49
0x32
50
0x33
51
0x34
52
0x35
53
0x36
54
0x37
55
0x38
56
0x39
57
Register Name
DEVID
Reserved
THRESH_SHOCK
OFSX
OFSY
OFSZ
DUR
Latent
Window
THRESH_ACT
THRESH_INACT
TIME_INACT
ACT_INACT_CTL
SHOCK_AXES
ACT_SHOCK_STATUS
BW_RATE
POWER_CTL
INT_ENABLE
INT_MAP
INT_SOURCE
DATA_FORMAT
DATAX0
DATAX1
DATAY0
DATAY1
DATAZ0
DATAZ1
FIFO_CTL
FIFO_STATUS
Access Type
R
N/A
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R
R/W
R
R
R
R
R
R
R/W
R
Reset Value
11100101
N/A
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00001010
00000000
00000000
00000000
00000010
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
Rev. B | Page 20 of 32
Description
Device ID
Reserved; do not access
Shock threshold
X-axis offset
Y-axis offset
Z-axis offset
Shock duration
Shock latency
Shock window
Activity threshold
Inactivity threshold
Inactivity time
Axis enable control for activity and inactivity detection
Axis control for single shock/double shock
Source of single shock/double shock
Data rate and power mode control
Power saving features control
Interrupt enable control
Interrupt mapping control
Interrupt source
Data format control
X-Axis Data 0
X-Axis Data 1
Y-Axis Data 0
Y-Axis Data 1
Z-Axis Data 0
Z-Axis Data 1
FIFO control
FIFO status
Data Sheet
ADXL375
REGISTER DESCRIPTIONS
D6
1
D5
1
D4
0
D3
0
D2
1
D1
0
D0
1
D6
ACT_X enable
D2
INACT_X enable
D5
ACT_Y enable
D1
INACT_Y enable
D4
ACT_Z enable
D0
INACT_Z enable
Rev. B | Page 21 of 32
ADXL375
Data Sheet
Asleep Bit
D6
0
D2
SHOCK_X enable
D5
0
D1
SHOCK_Y enable
D4
0
D0
SHOCK_Z enable
Suppress Bit
Setting the suppress bit suppresses double shock detection if
acceleration greater than the value in the THRESH_SHOCK
register is present during the latency time between shocks. For
more information, see the Shock Detection section.
D6
ACT_X source
D2
SHOCK_X source
D5
ACT_Y source
D1
SHOCK_Y source
D4
ACT_Z source
D0
SHOCK_Z source
D6
0
D5
0
D4
LOW_POWER
D3
D2
D1
Rate
D0
LOW_POWER Bit
A setting of 0 in the LOW_POWER bit selects normal operation; a setting of 1 selects reduced power operation, which has
somewhat higher noise. For more information, see the Low
Power Mode section.
Rate Bits
The rate bits select the device bandwidth and output data rate
(see Table 6 and Table 8). The default value for these bits is 0x0A,
which translates to a 100 Hz output data rate. The selected output
data rate must be appropriate for the communication protocol
and frequency selected. Selecting an output data rate that is too
high for the communication speed may result in samples being
discarded (for more information, see the Serial Communications
section).
D6
0
D5
Link
D4
AUTO_SLEEP
D3
Measure
D2
Sleep
D1
D0
Wakeup
Link Bit
The link bit serially links the activity and inactivity functions. If
both the activity and inactivity functions are enabled, a setting of
1 in the link bit delays the start of the activity detection function
until inactivity is detected. After activity is detected, inactivity
detection begins, preventing the detection of activity. When this
bit is set to 0, the inactivity and activity functions are concurrent.
For more information about the link feature, see the Link Mode
section.
Before clearing the link bit, it is recommended that the part be
placed in standby mode (set the measure bit, Bit D3, to 0). After
clearing the link bit, reset the part to measurement mode (set the
measure bit, Bit D3, to 1). This configuration sequence ensures
that the device is properly biased if sleep mode is manually
disabled; otherwise, the first few samples of data after the link
bit is cleared may have additional noise, especially if the device
is asleep when the bit is cleared.
Rev. B | Page 22 of 32
Data Sheet
ADXL375
AUTO_SLEEP Bit
Measure Bit
A setting of 0 in the measure bit places the part into standby
mode; a setting of 1 places the part into measurement mode.
The ADXL375 powers up in standby mode with minimum
power consumption (see the Power Sequencing section).
Sleep Bit
A setting of 0 in the sleep bit places the part into the normal
mode of operation; a setting of 1 places the part into sleep mode.
Sleep mode suppresses the DATA_READY interrupt, stops transmission of data to the FIFO buffer, and switches the sampling
rate to the rate specified by the wakeup bits (Bits[D1:D0]). In
sleep mode, only the activity function can be used. When the
DATA_READY interrupt is suppressed, the output data registers
(Register 0x32 to Register 0x37) are still updated at the sampling
rate set by the wakeup bits.
Before clearing the sleep bit, it is recommended that the part be
placed in standby mode (set the measure bit, Bit D3, to 0). After
clearing the sleep bit, reset the part to measurement mode (set the
measure bit, Bit D3, to 1).
Wakeup Bits
The wakeup bits control the sampling rate during sleep mode
(see Table 16).
D1
0
0
1
1
Setting
D0
0
1
0
1
Frequency (Hz)
8
4
2
1
D6
SINGLE_SHOCK
D2
0
D5
DOUBLE_SHOCK
D1
Watermark
D4
Activity
D0
Overrun
D6
SINGLE_SHOCK
D2
0
D5
DOUBLE_SHOCK
D1
Watermark
D4
Activity
D0
Overrun
D6
SINGLE_SHOCK
D2
X1
D5
DOUBLE_SHOCK
D1
Watermark
D4
Activity
D0
Overrun
Rev. B | Page 23 of 32
ADXL375
Data Sheet
D5
D4
INT_INVERT 0
D3
1
D2
Justify
D0
1
D7
D6
FIFO_MODE
D5
Trigger
D4
D3
D2
D1
Samples
D0
SELF_TEST Bit
SPI Bit
A value of 1 in the SPI bit configures the device for 3-wire SPI
mode; a value of 0 configures the device for 4-wire SPI mode.
INT_INVERT Bit
A value of 0 in the INT_INVERT bit sets the polarity of the
interrupt pins to active high; a value of 1 sets the polarity of
the interrupt pins to active low.
FIFO_MODE Bits
These bits set the FIFO mode, as described in Table 17.
Table 17. FIFO Modes
Setting
D7
D6
0
0
0
1
FIFO
Mode
Bypass
FIFO
Stream
Trigger
Justify Bit
A setting of 1 in the justify bit selects left justified (MSB) mode; a
setting of 0 selects right justified (LSB) mode with sign extension.
Description
FIFO buffer is bypassed.
FIFO buffer collects up to 32 samples and
then stops collecting data, collecting new
data only when the buffer is not full.
FIFO buffer holds the last 32 samples.
When the buffer is full, the oldest data
is overwritten with newer data.
FIFO buffer holds the last samples before
the trigger event and continues to collect
data until full. New data is collected only
when the buffer is not full.
Trigger Bit
A value of 0 in the trigger bit links the trigger event of trigger
mode to the INT1 pin, and a value of 1 links the trigger event
to the INT2 pin.
Samples Bits
The function of the samples bits depends on the FIFO mode
selected (see Table 18). Entering a value of 0 in the samples bits
immediately sets the watermark bit in the INT_SOURCE register,
regardless of the FIFO mode selected. Undesirable operation may
occur if a value of 0 is used for the samples bits when trigger
mode is used.
Table 18. Samples Bits Functions
FIFO Mode
Bypass
FIFO
Stream
Trigger
Rev. B | Page 24 of 32
Data Sheet
ADXL375
D6
0
D5
D4
D3
D2
Entries
Entries Bits
D1
D0
FIFO_TRIG Bit
When the FIFO_TRIG bit is set to 1, a trigger event has occurred;
when the FIFO_TRIG bit is set to 0, no trigger event has occurred.
The entries bits report how many data values are stored in the
FIFO buffer. The data stored in the FIFO buffer is accessed by
reading the data registers (Address 0x32 to Address 0x37). FIFO
reads must be done in burst mode (multiple-byte mode) because
each FIFO level is cleared after any read (single- or multiplebyte) of the FIFO buffer. The FIFO buffer stores a maximum of
32 entries, which equates to a maximum of 33 entries available
at any given time because an additional entry is available at the
output filter of the device.
Rev. B | Page 25 of 32
ADXL375
Data Sheet
APPLICATIONS INFORMATION
POWER SUPPLY DECOUPLING
SHOCK DETECTION
A 1 F tantalum capacitor (CS) at VS and a 0.1 F ceramic capacitor (CI/O) at VDD I/O placed close to the ADXL375 supply pins are
recommended to adequately decouple the accelerometer from
noise on the power supply. If additional decoupling is necessary,
a resistor or ferrite bead (no larger than 100 ) in series with VS
may be helpful. Additionally, increasing the bypass capacitance
on VS to a 10 F tantalum capacitor in parallel with a 0.1 F
ceramic capacitor may also improve noise performance.
VDD I/O
VS
CI/O
CS
VDD I/O
ADXL375
FIRST SHOCK
11669-016
GND
3- OR 4-WIRE
SPI OR I2C
INTERFACE
ACCELEROMETERS
INTERRUPTS
LATENCY
TIME
(LATENT)
SINGLE SHOCK
INTERRUPT
DOUBLE SHOCK
INTERRUPT
Figure 33. Shock Interrupt Function with Valid Single and Double Shocks
11669-036
PCB
MOUNTING POINTS
THRESHOLD
(THRESH_SHOCK)
SECOND SHOCK
ACCELERATION
SDA/SDI/SDIO
INTERRUPT
CONTROL
11669-037
VS
Rev. B | Page 26 of 32
Data Sheet
ADXL375
LATENCY
TIME (LATENT)
11669-038
ACCELERATION
TIME LIMIT
FOR SHOCKS
(DUR)
ACCELERATION
LINK MODE
The link bit (Bit D5) in the POWER_CTL register (Address 0x2D)
can be used to reduce the number of activity interrupts that the
processor must service. The link bit configures the device to look
for activity only after inactivity.
TIME LIMIT
FOR SHOCKS
(DUR)
TIME LIMIT
FOR SHOCKS
(DUR)
LATENCY
TIME
(LATENT)
INVALIDATES
DOUBLE SHOCK AT
END OF DUR
11669-039
TIME LIMIT
FOR SHOCKS
(DUR)
ACCELERATION
Rev. B | Page 27 of 32
ADXL375
Data Sheet
OFFSET CALIBRATION
Accelerometers are mechanical structures containing elements
that are free to move. These moving parts can be very sensitive
to mechanical stresses, much more so than solid-state electronics.
The 0 g bias, or offset, is an important accelerometer metric
because it defines the baseline for measuring acceleration.
Additional stresses can be applied during assembly of a system
containing an accelerometer. These stresses can come from, but
are not limited to, component soldering, board stress during
mounting, and application of any compounds on or over the
component. If calibration is deemed necessary, it is recommended
that it be performed after system assembly to compensate for
these effects.
A simple method of calibration is to measure the offset while
assuming that the sensitivity of the ADXL375 is as specified in
Table 1. The offset can then be automatically accounted for by
using the built-in offset registers. The result of this calibration is
that the data acquired from the data registers already compensates
for any offset.
In a no-turn or single-point calibration scheme, the part is
oriented such that one axis, typically the z-axis, is in the 1 g field
of gravity, and the remaining axes, typically the x- and y-axes, are
in a 0 g field. The output is then measured by taking the average
of a series of samples.
Rev. B | Page 28 of 32
Data Sheet
ADXL375
7.
USING SELF-TEST
The self-test change is defined as the difference between the
acceleration output of an axis with self-test enabled and the
acceleration output of the same axis with self-test disabled. Due
to device filtering, the output reaches its final value after 4
when enabling or disabling self-test, where = 1/(data rate).
This definition assumes that the sensor does not move between
these two measurements; if the sensor moves, a non-self-test
related shift corrupts the test.
Proper configuration of the ADXL375 is necessary for an
accurate self-test measurement. To configure the part for selftest, follow this procedure.
1.
2.
3.
4.
5.
6.
Set the data rate from 100 Hz to 800 Hz, or set the data rate
to 3200 Hz by writing to the rate bits (Bits[D3:D0]) in the
BW_RATE register (Address 0x2C). Write a value from
0x0A to 0x0D, or write 0x0F to the BW_RATE register.
For accurate self-test measurements, configure the part for
normal power operation by clearing the LOW_POWER bit
(Bit D4) in the BW_RATE register (Address 0x2C).
After the part is configured for accurate self-test measurement, retrieve samples of x-, y-, and z-axis acceleration
data from the sensor and average them together.
The number of samples averaged is selected by the system
designer, but a recommended starting point is 0.1 sec worth
of data for data rates of 100 Hz or greaterthat is, 10 samples
at the 100 Hz data rate.
Store the averaged values and label them appropriately
as the values with self-test disabled, that is, XST_OFF,
YST_OFF, and ZST_OFF.
Enable self-test by setting the SELF_TEST bit (Bit D7)
in the DATA_FORMAT register (Address 0x31).
The output requires some time (approximately four samples)
to settle after self-test is enabled.
After allowing the output to settle, retrieve samples of x-, y-,
and z-axis acceleration data and average them together.
It is recommended that the same number of samples be taken
for the self-test average as was done for the non-self-test
average.
8.
With the stored values for self-test enabled and disabled, the
self-test change is as follows:
XST = XST_ON XST_OFF
YST = YST_ON YST_OFF
ZST = ZST_ON ZST_OFF
Because the measured output for each axis is expressed in LSBs,
XST, YST, and ZST are also expressed in LSBs. These values can be
converted to acceleration (g) by multiplying each value by the
49 mg/LSB scale factor.
If the self-test change is within the valid range, the test is considered
successful. Generally, a part is considered to pass if the minimum
magnitude of change is achieved. However, a part that changes by
more than the maximum magnitude is not necessarily a failure.
The self-test response in the x- and y-axes exhibits bimodal
behavior and, therefore, is not always a reliable indicator of
sensor health or potential shift in device sensitivity. For this
reason, perform the self-test check in the z-axis.
Another effective method for using the self-test to verify accelerometer functionality is to toggle the self-test at a certain rate
and then perform an FFT on the output. The FFT should have
a corresponding tone at the frequency where the self-test was
toggled. Using an FFT in this way removes the dependency of
the test on supply voltage and self-test magnitude, which can
vary within a rather wide range.
Rev. B | Page 29 of 32
ADXL375
Data Sheet
AX
11669-021
AY
Figure 36. Axes of Acceleration Sensitivity (Corresponding Output Voltage Increases When Accelerated Along the Sensitive Axis)
XOUT = 1g
YOUT = 0g
ZOUT = 0g
TOP
TOP
TOP
GRAVITY
XOUT = 0g
YOUT = 1g
ZOUT = 0g
XOUT = 1g
YOUT = 0g
ZOUT = 0g
XOUT = 0g
YOUT = 0g
ZOUT = 1g
Rev. B | Page 30 of 32
XOUT = 0g
YOUT = 0g
ZOUT = 1g
11669-022
TOP
XOUT = 0g
YOUT = 1g
ZOUT = 0g
Data Sheet
ADXL375
0.5500
0.2500
3.0500
11669-014
5.3400
0.2500
1.1450
Figure 38. Recommended Printed Wiring Board Land Pattern (Dimensions shown in millimeters)
PACKAGE INFORMATION
375B
#yww
vv v v
CNTY
11669-102
Figure 39 and Table 19 provide information about the package branding for the ADXL375.
Field Description
Part identifier for the ADXL375
RoHS-compliant designation
Date code
Factory lot code
Country of origin
Rev. B | Page 31 of 32
ADXL375
Data Sheet
OUTLINE DIMENSIONS
PAD A1
CORNER
3.00
BSC
0.49
BOTTOM VIEW
13
14
0.813 0.50
0.80
BSC
5.00
BSC
0.50
8
TOP VIEW
END VIEW
1.01
0.79
0.74
0.69
0.49
1.50
03-16-2010-A
1.00
0.95
0.85
SEATING
PLANE
ORDERING GUIDE
Model1
ADXL375BCCZ
ADXL375BCCZ-RL
ADXL375BCCZ-RL7
EVAL-ADXL375Z
EVAL-ADXL375Z-M
Temperature
Range
40C to +85C
40C to +85C
40C to +85C
40C to +85C
Measurement
Range (g)
200
200
200
Specified
Voltage (V)
2.5
2.5
2.5
EVAL-ADXL375Z-S
1
Package Description
14-Terminal Land Grid Array [LGA]
14-Terminal Land Grid Array [LGA]
14-Terminal Land Grid Array [LGA]
Evaluation Board
Inertial Sensor Evaluation System, Includes
ADXL375 Satellite
ADXL375 Satellite, Standalone (can be used
with other inertial sensor evaluation systems)
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
20132014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11669-0-4/14(B)
Rev. B | Page 32 of 32
Package
Option
CC-14-1
CC-14-1
CC-14-1