Differential Input, Quad, External Reference

Simultaneous Sampling, 16-Bit, SAR ADC

Data Sheet AD7380-4
FEATURES FUNCTIONAL BLOCK DIAGRAM
16-bit ADC family
Quad simultaneous sampling
Fully differential analog inputs
High throughput rate: 4 MSPS
SNR: 92 dB (typical) at VREF = 3.3 V
On-chip oversampling function
SNR: 97.7 dB (typical) with OSR = 8×, RES = 1
2-bit resolution boost
Out of range indicator (ALERT)
INL: 3 LSBs (maximum)
High-speed serial interface
Temperature range: −40°C to +125°C
4 mm × 4 mm, 24-lead LFCSP

APPLICATIONS Figure 1.
Motor control position feedback
Motor control current sense
Data acquisition systems
Erbium doped fiber amplifier (EDFA) applications
In phase and quadrature demodulation

GENERAL DESCRIPTION
The AD7380-4 is a 16-bit compatible, quad, simultaneous Table 1. Related Devices
sampling, high speed, successive approximation register (SAR), No. of
analog-to-digital converters (ADC) operating from a 3.3 V Channels Input Type 16 Bits 14 Bits 12 Bits
power supply with throughput rates up to 4 MSPS. The 4 Differential AD7380-4 AD7381-4
differential analog input accepts a wide common-mode input AD7389-4
voltage and is sampled and converted on the falling edge of CS. 2 Differential AD7380 AD7381
The AD7380-4 has on-chip oversampling blocks to improve AD4680
dynamic range and reduce noise at lower bandwidths. The AD4681
oversampling can boost up to two bits of added resolution. The Single-ended AD7386 AD7387 AD7388
REFIN pin can have a reference voltage of 2.5 V to 3.3 V.
PRODUCT HIGHLIGHTS
The conversion process and data acquisition use standard 1. Quad simultaneous sampling and conversion
control inputs allowing easy interfacing to microprocessors or 2. Pin-compatible product family.
digital signal processors (DSPs). The conversion result can 3. High throughput rate, 4 MSPS at 16-bit.
clock out simultaneously via 4-wire mode for faster throughput 4. Space-saving, 4 mm × 4 mm LFCSP.
or via 1-wire serial mode when slower throughput is allowed. 5. Integrated oversampling block to increase dynamic range,
The device is compatible with 1.8 V, 2.5 V, and 3.3 V interfaces reduce noise and reduce SCLK speed requirements.
using the separate logic supply. 6. Differential analog inputs with wide common-mode range.
The AD7380-4 is available in a 24-lead lead frame chip scale 7. Small sampling capacitor reduces amplifier drive burden.
package (LFCSP) and operates over a temperature range of −40°C
to +125°C.

Rev. 0 Document Feedback

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AD7380-4 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 Oversampling ............................................................................. 17
Applications ...................................................................................... 1 Resolution Boost ........................................................................ 19
Functional Block Diagram .............................................................. 1 Alert.............................................................................................. 19
General Description ......................................................................... 1 Power Modes .............................................................................. 20
Product Highlights ........................................................................... 1 External Reference ..................................................................... 20
Revision History ............................................................................... 2 Software Reset ............................................................................. 20
Specifications .................................................................................... 3 Diagnostic Self Test.................................................................... 20
Timing Specifications .................................................................. 5 Interface ........................................................................................... 21
Absolute Maximum Ratings ........................................................... 8 Reading Conversion Results ..................................................... 21
Thermal Resistance ...................................................................... 8 Low Latency Readback .............................................................. 22
Electrostatic Discharge (ESD) Ratings ...................................... 8 Reading from Device Registers ................................................ 23
ESD Caution.................................................................................. 8 Writing to Device Registers ...................................................... 23
Pin Configuration and Function Descriptions ............................ 9 CRC .............................................................................................. 23
Typical Performance Characteristics ........................................... 10 Registers ........................................................................................... 26
Terminology .................................................................................... 13 Addressing Registers.................................................................. 26
Theory of Operation ...................................................................... 14 Configuration 1 Register ........................................................... 27
Circuit Information ................................................................... 14 Configuration 2 Register ........................................................... 28
Converter Operation.................................................................. 14 Alert Indication Register ........................................................... 28
Analog Input Structure.............................................................. 14 Alert Low Threshold Register .................................................. 29
ADC Transfer Function ............................................................ 15 Alert High Threshold Register ................................................. 30
Applications Information.............................................................. 16 Outline Dimensions ....................................................................... 31
Power Supply .............................................................................. 16 Ordering Guide .......................................................................... 31
Modes of Operation ....................................................................... 17

REVISION HISTORY
1/2022—Revision 0: Initial Version

Rev. 0 | Page 2 of 31
Data Sheet AD7380-4

SPECIFICATIONS
VCC = 3.0 V to 3.6 V, VLOGIC = 1.65 V to 3.6 V, external reference voltage (VREF) = 2.5 V, fSAMPLE = 4 MSPS, TA = −40°C to +125°C, no
oversampling enabled, unless otherwise noted.

Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
RESOLUTION 16 Bits
THROUGHPUT
Conversion Rate (fSAMPLE) 4 MSPS
ANALOG INPUT
Voltage Range AINx+ − AINx− −VREF +VREF V
Absolute Input Voltage AINx+, AINx− −0.1 VREF + 0.1 V
Common-Mode Input Range AINx+, AINx− 0.2 VREF × 0.5 VREF − 0.2 V
Analog Input Common-Mode Rejection Ratio fIN = 500 kHz −76 dB
(CMRR)
DC Leakage Current 0.1 1 µA
Input Capacitance Track mode 18 pF
Hold mode 5 pF
DC ACCURACY
No Missing Codes 16 Bits
Differential Nonlinearity (DNL) Error −1.0 ±0.5 +1.0 LSB
Integral Nonlinearity (INL) Error −3.0 ±1 +3.0 LSB
Gain Error −0.015 ±0.001 +0.015 % FS 1
Gain Error Temperature Drift −5 ±1 +5 ppm/°C
Gain Error Match −0.015 ±0.01 +0.015 % FS
Offset Error −0.75 ±0.1 +0.75 mV
Zero Error Temperature Drift −1 ±0.5 +1 μV/°C
Zero Error Match −0.75 ±0.5 +0.75 mV
AC ACCURACY Input frequency (fIN) = 1 kHz
Dynamic Range VREF = 3.3 V 93 dB
91.3 dB
Oversampled Dynamic Range OSR = 4×, RES = 1 (decimal) 97.4 dB
Signal-to-Noise Ratio (SNR) VREF = 3.3 V 89 92 dB
87.5 90.5 dB
Rolling average OSR = 8×, RES = 1 97.7 dB
(decimal)
fIN = 100 kHz 89.2 dB
Spurious-Free Dynamic Range (SFDR) −110 dB
Total Harmonic Distortion (THD) −110 dB
fIN = 100 kHz −104.7 dB
Signal-to-Noise-and-Distortion (SINAD) Ratio VREF = 3.3 V 88.5 91.5 dB
87 90 dB
Channel to Channel Isolation −126 dB
POWER SUPPLIES
IVCC
Normal Mode (Operational) 38 42 mA
Power Dissipation
PTOTAL 163.1 180.2 mW
PVCC
Normal Mode (Operational) 136.8 151.2 mW
1
These specifications include full temperature range variation, but they do not include the error contribution from the external reference.

Rev. 0 | Page 3 of 31
AD7380-4 Data Sheet
VCC = 3.0 V to 3.6 V, VLOGIC = 1.65 V to 3.6 V, external VREF = 2.5 V, TA = −40°C to +125°C, no oversampling enabled, unless otherwise noted.

Table 3
Parameter Test Conditions/Comments Min Typ Max Unit
SAMPLING DYNAMICS
Input Bandwidth At −0.1 dB 6.6 MHz
At −3 dB 26.8 MHz
Aperture Delay 2 ns
Aperture Delay Match 46.8 145 ps
Aperture Jitter 20 ps
REFERENCE INPUT
VREF Input Voltage Range External reference 2.49 3.4 V
VREF Input Current External reference 0.9 1.2 mA
DIGITAL INPUTS (SCLK, SDI, CS)
Logic Levels
Input Voltage Low (VIL) VLOGIC < 2.3 V 0.45 V
VLOGIC ≥ 2.3 V 0.7 V
Input Voltage High (VIH) VLOGIC < 2.3 V VLOGIC − V
0.45 V
VLOGIC ≥ 2.3 V 0.8 × VLOGIC V
Input Current Low (IIL) −1 +1 µA
Input Current High (IIH) −1 +1 µA
DIGITAL OUTPUTS (SDOA, SDOB, SDOC,
SDOD/ALERT)
Output Coding Twos complement Bits
Output Voltage Low (VOL) Current sink (ISINK) = 300 µA 0.4 V
Output Voltage High (VOH) Current source (ISOURCE) = −300 µA VLOGIC − 0.3 V
Floating State Leakage Current ±1 µA
Floating State Output Capacitance 10 pF
POWER SUPPLIES
VCC 3.0 3.3 3.6 V
External reference = 3.3 V 3.15 3.3 3.6 V
VLOGIC 1.65 3.6 V
VCC Supply Current (IVCC)
Normal Mode (Static) 1.7 2 mA
Shutdown Mode 101 200 µA
VLOGIC Current (IVLOGIC) Analog inputs at positive full scale
Normal Mode (Static) 10 200 nA
Normal Mode (Operational) 7.3 8 mA
Shutdown Mode 10 200 nA
Power Dissipation
VCC Power (PVCC)
Normal Mode (Static) 6.1 7.2 mW
Shutdown Mode 363.6 720 µW
VLOGIC Power (PVLOGIC) Analog inputs at positive full scale
Normal Mode (Static) 36 720 nW
Normal Mode (Operational) 26.3 29 mW
Shutdown Mode 36 720 nW

Rev. 0 | Page 4 of 31
Data Sheet AD7380-4
TIMING SPECIFICATIONS
VCC = 3.0 V to 3.6 V, VLOGIC = 1.65 V to 3.6 V, VREF = 2.5 V, TA = −40°C to +125°C, unless otherwise noted. When referencing a single function
of a multifunction pin in the parameters, only the portion of the pin name that is relevant to the specification is listed, such as ALERT. For full
pin names of multifunction pins, refer to the Pin Configuration and Function Descriptions section.

Table 4.
Parameter Min Typ Max Unit Description
tCYC 250 ns Time between conversions
tSCLKED 5 ns CS falling edge to first SCLK falling edge
tSCLK 12.5 ns SCLK period
tSCLKH 5.5 ns SCLK high time
tSCLKL 5.5 ns SCLK low time
tCSH 20 ns CS pulse width
tQUIET 20 ns Interface quiet time prior to conversion
tSDOEN 5.5 ns CS low to SDOA and SDOB enabled
tSDOH 3 ns SCLK rising edge to SDOA and SDOB hold time
tSDOS 5 ns SCLK rising edge to SDOA and SDOB setup time
tSDOT 8 ns CS rising edge to SDOA and SDOB high impedance
tSDIS 4 ns SDI setup time prior to SCLK falling edge
tSDIH 4 ns SDI hold time after SCLK falling edge
tSCLKCS 0 ns SCLK rising edge to CS rising edge
tCONVERT 190 ns Conversion time
tACQUIRE 110 ns Acquire time
tRESET 250 ns Valid time to start conversion after soft reset
800 ns Valid time to start conversion after hard reset
tPOWERUP Supply active to conversion
5 ms First conversion allowed
5 ms Settled to within 1% with external reference
tREGWRITE 5 ms Supply active to register read write access allowed
tSTARTUP Exiting shutdown mode to conversion
10 µs Settled to within 1% with external reference
tCONVERT0 6 8 10 ns Conversion time for first sample in oversampling (OS) normal mode
tCONVERTx tCONVERT0 + (320 × (x – 1)) ns Conversion time for xth sample in OS normal mode, 4 MSPS, 16-bit devices
tALERTS 220 ns Time from CS to ALERT indication
tALERTC 10 ns Time from CS to ALERT clear
tALERTS_NOS 20 ns Time from internal conversion with exceeded threshold to ALERT indication

Rev. 0 | Page 5 of 31
AD7380-4 Data Sheet
Timing Diagrams
tCYC
tCSH
tSCLKH tSCLKL tQUIET
tSCLK
tSCLKED tSCLKCS

CS

SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

TRISTATE TRISTATE
SDOA DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

TRISTATE TRISTATE
SDOB DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
tSDOEN tSDOH tSDOS tSDOT

20802-002
SDI DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
tSDIS tSDIH

Figure 2. Serial Interface Timing Diagram

tCONVERT

CS

CONVERSION CONVERSION

20802-003
ACQUIRE ACQUIRE
tACQUIRE

Figure 3. Internal Conversion Acquire Timing

tPOWERUP

VCC

CS
20802-004

TIME TO ACCURATE CONVERSION

Figure 4. Power-Up Time to Conversion

tREGWRITE

VCC

CS
20802-005

SDI REG WRITE

Figure 5. Power-Up Time to Register Read Write Access

tSTARTUP

CS

SDI SHUTDOWN NORMAL

20802-006

SHUTDOWN NORMAL ACCURATE

MODE MODE CONVERSION

Figure 6. Shutdown Mode to Normal Mode Timing

CONVERT0

CS

INTERNAL CONVERSION ACQUIRE CONVERSION ACQUIRE CONVERSION ACQUIRE CONVERSION ACQUIRE

CONVERT1

CONVERT2
20802-007

CONVERT3

CONVERTx

Figure 7. Conversion Timing During OS Normal Mode

Rev. 0 | Page 6 of 31
Data Sheet AD7380-4
tALERTS tALERTC

CS

SDOA
NO OVERSAMPLING OR
ROLLING AVERAGE
OVERSAMPLING INTERNAL CONV ACQ CONV ACQ CONV ACQ CONV ACQ

ALERT

EXCEEDS THRESHOLD

CS

SDOA
NORMAL
OVERSAMPLING
INTERNAL C A C A C A C A C A C A C A C A C A C A C A C A C A C A C A C A

ALERT

20802-008
EXCEEDS THRESHOLD
tALERTC
tALERTS_NOS

Figure 8. ALERT Timing

Rev. 0 | Page 7 of 31
AD7380-4 Data Sheet

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE
Table 5.
Parameter Rating Thermal performance is directly linked to printed circuit board
VCC to GND −0.3 V to +4 V (PCB) design and operating environment. Careful attention to
VLOGIC to GND −0.3 V to +4 V PCB thermal design is required.
Analog Input Voltage to GND −0.3 V to VREF + 0.3 V, or θJA is the natural convection junction to ambient thermal
VCC + 0.3 V
Digital Input Voltage to GND −0.3 V to VLOGIC + 0.3 V
resistance measured in a one cubic foot sealed enclosure. θJC is
Digital Output Voltage to GND −0.3 V to VLOGIC + 0.3 V the junction to case thermal resistance.
REFIN Input to GND −0.3 V to VCC + 0.3 V
Table 6. Thermal Resistance
Input Current to Any Pin Except Supplies ±10 mA
Temperature Package Type θJA θJC Unit
Operating Temperature Range −40°C to +125°C CP-24-251 48.4 0.432 °C/W
Storage Temperature Range −65°C to +150°C 1
Test Condition 1: thermal impedance simulated values are based on
Maximum Junction Temperature 150°C JEDEC 2S2P thermal test board with four thermal vias. See JEDEC JESDS1.
Pb-Free Soldering Reflow Temperature 260°C 2
Test Condition 2: a cold plate attached to the package surface and measured
at the exposed pad.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a ELECTROSTATIC DISCHARGE (ESD) RATINGS
stress rating only; functional operation of the product at these The following ESD information is provided for handling of
or any other conditions above those indicated in the ESD-sensitive devices in an ESD protected area only.
operational section of this specification is not implied. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
Operation beyond the maximum operating conditions for
Field induced charge device model (FICDM) per
extended periods may affect product reliability.
ANSI/ESDA/JEDEC JS-002.
ESD Ratings for AD7380-4
Table 7. AD7380-4, 24-lead LFCSP
ESD Model Withstand Threshold (V) Class
HBM ±4000 3A
FICDM ±1250 C3
ESD CAUTION

Rev. 0 | Page 8 of 31
Data Sheet AD7380-4

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

SDOD/ALERT
SDOC

SDOB
SDOA
SCLK
SDI
24 23 22 21 20 19

GND 1 18 CS
VLOGIC 2 AD7380-4 17 REFIN
REGCAP 3 16 GND
VCC 4 15 DNC
GND 5 TOP VIEW 14 GND
(Not to Scale)
AIND– 6 13 AINA+

7 8 9 10 11 12

AINC–

AINB–

AINA–
AIND+

AINC+

AINB+
NOTES

20802-009
1. DNC = DO NOT CONNECT.
2. EXPOSED PAD. FOR CORRECT OPERATION OF THE DEVICE
THE EXPOSED PAD MUST BE CONNECTED TO GND.

Figure 9. Pin Configuration

Table 8. Pin Function Descriptions

Pin No. Mnemonic Description
1, 5, 14, 16 GND Ground Reference Point. These pins are the ground reference points for all circuitry on the device.
2 VLOGIC Logic Interface Supply Voltage, 1.65 V to 3.6 V. Decouple this pin to GND with a 1 µF capacitor.
3 REGCAP Decoupling Capacitor Pin for Voltage Output from Internal Regulator. Decouple this pin to GND with a 1
µF capacitor. The voltage at this pin is 1.9 V typical.
4 VCC Power Supply Input Voltage. 3.0 V to 3.6 V. Decouple this pin to GND using a 1µF capacitor.
6, 7 AIND−, AIND+ Analog Inputs of ADC D. These analog inputs form a fully differential pair.
8, 9 AINC−, AINC+ Analog Inputs of ADC C. These analog inputs form a fully differential pair.
10, 11 AINB-, AINB+ Analog Inputs of ADC B. These analog inputs form a fully differential pair.
12, 13 AINA−, AINA+ Analog Inputs of ADC A. These analog inputs form a fully differential pair.
15 DNC Do Not Connect.
17 REFIN Reference Input. An external reference of 2.5 V to 3.3 V can be input to this pin. Decoupling is required on
this pin. Apply a 1 µF capacitor from this pin to GND.
18 CS Chip Select Input. Active low, logic input. This input provides the dual function of initiating conversions
on the AD7380-4 and framing the serial data transfer.
19 SDOA Serial Data Output A. This pin functions as a serial data output pin to access the conversion results and
register contents.
20 SDOB Serial Data Output B. This pin functions as a serial data output pin to access the conversion results.
21 SDI Serial Data Input. This input provides the data written to the on-chip control registers.
22 SCLK Serial Clock Input. This serial clock input is for data transfers to and from the ADC.
23 SDOC Serial Data Output C. This pin functions as a serial data output pin to access the conversion results and
register contents.
24 SDOD/ALERT Serial Data Output D/Alert Indication Output. This pin can operate as a serial data output pin or alert
indication output.
SDOD. This pin functions as a serial data output pin to access the conversion results.
ALERT. This pin operates as an alert pin going low to indicate that a conversion result has exceeded a
configured threshold.
Not applicable EPAD Exposed Pad. For correct operation of the device, the exposed pad must be connected to GND.

Rev. 0 | Page 9 of 31
AD7380-4 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

0 94
fIN = 1kHz VREF = 2.5V (INTERNAL)
–20 SNR = 91.71dB 92 VREF = 3.3V (EXTERNAL)
THD = –104.71dB
SINAD = 91.51dB 90
–40 VREF = 3.3V
88
–60
MAGNITUDE (dB)

86

SINAD (dB)
–80
84
–100
82
–120
80
–140
78

–160 76

–180 74

20802-110

20802-113
0 200 400 600 800 1000 1 10 100 1000
FREQUENCY (kHz) FREQUENCY (kHz)

Figure 10. Fast Fourier Transform (FFT), External Reference Voltage = 3.3 V Figure 13. SINAD vs. Frequency

94 96
VREF = 2.5V (EXTERNAL) VREF = 3.3V (EXTERNAL)
92 VREF = 3.3V (EXTERNAL) VREF = 2.5V (EXTERNAL)
94
90

88
92
86
SNR (dB)

SNR (dB)

84 90

82
88
80

78
86
76

74 84

20802-114
1 10 100 1000
20802-111

–40 –25 –10 5 20 35 50 65 80 95 110 125

FREQUENCY (kHz) TEMPERATURE (°C)

Figure 11. SNR vs. Frequency Figure 14. SNR vs. Temperature

–70 –80
VREF = 2.5V (EXTERNAL) VREF = 3.3V (EXTERNAL)
VREF = 3.3V (EXTERNAL) –85 VREF = 2.5V (EXTERNAL)
–75

–80 –90

–85 –95

–90 –100
THD (dB)
THD (dB)

–95 –105

–100 –110

–105 –115

–110 –120

–115 –125

–120 –130
20802-115
20802-112

1 10 100 1000 –40 –25 –10 5 20 35 50 65 80 95 110 125

FREQUENCY (kHz) TEMPERATURE (°C)

Figure 12. THD vs. Frequency Figure 15. THD vs. Temperature

Rev. 0 | Page 10 of 31
Data Sheet AD7380-4
96 –40
VREF = 3.3V (EXTERNAL)
VREF = 2.5V (EXTERNAL)
94 –50

–60
92
SINAD (dB)

CMRR (dB)
–70
90
–80

88
–90

86
–100

84 –110

20802-119
20802-116
–40 –25 –10 5 20 35 50 65 80 95 110 125 0.1 1 10 100 1000
TEMPERATURE (°C) RIPPLE FREQUENCY (kHz)

Figure 16. SINAD vs. Temperature Figure 19. CMRR vs. Ripple Frequency

60 110
VREF = 2.5V (EXTERNAL)
IVCC 100
50 ILOGIC
DYNAMIC CURRENT (mA)

90
40

PSRR (dB)
80
30
70

20
60

10
50

0 40

20802-120
20802-117

0 1 2 3 4 0.1 1 10 100 1000

THROUGHPUT RATE (MSPS) RIPPLE FREQUENCY (kHz)

Figure 17. Dynamic Current vs. Throughput Rate Figure 20. PSRR vs. Ripple Frequency

60 104
THROUGHPUT RATE = 4MSPS 102
VREF = 2.5V (EXTERNAL)
50 IVCC 100
ILOGIC
DYNAMIC CURRENT (mA)

98
40
96
SNR (dB)

94
30
92

86
20
90

10 88 VREF = 3.3V (EXTERNAL), RES = 1

VREF = 2.5V (EXTERNAL), RES = 1
86 VREF = 3.3V (EXTERNAL), RES = 0
VREF = 2.5V (EXTERNAL), RES = 0
0 84
20802-121
20802-118

–40 –25 –10 5 20 35 50 75 80 95 110 125 1 2 4 8 16 32

TEMPERATURE (°C) OVERSAMPLING RATIO

Figure 18. Dynamic Current vs. Temperature Figure 21. Normal Averaging Oversampling

Rev. 0 | Page 11 of 31
AD7380-4 Data Sheet
100 1.0

0.8
98
0.6
96
0.4

94 0.2

DNL (LSB)
SNR (dB)

92 0

–0.2
90
–0.4
88
–0.6
VREF = 3.3V (EXTERNAL), RES = 1
86 VREF = 2.5V (EXTERNAL), RES = 1
VREF = 3.3V (EXTERNAL), RES = 0 –0.8
VREF = 2.5V (EXTERNAL), RES = 0
84 –1.0

20802-122

20802-124
1 2 4 8 –32000 –24000 –16000 –8000 0 8000 16000 24000 32000
OVERSAMPLING RATIO CODE
Figure 22. Rolling Average Oversampling Figure 24. DNL vs. Code

1.0 180000
0.8
160000 153140
0.6
140000
0.4 NUMBER OF HITS
120000 AINx+ = AINx– = VREF ÷ 2
0.2 VREF = 2.5V
INL (LSB)

100000
0
80000
–0.2
62249
–0.4 60000
43957
–0.6 40000

–0.8 20000

0 2520 7
–1.0 0
20802-123

20802-125
–32000 –24000 –16000 –8000 0 8000 16000 24000 32000 –4 –3 –2 –1 0 1 2 3 4
CODE CODE
Figure 23. INL vs. Code Figure 25. Histogram

Rev. 0 | Page 12 of 31
Data Sheet AD7380-4

TERMINOLOGY
Differential Nonlinearity (DNL) Signal-to-Noise Ratio (SNR)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the SNR is the ratio of the rms value of the actual input signal to
maximum deviation from this ideal value. DNL is often the rms sum of all other spectral components below the
specified in terms of resolution for which no missing codes are Nyquist frequency, excluding harmonics and dc. The value for
guaranteed. SNR is expressed in decibels.
Integral Nonlinearity (INL) Spurious-Free Dynamic Range (SFDR)
INL is the deviation of each individual code from a line drawn SFDR is the difference, in decibels, between the rms amplitude
from negative full scale through positive full scale. The point of the input signal and the peak spurious signal.
used as negative full scale occurs ½ LSB before the first code Total Harmonic Distortion (THD)
transition. Positive full scale is defined as a level 1½ LSB THD is the ratio of the rms sum of the first five harmonic
beyond the last code transition. The deviation is measured from components to the rms value of a full-scale input signal and
the middle of each code to the true straight line. is expressed in decibels.
Gain Error Signal-to-Noise-and-Distortion (SINAD) Ratio
The first transition (from 100 … 000 to 100 …001) occurs at a SINAD is the ratio of the rms value of the actual input signal to
level ½ LSB above nominal negative full scale. The last transition the rms sum of all other spectral components that are less than
(from 011 … 110 to 011 … 111) occurs for an analog voltage the Nyquist frequency, including harmonics but excluding dc.
1½ LSB below the nominal full scale. The gain error is the The value for SINAD is expressed in decibels.
deviation of the difference between the actual level of the last
transition and the actual level of the first transition from the Common-Mode Rejection Ratio (CMRR)
difference between the ideal levels. CMRR is the ratio of the power in the ADC output at the
frequency, f, to the power of a 200 mV p-p sine wave applied to
Gain Error Drift the common-mode voltage of AINx+ and AINx− of frequency, f.
The gain error change due to a temperature change of 1°C. CMRR is expressed in decibels.
Gain Error Matching CMRR = 10log(PADC_IN/PADC_OUT)
Gain error matching is the difference in negative full-scale error
between the input channels and the difference in positive full- where:
scale error between the input channels. PADC_IN is the common-mode power at the frequency, f, applied
to the AINx+ and AINx− inputs.
Zero Error PADC_OUT is the power at the frequency, f, in the ADC output.
Zero error is the difference between the ideal midscale voltage,
0 V, and the actual voltage producing the midscale output code, Aperture Delay
0 LSB. Aperture delay is the measure of the acquisition performance
and is the time between the falling edge of the CS input and
Zero Error Temperature Drift
when the input signal is held for a conversion.
Zero error temperature drift is the zero error change due to a
temperature change of 1°C. Aperture Jitter
Aperture jitter is the variation in aperture delay.
Zero Error Match
Zero error match is the difference in zero error between the
input channels.

Rev. 0 | Page 13 of 31
AD7380-4 Data Sheet

THEORY OF OPERATION
CIRCUIT INFORMATION back into a balanced condition. When the comparator is
The AD7380-4 is a high speed, quad, fully differential 16-bit, SAR rebalanced, the conversion is complete. The control logic
analog-to-digital converters. The device operates from a 3.0 V generates the ADC output code. The output impedances of
to 3.6 V power supply and features throughput rates up to 4 the sources driving the AINx+ and AINx− pins must be matched.
MSPS. Otherwise, the two inputs have different settling times,
resulting in errors.
The AD7380-4 contains four successive approximation ADCs,
CAPACITIVE
and a serial interface with four separate data output pins. The DAC
device is housed in a 24-lead LFCSP, offering the user B CS COMPARATOR

considerable space-saving advantages over alternative AINx+

A SW1
solutions. CS
SW3 CONTROL
LOGIC
A SW2
AINx–
Data is accessed from the device via the serial interface. The
B
interface can be operated with two, four or one serial outputs.

20802-013
CAPACITIVE
The AD7380-4 uses an external reference voltage value ranging VREF DAC

from 2.5 V to VCC. The differential analog input range for the Figure 27. ADC Conversion Phase
AD7380-4 is VCM ± VREF/2.
ANALOG INPUT STRUCTURE
The AD7380-4 features on-chip oversampling blocks to
improve performance. Normal averaging and rolling average Figure 28 shows the equivalent circuit of the analog input struc-
oversampling modes are available. Power-down options to ture of the AD7380-4. The four diodes provide ESD protection
allow power saving between conversions are available. for the analog inputs. Ensure that the analog input signals never
Configuration of the device is implemented via the standard exceed the supply rails by more than 300 mV. Exceeding the limit
serial interface, as described in the Interface section. causes these diodes to become forward-biased and start
conducting into the substrate. These diodes can conduct up to
CONVERTER OPERATION 10 mA without causing irreversible damage to the device.
The AD7380-4 has four successive approximation ADCs, each The C1 capacitors in Figure 28 are typically 3 pF and can
based around two capacitive DACs. Figure 26 and Figure 27 primarily be attributed to pin capacitance. The R1 resistors
show simplified schematics of one of these ADCs in acquisition are lumped components made up of the on resistance of the
and conversion phases, respectively. The ADC comprises switches. The value of these resistors is typically about 200 Ω.
control logic, a SAR, and two capacitive DACs. In Figure 26 The C2 capacitors are the ADC sampling capacitors with a
(the acquisition phase), SW3 is closed, SW1 and SW2 are in typical capacitance of 15 pF.
Position A, the comparator is held in a balanced condition, VCC
and the sampling capacitor (CS) arrays can acquire the
differential signal on the input. D
R1 C2
AINx+
CAPACITIVE
DAC C1 D
B CS COMPARATOR
AINx+
A SW1
CONTROL VCC
SW3
CS LOGIC
A SW2
AINx–
D
B R1 C2
AINx–
20802-012

CAPACITIVE
VREF DAC C1 D
20802-014

Figure 26. ADC Acquisition Phase

When the ADC starts a conversion (see Figure 27), SW3 opens Figure 28. Equivalent Analog Input Circuit,
and SW1 and SW2 move to Position B, causing the comparator Conversion Phase—Switches Open, Track Phase—Switches Closed
to become unbalanced. Both inputs are disconnected when the
conversion begins. The control logic and charge redistribution
DACs are used to add and subtract fixed amounts of charge
from the sampling capacitor arrays to bring the comparator

Rev. 0 | Page 14 of 31
Data Sheet AD7380-4
ADC TRANSFER FUNCTION
The AD7380-4 uses a 2.5 V to 3.3 V reference. The AD7380-4
converts the differential voltage of the analog inputs (AINx+ and 011 ... 111

ADC CODE (TWOS COMPLEMENT)

AINx−) into a digital output. 011 ... 110
011 ... 101
The conversion result is MSB first, twos complement. The LSB
size is (2 × VREF)/2N, where N is the ADC resolution. The ADC
resolution is determined by the resolution of the device chosen
and if resolution boost mode is enabled. Table 9 outlines the
LSB size expressed in microvolts for different resolutions and
reference voltage options.
The ideal transfer characteristic of the AD7380-4 is shown in 100 ... 010

Figure 29. 100 ... 001

100 ... 000

–FSR –FSR – 1LSB +FSR – 1LSB

20802-015
–FSR – 0.5LSB +FSR – 1.5LSB

Figure 29. ADC Ideal Transfer Function (FSR = Full-Scale Range)

Table 9. LSB Size

Resolution (Bits) 2.5 V Reference (µV) 3.3 V Reference (µV)
16 76.3 100.7
18 19.1 25.2

V+ = 5V

V+

REF LDO LDO LDO

V+ 3.0V 1.65V
TO TO V–
3.6V 3.6V
VCM = VREF ÷ 2
10kΩ

10kΩ VREF = 2.5V TO 3.3V

1µF 1µF
AINx+ V+
VREF
VCM REFIN VCC
R
0V AINA+
C1 VLOGIC
V–
AINx– V+ C2 AD7380-4 1µF
VREF
VCM SDI
0V
R
AINA– 100Ω
SDOA
C1 100Ω
V– EXPOSED SDOB DIGITAL HOST
PAD (MICROPROCESSOR/
AINC+ SCLK FPGA)
AINC– CS
100Ω
AIND+ SDOC
100Ω
AIND– SDOD/ALERT

REGCAP GND

1µF

NOTES
20802-016

1. V– IS THE EXTERNAL SUPPLY VOLTAGE (–2.5V) FOR THE DRIVER AMPLIFIER.

2. PLACE DECOUPLING CAPACITORS CLOSE TO (IDEALLY, RIGHT UP AGAINST)
THE DEVICE SUPPLY PINS AND REFERENCE PIN.

Figure 30. Typical Application Circuit

Rev. 0 | Page 15 of 31
AD7380-4 Data Sheet

APPLICATIONS INFORMATION
Figure 30 shows an example of a typical application circuit for POWER SUPPLY
the AD7380-4. Decouple the VCC, VLOGIC, REGCAP, and REFIN For a typical application, the AD7380-4 circuitry shown in
pins with suitable decoupling capacitors as shown. The exposed Figure 30 can be driven from a 5 V (V+) supply to power the
pad is a ground reference point for circuitry on the device and system. The 5 V (V+) can be supplied from the ADP7104. The
must be connected to the board ground. ADC driver can be supplied by a 5 V (V+) and a −2.5 V (V−)
A differential RC filter must be placed on the analog inputs to derived from the inverting charge pump, the ADP5600, that
ensure optimal performance is achieved. In a typical converts 5 V to −5 V, then to the ADP7182 for the low noise
application, R = 33 Ω, C1 = 68 pF, and C2 = 68 pF are voltage regulator to output −2.5 V. Two independent power
recommended. These RC combinations must be the same for supply sources are derived from a low dropout (LDO) regulator
all channels of the AD7380-4. to power the VCC supply for the analog circuitry and the VLOGIC
The four differential channels of the AD7380-4 can accept an supply for the digital interface of the AD7380-4. A very low
input voltage range from 0 V to VREF and have a wide common- quiescent current LDO regulator like the ADP166 is a suitable
mode range to convert a variety of signals. These analog input supply with a fixed output voltage range from 1.2 V to 3.3 V for
pins (AINx±) can easily be driven with an amplifier. See Table 10 typical VCC and VLOGIC levels. The VCC supply and the VLOGIC
for the recommended driver amplifiers that can best fit and add supply must be decoupled separately with a 1 µF capacitor.
value to the application. Additionally, an LDO regulator supplies the AD7380-4. The on-
chip regulator provides a 1.9 V supply only for internal use on
The performance of the AD7380-4 can be impacted by noise on the device. Decouple the REGCAP pin with a 1 µF capacitor to
the digital interface. This impact is dependent on board layout GND.
and design. Keep a minimal distance of the digital line to the
digital interface or place a 100 Ω resistor in series and close to Power-Up
the SDOA, SDOB, SDOC, and SDOD/ALERT pins to reduce The AD7380-4 is not easily damaged by power supply
noise from the digital interface coupling of the AD7380-4. sequencing. VCC and VLOGIC can be applied in any sequence. The
external reference must be applied after VCC and VLOGIC are
The reference voltage of the AD7380-4 ranges from 2.5 V to
applied. Analog and digital signals must be applied after the
3.3 V. The ADR4533 or ADR4525 is an ultralow noise, high
external reference is applied.
accuracy voltage reference recommended to drive the AD7380-4
REFIN pin. A 1 µF reservoir capacitor is recommended to be The AD7380-4 requires tPOWERUP from applying VCC and VLOGIC
connected between the REFIN pin and the ground. When using until the ADC conversion results are stable. Interfacing with
this external reference voltage in another circuit within the the AD7380-4 prior to the setup time elapsing does not have a
application, for example, as a common-mode voltage for the negative impact on ADC operation. See Figure 4 for the
driver amplifier, it is recommended to use a buffer amplifier recommended signal condition during power-up. It is highly
like the ADA4807-2 for a stable reference. recommended to issue a software reset after power-up (see the
Software Reset section for details). Conversion results are not
guaranteed to meet data sheet specifications during this time,
however.

Table 10. Signal Chain Components

Companion Devices Part Name Description Typical Application
ADC Driver ADA4896-2 1 nV/√Hz, rail to rail output amplifier Precision, low noise, high frequency
ADA4940-2 Ultra low power, full differential, low distortion amplifier Precision, low density, low power
ADA4807-2 1 mA, rail to rail output amplifier Precision, low power, high frequency
External Reference ADR4525 Ultralow noise, high accuracy voltage reference 2.5 V reference voltage
ADR4533 Ultralow noise, high accuracy voltage reference 3.3 V reference voltage
Reference Buffer ADA4807-2 1 mA, rail to rail output amplifier Precision, low power, high frequency
LDO Regulator ADP166 Very low quiescent, 150 mA LDO regulator 3.0 V to 3.6 V supply for VCC and VLOGIC
ADP7104 500 mA low noise, CMOS LDO regulator 5 V supply
ADP7182 Low noise line regulator −2.5 V supply for ADC driver amplifier
ADP5600 Interleaved inverting charge pump with negative LDO Voltage inverter for negative supply

Rev. 0 | Page 16 of 31
Data Sheet AD7380-4

MODES OF OPERATION
The AD7380-4 has several on-chip configuration registers for in the OSR bits. The oversampling ratio of the digital filter is
controlling the operational mode of the device. controlled using the oversampling bits, OSR (see Table 11)
OVERSAMPLING Table 11 provides the oversampling bit decoding to select the
Oversampling is a common method used in analog electronics different oversample rates. The output result is decimated to
to improve the accuracy of the ADC result. Multiple samples of 16-bit resolution. If required, additional resolution can be
the analog input are captured and averaged to reduce the noise achieved by configuring the resolution boost bit (RES) in the
component from quantization noise and thermal noise (kTC Configuration 1 register. See the Resolution Boost section for
noise) of the ADC. The AD7380-4 offers an oversampling further details.
function on-chip. The AD7380-4 has two user configurable The number of samples (n), defined by the OSR bits, are taken
oversampling modes: normal averaging and rolling average. and added together, and the result is divided by n. The initial
The oversampling functionality is configured by programming ADC conversion is initiated by the falling edge of CS and the
the OS_MODE bit and OSR bits in the Configuration 1 AD7380-4 controls all subsequent samples in the oversampling
register. sequence internally. The sampling rate of the additional n
samples at the device maximum sampling rate is 4 MSPS. The
Normal Averaging Oversampling data is ready for readback on the next serial interface access.
Normal averaging oversampling mode can be used in After the averaging technique is applied, the sample data used
applications where slower output data rates are allowed and in the calculation is discarded. This process is repeated every
where higher SNR or dynamic range is desirable. Normal time the application needs a new conversion result and is
averaging involves taking a number of samples, adding them initiated by the next falling edge of CS.
together and dividing the result by the number of samples
As the output data rate is reduced by the oversampling ratio,
taken. This result is then output from the device. The sample
the serial peripheral interface (SPI) frequency required to
data is cleared when the process completes.
transmit the data is reduced accordingly.
Normal averaging oversampling mode is configured by setting
the OS_MODE bit to Logic 0 and having a valid nonzero value

Table 11. Normal Averaging Oversampling Overview

SNR (dB Typical)
2.5 V External Reference 3.3 V External Reference Data Output Rate
OSR, Bits[2:0] OS Ratio RES = 0 RES = 1 RES = 0 RES = 1 (kSPS Maximum)
000 No OS 90.8 90.8 92.5 92.5 4000
001 2 92 93 94 95.5 1500
010 4 94 96.5 95.2 98.2 750
011 8 95.8 99.2 96.3 100.5 375
100 16 96.3 100.4 96.8 101.2 187.5
101 32 96 101.2 97 102.2 93.75
110 Invalid Not applicable Not applicable Not applicable Not applicable Not applicable
111 Invalid Not applicable Not applicable Not applicable Not applicable Not applicable

CS

INTERNAL S1 ACQ S2 Sn ACQ S1 ACQ S2 Sn ACQ

SDOA DON’T CARE t0 RESULT

SDOB DON’T CARE t0 RESULT

20802-017

CONVERT START AT t0 CONVERT START AT t1

Figure 31. Normal Averaging Oversampling Operation

Rev. 0 | Page 17 of 31
AD7380-4 Data Sheet
Rolling Average Oversampling resolution can be achieved by configuring the resolution boost
Rolling average oversampling mode can be used in applications bit in the CONFIGURATION1 register. See the Resolution
where higher output data rates are required and where a higher Boost section for further details.
SNR or dynamic range is desirable. Rolling averaging involves In rolling average oversampling mode, all ADC conversions are
taking a number of samples, adding them together, and controlled and initiated by the falling edge of CS. When a
dividing the result by the number of samples taken. This result conversion is complete, the result is loaded into the FIFO. The
is then output from the device. The sample data is not cleared FIFO length is 8, regardless of the oversampling ratio set. The
when the process completes. The rolling oversampling mode FIFO is filled on the first conversion after a power-on reset
uses a first in, first out (FIFO) buffer of the most recent samples (POR), on the first conversion after a software controlled hard
in the averaging calculation, allowing the ADC throughput rate or soft reset. A new conversion result is shifted into the FIFO
and output data rate to stay the same. on completion of every ADC conversion regardless of the status
Rolling average oversampling mode is configured by setting the of the OSR bits and the OS_MODE bit. This conversion allows
OS_MODE bit to Logic 1 and having a valid nonzero value in a seamless transition from no oversampling to rolling average
the OSR bits. The oversampling ratio of the digital filter is oversampling, or different rolling average oversampling ratios
controlled using the oversampling bits, OSR (see Table 12). without waiting for the FIFO to fill.
Table 12 provides the oversampling bit decoding to select the The number of samples, n, defined by the OSR bits are taken
different oversample rates. The output result is decimated to from the FIFO, added together and the result is divided by n.
16-bit resolution for the AD7380-4. If required, additional

Table 12. Rolling Average Oversampling Overview

SNR (dB Typical)
2.5 V External Reference 3.3 V External Reference Data Output Rate
OSR, Bits[2:0] OS Ratio RES = 0 RES = 1 RES = 0 RES = 1 (kSPS Maximum)
000 No oversampling 91 91 92.5 92.5 4000
001 2 92 93 93 94 4000
010 4 94 95.4 95 97 4000
011 8 95.5 98 97 99 4000
110 Invalid Not applicable Not applicable Not applicable Not applicable Not applicable
111 Invalid Not applicable Not applicable Not applicable Not applicable Not applicable

VCC
tCYC
CS

INTERNAL S1 ACQ S2 ACQ S3 ACQ S4 ACQ S5 ACQ S6 ACQ S7 ACQ ...

SDI ENABLE OS = 2 ENABLE OS = 4

(FIFO1 + (FIFO1 + (FIFO1 + (FIFO1 + FIFO2 +

FIFO2)/2 FIFO2)/2 FIFO2)/2 FIFO3 + FIFO4)/4
SDOA
DON’T CARE S1 S2
SDOB

FIFO FIFO FIFO FIFO FIFO FIFO FIFO

1 S1 1 S2 1 S3 1 S4 1 S5 1 S6 1 S7
2 S1 2 S1 2 S2 2 S3 2 S4 2 S5 2 S6
3 S1 3 S1 3 S1 3 S2 3 S3 3 S4 3 S5
4 S1 4 S1 4 S1 4 S1 4 S2 4 S3 4 S4
5 S1 5 S1 5 S1 5 S1 5 S1 5 S2 5 S3
6 S1 6 S1 6 S1 6 S1 6 S1 6 S1 6 S2
20802-018

7 S1 7 S1 7 S1 7 S1 7 S1 7 S1 7 S1
8 S1 8 S1 8 S1 8 S1 8 S1 8 S1 8 S1

Figure 32. Rolling Average Oversampling Mode Configuration

Rev. 0 | Page 18 of 31
Data Sheet AD7380-4
RESOLUTION BOOST alert signals for all ADCs creates a common alert value. This
The default resolution and output data size for the AD7380-4 is value can be configured to drive out on the ALERT function of
16 bits. When the on-chip oversampling function is enabled the the SDOD/ALERT pin. The SDOD/ALERT pin is configured as
performance of the ADC can exceed the default resolution. To ALERT by configuring the following bits in CONFIGURATION1
accommodate the performance boost achievable, it is possible and CONFIGURATION2:
to enable an additional two bits of resolution. If the RES bit in • Set the SDO bits to any value other than 0b10.
the CONFIGURATION1 register is set to Logic 1 and the • Set the ALERT_EN bit to 1.
AD7380-4 is in a valid oversampling mode, the conversion
• Set a valid value in the alert high threshold register and the
result size for the AD7380-4 is 18 bits. In this mode, 18 SCLK
alert low threshold register.
cycles are required to propagate the data for the AD7380-4.
The alert indication function is available in oversampling
ALERT
(rolling average, normal averaging, and in nonoversampling
The alert functionality is an out of range indicator and can be modes).
used as an early indicator of an out of bounds conversion
The alert function of the SDOD/ALERT pin updates at the end
result. An alert event triggers when the value in the conversion
result register exceeds the alert high limit value in the alert high of conversion. The alert indication status bits in the ALERT
threshold register or falls below the alert low limit value in the register are updated as well and must be read before the end of
alert low threshold register. The alert high threshold register the next conversion.
and the alert low threshold register are common to all ADCs. Bits[7:0] in the alert indication register are cleared by reading
When setting the threshold limits, the alert high threshold must the alert indication register contents. The alert function of the
always be greater than the alert low threshold. Detailed alert SDOD/ALERT pin is cleared with a falling edge of CS. Issuing a
information is accessible in the alert indication register. software reset also clears the alert status in the alert indication
The register contains two status bits per ADC, one corresponding register.
to the high limit, and the other to the low limit. A logical OR of See Figure 8 for the ALERT timing diagram.
CS

SCLK 1 2 3 14 15 16 17 18

SDOA,
DB17 DB16 DB15 DB4 DB3 DB2 DB1 DB0
SDOB

20802-019
SDI DB15 DB14 DB13 DB2 DB1 DB0

Figure 33. Resolution Boost

Rev. 0 | Page 19 of 31
AD7380-4 Data Sheet
POWER MODES leaving shutdown mode. After exiting shutdown mode, allow
The AD7380-4 has two power modes that can be set in the sufficient time for the circuitry to turn on before starting a
Configuration 1 register: normal mode and shutdown mode. conversion.
These modes of operation provide flexible power management EXTERNAL REFERENCE
options, allowing optimization of the power dissipation and The AD7380-4 core refers to the voltage in the REFIN pin
throughput rate ratio for different application requirements. during ADC conversion. The reference voltage of the
Program the PMODE bit in the Configuration 1 register to AD7380-4 is driven through the REFIN pin. This pin can be
configure the power modes in the AD7380-4. Set PMODE to supplied with a voltage ranging from 2.5 V to 3.3 V. The
Logic 0 for normal mode and Logic 1 for shutdown mode. external reference voltage must have enough current to drive
Normal Mode the AD7380-4, which is a maximum of 1.2 mA. Connecting a
1 µF capacitor to the REFIN pin is recommended. The
Keep the AD7380-4 in normal mode to achieve the fastest
recommended external voltage reference is the ADR4525 for
throughput rate. All blocks within the AD7380-4 always remain
2.5 V and the ADR4533 for 3.3 V.
fully powered and an ADC conversion can be initiated by a
falling edge of CS when required. When the AD7380-4 is not SOFTWARE RESET
converting, it is in static mode and power consumption is The AD7380-4 has two reset modes: a soft reset and a hard
automatically reduced. Additional current is required to reset. A reset is initiated by writing to the reset bits in the
perform a conversion. Therefore, power consumption of the Configuration 2 register.
AD7380-4 scales with throughput. A soft reset maintains the contents of the configurable registers
Shutdown Mode but refreshes the interface and the ADC blocks. Any internal
When slower throughput rates and lower power consumption state machines are reinitialized, and the oversampling block
are required, use shutdown mode by either powering down the and FIFO are flushed. The alert indication register is cleared.
ADC between each conversion or by performing a series of The reference and LDO regulator remain powered.
conversions at a high throughput rate and then powering down A hard reset, in addition to the blocks reset by a soft reset,
the ADC for a relatively long duration between these burst resets all user registers to the default status, and resets the
conversions. When the AD7380-4 is in shutdown mode, all internal oscillator block.
analog circuitry powers down. The serial interface remains
DIAGNOSTIC SELF TEST
active during shutdown mode to allow the AD7380-4 to exit
shutdown mode. The AD7380-4 runs a diagnostic self test after a POR or after a
software hard reset to ensure that the correct configuration is
To enter shutdown mode, write to the power mode
loaded into the device.
configuration bit, PMODE, in the Configuration 1 register.
The result of the self test is displayed in the SETUP_F bit in the
The AD7380-4 shuts down, and current consumption reduces.
alert indication register. If the SETUP_F bit is set to Logic 1, the
To exit shutdown mode and return to normal mode, set the
diagnostic self test has failed. If the test fails, perform a software
PMODE bit in the CONFIGURATION1 register to Logic 0. All
hard reset to reset the AD7380-4 registers to the default status.
register configuration settings remain unchanged entering or
tSTARTUP

CS

SDI SHUTDOWN NORMAL

20802-021

POWER-DOWN NORMAL ACCURATE

MODE MODE CONVERSION

Figure 34. Shutdown Mode Operation

tRESET
CS
20802-022

SDI SOFTWARE RESET

Figure 35. Software Reset Operation

Rev. 0 | Page 20 of 31
Data Sheet AD7380-4

INTERFACE
The interface to the AD7380-4 is via a serial interface. The take the CS signal low, and the conversion result clocks out on
interface consists of CS, SCLK, SDOA, SDOB, SDOC, and the serial data output pins. The next conversion is also initiated
SDOD, and SDI. When referencing a single function of a at this point.
multifunction pin, only the portion of the pin name that is relevant The conversion result is shifted out of the device as a 16-bit
to the specification is listed, such as SDOD. For full pin names of result for the AD7380-4. The MSB of the conversion result is
multifunction pins, refer to the Pin Configuration and Function shifted out on the CS falling edge. The remaining data is shifted
Descriptions section.
out of the device under the control of the serial clock (SCLK)
The CS signal frames a serial data transfer and initiates an ADC input. The data is shifted out on the rising edge of SCLK, and
conversion process. The falling edge of CS puts the track-and- the data bits are valid on both the falling edge and the rising
hold into hold mode, at which point the analog input is edge. After the final SCLK falling edge, take CS high again to
sampled and the bus is taken out of three-state. The ADC return the serial data output pins to a high impedance state.
conversion operation is driven internally by an on-board The number of SCLK cycles to propagate the conversion results
oscillator and is independent of the SCLK signal. on the serial data output pins is dependent on the serial mode
The SCLK signal synchronizes data in and out of the device via of operation configured and if resolution boost mode is enabled
the SDOA, SDOB, SDOC, SDOD, and SDI signals. A minimum (see Figure 36 and Table 13 for details). If CRC reading is
of 16 SCLK cycles are required for a write to or read from a enabled, additional SCLK pulses are required to propagate the
register. The minimum numbers of SCLKs for a conversion CRC information. See the CRC section for more details.
read is dependent on the resolution of the device and the Because the CS signal initiates a conversion as well as framing
configuration settings (see Table 13).
the data any data access must be completed within a single frame.
The AD7380-4 has four serial output signals: SDOA, SDOB,
SDOC, and SDOD. Programming the SDO bits in the Table 13. Number of SCLK Cycles (n) Required for Reading
CONFIGURATION2 register configures 2-wire, 1-wire, or Conversion Results
4-wire mode. To achieve the highest throughput of the device, Interface Resolution No. of SCLK
it is required to use either the 2-wire or 4-wire mode to read the Configuration Boost Mode CRC Read Cycles
conversion results. If a reduced throughput is required or 4-Wire Disabled Disabled 16
oversampling is used, it is possible to use 1-wire mode, SDOA Enabled 24
signal only, for reading conversion results. Enabled Disabled 18
Enabled 26
Configuring cyclic redundancy check (CRC) operation for SPI
2-Wire Disabled Disabled 32
reads, SPI writes and oversampling mode with resolution boost
Enabled 40
mode enabled can alter the operation of the interface. Refer to
Enabled Disabled 36
the CRC section to ensure correct operation.
Enabled 44
READING CONVERSION RESULTS 1-Wire Disabled Disabled 64
The CS signal initiates the conversion process. A high to low Enabled 72
transition on the CS signal initiates a simultaneous conversion Enabled Disabled 72
of the four ADCs, ADC A, ADC B, ADC C, and ADC D. The Enabled 80
AD7380-4 has a one cycle readback latency. Therefore, the
conversion results are available on the next SPI access. Then,

CS

1 2 3 n–2 n–1 n1
SCLK

SDOx CONVERSION RESULTS

20802-223

1CONSULT TABLE 12 FOR VALUES FOR n, THE NUMBER OF SCLK PULSES REQUIRED.

Figure 36. Reading Conversion Results

Rev. 0 | Page 21 of 31
AD7380-4 Data Sheet
Serial 4-Wire Mode be configured to operate in 1-wire mode. In 1-wire mode, the
Configure 4-wire mode by setting the SDO bits to 0b10 in the conversion results from ADC A, ADC B, ADC C, and ADC D
CONFIGURATION2 register. In 4-wire mode, the conversion are output on SDOA. Additional SCLK cycles are required to
results for ADC A is output on SDOA, ADC B on SDOB, ADC propagate all data. ADC A data is output first followed by the
C on SDOC, and ADC D on SDOD. ADC B, ADC C, and ADC D conversion results.

Serial 2-Wire Mode LOW LATENCY READBACK

Configure 2-wire mode by setting the SDO bits to 0b00 in the The interface on the AD7380-4 has a one-cycle latency as shown
CONFIGURATION2 register. In 2-wire mode, the conversion in Figure 38. For applications that operate at lower throughput
results for ADC A and ADC C are output on SDOA. The rates the latency of reading the conversion result can be reduced.
conversion result for ADC B and ADC D are output on SDOB. After the conversion time (tCONVERT) elapses, a second CS pulse
Serial 1-Wire Mode after the initial CS pulse that initiated the conversion can be
used to read back the conversion result. This operation is shown
In applications where slower throughput rates are allowed or
in Figure 40
normal averaging oversampling is used the serial interface can
S0 S1 S2

CS

SDOA DON’T CARE ADC A S0 ADC A S1

SDOB DON’T CARE ADC B S 0 ADC B S1

SDOC DON’T CARE ADC C S 0 ADC C S1

SDOD DON’T CARE ADC D S 0 ADC D S1

SDI NOP NOP NOP

20802-038
tCYC

Figure 37. Read Conversion Results, 4-Wire Mode

S0 S1 S2 S3

CS

SDOA INVALID S0A S0C S1A S1C

SDOB INVALID S0B S0D S1B S1D

20802-024

SDI NOP NOP NOP

Figure 38. Read Conversion Results, 2-Wire Mode

S0 S1 S2 S3

CS

SDOA INVALID S0A S0B S0C S0D S1A S1B S1C S1D
20802-025

SDI NOP NOP NOP

Figure 39. Reading Conversion Results, 1-Wire Mode

CS

INTERNAL CNVn DON’T CARE ACQ CNV n + 1 DON’T CARE ACQ

SDOA, SDOB,
RESULTn RESULTn + 1
SDOC, SDOD
20802-026

SCLK
TARGET SAMPLE PERIOD

Figure 40. Low Throughput Low Latency

Rev. 0 | Page 22 of 31
Data Sheet AD7380-4
READING FROM DEVICE REGISTERS CRC
All registers in the device can be read over the serial interface. A The AD7380-4 has CRC checksum modes that can be used to
register read is performed by issuing a register read command improve interface robustness by detecting errors in data
followed by an additional SPI command that can be either a transmissions. The CRC feature is independently selectable for
valid command or no operation command (NOP). The format SPI interface reads and writes. For example, enable the CRC
for a read command is shown in Table 16. Bit D15 must be set function for SPI writes to prevent unexpected changes to the
to 0 to select a read command. Bits[D14:D12] contain the device configuration but do not enable it on SPI reads to maintain
register address. The subsequent 12 bits, Bits[D11:D0], are a higher throughput rate. The CRC feature is controlled by
ignored. programming of the CRC_W bit and CRC_R bit in the
CONFIGURATION1 register.
WRITING TO DEVICE REGISTERS
All the read/write registers in the AD7380-4 can be written to CRC Read
over the serial interface. The length of a SPI write access is If enabled, a CRC consisting of an 8-bit word is appended to the
determined by the CRC write function. An SPI access is 16 bits conversion result or register reads. The CRC is calculated on the
if CRC write is disabled and 24 bits when CRC write is enabled. conversion result for ADC A, ADC B, ADC C, and ADC D, and
The format for a write command is shown in Table 16. Bit D15 is output on SDOA. A CRC is also calculated and appended to
must be set to 1 to select a write command. Bits[D14:D12] register read outputs.
contain the register address. The subsequent 12 bits, Bits[D11:D0], The CRC read function can be used in 2-wire SPI mode, 1-wire
contain the data to be written to the selected register. SPI mode, 4-wire SPI mode, and resolution boost mode.

S0 S1 S2 S3 S4

CS

SDI NOP READ REG1 READ REG2 NOP NOP

SDOA INVALID RESULT S0 REG1 DATA REG 2 DATA RESULT S3

20802-027
SDOB,
SDOC, INVALID RESULT S0 RESULT S3
SDOD

Figure 41. Register Read

S0 S1 S2 S3

CS

SDI NOP WRITE REG 1 WRITE REG 2 NOP

20802-028

SDOx INVALID RESULT S0 RESULT S1 RESULT S2

Figure 42. Register Write

Rev. 0 | Page 23 of 31
AD7380-4 Data Sheet
CRC Write eight Logic 0s. The polynomial is aligned such that its MSB is
To enable the CRC write function, the CRC_W bit in the adjacent to the leftmost Logic 1 of the data. An exclusive OR
CONFIGURATION1 register must be set to 1. To set the (XOR) function is applied to the data to produce a new, shorter
CRC_W bit to 1 to enable the CRC feature, a valid CRC must number. The polynomial is again aligned such that its MSB is
be appended to the request frame. adjacent to the leftmost Logic 1 of the new result, and the
procedure is repeated. This process repeats until the original
After the CRC feature is enabled, all register write requests are
data is reduced to a value less than the polynomial, which is the
ignored unless they are accompanied by a valid CRC command.
8-bit checksum.
A valid CRC is required to both enable and disable the CRC
write feature. For example, the AD7380-4 polynomial is 100000111. Let the
original data of four channels be 0xAAAA, 0x5555, 0xAAAA,
CRC Polynomial and 0x5555. The eight MSBs of the data are inverted. The data
For CRC checksum calculations the following polynomial is is then appended to include eight 0s on right. In the final XOR
always used: x8 + x2 + x + 1. operation, the reduced data is less than the polynomial.
To generate the checksum, the 16-bit data conversion result Therefore, the remainder is the CRC for the assumed data.
of the four channels are combined to produce a 64-bit data
stream. The eight MSBs of the 64-bit data are inverted and the
data is appended by eight bits to create a number ending in
Table 14. Example CRC Calculation for 4-Channel, 16-Bit Data
Data 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X 1 X1 X1 X1 X1 X1 X1 X1
Process Data 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0
1 0 0 0 0 0 1 1 1
1 0 1 0 0 0 1 1 0
1 0 0 0 0 0 1 1 1
1 0 0 0 0 0 1 1 0
1 0 0 0 0 0 1 1 1
1 1 0 0 1 0 1 0 1
1 0 0 0 0 0 1 1 1
1 0 0 1 0 0 1 0 0
1 0 0 0 0 0 1 1 1
1 0 0 0 1 1 1 0 1
1 0 0 0 0 0 1 1 1
1 1 0 1 0 0 1 0 1
1 0 0 0 0 0 1 1 1
1 0 1 0 0 0 1 0 0
1 0 0 0 0 0 1 1 1
1 0 0 0 0 1 1 1 0
1 0 0 0 0 0 1 1 1
1 0 0 1 0 0 0 0 0
1 0 0 0 0 0 1 1 1
CRC 1 0 0 1 1 1 0 0
1
X means don’t care.

Rev. 0 | Page 24 of 31
Data Sheet AD7380-4
16 + 16 + 8 = 40 BITS

SDOA RESULT A RESULT C CRC A,B,C,D

2-WIRE 16-BIT
SDOB RESULT B RESULT D

16 + 16 + 16 + 16 + 8 = 72 BITS

1-WIRE 16-BIT SDOA RESULT A RESULT B RESULT C RESULT D CRC A,B,C,D

18 + 18 + 8 = 44 BITS

SDOA RESULT A RESULT C CRC A,B,C,D

2-WIRE 18-BIT
SDOB RESULT B RESULT D

18 + 18 + 18 + 18 + 8 = 80 BITS

1-WIRE 18-BIT SDOA RESULT A RESULT B RESULT C RESULT D CRC A,B,C,D

16 + 8 = 24 BITS

SDOA RESULT A CRC A,B,C,D

4-WIRE 16-BIT
SDOx RESULT x

18 + 8 = 26 BITS

SDOA RESULT A CRC A,B,C,D

4-WIRE 18-BIT
SDOx RESULT x

16 + 8 = 24 BITS

REGISTER SDOA REGISTER x CRC REG x

READ RESULT

16 + 8 = 24 BITS

REGISTER SDI REGISTER x CRC REG x

READ REQUEST

16 + 8 = 24 BITS

20802-030
REGISTER SDI WRITE REGISTER x CRC REG x
WRITE

Figure 43. CRC Operation

Rev. 0 | Page 25 of 31
AD7380-4 Data Sheet

REGISTERS
The AD7380-4 has user-programmable on-chip registers for configuring the device. Table 15 shows a complete overview of the registers
available on the AD7380-4.
The registers are either read/write (R/W) or read only (R).Any read request to a write only register is ignored. Any write to a read only
register is ignored. Writes to the NOP registers and the reserved register are ignored. Any read request to the NOP registers or reserved
registers are considered a no operation and the data transmitted in the next SPI frame are the conversion results.

Table 15. Register Description

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Reg Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset R/W
0x1 Configuration 1 [15:8] WR ADDRESSING RESERVED OS_MODE OSR, Bit 2 0x0000 R/W
[7:0] OSR, Bits[1:0] CRC_W CRC_R ALERTEN RES RESERVED PMODE
0x2 Configuration 2 [15:8] WR ADDRESSING RESERVED SDO, Bits[1:0] 0x0000 R/W
[7:0] RESET, Bits[7:0]
0x3 Alert [15:8] WR ADDRESSING RESERVED CRCW_F SETUP_F 0x0000 R
[7:0] AI_D_HIGH AI_D_LOW AI_C_HIGH AI_C_LOW AI_B_HIGH AI_B_LOW AI_A_HIGH AI_A_LOW
0x4 Alert Low [15:8] WR ADDRESSING ALERT_LOW, Bits[11:8] 0x0800 R
threshold [7:0] ALERT_LOW, Bits[7:0]
0x5 Alert high [15:8] WR ADDRESSING ALERT_HIGH, Bits[11:8] 0x07FF R/W
threshold [7:0] ALERT_HIGH, Bits[7:0]

ADDRESSING REGISTERS
A serial register transfer on the AD7380-4 consists of 16 SCLK cycles. The 4 MSBs written to the device are decoded to determine which
register is addressed. The four MSBs consist of the register address (REGADDR), Bits[2:0], and the read/write bit (WR). The register
address bits determine which on-chip register is selected. If the addressed register is a valid write register, the read/write bit determines
whether the remaining 12 bits of data on the SDI input are loaded into the addressed register. If the WR bit is 1, the bits load into the
register addressed by the register select bits. If the WR bit is 0, the command is seen as a read request. The addressed register data is
available to be read during the next read operation.

Table 16. Addressing Register Format

MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
WR REGADDR, Bits[2:0] Data, Bits[11:0]

Table 17. Bit Descriptions for Addressing Registers

Bit Mnemonic Description
D15 WR When a 1 is written to this bit, Bits[11:0] of this register are written to the register specified by REGADDR if it
is a valid address.
Alternatively, when a 0 is written, the next data sent out on the SDOA pin is a read from the designated
register if it is a valid address.
D14 to D12 REGADDR When WR = 1, the contents of REGADDR determine the register for selection as outlined in Table 15.
When WR = 0 and the REGADDR bits contain a valid register address, the contents on the requested register
are output on the SDOA pin during the next interface access.
When WR = 0 and the REGADDR bits contain 0x0, 0x6, or 0x7, the contents on the SDI line are ignored. The
next interface access results in the conversion results being read back.
D11 to D0 Data These bits are written into the corresponding register specified by the REGADDR bits when the WR bit = 1
and the REGADDR bits contain a valid address.

Rev. 0 | Page 26 of 31
Data Sheet AD7380-4
CONFIGURATION 1 REGISTER
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

[15:12] ADDRESSING (R/W) [0] PMODE (R/W)

Addressing. Power-Down Mode.

[11:10] RESERVED [1] RESERVED

[9] OS_MODE (R/W) [2] RES (R/W)

Oversampling Mode. Resolution.

[8:6] OSR (R/W) [3] ALERT_EN (R/W)

Oversampling Ratio. Enable Alert Indicator Function.

[5] CRC_W (R/W) [4] CRC_R (R/W)

CRC Write. CRC Read.

Table 18. Bit Descriptions for Configuration 1 Register

Bits Bit Name Description Reset Access
[15:12] ADDRESSING Addressing. Bits[15:12] define the address of the relevant register. See the Addressing 0x0 R/W
Registers section for further details.
[11:10] RESERVED Reserved. 0x0 R
9 OS_MODE Oversampling Mode. Sets the oversampling mode of the ADC. 0x0 R/W
0: normal averaging.
1: rolling average.
[8:6] OSR Oversampling Ratio. Sets the oversampling ratio for all the ADCs in the relevant mode. 0x0 R/W
Normal averaging mode supports oversampling ratios of 2×, 4×, 8×, 16×, and 32×. Rolling
average mode supports oversampling ratios of 2×, 4×, and 8×.
000: disabled.
001: 2×.
010: 4×.
011: 8×.
100: 16×.
101: 32×.
110: disabled.
111: disabled.
5 CRC_W CRC Write. Controls the CRC functionality for the SDI interface When setting this bit from a 0 0x0 R/W
to a 1, the command must be followed by a valid CRC to set this configuration bit. If a valid
CRC is not received, the entire frame is ignored. If the bit is set to 1, it requires a CRC to clear
it to 0.
0: no CRC function.
1: CRC function.
4 CRC_R CRC Read. Controls the CRC functionality for the SDOx interface 0x0 R/W
0: no CRC function.
1: CRC function.
3 ALERT_EN Enable Alert Indicator Function. This bit functions when the SDO bits = 01. Otherwise, the 0x0 R/W
ALERT_EN bit is ignored.
0: SDOB.
1: ALERT.
2 RES Resolution. Sets the size of the conversion result data. If OSR = 0, these bits are ignored and 0x0 R/W
the resolution is set to default resolution.
0: normal resolution.
1: 2-bit higher resolution.
1 Reserved Reserved. 0x0 R
0 PMODE Power-Down Mode. Sets the power modes 0x0 R/W
0: normal mode.
1: shutdown mode.

Rev. 0 | Page 27 of 31
AD7380-4 Data Sheet
CONFIGURATION 2 REGISTER
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

[15:12] ADDRESSING (R/W) [7:0] RESET (R/W)

Addressing Reset

[11:10] RESERVED [9:8] SDO (R/W)

SDO

Table 19. Bit Descriptions for Configuration 2 Register

Bits Bit Name Description Reset Access
[15:12] ADDRESSING Addressing Bits. These bits define the address of the relevant register. See the Addressing 0x0 R/W
Registers section for further details.
[11:10] RESERVED Reserved. 0x0 R
[9:8] SDO SDO. Conversion Results Serial Data Output 0x0 R/W
00: 2-wire output. Conversion data are output on both SDOA and SDOB.
01: 1-wire output. Conversion data are output on SDOA only.
10: 4-wire. Conversion data are output on SDOA, SDOB, SDOC, and SDOD/ALERT.
11: 1-wire. Conversion data are output on SDOA, only.
[7:0] RESET Reset. 0x0 R/W
0x3C: performs a soft reset. Refreshes some blocks, register contents remain unchanged.
Clears alert indication register and flushes any oversampling stored variables or active state
machine.
0xFF: performs a hard reset. Resets all possible blocks in the device. Registers contents are
set to defaults. All other values are ignored.

ALERT INDICATION REGISTER

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

[15:12] ADDRESSING (R) [0] AL_A_LOW (R)

Addressing. Alert A Low.
[11:10] RESERVED [1] AL_A_HIGH (R)
Alert A High.
[9] CRCW_F (R)
CRC Error. [2] AL_B_LOW (R)
Alert B Low.
[8] SETUP_F (R)
Load Error. [3] AL_B_HIGH (R)
Alert B High.
[7] AL_D_HIGH (R)
Alert D High. [4] AL_C_LOW (R)
Alert C Low.
[6] AL_D_LOW (R)
Alert D Low. [5] AL_C_HIGH (R)
Alert C High.

Table 20. Bit Descriptions for Alert Indication Register

Bits Bit Name Description Reset Access
[15:12] ADDRESSING Addressing. Bits[15:12] define the address of the relevant register. See the Addressing 0x0 R
Registers section for further details.
[11:10] RESERVED Reserved. 0x0 R
9 CRCW_F CRC Error. Indicates that a register write command failed due to a CRC error. This fault bit is 0x0 R
sticky and remains set until the register is read
0: no CRC error.
1: CRC error.
8 SETUP_F Load Error. The SETUP_F indicates that the device configuration data did not load correctly 0x0 R
on startup. This bit does not clear on an alert indication register read. A hard reset via the
Configuration 2 register is required to clear this bit and restart the device setup.
0: no setup error.
1: setup error.
7 AL_D_HIGH Alert D High. The alert indication high bit indicates if a conversion result for the respective 0x0 R
input channel exceeds the value set in the alert high threshold register. This fault bit is sticky
and remains set until the register is read.
1: alert indication.
0: no alert indication.
Rev. 0 | Page 28 of 31
Data Sheet AD7380-4
Bits Bit Name Description Reset Access
6 AL_D_LOW Alert D Low. The alert indication low bit indicates if a conversion result for the respective 0x0 R
input channel exceeds the value set in the alert low threshold register. This fault bit is sticky
and remains set until the register is read.
0: no alert indication.
1: alert indication.
5 AL_C_HIGH Alert C High. The alert indication high bit indicates if a conversion result for the respective 0x0 R
input channel exceeds the value set in the alert high threshold register. This fault bit is sticky
and remains set until the register is read.
1: alert indication.
0: no alert indication.
4 AL_C_LOW Alert C Low. The alert indication low bit indicates if a conversion result for the respective 0x0 R
input channel exceeds the value set in the alert low threshold register. This fault bit is sticky
and remains set until the register is read.
1: alert indication.
0: no alert indication.
3 AL_B_HIGH Alert B High. The alert indication high bit indicates if a conversion result for the respective 0x0 R
input channel exceeds the value set in the alert high threshold register. This fault bit is sticky
and remains set until the register is read.
1: alert indication.
0: no alert indication.
2 AL_B_LOW Alert B Low. The alert indication low bit indicates if a conversion result for the respective 0x0 R
input channel exceeds the value set in the alert low threshold register. This fault bit is sticky
and remains set until the register is read.
1: alert indication.
0: no alert indication.
1 AL_A_HIGH Alert A High. The alert indication high bit indicates if a conversion result for the respective 0x0 R
input channel exceeds the value set in the alert high threshold register. This fault bit is sticky
and remains set until the register is read.
0: no alert indication.
1: alert indication.
0 AL_A_LOW Alert A Low. The alert indication low bit indicates if a conversion result for the respective 0x0 R
input channel exceeds the value set in the alert low threshold register. This fault bit is sticky
and remains set until the register is read.
1: alert indication.
0: no alert indication.

ALERT LOW THRESHOLD REGISTER

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0

[15:12] ADDRESSING (R/W) [11:0] ALERT_LOW (R/W)

Addressing. Alert Low.

Table 21. Bit Descriptions for Alert Low Threshold Register

Bits Bit Name Descriptions Reset Access
[15:12] ADDRESSING Addressing. Bits[15:12] define the address of the relevant register. See the Addressing 0x0 R/W
Registers section for further details.
[11:0] ALERT_LOW Alert Low. Bits[11:0] from ALERT_LOW move to the MSBs of the internal alert low register, 0x800 R/W
D[15:4]. The remaining bits, D[3:0] of the internal register are fixed at 0x0. Sets an alert when
the converter result is below the value in the alert low threshold register, and the alert is
disabled when it is above the value in the alert low threshold register.

Rev. 0 | Page 29 of 31
AD7380-4 Data Sheet
ALERT HIGH THRESHOLD REGISTER
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1

[15:12] ADDRESSING (R/W) [11:0] ALERT_HIGH (R/W)

Addressing. Alert High.

Table 22. Bit Descriptions for Alert High Threshold Register

Bits Bit Name Description Reset Access
[15:12] ADDRESSING Addressing. Bits [15:12] define the address of the relevant register. See the Addressing 0x0 R/W
Registers Section for further details.
[11:0] ALERT_HIGH Alert High. Bits D[11:0] from ALERT_HIGH move to the MSBs of the internal alert high 0xFFF R/W
register, D[15:4]. The remaining bits, D[3:0] of the internal are fixed at 0xF. Sets an alert when
the converter result is above the value in the alert high threshold register, and the alert is
disabled when it is below the value in the alert high threshold register.

Rev. 0 | Page 30 of 31
Data Sheet AD7380-4

OUTLINE DIMENSIONS
4.10 0.30
4.00 SQ 0.25
PIN 1 3.90 0.20
CORNER PIN 1
INDICATOR
19 24

18 1
0.50 0.60
BSC
0.50 SQ
0.40

0.45
0.40
13 6
0.30 12 7

TOP VIEW BOTTOM VIEW

0.60
FOR PROPER CONNECTION OF
0.55 SIDE VIEW 0.050 MAX THE EXPOSED PAD, REFER TO
0.50 0.035 NOM THE PIN CONFIGURATION AND
COPLANARITY FUNCTION DESCRIPTIONS
SEATING 0.08 SECTION OF THIS DATA SHEET.
PLANE
0.152 REF

01-30-2017-A
PKG-005367

COMPLIANT TO JEDEC STANDARDS MO-248-UGGD

Figure 44. 24-Lead Lead Frame Chip Scale Package LFCSP

4 mm × 4 mm Body and 0.55 mm Package Height
(CP-24-25)
Dimensions shown in millimeters

ORDERING GUIDE
Model1, 2 Resolution Temperature Range Package Description Package Option
AD7380-4BCPZ 16-Bit −40°C to +125°C 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-25
AD7380-4BCPZ-RL 16-Bit −40°C to +125°C 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-25
AD7380-4BCPZ-RL7 16-Bit −40°C to +125°C 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-25
EVAL-AD7380-4FMCZ AD7380-4 Evaluation Board
EVAL-SDP-CH1Z Evaluation Board Controller
1
Z = RoHS Compliant Part.
2
The EVAL-AD7380-4FMCZ is compatible with the EVAL-SDP-CH1Z high speed controller board.

©2022 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D20802-1/22(0)

Rev. 0 | Page 31 of 31