MAHALAKSHMI

ENGINEERING COLLEGE
TIRUCHIRAPALLI 621213

QUESTION BANK
SEMESTER III

DEPARTMENT: CSE

SUBJECT NAME: DIGITAL PRINCIPLES AND SYSTEM DESIGN

SUBJECT CODE: CS6201
UNIT 2 : Design of Combinational Circuits
PART -A (2 Marks)
1. Design a half subtractor. (AUC MAY 2013)

2. Write down the truth table of full subtractor. (AUC MAY 2012 , 2013)

A
0
0
0
0
1
1
1
1

B
0
0
1
1
0
0
1
1

D
0
1
0
1
0
1
0
1

DIFFERENCE
0
1
1
0
1
0
0
1

BORROW
0
1
1
1
0
0
0
1

3. What is meant by look ahead carry ?

(AUC NOV 2011,NOV 2008)
In parallel addition time delay occurs,the process of overcoming this time delay is called
look ahead carry.
4. Give the logical expression for sum output and carry output of a full adder.
(AUC NOV 2011)
Sum = A + B + C
Carry =AB+AC+BC
5. Design a single bit magnitude comparator to compare two words A and B. (AUC
APR 2011)

A
0
0
1
1

B
0
1
0
1

A=B
1
0
0
1

A>B
0
0
1
0

A<B
0
1
0
0

6. Write an expression for borrow and difference in a full subtractor circuit.

2

(AUC APR 2010)

Difference = ABD+ABD+ABD+ABD
Borrow
= A + B+ D
7. Draw the circuits diagram for 4 bit Odd parity generator. (AUC APR 2010, APR
2007)
A

U8
3

2
XOR2

U10
3

(A+B) XNOR (C+D)

XOR2

C
1

U9
3

2
XOR2

8. Suggest a solution to overcome the limitation on the speed of an adder.

(AUC NOV 2009)
By eliminating the interstage carry delay we can increase the speed of addition.
9. Differentiate a decoder from a demultiplexer.

(AUC NOV 2009)

DECODER

DEMULTIPLEXER

A decoder is a multiple input ,multipleoutput logic circuit which converts coded

input into coded outputs, where the input
and output codes are different.

A demultiplexer is a circuit that receives

information on a single line and transmit
this information on one of the 2n possible
output lines.

10. Define combinational logic .

When logic gates are connected together to produce a specified output for certain
specified combinations of input variables, with no storage involved, the resulting circuit is
called combinational logic.

11. Define Decoder?

A decoder is a multiple - input multiple output logic circuit that converts coded inputs
into coded outputs where the input and output codes are different.
12. What is binary decoder?
A decoder is a combinational circuit that converts binary information from n input lines
to a maximum of 2n out puts lines.
13. Define Encoder?

An encoder has 2n input lines and n output lines. In encoder the output lines generate
the
binary code corresponding to the input value.
14. What is priority Encoder?
A priority encoder is an encoder circuit that includes the priority function. In priority
encoder, if 2 or more inputs are equal to 1 at the same time, the input having the highest
priority will take precedence.
15. Define multiplexer?
Multiplexer is a digital switch. If allows digital information from several sources to be
routed onto a single output line.
16. What do you mean by comparator?
A comparator is a special combinational circuit designed primarily to compare the
relative magnitude of two binary numbers.
17. What is propagation delay?
Propagation delay is the average transition delay time for the signal to propogate form
input to output when the signals changes its value. It is expressed in ms.
Part B (16 Marks)
1. Design a full adder using two half adders. (AUC MAY 2013)
Full adder takes a three-bits input. Adding two single-bit binary values X, Y with a carry
input bit C-in produces a sum bit S and a carry out C-out bit.

Truth Table
A
0
0
0
0
1
1
1
1

SUM (X, Y, Z) =

B
0
0
1
1
0
0
1
1

(1, 2, 4, 7)

CIN
0
1
0
1
0
1
0
1

CARRY (X, Y, Z) =

SUM
0
1
1
0
1
0
0
1

CARRY
0
0
0
1
0
1
1
1

(3, 5, 6, 7)

Kmap-SUM

SUM = X'Y'Z + XY'Z' + X'YZ'

SUM = X

Kmap -CARRY

CARRY = XY + XZ + YZ
Logic diagram:
Full adder circuit using half adders:

U1A
1

U3A

3
2

sum

1
3
7486

2
7486
U4A

U2A

3
3

2
7408

U5A

7408

carry

3
2
7432

SUM= A xor B xor CIN

CARRY = AB+BC+CA

2. Design a 4 bit magnitude comparator and draw the circuit. (AUC MAY 2013)
A magnitude comparator is a combinational circuit that compares the magnitude of two
numbers (A and B) and generates one of the following outputs: A=B, A>B, A<B.
GROUP
I
II

III

IV

A3
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0

A2
x
x
1
0
1
0
1
1
0
0
1
1
0
0
1
0

A1
x
x
x
x
x
x
1
0
1
0
1
1
0
0
1
0

A0
x
x
x
x
x
x
x
x
x
X
1
0
1
0
1
0

B3
0
1
1
1
0
0
1
1
0
0
1
1
0
0
0
1

B2
x
x
0
1
0
1
1
1
0
0
1
1
0
0
0
1

B1
x
x
x
x
x
x
0
1
0
1
1
1
0
0
0
1

Bo
x
x
X
X
X
x
x
X
X
X
0
1
0
1
0
1

Condition
A>B
A<B
A>B
A<B
A>B
A<B
A>B
A<B
A>B
A<B
A>B
A<B
A>B
A<B
A=B
A=B

Let
A3 EXNOR B3 =x3
A2 EXNOR B2 =x2
A1 EXNOR B1 =x1
A0 EXNOR B0 =x0
From the table
A>B = A3B3+X3 A2B2+X3X2A1B1+X3X2X1A0B0
A<B =A3B3+X3A2B2+X3X2A1B1+X3X2X1A0B0
A=B = X3X2X1X0
LOGIC DIAGRAM

3. Design a combinational circuit to convert binary to gray code. (AUC MAY 2013,2009)

biary to gray code converter

4 bit binary gray

o/p

4 bit binary input

BLOCK DIAGRAM

K-Map for G3:

G3 =
B3
K-Map for G2:

K-Map for G1:

K-Map for G0:

TRUTH TABLE:
|
Binary input

Gray code output

B3

B2

B1

B0

G3

G2

G1

G0

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0

0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0

0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0

4. Design Half and Full subtractor circuits (AUC MAY 2012)

SUBTRACTOR
Half subtractor The half-subtractor is a combinational circuit which is used to perform
subtraction of two bits. It has two inputs, X (minuend) and Y (subtrahend) and two outputs D
(difference) and B (borrow).

X
0
0
1
1

Y
0
1
0
1

D
0
1
1
0

B
0
1
0
0

The Full_subtractor is a combinational circuit which is used to perform subtraction of three bits.
It has three inputs, X (minuend) and Y (subtrahend) and Z (subtrahend) and two outputs D
(difference) and B (borrow).
Y
Z
D
B
X
0
0
0
0
0

0
0
0
1
1
1
1

0
1
1
0
0
1
1

1
0
1
0
1
0
1

1
1
0
1
0
0
1

1
1
1
0
0
0
1

B=A B + A C + BC
C=A xor B xor C
5. a)Draw the circuit of BCD adder and explain. (AUC NOV 2011,2013)

BCD addition is the same as binary addition with a bit of variation: whenever a sum is
greater than 1001, it is not a valid BCD number, so we add 0110 to it, to do the
correction. This will produce a carry, which is added to the next BCD position. Add the
two 4-bit BCD code inputs.

10

if the sum of this addition is greater than 1001; if yes, then add 0110 to this sum and generate
a carry to the next decimal position.

LOGIC DIAGRAM:

K MAP
Y = S4 (S3 + S2)
TRUTH TABLE:
BCD SUM
S4
0
0
0

S3
0
0
0

S2
0
0
1

S1
0
1
0

CARRY
C
0
0
0

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0
0
0
0
0
1
1
1
1
1
1
1
1

0
1
1
1
1
0
0
0
0
1
1
1
1

1
0
0
1
1
0
0
1
1
0
0
1
1

1
0
1
0
1
0
1
0
1
0
1
0
1

0
0
0
0
0
0
0
1
1
1
1
1
1

b) What is priority encoder? How is it different from encoder? Draw the circuit of 4
bit priority encoder and explain. (AUC NOV 2011)
If more than two inputs are active simultaneously, the output is unpredictable or rather it
is not what we expect it to be. This ambiguity is resolved if priority is established so that
only one input is encoded, no matter how many inputs are active at a given point of
time. The priority encoder includes a priority function. The operation of the priority
encoder is such that if two or more inputs are active at the same time, the input having
the highest priority will take precedence.
Example - 4to3 Priority Encoder

The truth table of a 4-input priority encoder is as shown below. The input D3 has
the highest priority, D2 has next highest priority, and D0 has the lowest priority. This
means output Y2 and Y1 are 0 only when none of the inputs D1, D2, D3 are high and
only D0 is high. A 4 to 3 encoder consists of four inputs and three outputs, truth table
and symbols of which is shown below.
Truth Table

D3
0
0
0
0
1

D2
0
0
0
1
x

D1
0
0
1
x
x

D0
0
1
x
x
x

Y2
0
0
0
0
1

Y1
0
0
1
1
0

Y0
0
1
0
1
0

Kmaps

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6. (i) Implement full subtractor using demultiplexer. (10) (AUC NOV 2009)
Full Subtracter

A full subtracter is a combinational circuit that performs subtraction involving

three bits, namely minuend, subtrahend, and borrow-in. The logic symbol and truth
table are shown below.
Truth Table
A
B
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Difference = m(1,2,4,7)
Borrow
= m(1,2,3,7)
A
A

I0 ,I3 ------- A

I0
0
4
A

Bin
0
1
0
1
0
1
0
1

difference
0
1
1
0
1
0
0
1

I1
1
5
A

Borrow
0
1
1
1
0
0
0
1

I2
2
6
A

I3
3
7
A

I1 ,I2 ----------A

(ii) Implement the given Boolean function using 8 : 1 multiplexer

F(A, B, C) = (1, 3, 5, 6) . (6) (AUC NOV 2009)
A
A

I0
0
4
0

I1
1
5
1

I2
2
6
A

I3
3
7
A

I0 -----------0 I1 ----------1 I2 ----------- A I3-------------A

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