Psoc
Psoc
Psoc
Cypress Semiconductor
198 Champion Court
San Jose, CA 95134-1709
Phone (USA): 800.858.1810
Phone (Intnl): 408.943.2600
http://www.cypress.com
Copyrights
Copyrights
Cypress Semiconductor Corporation, 2011. The information contained herein is subject to change without notice. Cypress
Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress
product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor
intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express
written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in lifesupport systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The
inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use
and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by
and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty
provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create
derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source
Code except as specified above is prohibited without the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described
herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein.
Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure
may reasonably be expected to result in significant injury to the user. The inclusion of Cypress product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all
charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
PSoC Creator is a trademark, and PSoC and CapSense are registered trademarks of Cypress Semiconductor Corp. All
other trademarks or registered trademarks referenced herein are property of the respective corporations.
Flash Code Protection
Cypress products meet the specifications contained in their particular Cypress PSoC Data Sheets. Cypress believes that its
family of PSoC products is one of the most secure families of its kind on the market today, regardless of how they are used.
There may be methods, unknown to Cypress, that can breach the code protection features. Any of these methods, to our
knowledge, would be dishonest and possibly illegal. Neither Cypress nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as unbreakable.
Cypress is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly
evolving. We at Cypress are committed to continuously improving the code protection features of our products.
Contents
1. Introduction
1.1
1.2
1.3
1.4
1.5
2. Getting Started
2.1
2.2
2.3
2.4
2.5
Introduction ..................................................................................................................9
Programming PSoC 5 Device ......................................................................................9
4. Hardware
4.1
4.2
Introduction ..................................................................................................................7
CD Installation .............................................................................................................7
Install Hardware...........................................................................................................8
Install Software ............................................................................................................8
Uninstall Software........................................................................................................8
3. Kit Operation
3.1
3.2
11
Contents
5. Code Examples
5.1
5.2
5.3
5.4
5.5
5.6
A. Appendix
A.1
A.2
A.3
A.4
25
35
Schematic.................................................................................................................. 35
Board Layout ............................................................................................................. 40
A.2.1 PDC-09356 Top ............................................................................................. 40
A.2.2 PDC-09356 Power ......................................................................................... 41
A.2.3 PDC-09356 Ground ....................................................................................... 42
A.2.4 PDC-09356 Bottom........................................................................................ 43
BOM .......................................................................................................................... 44
Pin Assignment Table................................................................................................ 47
1.
Introduction
Thank you for your interest in the CY8CKIT-050 PSoC 5 Development Kit. This kit allows you to
develop precision analog and low power designs using PSoC 5. You can design your own projects
with PSoC Creator or by altering the sample projects provided with this kit.
The CY8CKIT-050 PSoC 5 Development Kit is based on the PSoC 5 family of devices. PSoC 5 is a
Programmable System-on-Chip platform for 8-bit, 16-bit, and 32-bit applications. It combines
precision analog and digital logic with a high-performance CPU. With PSoC, you can create the
exact combination of peripherals and integrated proprietary IP to meet your application
requirements.
1.1
Kit Contents
The PSoC 5 Development Kit contains:
Development board
Kit CD
Inspect the contents of the kit; if you find any part missing, contact your nearest Cypress sales office
for help.
1.2
PSoC Creator
Cypress's PSoC Creator software is a state-of-the-art, easy-to-use integrated development
environment (IDE) that introduces a hardware and software design environment based on classic
schematic entry and revolutionary embedded design methodology.
With PSoC Creator, you can:
Create and share user-defined, custom peripherals using hierarchical schematic design.
Automatically place and route select components and integrate simple glue logic, normally
located in discrete muxes.
Trade-off hardware and software design considerations allowing you to focus on what matters
and getting to market faster.
PSoC Creator also enables you to tap into an entire tools ecosystem with integrated compiler tool
chains, RTOS solutions, and production programmers to support both PSoC 3 and PSoC 5.
Introduction
1.3
1.4
1.5
Document History
Revision
PDF Creation
Date
Origin of
Change
**
03/01/11
PVKV
*A
04/28/11
RKAD
Updated Schematic
*B
12/15/11
RKAD
Description of Change
Documentation Conventions
Table 1-1. Document Conventions for Guides
Convention
Usage
Courier New
Italics
[Bracketed, Bold]
Bold
Displays an equation:
2+2=4
2.
2.1
Getting Started
Introduction
This chapter describes how to install and configure the PSoC 5 Development Kit. Chapter 3
describes the kit operation. It explains how to program a PSoC 5 device with PSoC Programmer and
use the kit with the help of a code example code example. To reprogram the PSoC device with PSoC
Creator, see the CD installation instructions for PSoC Creator. Chapter 4 details the hardware
operation. Chapter 5 provides instructions to create a simple code example. The Appendix section
provides the schematics and BOM associated with the PSoC 5 Development Kit.
2.2
CD Installation
Follow these steps to install the PSoC 5 Development Kit software:
1. Insert the kit CD into the CD drive of your PC. The CD is designed to auto-run and the kit menu
appears.
Figure 2-1. Kit Menu
Note If auto-run does not execute, double-click cyautorun.exe on the root directory of the CD.
Getting Started
After the installation is complete, the kit contents are available at the following location:
C:\Program Files\Cypress\PSoC 5 Development Kit\1.0
2.3
Install Hardware
No hardware installation is required for this kit.
2.4
Install Software
When installing the PSoC 5 Development Kit, the installer checks if your system has the required
software. These include PSoC Creator, PSoC Programmer, Windows Installer, .NET, Acrobat
Reader, and KEIL Complier. If these applications are not installed, then the installer prompts you to
download and install them.
Install the following software from the kit CD:
1. PSoC Creator
2. PSoC Programmer 3.12.4 or later
Note When installing PSoC Programmer, select Typical on the Installation Type page.
3. Code examples (provided in the Firmware folder)
2.5
Uninstall Software
The software can be uninstalled using one of the following methods:
Go to Start > Control Panel > Add or Remove Programs; select the Remove button.
Go to Start > All Programs > Cypress > Cypress Update Manager > Cypress Update Manager; select the Uninstall button.
Insert the installation CD and click Install PSoC 5 Development Kit button. In the CyInstaller
for PSoC 5 Development Kit 1.0 window, select Remove from the Installation Type drop-down
menu. Follow the instructions to uninstall.
3.
3.1
Kit Operation
Introduction
The code examples in the PSoC 5 Development Kit help you develop applications using the PSoC 5
family of devices. The kit is designed to develop precision analog applications using PSoC 5. The
board also has hooks to enable low-power measurements for low-power application development
and evaluation.
3.2
When plugged in, the board enumerates as DVKProg5. After enumeration, initiate, build, and then
program using PSoC Creator.
When using on-board programming, it is not necessary to power the board from the 12-V or 9-V DC
supply or a battery. The USB power to the programming section can be used.
If the board is already powered from another source, plugging in the programming USB does not
damage the board.
Kit Operation
The PSoC 5 device on the board can also be programmed using a MiniProg3 (CY8CKIT-002). To
use MiniProg3 for programming, use the connector J3 on the board, as shown in Figure 3-2.
Note The MiniProg3 (CY8CKIT-002) is not part of the PSoC 5 Development Kit contents. It can be
purchased from the Cypress Online Store.
Figure 3-2. Connect MiniProg
With the MiniProg3, programming is similar to the on-board programmer; however, the setup
enumerates as a MiniProg3.
10
4.
4.1
Hardware
Programming interface
USB communications
Boost convertor
32-kHz crystal
24-MHz crystal
Prototyping area
11
Hardware
Power Adapter
Boost Converter
9 V Battery
Input
10-Pin JTAG/SWD/SWO
Debug and Prog Header
On-board
Programming
USB
10-Pin MiniTrace
Connector
32-kHz Crystal
24-MHz Crystal
Port D (CapSense/
Miscellaneous
Port)
Port E
(Analog Port)
Reset Button
Variable
Resistor/
Potentiometer
CapSense
RS-232
Interface
Prototyping Area
Switches/LEDs
4.2
Functional Description
4.2.1
Power Supply
The power supply system on this board is versatile; input supply can be from the following sources:
12
Power through boost convertor that uses the input test points VBAT and GND
Hardware
Vin rail: This is where the input of the on-board regulators are connected. This domain is
powered through protection diodes.
5-V rail: This is the output of the 5-V regulator U2. The rail is a fixed 5-V output regardless of
jumper settings. The voltage in this rail can be less than 5 V only when the board is powered by
the USB. This 5-V rail powers the circuits that require fixed 5-V supply.
3.3-V rail: This is the output of the 3.3-V regulator U4. This rail remains 3.3 V regardless of
jumper settings or power source changes. It powers the circuits requiring fixed 3.3-V supply such
as the on-board programming section.
Vddd rail: This rail provides power to the digital supply for the PSoC device. It can be derived
from either the 5-V or 3.3-V rail. The selection is made using J10 (3-pin jumper).
Vdda rail: This rail provides power to the analog supply of the PSoC device. It is the output of a
low noise regulator U1. The regulator is a variable output voltage and can be either 3.3 V or 5 V.
This is done by changing the position on J11 (3-pin jumper).
The following block diagram shows the structure of the power system on the board.
Figure 4-2. Power System Structure
USB
Programming
USB
Communication
Power
3.3 V
5V
Vin
3.3-V Regulator
Vddd
Selection
(J10)
Vddd
9-V Battery
5V
5-V Regulator
12-V/9-V Wall
wart
4.2.1.1
5-V/3.3-V Analog
Regulator
Vdda
Selection
(J11)
Vdda
13
Hardware
Two jumpers govern the power rails on the board. J10 is responsible for the selection of Vddd (digital
power) and J11 selects Vdda (analog power).
The jumper settings for each power scheme are as follows.
Powering Scheme
Jumper Settings
Vdda = 5 V, Vddd = 5 V
Warning:
4.2.1.2
The PSoC device performance is guaranteed when Vdda is greater than or equal to Vddd. Failure to meet this condition can have implications on the silicon performance.
When USB power is used, ensure a 3.3 V setting on both analog and digital supplies. This is
because, the 5 V rail of the USB power is not accurate and is not recommended.
Grounding Scheme
The board is designed considering analog designs as major target applications. Therefore, the
grounding scheme in the board is unique to ensure precision analog performance.
There are three types of ground on this board:
GND - This is the universal ground where all the regulators are referred. Both Vssd and Vssa
connect to this ground through a star connection.
Vssd - This is the digital ground and covers the digital circuitry on the board, such as RS-232 and
LCD.
Vssa - This is the analog ground and covers the grounding for analog circuitry present on the
board, such as the reference block.
When creating custom circuitry in the prototyping area provided on the board, remember to use the
Vssa for the sensitive analog circuits and Vssd for the digital ones.
Port E on the board is the designated analog expansion connector. This connector brings out
ports 0, 3, and 4, which are the best performing analog ports on PSoC 3 and PSoC 5 devices. The
expansion connector, port E, has two types of grounds. One is the analog ground (GND_A in silk
screen, Vssa in the schematic), which connects directly to the analog ground on the board. The
other ground, known as GND, is used for the digital and high current circuitry on the expansion
board. This differentiation on the connector grounds helps the expansion board designer to separate
the analog and digital ground on any high precision analog boards being designed for port E.
4.2.1.3
14
Hardware
The board provides the ability to measure analog and digital power separately. To measure power at
a single point, rather than at analog and digital separately, remove the resistor R23 to disconnect the
analog regulator from powering the Vdda and short Vdda and Vddd through R30. Now, the net
power can be measured at the J10 jumper similar to the digital power measurement. To switch
repeatedly between R23 and R30, moving around the zero-ohm resistors can be discomforting.
Hence, a J38 (unpopulated) is provided to populate a male 3-pin header and have a shorting jumper
in the place of R23/R30.
While measuring device power, make the following changes in the board to avoid leakage through
other components that are connected to the device power rails.
4.2.1.4
Disconnect the RS-232 power by disconnecting R58. An additional jumper capability is available
as J37 if you populate it with a 2-pin male header.
Ground the boost pins if boost operation is not used by populating R1, R28, and R29. Also make
sure R25 and R31 are not populated.
Power output: 12 W
Certification: CE certified
Some recommended part numbers include EPSA120100U-P5P-EJ (CUI Inc.) and LTE12W-S2 (Li
Tone Electronics Co. Ltd).
4.2.1.5
Battery Specifications
Use batteries with the following specifications:
Battery size: 9 V
Some recommended part numbers include 6LR61XWA/1SB (Panasonic), MN1604 (Duracell), and
6LR61 (Energizer).
4.2.2
Programming Interface
This kit allows programming in two modes:
4.2.2.1
15
Hardware
When the USB programming is plugged into the PC, it enumerates as DVKProg5 and you can use
the normal programming interface from PSoC Creator to program this board through the on-board
programmer.
A zero-ohm resistor R9 is provided on the board to disconnect power to the on-board programmer.
4.2.2.2
JTAG/SWD Programming
Apart from the on-board programming interface, the board also provides the option of using the
MiniProg3. This interface is much faster than the on-board program interface. The JTAG/SWD
programming is done through the 10-pin connector, J3.
Figure 4-5. JTAG/SWD Programming
16
Hardware
The JTAG/SWD programming using J3 requires the programmer, which can be purchased from
http://www.cypress.com/go/CY8CKIT-002.
4.2.3
USB Communication
The board has a USB communications interface that uses the connector, as shown in Figure 4-6.
The USB connector connects to the D+ and D lines on the PSoC to enable development of USB
applications using the board. This USB interface can also supply power to the board, as discussed in
Power Supply on page 12.
Figure 4-6. USB Interface
4.2.4
Boost Convertor
The PSoC 5 device has a unique capability of working from a voltage supply as low as 0.5 V. This is
possible using the boost convertor. The boost convertor uses an external inductor and a diode.
These components are prepopulated on the board. Figure 4-7 shows the boost convertor.
To enable the boost convertor functionality, make the following hardware changes on the board.
After making these changes, you can make a boost convertor based design by making the
appropriate configurations in the project. The input power supply to the boost convertor must be
provided through the test points marked Vbat and GND.
Note Due to a silicon defect, the boost circuitry works only for input greater than 1.8 V.
17
Hardware
4.2.5
4.2.6
4.2.6.1
Port D
This is the miscellaneous port on the board. It is designed to handle CapSense based application
boards and digital application boards. The signal routing to this port adheres to the stringent
requirements posed to provide good performance CapSense. This port can also be used for other
functions and Expansion Board Kits (EBKs).
This port is not designed for precision analog performance. The pins on the port are functionally
compatible to port B of the PSoC Development Kit. So any project made to function on port B of the
PSoC Development Kit can be easily ported over to port D on this board. A caveat to this is that
there is no opamp available on this port; therefore, opamp based designs are not recommended for
use on this port.
The following figure shows the pin mapping for the port.
18
Hardware
19
Hardware
4.2.6.2
Port E
This is the analog port on this kit and has special layout considerations. It also brings out all analog
resources such as dedicated opamps to a single connect. Therefore, this port is ideal for precision
analog design development. This port is functionally compatible to port A of the PSoC Development
Kit and it is easy to port an application developed on port A.
There are two types of grounds on this port, CGND1 and CGND2. The two grounds are connected to
the GND on the board, but are provided for expansion boards designed for analog performance. The
expansion boards have an analog and digital ground. The two grounds on this port help to keep it
distinct even on this board until it reaches the GND plane.
Figure 4-9. Port E
20
Hardware
4.2.7
RS-232 Interface
The board has an RS-232 transceiver for designs using RS-232 (UART). The RS-232 section power
can be disconnected through a single resistor R58. This is useful for low-power designs.
Figure 4-10. RS-232 Interface
4.2.8
Prototyping Area
The prototyping area on the board has two complete ports of the device for simple custom circuit
development. The ports in the area are port 0 and port 3, which bring out the four dedicated opamp
pins on the device. Therefore, these ports can be used with the prototyping area to create simple yet
elegant analog designs. It also brings SIOs such as port 12[4], port 12[5], port 12[6], and port 12[7]
and GPIOs such as port P6[0] and port P6[6]. There is power and ground connections close to the
prototyping space for convenience.
The area also has four LEDs and two switches for applications development. The two switches on
the board are hard-wired to port 15[5] and port 6[1]. Two LEDs out of the four are hard-wired to port
6[2] and port 6[3] and the other two are brought out on pads closer to the prototyping area.
21
Hardware
This area also comprises of a potentiometer to be used for analog system development work. The
potentiometer connects from Vdda, which is a noise free supply and is hence capable of being used
for low noise analog applications. The potentiometer output is available on P6[5] and VR on header
P6 in the prototyping area.
4.2.9
Character LCD
The kit has a character LCD module, which goes into the character LCD header, P8. The LCD runs
on a 3.3-V supply and can function regardless of the voltage on which PSoC is powered. There is a
zero-ohm resistor setting available on the LCD section (R71/72), making it possible to convert it to a
3.3 V LCD.
CAUTION: When the resistor is shifted to support a 5 V LCD module, plugging in a 3.3 V LCD module into the board can damage the LCD module.
Figure 4-12. Pin 1 Indication
22
Hardware
4.2.10
CapSense Sensors
The board layout has considered the special requirements for CapSense. It has two CapSense
buttons and a 5-element CapSense slider. The CapSense buttons are connected to pins P5[6] and
P5[5]. The slider elements are connected to pins P5[0:4].
The Cmod (modulation capacitor) is connected to pin P6[4] and an optional Rb (bleeder resistor) is
available on P15[4].
23
Hardware
24
5.
Code Examples
To access code examples described in this section, open the PSoC Creator start page. For
additional code examples, visit http://www.cypress.com.
Figure 5-1. PSoC Creator Start Page
25
Code Examples
5.1
Project: VoltageDisplay_SAR_ADC
5.1.1
Project Description
This example code measures an analog voltage controlled by the potentiometer. The code uses the
internal SAR ADC configured for a 12-bit operation; the ADC range is 0 to Vdda. The results are displayed on the character LCD.
Note The PSoC 5 Development Kit is factory-programmed with this example.
5.1.2
Hardware Connections
The example requires the character LCD on P8. Because it uses the potentiometer, the jumper
POT_PWR should be in place. This connects the potentiometer to the Vdda.
5.1.3
26
Free-running mode of operation is selected because the ADC scans only one channel continuously.
Conversion rate is set to 100 ksps. The code waits for each sample, processes it, and displays
the result on the LCD.
Range is set to Vssa to Vdda in single-ended mode because the potentiometer output is a single
ended signal that can go from 0 to Vdda. Therefore, at 12-bit resolution, the ADC will resolve in
steps of Vdda/212.
Code Examples
5.1.4
Voltage Reference should be set to Vdda supply voltage when Input Range is set to Vssa to
Vdda. It is set to 3.3 V here, because by default Vdda jumper setting on the board is set to 3.3 V.
If J11 is changed to select 5 V then this parameter should be changed to 5 V accordingly.
Verify Output
Build and program the code example and reset the device. The LCD shows the voltage reading corresponding to the voltage on the potentiometer. Figure 5-3 demonstrates the functionality. When you
turn the potentiometer, the voltage value changes. You can also verify the voltage on the potentiometer using a precision multimeter.
Note The potentiometer connects to a differential ADC, which works in single-ended mode. This
means the ADC input is measured against internal Vssa. Any offset in the measurement can be positive or negative. This can result in a small offset voltage even when the potentiometer is zero.
Figure 5-3. Voltage Display using SAR ADC
5.2
Project: VoltageDisplay_DelSigADC
5.2.1
Project Description
This example code measures a simple analog voltage controlled by the potentiometer. The code
uses the internal Del-Sig ADC configured for a 20-bit operation; the ADC range is 0 to Vdda. The
voltage measurement resolution is in microvolts. The results are displayed on the character LCD
module.
5.2.2
Hardware Connections
The example requires the character LCD on P8. Because it uses the potentiometer, the jumper
POT_PWR should be in place. This connects the potentiometer to the Vdda.
27
Code Examples
5.2.3
Continuous mode of operation is selected because the ADC scans only one channel.
Conversion rate is set to 187 samples/sec, which is the maximum sample rate possible at 20-bit
resolution.
Range is set to Vssa to Vdda in single ended mode because the potentiometer output is a single
ended signal that can go from 0 to Vdda. Therefore, at 20-bit resolution, the ADC will resolve in
steps of Vdda/220.
Note Internal Vdda/3 Reference option is not available in the current PSoC 5 silicon. In this project,
Vdda = 5 V. The project will not work if Vdda = 3.3 V, because it needs Vdda/3 reference for DelSig
ADC. To set Vdda to 5 V, in the VoltageDisplay_DelSigADC.cydwr window of PSoC Creator, click on
the System tab, go to Operating Conditions options. Set Vdda to 5 V.
28
Code Examples
5.2.4
Verify Output
Build and program the code example and reset the device. The LCD shows the voltage reading
corresponding to the voltage on the potentiometer. Figure 5-5 demonstrates the functionality. When
you turn the potentiometer, the voltage value changes. You can also verify the voltage on the
potentiometer using a precision multimeter.
Note The potentiometer connects to a differential ADC, which works in single ended mode. This
means the ADC input is measured against internal Vssa. Any offset in the measurement can be
positive or negative. This can result in a small offset voltage even when the potentiometer is zero.
Figure 5-5. Voltage Display using Del-Sig ADC
5.3
Project: IntensityLED
5.3.1
Project Description
This example code uses a pulse width modulator (PWM) to illuminate an LED. When the pulse width
of the PWM varies, the LED brightness changes. By continuously varying the pulse width of the
PWM, the example code makes an LED go from low brightness to a high brightness and back.
5.3.2
Hardware Connections
No hardware connections are required for this project, because all the connections are hard wired to
specific pins on the board.
5.3.3
Verify Output
When the example code is built and programmed into the device, reset the device by pressing the
Reset button or power cycling the board.
The project output is LED3 glowing with a brightness control that changes with time (see Figure 5-6).
29
Code Examples
5.4
Project: LowPowerDemo
5.4.1
Project Description
This code example demonstrates the low power functionality of PSoC 5. The project implements a
sleep timer based code, which goes to sleep and wakes up depending on the Sleep Timer interval.
The Sleep Timer component is configured to wake the device up every 16 ms. The LCD displays
time, which is updated once in a second.
5.4.2
Hardware Connections
The project requires a 3.3 V LCD to view the time display. No extra connections are required for
project functionality. To make low power measurements using this project, refer and implement the
changes proposed in Low Power Functionality on page 14.
5.4.3
Verify Output
The project displays the time on LCD starting from 00:00:01. The LCD will be on and display the time
when the device is in active mode; the LCD will be off when the device is in sleep mode. If an
ammeter is connected to measure the system current (see Low Power Functionality on page 14), a
system current of less than 730 A is displayed.
Note
The constant LCD_DELAY in the firmware is used to specify the delay required for the data to
remain on the LCD. The current consumption exceeds as the delay is increased. By default, this
delay is set to 300 msecs for the data to be visible clearly and current consumption is less than
730 A.
If the bus clock is 3 MHz and the LCD delay of 100 msecs, the current consumption is 250 A. To
set the bus clock, go to LowPowerDemo.cydwr, click on the Clocks tab, select Edit Clock, and
change IMO to 3 MHz.
30
Code Examples
5.5
Project: CapSense
5.5.1
Project Description
This code example provides a platform to build CapSense based projects using PSoC 5. The
example uses two CapSense buttons and one 5-element slider provided on the board. Each
capacitive sensor on the board is scanned using the Cypress CSD algorithm. The buttons are pretuned in the example code to take care of factors such as board parasitic.
5.5.2
Hardware Connections
This project uses the LCD for display; therefore, ensure that it is plugged into the port. There are no
specific hardware connections required for this project because all connections are hard wired on
the board.
5.5.3
Verify Output
Build and program the code example and reset the device. The LCD displays the status of the two
buttons as On/Off. The LCD also shows the slider touch position as a percentage. When you touch a
31
Code Examples
button, the LCD displays ON; when you remove the finger from the button, the LCD displays OFF.
When the slider is touched, the corresponding finger position is displayed as a percentage on the
LCD.
Figure 5-9. CapSense Slider
32
Code Examples
5.6
Project: ADC_DAC
5.6.1
Project Description
This project demonstrates sine wave generation by using an 8-bit DAC and DMA. The sine wave
period is based on the current value of the ADC value of the potentiometer.
The firmware reads the voltage output by the board potentiometer and displays the raw counts on
the board character LCD display. An 8-bit DAC outputs a table generated sine wave to an LED using
DMA at a frequency proportional to the ADC count.
5.6.2
Hardware Connections
For this example, the character LCD must be installed on P8. The example uses the potentiometer;
therefore, the jumper POT_PWR should also be in place. This jumper connects the potentiometer to
the Vdda.
5.6.3
Verify Output
Build, program the device, and press the Reset button on the PSoC 5 Development Kit to see the
ADC output displayed on the LCD. LED4 is an AC signal output whose period is based on the ADC.
Turning the potentiometer results in LCD value change. This also results in change in the period of
the sine wave fed into LED4. When the potentiometer changes, the blinking rate of LED4 changes.
Figure 5-11. ADC Output
33
Code Examples
34
Schematic
Power Supply
NO LOAD
TP4 RED
V5.0
5.0V/1A LDO
U2
3
3216
R24
AP1117D50G
TO-252
VIN
VOUT
2
C143216 +
D-64
9V Battery
Terminals
10 uFd 16v
GND
TP3 RED
NO LOAD
VSSD
GND
V3.3
R26
ZERO
V5.0
0805
SS12-E3/61T
GND
LM1117MPX-3.3
VOUT
GND
TAB
3216
U4
+ C15
10 uFd 16v
VDDA
GND
+ C5
GND
GND1
GND2
nSHDN
Byp
VDDA
GND
VSSD
1
1
VSSB
ZERO
NO LOAD
VSSA
VSSD
NO LOAD
VDDD
R11
1K
3
2
1
0805
0805
1
2
3
VSSA
LED Green
D5
R57
J38
V5.0
V3.3
VSSA
2 2
1
2
3
+ C13
330 ohm
0805
ZERO NO LOAD
3216
R15
GND
0805
1
0805
R13
3.74K
V5.0
VDDD
R30
R12
3.16K
SENSE
3
6
7
GND
0.1 uFd
C17
SENSE
5
10 uFd 16v
OUT
3
2 SENSE
1 SEL3V3
IN
0603
3216
BAT 9V MALE
VDDA_P
LT1763CS8
VDDA_P
RED
VDDD VDDA
VSSD
SEL3V3 2
U1
NEG2
NEG1
NEG3
9V
0402
BH1
5V/3.3V/0.5A LDO
0603
GND
2
1
3
R23
ZERO
0805
BAT 9V FEMALE
J33
3.3V/0.8A LDO
VIN
+ C2
10 uFd 16v
10 uFd 16v
3216
SOT-223
3
2
1
3
POS2
POS1
POS3
BH2
C4
D4
0805
ZERO
VIN
SS12-E3/61T
1
J4
D-64
10 uFd 16v
D3
1 2
3
2
GND
+9V/+12V, 1A
3
2
1
A.1
Appendix
VSSD
VSSA
J11
3
2
1
A.
J10
Note:
For 5V: J11-3 to J11-2, J10-3 to J10-2
For 3.3V: J11-2 to J11-1, J10-2 to J10-1
For 5V Analog,3.3V Digital: J11-3 to J11-2, J10-2 to J10-1
Note: Load R25, R29 and R31 for operating the device on Boost
VDDD
Ind
VDDA
R31
NO LOAD
0805
R25
NO LOAD
L1
Vboost
0805
R29
NO LOAD
VBAT
TP2
RED
0805
VBAT
D6
1 R27
ZERO
SOT23
7032
0805
22 uH
0805
0402
GND
GND
0.1 uFd
1210
C6
22 uFd
10V
C22
22 uFd
10V
TP1
BLACK
GND
1210
GND
C23
0805
C3
R1
NO LOAD
ZHCS
0402
0.1 uFd
R28
NO LOAD
VSSB
Note: Load R1,R28 and Un-Load R27 for low power application
35
VDDD
VDDD
VCCd
C42
1.0 uFd
C44
1.0 uFd VDDD
ZERO
CY 8C5568AXI-060 TQFP100
VDDD
P3[0]
P3[1]
P3[2]
P3[3]
P3[4]
P3[5]
NO LOAD
1
1
1
R39
ZERO
P0[3]
P0[2]
P0[1]
P0[0]
P4[1]
P4[0]
P12[3]
P12[2]
C40
0.1 uFd
VDDA
VSSA
VCCa
C37
C36
C38
1.0 uFd
0.1 uFd
0.1 uFd
VSSA
VSSD
32.768KHz XTAL
Y2
1
2
P12[1]
P12[0]
P3[7]
P3[6]
VSSA
J16
1
P1[6]
P1[7]
P12[6]
P12[7]
P5[4]
P5[5]
P5[6]
P5[7]
DP_P
DM_P
R36
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDDio0
P0_3
P0_2
P0_1
P0_0
P4_1
P4_0
SIO_P12_3
SIO_P12_2
VSSd
VDDa
VSSa
VCCa
NC8
NC7
NC6
NC5
NC4
NC3
P15_3
P15_2
SIO, I2C1_SDA P12_1
SIO, I2C1_SCL P12_0
P3_7
P3_6
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
TP5
NO LOAD
P2_5
P2_6
P2_7
P12_4 I2C0_SCL, SIO
P12_5 I2C0_SDA, SIO
P6_4
P6_5
P6_6
P6_7
VSSb
Ind
Vboost
Vbat
VSSd
XRES
P5_0
P5_1
P5_2
P5_3
P1_0
P1_1
P1_2
P1_3
P1_4
P1_5
VDDA
1 PIN HDR
NO LOAD
VSSD
VSSB
/XRES
P5[0]
P5[1]
P5[2]
P5[3]
SWDIO
SWDCK
P1[2]
SWO
TDI
P1[5]
VSSD
3
4
5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Ind
Vboost
VBAT
J22
VDDio2
P2_4
P2_3
P2_2
P2_1
P2_0
P15_5
P15_4
P6_3
P6_2
P6_1
P6_0
VDDd
VSSd
VCCd
P4_7
P4_6
P4_5
P4_4
P4_3
P4_2
P0_7
P0_6
P0_5
P0_4
R8 NO LOAD
1.5K
P2[5]
P2[6]
P2[7]
P12[4]
P12[5]
P6[4]
P6[5]
P6[6]
P6[7]
C39
J8
NO LOAD
R38
2.2K
R2
3K
U7
VSSD
J12
C25
22 pFd
VBUS2
VSSD
0.1 uFd
C43
P4[7]
P4[6]
P4[5]
P4[4]
P4[3]
P4[2]
P0[7]
P0[6]
P0[5]
P0[4]
P2[4]
P2[3]
P2[2]
P2[1]
P2[0]
P15[5]
P15[4]
P6[3]
P6[2]
P6[1]
P6[0]
1 PIN HDR
NO LOAD
P15[4]
Rbleed
J26
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
1 PIN HDR
VDDA
VSSD
VDDio1
P1_6
P1_7
P12_6_SIO
P12_7_SIO
P5_4
P5_5
P5_6
P5_7
P15_6 DP
P15_7 DM
VDDd
VSSd
VCCd
NC1
NC2
P15_0
P15_1
P3_0
P3_1
P3_2
P3_3
P3_4
P3_5
VDDio3
J25
R47
C41
0.1 uFd
C27
22 pFd
NO LOAD
1 PIN HDR
VSSA
VSSA
VDDA
1 PIN HDR
NO LOAD
C34
0.1 uFd
VDDD
C29
C33
0.1 uFd
VSSD
C31
22 pFd
VSSD
1.0 uFd
R35
ZERO
VCCd
DP 1
DM 1
22E R33
2
2
22E R32
ZERO
J18
C35
0.1 uFd
VSSD
Y3
24 MHz Cry stal
C30
22 pFd
C26
0.1 uFd
VSSA
PSoC 5
VSSA
Note:
Place De-Caps near to the Chip
36
C7
0402
C18
0402
0.1 uFd
C12
0402
0.1 uFd
C20
VDDD
13
TV-20R
TV2
1
TP2
3V3_FX12P
VCC
8-SOIC
1
2
R5
2.2K
15
16
XTALOUT
45
46
47
48
49
50
51
52
J40
1
3
5
7
9
/XRES
1 TV1
P2[3]
P2[4]
P2[5]
P2[6]
P2[7]
2
4
6
8
10
SWDIO
SWDCK
SWO
VBUS1
R21
39K
1%
GND
GND
P3[0]
P3[1]
P3[2]
P3[3]
P3[4]
P3[5]
P3[6]
P3[7]
8
7
6
5
4
3
2
1
VDDD
J5
330 ohm
2
330 ohm
2
P5[6]
330 ohm
2
R60
P5[5]
R61
P5[4]
NO LOAD
P5[3]
VSSD
1 PIN HDR
P5[0]
LED2
1
2
0805
0805
LED Red
VSSD
R55 10K
VSSA
NO LOAD
P15[5]
Note: Load R56 for
high precision analog
SW3
SW2
1A
1B
2A
2B
1A
1B
P6[1]
SW PUSHBUTTON
2A
2B
NO LOAD
VSSA
R48
0603
ZERO
0603
0603
0603
ZERO
0603
0603
ZERO
ZERO
ZERO
P6[5]
LED1
LED2
SW PUSHBUTTON
ZERO
CSB1
CapSense
0805
R54
330 ohm
2
V5.0 V3.3
8
7
6
5
4
3
2
1
ZERO
8
7
6
5
4
3
2
1
C45 P6[3]
R59
VDDA
P6
10 uFd 16v
LED Red
LED4
0805
1
0805
0805
P6[5]
P6[2]
3216
1
POT 10K R56
0603
LED Red
LED3
P6[5]
LED Red
LED2
J30
1
2
R62
1
0805
0805
VDDA
2A
2B
SW PUSHBUTTON
NO LOAD
P5[2]
P3
RECP 8X1
LED1
LED1
Breadboard
NO LOAD
SW1
1A
1B
/XRES
P5[1]
NO LOAD
P4
RECP 8X1
Prototype Area
8
7
6
5
4
3
2
1
P0[0]
P0[1]
P0[2]
P0[3]
P0[4]
P0[5]
P0[6]
P0[7]
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
GND
J50
R22
62K
1%
14
57
26
28
53
56
12
41
FX2LP Programmer
FIRMWARE UPDATE
REQUIRED FOR
USB BACKVOLTAGE
COMPLIANCE.
0603
6
10
CP
GND3
GND4
GND5
GND6
GND
24LC00/SN 8-SOIC
GND1
GND2
AGND1
AGND2
1
2
3
7
SDA
SCL
SDA
18
19
20
21
22
23
24
25
SWD/SWV/JTAG
VDDD
0603
PD0/FD8
PD1/FD9
PD2/FD10
PD3/FD11
PD4/FD12
PD5/FD13
PD6/FD14
PD7/FD15
RDY0/SLRD
RDY1/SLWR
GND
NC1
NC2
NC3
NC4
R6
2.2K
0402
SCL
0402
U3
CTL0/FLAGA
CTL1/FLAGB
CTL2/FLAGC
33
34
35
36
37
38
39
40
RESERVED
6
7
0402
GND
WAKEUP#
29
30
31
NO LOAD
0.01 uFd
CLKOUT
44
VSSD
PB0/FD0
PB1/FD1
PB2/FD2
PB3/FD3
PB4/FD4
PB5/FD5
PB6/FD6
PB7/FD7
IFCLK
54
0.1 uFd
SWDIO
SWDCK
SWO
TDI
/XRES
2
4
6
8
10
10K
0402
0402
D-64
D-64
D-64
R17
J9
DMINUS
DPLUS
3V3_FX12P
100K
0402
PA0/nINT0
PA1/nINT1
PA2/SLOE
PA3/WU2
PA4/FIFOADR0
PA5/FIFOADR1
U5
PA6/PKTEND
PA7/FLAGD
CY7C68013A-56LTXC
RESET#
9
8
USB MINI B
C8
AVCC1
AVCC2
D11
1
D9
1
D10
1
D+
D-
1
3
5
7
9
C1
3
7
42
J3
1
Y1
24 MHz
XTALIN
0.1 uFd
GND
0805
2
11
32
C16
0402
VBUS1
R3
GND
VCC1
VCC2
C11
2.2 uFd
6.3V
0402
0.1 uFd
1
2
3
4
5
VBUS
DM
DP
ID
GND
R9
ZERO
17
27
43
55
VBUS1 2
C19
0402
GND
S1
S2
0.1 uFd
VCC3
VCC4
VCC5
VCC6
D-64
D-64
0603
R14
100K
1%
J1
S3
S4
C10
0402
0.1 uFd
1
1
SS12-E3/61T
SS12-E3/61T
D2
8
9
0402
V3.3
V5.0
VBUS1 2
D8
C21
0.1 uFd
GND
3V3_FX12P
VIN
0402
0.1 uFd
CSB2
CapSense
VSSD
J14
VSSD
P6[6]
P6[0]
P12[7]
P12[6]
P12[5]
P12[4]
J32
NO LOAD
J34
NO LOAD
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
J31
NO LOAD
VSSA
VDDD
J29
NO LOAD
J28
1
VSSA
NO LOAD
1 PIN HDR
VDDA
NO LOAD
1 PIN HDR
VDDD
J35
J6
1 PIN HDR
VSSD
NO LOAD J7
1
1
NO LOAD J36
1
1
J27
VDDA
VSSD
VSSD
VDDD
VSSD
VSSA
VSSD
P9 RECP 8X1
37
GND
CGND1
Use Separate Track
for CGND1 to GND
P1
P3[6]
P3[4]
P3[2]
P3[0]
J23
P0[6]
P0[4]
P0[2]
P0[0]
NO LOAD
J20
P4[6]
P4[4]
P4[2]
P4[0]
NO LOAD
J17
1
NO LOAD
J13
P12[2]
SCL P12[0]
V5.0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
P3[7]
P3[5]
P3[3]
P3[1]
Expansion Connectors
P2
J15
P0[7]
P0[5]
P0[3]
P0[1]
P2[6]
P2[4]
P2[2]
P2[0]
NO LOAD
J19
P4[7]
P4[5]
P4[3]
P4[1]
1
P5[6]
P5[4]
P5[2]
P5[0]
NO LOAD
J21
P12[3]
P12[1] SDA
VSSA
V3.3
1
NO LOAD
J24
VIN
1
P12[2]
SCL P12[0]
V5.0
NO LOAD
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
P1[6]
TDI
P1[2]
SWDIO
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
P1[7]
P1[5]
SWO
SWDCK
P2[7]
P2[5]
P2[3]
P2[1]
P5[7]
P5[5]
P5[3]
P5[1]
P12[3]
P12[1] SDA
V3.3
VIN
NO LOAD
20x2 RECP RA
20x2 RECP RA
CGND1
CGND1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
VSSD
VSSD
VDDA
NO LOAD
J39
1 R73
ZERO
VREF
2 P0[3]
LM4140 NO LOAD
VIN
VREF
VREF
NO LOAD
1 R34
ZERO
C24
1.0 uFd
NO LOAD
1 R37
ZERO
0603
NC
VSSA
3216
C32
+
C28
0402
0.1 uFd
VSSA
1
4
7
8
GND
GND1
GND2
GND3
EN
10 uFd 16v
0805
2 P3[2]
0805
0805
U6
VSSA
38
Voltage Reference
39
A.2
Board Layout
A.2.1
PDC-09356 Top
40
A.2.2
PDC-09356 Power
41
A.2.3
42
PDC-09356 Ground
A.2.4
PDC-09356 Bottom
43
A.3
BOM
Item Qty
Reference
Value
Description
Manufacturer
PCB
Cypress
PDC-09356
BH1
BAT 9V MALE
Keystone Electronics
593
BH2
BAT 9V FEMALE
594
C2,C4,C5,C13,C14,C
15,C28,C45,C46
10 uFd 16v
TAJA106K016R
C6,C22
22 uFd
C1210C226K8PACTU
29
C7,C10,C12,C16,C17,
C18,C19,C20,C21,C2
6,C32,C33,C34,C35,C
36,C38,C40,C41,C43, 0.1 uFd
C47,C48,C49,C50,C5
1,C52, C53, C1, C3,
C23
Panasonic - ECG
ECJ-0EF1C104Z
C8,C9
0.01 uFd
Panasonic - ECG
ECJ-0EB1C103K
C11
2.2 uFd
Panasonic - ECG
ECJ-0EB0J225M
C29,C37,C42,C44
1.0 uFd
TMK107BJ105KA-T
C25, C27
22pF
ECJ-0EC1H220J
10
C39
2200 pFd
GRM2165C1H222JA01
D
11
D1,D2,D3,D4, D7, D8
SS12-E3/61T
Vishay/General Semiconductor
SS12-E3/61T
12
D5
LED Green
Chicago Miniature
CMD17-21VGC/TR8
13
D6
ZHCS
Zetex
ZHCS1000TA
14
J1,J2
USB MINI B
TYCO
1734035-2
15
J3, J40
50MIL KEYED
SMD
16
J4
CUI
PJ-102A
17
BLACK TEST
POINT
Keystone Electronics
5001
19
LED1,LED2,LED3,LE
D4
LED Red
Rohm Semiconductor
SML-210LTT86
20
L1
22 uH
TDK Corporation
SLF7032T-220MR96-2PF
21
P1,P2
20x2 RECP RA
PPPC202LJBN-RC
22
P7
DB9 FEMALE
Norcomp Inc.
191-009-223R001
23
P8
Tyco Electronics
1-534237-4
24
R3,R4
100K
Panasonic - ECG
ERJ-2GEJ104X
44
AVX
Panasonic - ECG
FTSH-105-01-L-DV-K
Item Qty
Reference
25
R9,R23,R24,R26,R27,
ZERO
R71
Value
Description
Manufacturer
ERJ-6GEY0R00V
26
R5,R6
2.2K
ERJ-2GEJ222X
27
R11
1K
ERJ-6GEYJ102V
28
R12
3.16K
Yageo
RT0603DRD073K16L
29
R13
3.74K
Panasonic - ECG
ERJ-3EKF3741V
30
R14
100K
Yageo
RC0603FR-07100KL
31
R15,R59,R60,R61,R6
330 ohm
2
ERJ-6GEYJ331V
32
R17,R40,R41,R42,R4
10K
3,R44,R45,R46
33
13
R35,R36,R39,R47,R4
8,R49,R50,R51,R52,R ZERO
53,R54,R64,R66
Panasonic - ECG
ERJ-3GEY0R00V
34
R32,R33
22E
Panasonic - ECG
ERJ-3EKF22R0V
35
R63,R65
100 ohm
Rohm
MCR10EZHJ101
36
R56
POT 10K
3310Y-001-103L
37
R58
10E
RMCF 1/10 10 5% R
38
R68
100 ohm
ERJ-3GEYJ101V
39
R69
10K
ERJ-3GEYJ103V
40
SW1,SW2,SW3
SW PUSHBUTTON
EVQ-Q2P02W
41
U1
LT1763CS8
LT1763CS8#PBF
42
U2
AP1117D50G
AP1117D50G-13
24LC00/SN
Panasonic - ECG
Stackpole Electronics
Inc
Panasonic - ECG
43
U3
24LC00/SN
44
U4
LM1117MPX-3.3
45
U5
CY7C68013A56LTXC
46
U7
CY8C5568AXI060 TQFP100
47
U8
MAX3232CDR
Texas Insturments
MAX3232IDR
48
Y1
24 MHz
RESONATOR, 24.000MHZ,
WITH CAPS, SMD
Murata
CSTCE24M0XK2010R0
49
Y2
32.768KHz XTAL
50
J8,J33, TP2
RED TEST
POINT
Keystone Electronics
Microchip Technology
5000
45
Item Qty
Reference
Value
Description
Manufacturer
Panasonic - ECG
ERA-V27J222V
51
R38
2.2K
52
J10,J11
3p_jumper
3M
961103-6404-AR
53
J30
2p_jumper
3M
961102-6404-AR
54
NA
55
NA
16 pin header
3M
961116-6404-AR
56
ESD diode
Bourns Inc.
CG0603MLC-05LE
57
R21
39K
Rohm Semiconductor
MCR03EZPFX3902
58
R22
62K
Rohm Semiconductor
MCR03EZPFX6202
59
Y3
24 MHz Crystal
ECS Inc
ECS-240-20-5PX-TR
60
C30,C31
22pF
Panasonic - ECG
ECJ-0EC1H220J
1.0 uFd
TMK107BJ105KA-T
LCM-S01602DTR/A-3
No Load Components
61
C24
62
13
J5,J6,J12,J14,J29,J31
,J18,J22,J25,TP3,TP4 RED
,J16,J39
Keystone Electronics
5000
63
J7,J32,J34,J36
BLACK
Keystone Electronics
5001
64
TP5
WHITE
Keystone Electronics
5002
65
J50
Breadboard
BREADBOARD 17x5x2
3M
66
P3,P4,P6,P9
RECP 8X1
929850-01-08-RA
67
R67
10K
3362P-1-103LF
68
10
R30,R34,R57,R72,R2
5,R31,R70,R37,R29, ZERO
R73
ERJ-6GEY0R00V
69
R55
10K
3214W-1-103E
70
R1,R28
ZERO
Panasonic - ECG
ERJ-3GEY0R00V
71
U6
LM4140
72
R8
1.5K
Panasonic - ECG
ERA-S15J152V
73
R2
3K
Stackpole Electronics
Inc
RNC 20 T9 3K 0.1% R
74
P5
4x1 RECP
3M
929850-01-04-RA
75
J38
3p_jumper
3M
961103-6404-AR
76
J37
2p_jumper
3M
961102-6404-AR
46
923273-I
Item Qty
Reference
Value
Description
Manufacturer
77
CSB1,CSB2
CapSense
CapSense Button
Cypress
78
CSS1
CapSense Slider
Cypress
79
J9,J13,J15,J17,J19,J2
PADS
0,J21,J23,J24
PADS
80
TV1,TV2
PADS
PADS
Richco Plastic Co
RBS-3R
J30
Kobiconn
151-8030-E
83
J10, J11
Kobiconn
151-8030-E
External Assembly
84
3.3V label
85
4-40 X 5 +13
Brass Spacer
Stud with Nut
47
A.4
Port
Port 0
Pin Name
71
P0[0]
72
P0[1]
73
P0[2]
74
P0[3]
Connected to 2 points:
1. Voltage reference Chip*
2. Connected to Pin 15 on Port E
76
P0[4]
77
P0[5]
78
P0[6]
79
P0[7]
P1[0]
Connected to 3 points:
1. Connected to Pin 2 on programming header J3
2. Connected to Pin 45 on U5
3. Connected to Pin 8 (SWDIO) on Port D
21
P1[1]
Connected to 3 points:
1. Connected to Pin 4 on programming header
2. Connected to Pin 56 on U5
3. Connected to Pin 7 (SWDCK) on Port D
22
P1[2]
23
P1[3]
Connected to 3 points:
1. Connected to Pin 6 on programming header
2. Connected to Pin 47 on U5
3. Connected to Pin 5 (SWO) on Port D
24
P1[4]
Connected to 2 points:
1. Connected to Pin 8 on programming header
2. Connected to Pin 4 (TDI) on Port D
25
P1[5]
27
P1[6]
28
P1[7]
20
Port 1
48
Description
Port
Pin
Pin Name
95
P2[0]
Connected to 2 points:
1. Connected to LCD module
2. Connected to Pin 18 on Port D
96
P2[1]
Connected to 2 points:
1. Connected to LCD module
2. Connected to Pin 17 on Port D
97
P2[2]
Connected to 2 points:
1. Connected to LCD module
2. Connected to Pin 16 on Port D
P2[3]
Connected to 3 points:
1. Connected to Pin 2 on trace header J40
2. Connected to LCD module
3. Connected to Pin 15 on Port D
P2[4]
Connected to 3 points:
1. Connected to Pin 4 on trace header J40
2. Connected to LCD module
3. Connected to Pin 14 on Port D
P2[5]
Connected to 3 points:
1. Connected to Pin 6 on trace header J40
2. Connected to LCD module
3. Connected to Pin 13 on Port D
P2[6]
Connected to 3 points:
1. Connected to Pin 8 on trace header J40
2. Connected to LCD module
3. Connected to Pin 12 on Port D
P2[7]
Connected to 3 points:
1. Connected to Pin 10 on trace header J40
2. Connected to LCD module
3. Connected to Pin 11 on Port D
44
P3[0]
45
P3[1]
46
P3[2]
Connected to 2 points:
1. Voltage reference Chip*
2. Connected to Pin 6 on Port E
47
P3[3]
48
P3[4]
49
P3[5]
51
P3[6]
52
P3[7]
69
P4[0]
70
P4[1]
80
P4[2]
81
P4[3]
82
P4[4]
83
P4[5]
84
P4[6]
85
P4[7]
98
Port 2
99
Port 3
Port 4
Description
49
Port
Port 5
Port 6
Port 12
50
Pin
Pin Name
Description
16
P5[0]
Connected to 2 points:
1. Connected to CapSense slider segment
2. Connected to Pin 28 on Port D
17
P5[1]
Connected to 2 points:
1. Connected to CapSense slider segment
2. Connected to Pin 27 on Port D
18
P5[2]
Connected to 2 points:
1. Connected to CapSense slider segment
2. Connected to Pin 26 on Port D
19
P5[3]
Connected to 2 points:
1. Connected to CapSense slider segment
2. Connected to Pin 25 on Port D
31
P5[4]
Connected to 2 points:
1. Connected to CapSense slider segment
2. Connected to Pin 24 on Port D
32
P5[5]
Connected to 2 points:
1. Connected to CapSense button CSB1
2. Connected to Pin 23 on Port D
33
P5[6]
Connected to 2 points:
1. Connected to CapSense button CSB2
2. Connected to Pin 22 on Port D
34
P5[7]
89
P6[0]
Connected to Pin 5 on P9
90
P6[1]
91
P6[2]
Connected to LED3
92
P6[3]
Connected to LED4
P6[4]
P6[5]
Connected to 2 points:
1. Connected to VR POT
2. Connected to Pin 5 on P6
P6[6]
Connected to Pin 6 on P9
P6[7]
Unused/No Connect
53
P12[0]
54
P12[1]
67
P12[2]
68
P12[3]
P12[4]
Connected to Pin 1 on P9
P12[5]
Connected to Pin 2 on P9
29
P12[6]
Connected to Pin 3 on P9
30
P12[7]
Connected to Pin 4 on P9
Port
Port 15
Other Pins
Pin
Pin Name
Description
42
P15[0]
43
P15[1]
55
P15[2]
56
P15[3]
93
P15[4]
94
P15[5]
35
P15[6]
Connected to USB D+
36
P15[7]
Connected to USB D-
13
Vbat
Connected to Vbat
12
Vboost
Connected to Vboost
63
VCCa
Connected to VCCa
39
VCCd
Connected to VCCd
86
VCCd
Connected to VCCd
65
VDDa
Connected to VDDa
37
VDDd
Connected to VDDd
88
VDDd
Connected to VDDd
75
VDDio0
Connected to VDDio0
26
VDDio1
Connected to VDDio1
100
VDDio2
Connected to VDDio2
50
VDDio3
Connected to VDDio3
64
VSSa
Connected to GND
10
VSSb
Connected to GND
14
VSSd
Connected to GND
38
VSSd
Connected to GND
66
VSSd
Connected to GND
87
VSSd
Connected to GND
15
XRES
Connected to 3 points:
1. Connected to Pin 10 on J3
2. Connected to SW1
3. Connected to Pin 20 on U5
11
Ind
Connected to Inductor
40
NC1
Unused/No Connect
41
NC2
Unused/No Connect
57
NC3
Unused/No Connect
58
NC4
Unused/No Connect
59
NC5
Unused/No Connect
60
NC6
Unused/No Connect
61
NC7
Unused/No Connect
62
NC8
Unused/No Connect
Note*: To enable voltage reference, populate the resistors R34, R37, R73, and low droput voltage reference IC
LM4140. See the BOM on page 44 for component details.
51
52