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TPS92512, TPS92512HV
SLVSCT1A FEBRUARY 2015 REVISED MARCH 2015

TPS92512 2.5A Buck LED Driver with Integrated Analog Current Adjust
1 Features

3 Description

The TPS92512/HV are 2.5A step-down (buck) current

regulators with an integrated MOSFET to drive high
current LEDs. Available with 42 V and 60 V (HV)
input ranges, these LED drivers operate at a user
selected fixed-frequency with peak-current mode
control and deliver excellent line and load regulation.

Integrated 200-m High-Side MOSFET

4.5-V to 42-V Input Voltage Range
(4.5 V to 60 V for the TPS92512HV)
0 V to 300 mV Adjustable Voltage Reference
5% LED Current Accuracy
100-kHz to 2-MHz Switching Frequency Range
Dedicated PWM Dimming Input
Adjustable Undervoltage-Lock-Out
Overcurrent Protection
Overtemperature Protection
MSOP-10 Package with PowerPAD

2 Applications

Street Lighting
Emergency/Exit Lighting
General Industrial and Commercial Illumination
Retail Lighting
Appliance Lighting
Transportation Lighting
Channel Letters
Light Bars

The TPS92512/HV LED drivers feature separate

inputs for analog and pulse width modulation (PWM)
dimming for no compromise brightness control
achieving contrast ratios of greater than 10:1 and
greater than 100:1, respectively. The PWM input is
compatible with low-voltage logic standards for easy
interface to a broad range of microcontrollers. The
analog LED current setpoint is adjustable from 0 V to
300 mV using the IADJ input with an external 0 V to
1.8 V signal.
For multi-string applications using two or more
TPS92512/HV LED drivers, the internal oscillator can
be overdriven by an external clock ensuring all of the
converters operate at a common frequency thereby
reducing the potential for beat frequencies and
simplifying system EMI filtering. An adjustable input
under-voltage lockout (UVLO) with hysteresis
provides flexibility in setting start/stop voltages based
upon supply voltage conditions.
The TPS92512 includes cycle-by-cycle overcurrent
protection and thermal shutdown protection. It is
available in a 10-pin HVSSOP PowerPAD package.
Device Information(1)
PART NUMBER

PACKAGE

TPS92512

HVSSOP (10)

TPS92512HV

BODY SIZE (NOM)

5.00 mm x 3.00 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

4 Simplified Schematics
0.18V 1.8V
6

IADJ

BOOT

VIN

PDIM

UVLO

COMP

RT/CLK

97.5

TPS92512

ISENSE
GND

Pad

100

PH 10

Efficiency (%)

Efficiency vs Input Voltage

7 White LEDs at 1.5A (VOUT = 23 V)

95
92.5
90
87.5
85
25

30

35

40
45
Input Voltage (V)

50

55

60
D001

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS92512, TPS92512HV
SLVSCT1A FEBRUARY 2015 REVISED MARCH 2015

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Table of Contents
1
2
3
4
5
6
7

Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematics...........................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................

1
1
1
1
2
3
4

7.1
7.2
7.3
7.4
7.5
7.6
7.7

4
4
4
5
5
6
7

Absolute Maximum Ratings ......................................

ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................

Detailed Description .............................................. 9

8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................... 9

8.4 Device Functional Modes........................................ 13

Application and Implementation ........................ 15

9.1
9.2
9.3
9.4
9.5

Application Information............................................
Typical Application .................................................
Design Requirements..............................................
Detailed Design Procedure .....................................
Application Curves ..................................................

15
17
17
18
20

10 Power Supply Recommendations ..................... 20

11 Layout................................................................... 21
11.1 Layout Guidelines ................................................. 21
11.2 Layout Example .................................................... 21

12 Device and Documentation Support ................. 22

12.1
12.2
12.3
12.4

Related Links ........................................................

Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................

22
22
22
22

13 Mechanical, Packaging, and Orderable

Information ........................................................... 22

5 Revision History
Changes from Original (February 2015) to Revision A

Page

Changed the device status From: Product Preview To: Production Data .............................................................................. 1

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6 Pin Configuration and Functions

DGQ (HVSSOP) Package
Top View

BOOT

10

PH

VIN

GND

UVLO

COMP

PDIM

ISENSE

RT/CLK

IADJ

Pin Functions
PIN

TYPE (1)

DESCRIPTION

NAME

NO.

BOOT

A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the
minimum required by the output device, the output is forced to switch off until the capacitor is recharged.

COMP

Error amplifier output, and input to the output switch current comparator. Connect frequency compensation
components to this pin.

GND

Ground.

IADJ

Analog current adjust pin. The voltage applied to this pin will set the current sense (ISENSE pin) voltage.
The range of the ADJ pin is 180 mV to 1.8 V and the corresponding ISENSE pin voltage is the IADJ pin
voltage divided by 6.

ISENSE

Inverting node of the transconductance (gM) error amplifier.

PDIM

PWM dimming input pin. The duty cycle of the PWM signal linearly controls the average output current of the
converter.

PH

10

The source of the internal high-side MOSFET.

PAD

GND pin must be electrically connected to the exposed pad directly beneath the device on the printed circuit
board for proper operation.

PowerPAD

RT/CLK

Resistor timing and external clock. An internal amplifier holds this pin at a fixed voltage when using an
external resistor to ground to program the switching frequency. If the pin is pulled above the PLL upper
threshold, a mode change occurs and the pin becomes a synchronization input. The internal amplifier is
disabled and the pin becomes a high impedance clock input to the internal PLL. If the clocking edges stop,
the internal amplifier is re-enabled and the mode returns to the resistor-programmed function.

UVLO

Adjustable undervoltage lockout. Set with resistor divider from VIN.

VIN

Input supply voltage, 4.5V to 42V or 4.5V to 60V for the HV version.

(1)

I = Input, O = Output, P = Supply, G = Ground

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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)

Input voltage

Output voltage

(1)

MIN

MAX

VIN (TPS92512HV)

0.3

65

VIN (TPS92512)

0.3

45

PDIM, UVLO

0.3

BOOT

(PH + 8)

UNIT

ISENSE, IADJ, COMP

0.3

RT/CLK

0.3

3.6

PH (TPS92512HV)

0.6

65

PH (TPS92512)

0.6

45

PH, 10-ns Transient

Voltage Difference

PAD to GND

200

mV

Source Current

PH

Current Limit

VIN

Current Limit

mA

Sink current

BOOT

TJ

Operating junction temperature

40

150

Tstg

Storage temperature

65

150

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

V(ESD)
(1)
(2)

Electrostatic discharge

Human-body model (HBM),ESD stress voltage

(1)

Charged-device model (CDM), ESD stress voltage (2)

VALUE

UNIT

2000

500

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as 2 kV may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as 500 V may actually have higher performance.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

VIN
fSW
tMIN(RT

MIN

MAX

Input voltage (TPS92512HV)

4.5

60

Input voltage (TPS92512)

4.5

42

Switching frequency range using RT mode

100

2000

Switching frequency range using CLK mode

300

2000

Minimum RT/CLK input pulse width for switching frequency synchronization

51

UNIT
V
kHz
ns

/CLK)

TJ

Operating junction temperature

40

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7.4 Thermal Information

TPS92512
TPS92512HV

THERMAL METRIC (1)

UNIT

DGQ (10 PINS)

RJA

Junction-to-ambient thermal resistance

66.7

RJC(top)

Junction-to-case (top) thermal resistance

45.8

RJB

Junction-to-board thermal resistance

37.5

JT

Junction-to-top characterization parameter

1.8

JB

Junction-to-board characterization parameter

37.1

RJC(bot)

Junction-to-case (bottom) thermal resistance

15.4

(1)

C/W

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

40C TJ 125C, VVIN = 12V (unless otherwise noted)
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY VOLTAGE (VIN)

VINUVLO

VIN undervoltage lockout threshold

No voltage hysteresis, rising and falling

IVINSD

Shutdown supply current

VUVLO = 0 V, 4.5 V VVIN 42 V (60 V for HV)

Non-switching supply current

VISENSE = 220 mV, 4.5V VVIN 42 V (60 V

for HV)

IVIN

2.94

V
11.5

337

407

1.22

1.30

UNDER VOLTAGE LOCKOUT (UVLO)

VUVLO

UVLO threshold voltage

Rising threshold

UVLO pin source current

1.12

VUVLO = 1.5 V (device enabled)

3.97

VUVLO = 1 V (device disabled)

1.05

ANALOG CURRENT ADJUST (VIADJ, VISENSE)

VIADJ

VISENSE

IADJ clamp voltage

Current sense voltage

Current sense voltage level

IIADJ = 1 A

1.8

IIADJ = 100 A

2.77

VIADJ = 1.2 V, TJ = 25C to 125C

191

200

210

VIADJ = 0.18 V, TJ = 25C to 125C

21.4

30.0

40.0

IIADJ = 1 A, TJ = 25C to 125C

285

300

309

IIADJ = 100 A, TJ = 25C to 125C

286

300

309

180 mV VIADJ 1.8V

mV

VIADJ/6

HIGH-SIDE MOSFET (BOOT, PH)

VVIN = 4.5 V, (VBOOT VPH) = 3.5 V

232

(VBOOT VPH) = 6 V

200

RDS(on)

On-resistance

VBOOT

BOOT-PH voltage

VPDIM = 3V

IBOOT

BOOT-PH current

VPDIM = 0V, (VBOOT VPH) = 5V

93.9

VBOOTUV

BOOT-PH under voltage lockout

Rising threshold

2.25

2.81

Falling threshold

1.99

2.40

tON(min)

Minimum on time

VCOMP = 0

140

ns

20

nA

331

A/V

342

ERROR AMPLIFIER (ISENSE, COMP)

gM(ea)

Input bias current

VISENSE = 200 mV

Transconductance gain

VIADJ = 1.2 V, 180 mV < VISENSE < 220 mV,

VCOMP = 1 V

DC gain

VIADJ = 1.2 V , VISENSE = 0.2 V

Bandwidth
Source/sink current

VIADJ = 1.2 V , VCOMP = 1 V,

VISENSE = 200 mV 100 mV

10

kV/V

2.7

MHz

28

CURRENT LIMIT
Current limit threshold

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Electrical Characteristics (continued)

40C TJ 125C, VVIN = 12V (unless otherwise noted)
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

THERMAL SHUTDOWN
TSD

Thermal shutdown

165

Thermal shutdown hysteresis

20

TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK)

VRT

RT/CLK regulated voltage

RRT = 200 k

474

500

513

mV

fSW

Switching frequency

VVIN = 6 V, RRT = 200 k

447

557

648

kHz

RT/CLK high threshold

VVIN = 6 V

1.49

1.81

RT/CLK low threshold

VVIN = 6 V

0.63

1.02

1.04

PWM DIMMING (PDIM)

IPDIM

PDIM source current

VIH

High-level input voltage

VIL

Low-level input voltage

VPDIM = 0

1.34
0.79

1.45

0.88

7.6 Timing Requirements

MIN

NOM

MAX

UNIT

TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK)

RT/CLK falling edge to PH rising
edge delay

Measured at 500 kHz with RT

resistor in series, VVIN = 6 V

92.1

ns

Phase loop (PLL) lock-in time

fSW = 500 kHz

100

PWM DIMMING (PDIM)

tRISE

Rising propagation delay

305

tFALL

Falling propagation delay

535

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7.7 Typical Characteristics

VIN = 24V, Unless otherwise specified
1.53

100
98

1.52

96

LED Current (A)

Efficiency (%)

94
92
90
88
86
84

1.51
1.5
1.49
1.48

82
80
15

20

25

1.5 A LED Current

fSW = 570 kHz

30

35
40
45
Input Voltage (V)

50

55

1.47
10

60

15

20

4 LEDs in Series
VOUT = 13.1 V

VIADJ = 1.8 V

1.5 A LED Current

2000

550

1800

500

1600
1400
1200
1000
800

60
D001

3 LEDs in Series
VOUT = 9.9 V

VIADJ = 1.8 V

300
250
200
150

180

55

350

100
200

160

50

400

400
40

100
120
140
Resistor, RT (k:)

45

450

600
80

30
35
40
Input Voltage (V)

Figure 2. Line Regulation

600

Switching Frequency (kHz)

Switching Frequency (kHz)

Figure 1. Efficiency vs Input Voltage

2200

60

25

D001

200

300

400

500

D001

Figure 3. Switching Frequency vs RT Resistor

600 700 800 900 1000 1100 1200

Resistor, RT (k:)
D001

Figure 4. Switching Frequency vs RT Resistor

1.6

1.5

1.4

1.25

LED Current (A)

LED Current (A)

1.2
1
0.75
0.5

1
0.8
0.6
0.4

0.25

0.2
0

0
0

0.2

0.4

1.5 A LED Current

0.6

0.8
1
1.2
IADJ Voltage (V)

1.4

1.6

3 LEDs in Series
VOUT = 9.9 V

1.8

10

20

30

D001

1.5 A LED Current

250 Hz PWM Frequency

Figure 5. LED Current vs IADJ Voltage

40
50
60
70
PDIM Duty Cycle (%)

3 LEDs in Series
VOUT = 9.9 V

80

90

100
D001

VIADJ = 1.8 V

Figure 6. LED Current vs PDIM Duty Cycle

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Typical Characteristics (continued)

VIN = 24V, Unless otherwise specified
340

310

320

307.5
ISENSE Voltage (mV)

Switch RDS(on) (m:)

300
280
260
240
220
200

305
302.5
300
297.5
295

180

292.5

160
140
-40

-20

20
40
60
80 100
Junction Temperature (qC)

120

140

290
-40

160

VIN = 12 V

1.5
1.4

VIN Shutdown Input Current (PA)

VIN Shutdown Input Current (PA)

20
40
60
80 100
Junction Temperature (qC)

120

140

160
D001

Figure 8. VISENSE vs Junction Temperature

2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3

1.3
1.2
1.1
1
0.9
0.8
0.7
0.6

-20

20
40
60
80
100
Junction Temperature (qC)

120

140

10

D001

VVIN = 12 V

15

20

25 30 35 40
Input Voltage (V)

45

50

55

60
D001

TJ = 25C

Figure 9. Shutdown Input Current vs Junction Temperature

VIADJ = 1.8 V

Figure 7. PH Switch RDS(on) vs Junction Temperature

0
-40

-20

D001

Figure 10. Shutdown Input Current vs Input Voltage

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8 Detailed Description
8.1 Overview
The TPS92512 is a high voltage, up to 2.5-A, step-down (buck) regulator with an integrated high-side N-channel
MOSFET. To improve performance during line and load transients the device implements a constant frequency,
peak-current mode control which reduces output capacitance and simplifies external frequency compensation
design. The wide switching frequency of 100 kHz to 2000 kHz allows for efficiency and size optimization when
selecting the output filter components.

8.2 Functional Block Diagram

1A 2. 9 A

Thermal
Shutdown

VIN
UVLO

VIN

BOOT

10

PH

GND

BOOT
Charge

UVLO

Shutdown
Logic

1. 22 V

COMP

ISENSE

BOOT
UVLO
Error
Amplifier

COMP S / H

+
6

PWM
Comparator

S
-

10k

IADJ

R
R

Logic and
PWM Latch

1/6

Current
Sense

COMP
Clamp

1A

1.8V
Slope
Compensation

PDIM

Oscillator
with PLL

1.34 V

+
5

RT / CLK

8.3 Feature Description

8.3.1 Undervoltage Lockout and Low Power Shutdown (UVLO Pin)
The TPS92512 contains an internal under-voltage lockout circuit on the VIN pin of the device. However, this
internal UVLO is for device protection only and does not contain hysteresis. The UVLO pin of the device should
always be used to set the minimum VIN voltage that the circuit operates at. This level should be set using the
minimum input voltage expected for the application with a minimum setting of 4.5 V.
The UVLO pin has an internal pull-up current source of 1 A (I1) that will provide a default ON state in the event
the UVLO pin is left floating (not recommended). When the UVLO pin voltage exceeds 1.22 V (VEN), an
additional 2.9 A of hysteresis current is added (see Figure 11). This additional current provides the input voltage
hysteresis. Use Equation 1 to set the external hysteresis (VHYS) for the input voltage. Use Equation 2 to set the
input rising start voltage, VSTART. When the UVLO pin is pulled low, the internal regulators are shut down, the
device enters a low-power shutdown mode and the compensation capacitor on the COMP pin, CCOMP, is
discharged.

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Feature Description (continued)

TPS92512

VIN

I1

IHYS

1A

2.9 A

R1

UVLO

3
R ESD

R2

1.22V
VEN

Figure 11. Adjustable Undervoltage Lockout (UVLO)

VHYS VEN - (I1 RESD ) - IHYS RESD VSTART

R1 =

IHYS VEN

R2 =

(1)

))

R1 VEN - RESD (I1 + IHYS )

(VSTOP - VEN ) + (I1 + IHYS ) (R1 + RESD )

(2)

VHYS = VSTART - VSTOP

(3)

RESD = 10 kW

(4)

8.3.2 Adjustable Switching Frequency (RT/CLK Pin)

The switching frequency of the TPS92512 is adjustable over a wide range from 100 kHz to 2 MHz by placing a
resistor, RRT, on the RT/CLK pin. The RT/CLK pin voltage is typically 0.5 V and must have a resistor to ground to
set the switching frequency. To determine the timing resistance for a given switching frequency, use Equation 5
or the curves in Figure 3 or Figure 4. To reduce the solution size one typically sets the switching frequency as
high as possible, but tradeoffs of the supply efficiency, maximum input voltage and minimum controllable on time
should be considered. The minimum controllable on time, tON(min), limits the maximum operating input voltage.
206033
RRT (kW ) =
(fSW )1.092 (kHz )
(5)

206033 (1.092 )
=

RRT (kW)
1

fSW

(6)

8.3.3 Synchronizing the Switching Frequency to an External Clock (RT/CLK Pin)

The RT/CLK pin can be used to synchronize the regulator to an external system clock by connecting a square
wave to the RT/CLK pin through the circuit network as shown in Figure 12. The square wave amplitude must
transition lower than 0.63 V and higher than 1.81 V on the RT/CLK pin and have an on-time greater than 51 ns
and an off-time greater than 100 ns. The synchronization frequency range is 300 kHz to 2 MHz. The rising edge
of the PH is synchronized to the falling edge of RT/CLK pin signal. The internal oscillator provides default
switching frequency set by connecting the resistor from the RT/CLK pin to ground should the synchronization
signal turn off.

10

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Feature Description (continued)

It is required to AC couple the synchronization signal through a 470 pF ceramic capacitor and a 4 k series
resistor to the RT/CLK pin. The series resistor reduces PH jitter in heavy load applications when synchronizing to
an external clock and in applications which transition from synchronizing to RT mode. The first time the RT/CLK
pin is pulled above the CLK threshold the device switches from the RT resistor frequency to PLL mode. The
internal 0.5 V voltage source is removed and the CLK pin becomes high impedance as the PLL starts to lock
onto the external signal. Since there is a PLL on the regulator, the switching frequency can be higher or lower
than the frequency set with the external resistor. The device transitions from the resistor mode to the PLL mode
and then increases or decreases the switching frequency until the PLL locks onto the CLK frequency within 100
microseconds.
When the device transitions from the PLL to resistor mode, the switching frequency slows down from the CLK
frequency to 150 kHz, then reapplies the 0.5 V voltage and the resistor then sets the switching frequency. It is
not recommended that a system transition from PLL mode to resistor mode repeatedly during operation. When
the PLL loses the external clock input the default 150 kHz switching frequency creates long on-times, which
result in higher inductor ripple currents. This can lead to inductor saturation if the system is not designed to
operate at this frequency.

TPS92512

470 pF

4 k

RT/CLK
5

Phase-Lock
Loop (PLL)

RRT

Figure 12. Frequency Synchronization

8.3.4 Adjustable LED Current (IADJ and ISENSE Pins)
The LED current can be set, and controlled dynamically, by using the IADJ pin of the TPS92512. Equation 7
shows the relationship between the voltage applied to IADJ (VIADJ) and the regulation setpoint at the ISENSE pin.
Equation 8 shows how to calculate the value of the current setting resistor (RISENSE) from the ISENSE pin to
ground for the desired LED current.
V
VISENSE = IADJ
6
(7)
VISENSE
RISENSE =
ILED
(8)
The IADJ pin voltage range is 0 V to 1.8 V and is internally clamped at 1.8 V. If analog current adjustment will
not be used, the IADJ pin can be connected to VIN through a resistor for a default ISENSE voltage of 300 mV.
This resistor should be sized so that the current into the IADJ pin is limited to 100 A or less at the maximum
input voltage. A precision reference between 0 V and 1.8 V can also be used on IADJ to control the ISENSE
voltage. If no external voltage source is available, the IADJ pin can be tied to the RT/CLK pin either directly or
using a resistor divider to generate a voltage between 0 V and 500 mV. If a resistor divider is used off the
RT/CLK pin to generate the IADJ voltage it will introduce a parallel resistance with the RT resistor. High value
resistors are recommended in that case and the parallel combination must be used to calculate the switching
frequency. The current sense voltage is most accurate with IADJ voltages between 180 mV and 1.8 V for a
dimming range of 10:1. Below 180 mV the TPS92512 dims well but may have more variation between circuits.
Due to internal offsets pulling IADJ to 0 V will not result in a current sense voltage of 0 V. Some small current will
continue to run unless the PDIM pin is pulled low or the device is disabled using the UVLO pin. Analog dimming
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Feature Description (continued)

is also most accurate when the device is in continuous conduction mode (CCM). If the highest accuracy possible
is desired during analog dimming, size the inductor so that 1/2 the peak-to-peak inductor ripple is less than the
minimum LED current to remain in CCM. The IADJ pin should be decoupled with a 10 nF capacitor to ground. A
1 k resistor should be used between the ISENSE pin and RISENSE to protect the pin in the event RISENSE opens
or there is a transient due to one or more LEDs shorting.
8.3.5 PWM Dimming (PDIM Pin)
The TPS92512 incorporates a PWM dimming input pin, which directly controls the enable/disable state of the
internal gate driver. When PDIM is low, the gate driver is disabled. The PDIM pin has a 1 A pull-up current
source, which creates a default ON state when the PDIM pin is floating. When PDIM goes low, the gate driver
shuts off and the LED current quickly reduces to zero. A square wave of variable duty cycle should be used and
should have a low level below 0.79 V and a high level of 1.45 V or above.
The TPS92512 uses a sample-and-hold switch on the error amplifier output. During the PDIM off-time the COMP
voltage remains unchanged. Also, the error amplifier output is internally clamped low. These techniques help the
system recover to its regulation duty cycle quickly. The dimming frequency range is 100 Hz to 1 kHz and the
minimum duty cycle is only limited in cases where the BOOT capacitor can discharge below its under-voltage
threshold of 2 V (VIN is within 2 V of the total output voltage).
8.3.6 External Compensation (COMP Pin)
The TPS92512 error amplifier output is connected to the COMP pin. The TPS92512 is a simple device to
stabilize and only requires a capacitor from the COMP pin to ground (CCOMP). A 0.1 F capacitor is
recommended and will work well for most all applications. If an application requires faster response to input
voltage transients, a capacitor as small as 0.01 F will work for most applications if needed. The overall system
bandwidth can be approximated using Equation 9.
gM(ea)
BW =
2p CCOMP
(9)
8.3.7 Overcurrent Protection
Overcurrent can be the result of a shorted sense resistor or a direct short from VOUT to GND. In either case, the
voltage at the ISENSE pin is zero and this causes the COMP pin voltage to rise. When VCOMP reaches
approximately 2.2 V, it is internally clamped and functions as a MOSFET current limit. The TPS92512 limits the
MOSFET current to 6 A (typical). If the shorted condition persists, the TPS92512 junction temperature increases.
If it increases above 165C, the thermal shutdown protection is activated.
8.3.8 Overtemperature Protection
The TPS92512 includes a thermal shutdown circuit to protect the device from over-temperature conditions. The
device can overheat due to high ambient temperatures, high internal power dissipation, or both. In the event the
die temperature reaches 165C the device will shut down until the die temperature falls 20C at which point it will
turn back on.

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8.4 Device Functional Modes

8.4.1 Start-Up
To reduce inrush current and to keep the regulator in control during all startup conditions the TPS92512 employs
a startup mode that behaves differently than during normal operation (regulation mode). The UVLO conditions
must be satisfied before the TPS92512 is allowed to switch. When the UVLO pin is held low the device enters a
low-power shutdown mode, and some internal circuits are deactivated to conserve power. When UVLO returns
high these circuits are enabled, which results in a delay of approximately 50 s (typical) before switching starts.
During start-up the TPS92512 operates in a minimum pulse width mode which is an open-loop control. At the
start of each switching cycle the internal oscillator initiates a SET pulse. The high-side MOSFET turns on with a
minimum pulse width of 140 ns (typical), independent of the COMP voltage. The device does not pulse skip.
While operating in minimum pulse width mode, the LED bypass capacitor is being charged causing an in-rush
current. Also, the COMP voltage begins to rise as the error amplifier output current charges the compensation
capacitor. When the COMP voltage reaches approximately 0.7 V, the error amplifier is ensured to be out of
saturation and to have sufficient gain to regulate the loop. The TPS92512 then transitions from minimum pulse
width mode to regulation mode. During regulation mode the error amplifier is now in closed-loop control of the
system. The gain of the error amplifier quickly increases the duty cycle, which causes the output voltage to
increase. Once the output voltage approaches the forward voltage of the LED string, the LED current quickly
begins to increase until it reaches regulation.
There is a slight delay from the time the VIN and EN UVLO conditions are satisfied until the time the error
amplifier has control of the feedback loop. This delay is a result of the time it takes COMP to charge the
compensation capacitor to 0.7 V. This delay can be approximated as shown in Equation 10.
0.7 V
tDELAY = CCOMP
28 mA
(10)
The peak inrush current, IPEAK, can be calculated to a first order approximation using Equation 11 and the value
of the output capacitor, COUT.
VIN t ON(min) fSW
IPEAK =
L
+ RISENSE
COUT
(11)
8.4.2 Minimum Pulse Width and Limitations
The TPS92512 is designed to output a minimum pulse width during each switching cycle of 140 ns (typical). The
control loop cannot regulate the system to an on-time less than this amount, and it does not skip pulses. When
attempting to operate below the minimum on-time the system loses regulation and the LED current increases.
This puts a practical limitation on the system operating conditions, as shown in Equation 12.
VOUT
VIN =
fSW t ON(min)
(12)
Where VOUT equals the forward voltage of the LED string plus the reference voltage VISENSE.
The system can avoid this operating condition by limiting the maximum input voltage as shown in Equation 12. If
the input voltage cannot be limited due to application, then the switching frequency can be lowered, or the output
voltage increased. This region of operation typically occurs with high input voltages, high operating frequencies,
and low output voltages.
8.4.3 Maximum Duty Cycle and Bootstrap Voltage (BOOT)
The TPS92512 requires a small 0.1 F ceramic capacitor between the BOOT and PH pins to provide the gate
drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed when the high-side MOSFET turns
off, and the freewheeling rectifier diode conducts. A ceramic capacitor with an X7R or X5R dielectric and a
minimum voltage rating of 10 V is recommended.

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Device Functional Modes (continued)

The TPS92512 is designed to operate up to 100% duty cycle as long as the BOOT to PH voltage is greater than
at least 2 V. If the BOOT capacitor voltage drops below 2 V, then the BOOT UVLO circuit turns off the MOSFET,
which allows the BOOT capacitor to be recharged. The current required from the BOOT capacitor to keep the
MOSFET on is quite low. Therefore, many switching cycles occur before the BOOT capacitor is refreshed. In this
way, the effective duty cycle of the converter is quite high.
Attention must be taken in maximum duty cycle applications which experience extended time periods with little or
no load current such as during PWM dimming. When the voltage across the BOOT capacitor falls below the 2 V
UVLO threshold, the high-side MOSFET is turned off, but there may not be enough inductor current to pull the
PH pin down to recharge the BOOT capacitor. The high-side MOSFET of the regulator stops switching because
the voltage across the BOOT capacitor is less than 2 V. The output capacitor then decays until the difference
between the input voltage and output voltage is greater than 2 V, at which point the BOOT UVLO threshold is
exceeded, and the device starts switching again until the desired output current is reached. This operating
condition persists until the input voltage and/or the load current increases. It is recommended to adjust the VIN
stop voltage, VSTOP, to be greater than the BOOT UVLO trigger condition at the minimum load of the application
using the adjustable UVLO feature.
8.4.4 Thermal Shutdown and Thermal Limitations
The TPS92512 is a high current density device in a small package. Therefore; it is not capable of providing the
full 2.5 A of output current under all conditions without the die reaching the thermal shutdown temperature. To
ensure the device will not get too hot the package power dissipation should be calculated and used in
conjunction with the device Thermal Information to estimate the maximum die temperature for a given
application. The total device power dissipation can be closely approximated using the following equations:
V
D = OUT
(13)
VIN

PD(sw ) = D RDS(on) ILED2

(14)

2 mA fSW

PD(IQ) = VIN 400 mA +

1 MHz

PD(AC) = 0.73

-9

(15)

fSW VIN ILED

PTOT = PD(SW ) + PD(IQ) + PD(AC)

(16)
(17)

Where each are in Watts and

D is the maximum duty cycle (at minimum input voltage)
VOUT is the LED stack voltage plus the reference voltage VISENSE
PD(SW) is the power dissipated in the MOSFET
PD(IQ) is the power dissipated by the internal circuitry
PD(AC) are the approximate AC losses due to the MOSFET transitions
PTOT is the total device dissipation

14

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TIs customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

This section describes power component selection not discussed in the Feature Description section.
9.1.1 Inductor Selection
The value of the buck inductor impacts the peak-to-peak ripple-current amplitude. The peak inductor current is
used in current mode control and to maintain a good signal to noise ratio it is recommended that the peak-topeak ripple current (IR Equation 18) is greater than 75 mA for dependable operation. This allows the control
system to have an adequate current signal even at the lowest input voltage. Equation 18 calculates the value for
the buck inductance given the minimum ripple current of IR = 75 mA. Enter the lowest input voltage and the
highest output voltage to yield the maximum inductance value.

L=

VOUT (VIN - VOUT )

IR VIN fSW

(18)

Calculate the maximum inductor value for the particular application and choose the next lowest standard value
for applications requiring low ripple current. Choose a lower value for size sensitive applications that can tolerate
higher LED current ripple or use larger output capacitors. With the chosen value the user can calculate the actual
inductor current ripple using Equation 19.

IRIPPLE =

VOUT (VIN - VOUT )

L VIN fSW

(19)

The inductor RMS current and saturation current ratings must be greater than those seen in the application. This
ensures that the inductor does not overheat or saturate. During power-up, transient conditions, or fault
conditions, the inductor current can exceed its normal operating current. For this reason, the most conservative
approach is to specify an inductor with a saturation current rating equal to or greater than the converter current
limit. This is not always possible due to application size limitations. The peak inductor current and the RMS
current equations are shown in Equation 20 and Equation 21.
I
IL _ PEAK = ILED + RIPPLE
2
(20)

IL _ RMS = ILED2 +

IRIPPLE2
12

(21)

9.1.2 Input Capacitor Selection

The TPS92512 requires a high-quality ceramic, type X5R or X7R, input decoupling capacitor of at least 2 F of
effective capacitance per 1 A of output current. Ceramic capacitance tends to decrease as the applied dc voltage
increases. This depreciation must be accounted for to ensure that the minimum input capacitance is satisfied. In
some applications, additional capacitance is needed to provide bulk energy storage such as high current PWM
dimming applications. The input capacitor voltage rating must be greater than the maximum input voltage and
have a ripple current rating greater than the maximum input current ripple of the converter. The RMS input ripple
current is calculated in Equation 22, where D is the duty cycle (output voltage divided by input voltage). The
maximum RMS input ripple current can be calculated by using the minimum input voltage for the application.

IIN _ RMS = ILED D (1 - D )

(22)

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Application Information (continued)

The input capacitance (CIN) is inversely proportional to the input ripple voltage of the converter. The peak-to-peak
input ripple voltage can be calculated as shown in Equation 23. Additionally, this equation can be used to solve
for the required input capacitance to keep the input ripple voltage to a defined limit.

VIN =

ILED D (1 - D )
CIN fSW

(23)

9.1.3 Output Capacitor Selection

During start-up, the TPS92512 uses the discharged output capacitor as a charging path for the BOOT capacitor.
In order to ensure that the BOOT capacitor charges and that the converter begins switching immediately, the
value of the output capacitor should be 10 times larger than the BOOT capacitor. If the BOOT capacitor is 0.1
F, then the minimum output capacitor should be 1 F for the fastest startup time. If the output capacitor is
chosen to be a smaller value or none at all, then the BOOT capacitor can charge through the LED string itself.
However, this method of charging the BOOT capacitor will result in longer startup times.
The output capacitor also reduces the high-frequency ripple current through the LED string. Various guidelines
disclose how much high-frequency ripple current is acceptable in the LED string. Excessive ripple current in the
LED string increases the RMS current in the LED string, and therefore the LED temperature also increases. First,
calculate the total dynamic resistance of the LED string (RLED) using the LED manufacturers data sheet. Second,
calculate the required impedance of the output capacitor (ZOUT) given the acceptable peak-to-peak ripple current
through the LED string, ILED. IRIPPLE is the peak-to-peak inductor ripple current as calculated previously in
Inductor Selection. Third, calculate the minimum effective output capacitance required. Finally, increase the
output capacitance appropriately due to the derating effect of applied dc voltage. See Equation 24, Equation 25,
and Equation 26.
DV
RLED = F # of LEDs
DIF
(24)

ZCOUT =
COUT =

RLED D
ILED
IRIPPLE - DILED

(25)

1
2 p fSW ZCOUT

(26)

9.1.4 Rectifier Diode Selection

The rectifier diode conducts the inductor current only during the high-side MOSFET off-time. The rectifier diode
must have a reverse voltage rating greater than the maximum input voltage and a current rating greater than the
peak inductor current. A Schottky diode is recommended for highest efficiency and optimal performance. The
package size chosen for the rectifier diode must be capable of handling the power dissipation of the diode. The
diode power dissipation is equal to the average diode current times the diode forward voltage, VF. See
Equation 27 and Equation 28.
ID _ AVE = ILED (1 - D)
(27)

PDIODE = ID _ AVE VF

(28)

When calculating the diode average current, the worst case duty cycle, D, for the diode should be used. D should
be calculated using the maximum input voltage for the application in this case.
9.1.5 Output Protection Clamp (Optional)
In the event of an output open circuit during normal operation the output voltage will rise up to the input voltage.
This is a safe operating mode provided the output capacitor can sustain the voltage without damage. However,
the inductor will still have energy stored at the moment of the event. This can cause significant ringing between
the inductor and output capacitor that can shoot higher than VIN. To prevent this, a single Schottky diode from
VOUT to VIN can be used to clamp the ringing. This diode should be rated for at least 500 mA and have a voltage
rating greater than or equal to the voltage rating of the rectifier diode. A zener diode across the output capacitor
can also be used to clamp the output voltage to a lower level. The output will clamp at the zener voltage plus the
ISENSE voltage since when the zener begins to conduct it will pull the ISENSE pin up and reduce the duty cycle.
16

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9.2 Typical Application

The TPS92512 is a switching regulator designed to provide tight current regulation and high performance over a
wide range of conditions. The following application is a design example for a wide input voltage range, high
current regulator.
Figure 13 shows the schematic for the wide input voltage range converter with the design requirements below. A
detailed design procedure to calculate various component values follows.

6
10 0

0.01 PF

VIN
R1
176 N
CIN
10 PF

R2
19.3 N

CCOMP
0.1 F

RRT
200 N

CBOOT
0.1 PF

IADJ

BOOT
U1
TPS92512

VIN

PH

PDIM

UVLO

COMP

RT/CLK ISENSE

L
33 H
10
D

COUT
4.7 PF

1 N
7

GND

RISENSE
0.2
0.5 W

Figure 13. High Current, Low LED Current Ripple Buck Converter

9.3 Design Requirements

VIN range of 12 V to 48 V
UVLO set to 12 V with 0.8 V hysteresis
3 LED output, 9.7 V stack, VOUT = 10 V
1.5A LED current (at VISENSE = 300 mV for best accuracy)
Switching frequency of 570 kHz
LED current ripple of 10 mA or less

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9.4 Detailed Design Procedure

This section provides a detailed design procedure for selecting the component values for the application with the
given design requirements.
9.4.1 Standard Component Selection
Choose a 0.1 F ceramic capacitor with a 10 V or greater rating for CCOMP and CBOOT. Connect IADJ to VIN
through a 10 M resistor to clamp it at 1.8 V and provide an ISENSE voltage regulation point of 300 mV.
Connect a 10 nF capacitor from IADJ to ground. Connect ISENSE to R(ISENSE) through a 1 k resistor.
9.4.2 Calculate UVLO Resistor Values
Using Equation 1 and Equation 2 the UVLO resistors R1 and R2 can be calculated using Equation 29,
Equation 30, and the following parameters:
VSTART = 12 V
VSTOP = 11.2 V
VHYS = 0.8 V
R1 =

0.8 1.22 V - (1 A 10 kW ) - 2.9 A 10 kW 12 V

2.9 A 1.22 V

= 175 kW
(29)

Choose the closest standard 1% value of 176 k for R1. This value can then be used to calculate the value of
R2 as shown in Equation 30.
R2 =

))

174 kW
1.22 V - 10 kW (1 A + 2.9 A )

(11.2 V - 1.22 V ) + (1 A + 2.9 A ) (174 kW + 10 kW )

= 19.2 kW
(30)

Choose the closest standard 1% value of 19.3 k for R2.

9.4.3 Calculate the RT Resistor Value (RRT)
The desired switching frequency is 570 kHz, so the value of RRT can be calculated using Equation 5 as shown in
Equation 31.
206033
RRT (kW ) =
= 201.6 kW
(570 )1.092
(31)
Choose the closest standard 1% value of 200 k for RRT.
9.4.4 Calculate the ISENSE Resistor Value (R(ISENSE))
This design uses a VISENSE voltage of 300 mV and the desired LED current (ILED) is 1.5 A. Given these values the
sense resistor value can be calculated using Equation 8 as shown in Equation 32.
300 mV
RISENSE =
= 0.2 W
1.5 A
(32)
0.2 is a standard 1% resistor value. The power dissipation is VISENSE multiplied by ILED, in this case 0.45 W.
Choose a 0.5 W or greater resistor.
9.4.5 Calculate the Inductor Value and Operating Parameters (L)
For this application, low LED ripple current is important. One way to reduce LED ripple current is to reduce
inductor ripple current. For this low ripple current application, the maximum inductor value (minimum 75 mA
current ripple IR) will be calculated and the next lower value will be used. The maximum inductor value can be
calculated using Equation 18 as shown in Equation 33.
L=

10 V (12 V - 10 V )
75 mA 12 V 570 kHz

= 39 mH

(33)

Choose the next lowest standard value of 33 H. Now the actual inductor current ripple, the peak inductor
current, and the RMS inductor current can be calculated using Equation 19, Equation 20, and Equation 21 as
shown in Equation 34, Equation 35, and Equation 36.
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Detailed Design Procedure (continued)

IRIPPLE =

10 V (12 V - 10 V )

= 89 mA

33 mH 12 V 570 kHz

(34)

88mA

= 1.544 A
IL _ PEAK =1
.5 A +
2

IL _ RMS = 1.5 A 2 +

88 mA
12

(35)

= 1.5002 A

(36)

The inductor chosen should have a saturation current rating higher than IL_PEAK and a DC current rating higher
than IL_RMS.
9.4.6 Calculate the Minimum Input Capacitance and the Required RMS Current Rating (CIN)
Given a minimum of 2 F of capacitance for every 1 A of LED current, a 1.5 A design would require a minimum
of 3 F. To account for ceramic capacitor tolerances and capacitance drops due to bias voltage this capacitance
should be at least doubled. Higher values will also give better overall performance. Choose a 10 F capacitor
with a voltage rating of 50 V or greater. Using Equation 13, Equation 22, and Equation 23 the user can calculate
the RMS current rating required for the capacitor and the resulting input voltage ripple as shown in Equation 38
and Equation 39.
10 V
D =
= 0.83
12 V
(37)

IIN _ RMS =1
.5 A 0.83 (1 - 0.83 ) = 0.56 A

DVIN =

1.5 A 0.83 (1 - 10.83 )

10 mF 570 kHz

(38)

= 37 mV
(39)

9.4.7 Calculate the Output Capacitor Value (COUT)

The required output capacitor value to get the required LED ripple current can be calculated by first determining
the dynamic resistance of the LEDs used, RLED, by using the forward voltage versus forward current graph in the
manufacturers datasheet. Place a tangent line on the curve at the forward current required to get the slope and
the corresponding V and F. For this design example, the RLED is 0.22 per LED. So the total RLED is 0.22
X 3, or 0.66 . Then find the required output impedance, ZCOUT, using Equation 25 as shown in Equation 40.
Using the required ZCOUT calculate the minimum output capacitance using Equation 26 as shown in Equation 41.
0.66 W 10 mA
= 0.0835 W
ZCOUT =
89 mA - 10 mA
(40)
1
COUT =
= 3.34 mF
2 p 570 kHz 0.0835 W
(41)
Choose a 4.7 F ceramic capacitor with a X5R or X7R dielectric and 16 V or greater voltage rating.
9.4.8 Calculate the Diode Power Dissipation (D)
The maximum input voltage is 48 V, so a 60 V or greater Schottky diode should be used for this application.
Calculate the required current rating and power dissipation to size the diode correctly. This should be done at the
maximum input voltage since that is where the diode conducts for the most time and will have the highest power
dissipation. The duty cycle, D, at the maximum input voltage is 10 V/48 V, or 0.208. Using this duty cycle and
Equation 27 calculate the average diode current, ID_AVE, as shown in Equation 42. Then calculate the diode
power dissipation, PDIODE, using Equation 28 as shown in Equation 43.
ID _ AVE = 1.5 A (1 - 0.208 ) = 1.19 A
(42)

PDIODE = 1.19 A 0.7 V = 0.833 W

(43)

The power dissipation calculation is assuming a diode forward voltage drop, VF, of 0.7 V. If a diode with a
different forward drop is chosen the calculation should be re-done. Choose a Schottky diode with a 1.5 A or
greater current rating that can dissipate at least 1 W of power.
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2 V/div

PDIM

500 mA/div

500 mA/div

2 V/div

9.5 Application Curves

LED Current

PDIM

LED Current

Time = 40 ms/div

Time = 1 ms/div

,
Figure 15. 50% Duty Cycle, 250 Hz PWM Dimming

Figure 14. 1% Duty Cycle, 250 Hz PWM Dimming

2 V/div

PDIM

500 mA/div

LED Current

Time = 1 ms/div

Figure 16. 99% Duty Cycle, 250 Hz PWM Dimming

10 Power Supply Recommendations

Use any DC output power supply with a maximum voltage high enough for the application. The power supply
should have a current limit of at least 3A.

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11 Layout
The TPS92512 requires a proper layout for optimal performance. The following section gives some guidelines to
ensure a proper layout.

11.1 Layout Guidelines

An example of a proper layout for the TPS92512 is shown in Figure 17. Creating a large GND plane under the
integrated circuit (IC) for good electrical and thermal performance is important.

The GND pin of the device must connect to the GND plane directly beneath the IC.
Thermal vias can be used to connect the topside GND plane to additional printed-circuit board (PCB) layers
for heat spreading and more solid grounding.
The input capacitors must be located as close as possible to the VIN pin and the GND plane and should be
tied to a solid backside ground plane using multiple vias.
The compensation components must be located as close as possible to the COMP and GND pins in order to
minimize noise sensitivity.
The PH trace must be kept as short as possible to reduce the possibility of radiated noise/EMI.
The ISENSE node should be kept as short as possible and shielded from noise.
The RT/CLK pin is sensitive and its routing must be kept as short as possible.
In higher current applications, routing the load current of the current-sense resistor to the junction of the input
capacitor and rectifier diode GND node may be necessary. The easiest way to accomplish this is to use a
backside ground plane and arrays of vias to connect the top side ground connections solidly to the backside
plane. This steers the high current away from the sensitive RT/CLK to GND connection.
If possible, the current loop created when the internal MOSFET is on should be in the same direction as the
current loop when the internal MOSFET is off and the schottky diode is conducting. This will prevent magnetic
field reversal, reduce radiated noise, and simplify EMI filtering.

11.2 Layout Example

L

GND

LED+

+
D

CB OOT

COUT

CI N
BOOT

PH

VIN

RISENSE
VIN

RUVLO

GND

UVLO

COMP

PDIM

ISENSE

CCOMP

LED-

RP
RT/CLK

RUVLO

IADJ

RRT
RIADJ
GND
THERMAL/POWER VIA

Figure 17. Layout Example

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12 Device and Documentation Support

12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 1. Related Links
PARTS

PRODUCT FOLDER

SAMPLE & BUY

TECHNICAL
DOCUMENTS

TOOLS &
SOFTWARE

SUPPORT &
COMMUNITY

TPS92512

Click here

Click here

Click here

Click here

Click here

TPS92512HV

Click here

Click here

Click here

Click here

Click here

12.2 Trademarks
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.

12.3 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.4 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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Product Folder Links: TPS92512 TPS92512HV

PACKAGE OPTION ADDENDUM

www.ti.com

11-Mar-2015

PACKAGING INFORMATION
Orderable Device

Status
(1)

Package Type Package Pins Package

Drawing
Qty

Eco Plan

Lead/Ball Finish

MSL Peak Temp

(2)

(6)

(3)

Op Temp (C)

Device Marking
(4/5)

TPS92512DGQR

ACTIVE

MSOPPowerPAD

DGQ

10

2500

Green (RoHS
& no Sb/Br)

CU NIPDAUAG

Level-1-260C-UNLIM

-40 to 125

92512

TPS92512DGQT

ACTIVE

MSOPPowerPAD

DGQ

10

250

Green (RoHS
& no Sb/Br)

CU NIPDAUAG

Level-1-260C-UNLIM

-40 to 125

92512

TPS92512HVDGQR

ACTIVE

MSOPPowerPAD

DGQ

10

2500

Green (RoHS
& no Sb/Br)

CU NIPDAUAG

Level-1-260C-UNLIM

-40 to 125

512H

TPS92512HVDGQT

ACTIVE

MSOPPowerPAD

DGQ

10

250

Green (RoHS
& no Sb/Br)

CU NIPDAUAG

Level-1-260C-UNLIM

-40 to 125

512H

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)

Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Addendum-Page 1

Samples

PACKAGE OPTION ADDENDUM

www.ti.com

11-Mar-2015

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

21-Mar-2015

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)

B0
(mm)

K0
(mm)

P1
(mm)

W
Pin1
(mm) Quadrant

TPS92512DGQR

MSOPPower
PAD

DGQ

10

2500

330.0

12.4

5.3

3.4

1.4

8.0

12.0

Q1

TPS92512DGQT

MSOPPower
PAD

DGQ

10

250

330.0

12.4

5.3

3.4

1.4

8.0

12.0

Q1

TPS92512HVDGQR

MSOPPower
PAD

DGQ

10

2500

330.0

12.4

5.3

3.4

1.4

8.0

12.0

Q1

TPS92512HVDGQT

MSOPPower
PAD

DGQ

10

250

330.0

12.4

5.3

3.4

1.4

8.0

12.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

21-Mar-2015

*All dimensions are nominal

Device

Package Type

Package Drawing

Pins

SPQ

Length (mm)

Width (mm)

Height (mm)

TPS92512DGQR

MSOP-PowerPAD

DGQ

10

2500

364.0

364.0

27.0

TPS92512DGQT

MSOP-PowerPAD

DGQ

10

250

364.0

364.0

27.0

TPS92512HVDGQR

MSOP-PowerPAD

DGQ

10

2500

364.0

364.0

27.0

TPS92512HVDGQT

MSOP-PowerPAD

DGQ

10

250

364.0

364.0

27.0

Pack Materials-Page 2

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