8 JTAG Unit 8
8 JTAG Unit 8
8 JTAG Unit 8
JTAG, as defined by the IEEE Std.-1149.1 standard, is an integrated method for testing
interconnects on printed circuit boards (PCBs) that are implemented at the integrated circuit (IC)
level. The inability to test highly complex and dense printed circuit boards using traditional incircuit testers and bed of nail fixtures was already evident in the mid eighties. Due to physical
space constraints and loss of physical access to fine pitch components and BGA devices,
fixturing cost increased dramatically while fixture reliability decreased at the same time.
A Brief History of JTAG
In the 1980s, the Joint Test Action Group (JTAG) developed a specification for JTAG testing that
was standardized in 1990 as the IEEE Std. 1149.1-1990. In 1993 a new revision to the IEEE Std.
1149.1 standard was introduced (titled 1149.1a) and it contained many clarifications, corrections,
and enhancements. In 1994, a supplement containing a description of the Boundary-Scan
Description Language (BSDL) was added to the standard. Since that time, this standard has
been adopted by major electronics companies all over the world. Applications are found in high
volume, high-end consumer products, telecommunication products, defense systems, computers,
peripherals, and avionics. In fact, due to its economic advantages, some smaller companies that
cannot afford expensive in-circuit testers are using JTAG.
The JTAG test architecture provides a means to test interconnects between integrated circuits on
a board without using physical test probes. It adds a boundary-scan cell that includes a
multiplexer and latches to each pin on the device. Boundary-scan cells in a device can capture
data from pin or core logic signals, or force data onto pins. Captured data is serially shifted out
and externally compared to the expected results. Forced test data is serially shifted into the
boundary-scan cells. All of this is controlled from a serial data path called the scan path or scan
chain. Figure 1 depicts the main elements of a JTAG device. By allowing direct access to nets,
JTAG eliminates the need for a large number of test vectors, which are normally needed to
properly initialize sequential logic. Tens or hundreds of vectors may do the job that had
previously required thousands of vectors. Potential benefits realized from the use of JTAG are
shorter test times, higher test coverage, increased diagnostic capability and lower capital
equipment cost.
Boundary Scan
The main advantage offered by utilising boundary scan technology is the ability to set and read
the values on pins without direct physical access.The process of boundary scan can be most
easily understood with reference to the schematic diagram shown in figure 1.
All the signals between the device's core logic and the 'pins' are intercepted by a serial scan path
known as the Boundary Scan Register (BSR). In normal operation these boundary scan cells are
invisible. However, in test mode the cells can be used to set and/or read values: in external mode
these will be the values of the 'pins'; in 'internal' mode these will the values of the core logic.
The principles of interconnect test using JTAG are illustrated in Figure 2. Figure 2 depicts two
JTAG compliant devices, U1 and U2, which are connected with four nets. U1 includes four
outputs that are driving the four inputs of U2 with various values. In this case, we assume that
the circuit includes two faults: a short between Nets 2 and 3, and an open on Net 4. We will also
assume that a short between two nets behaves as a wired-AND and an open is sensed as logic 1.
To detect and isolate the above defects, the tester is shifting into the U1 boundary-scan register
the patterns shown in Figure 2 and applying these patterns to the inputs of U2. The inputs values
of U2 boundary-scan register are shifted out and compared to the expected results. In this case,
the results (marked in red) on Nets 2, 3, and 4 do not match the expected values and, therefore,
the tester detects the faults on Nets 2, 3, and 4.
JTAG tool vendors provide various types of stimulus and sophisticated algorithms, not only to
detect the failing nets, but also to isolate the faults to specific nets, devices, and pins.
In-system programming
In-Circuit Emulation
Functional testing
Signal
Connects to...
SWDIO
SWO
SWCLK
VCC
GND
Digital ground.
RESET
RSTIN/ pin Connect this pin to the (active low) reset input of the target CPU.
Additional ARM 10-pin cables with connectors are available directly from Samtec:
Note:
Abbreviation
Signal
TCK
Test Clock
TMS
TDI
Test Data In
TDO
TRST
Test Reset
Description
Synchronizes the internal state machine
operations
Sampled at the rising edge of TCK to
determine the next state
Represents the data shifted into the device's
test or programming logic. It is sampled at
the rising edge of TCK when the internal
state machine is in the correct state.
Represents the data shifted out of the
device's test or programming logic and is
valid on the falling edge of TCK when the
internal state machine is in the correct state
An optional pin which, when available, can
reset the TAP controller's state machine
EXTEST
Instruction
The EXTEST instruction performs a PCB interconnect test, places an IEEE 1149.1
compliant device into an external boundary test mode, and selects the boundary scan
register to be connected between TDI and TDO. During EXTEST instruction, the
boundary scan cells associated with outputs are preloaded with test patterns to test
downstream devices. The input boundary cells are set up to capture the input data for
later analysis.
SAMPLE/PRELOAD
Instruction
The SAMPLE/PRELOAD instruction allows an IEEE 1149.1 compliant device to remain
in its functional mode and selects the boundary scan register to be connected between the
TDI and TDO pins. During SAMPLE/PRELOAD instruction, the boundary scan register
can be accessed through a data scan operation, to take a sample of the functional data
input/output of the device. Test data can also be preloaded into the boundary-scan register
prior to loading an EXTEST instruction.
BYPASS
Instruction
Using the BYPASS instruction, a device's boundary scan chain can be skipped, allowing
the data to pass through the bypass register. This allows efficient testing of a selected
device without incurring the overhead of traversing through other devices. The BYPASS
instruction allows an IEEE 1149.1 compliant device to remain in a functional mode and
selects the bypass register to be connected between the TDI and TDO pins. Serial data is
allowed to be transferred through a device from the TDI pin to the TDO pin without
affecting the operation of the device.
JTAG Applications
While it is obvious that JTAG based testing can be used in the production phase of a product,
new developments and applications of the IEEE-1149.1 standard have enabled the use of JTAG
in many other product life cycle phases. Specifically, JTAG technology is now applied to product
design, prototype debugging and field service as depicted in Figure 3. This means the cost of the
JTAG tools can be amortized over the entire product life cycle, not just the production phase.
To facilitate this product life cycle concept, JTAG tool vendors such as Corelis offer an
integrated family of software and hardware solutions for all phases of a product's life-cycle. All
of these products are compatible with each other, thus protecting the user's investment.
Many boards include components that are assembled on both sides of the board. Most of
the through-holes and traces are buried and inaccessible.
Loss of physical access to fine pitch components, such as SMTs and BGAs, makes it
difficult to probe the pins and distinguish between manufacturing and design problems.
Often a prototype board is hurriedly built by a small assembly shop with lower quality
control as compared to a production house. A prototype generally will include more
assembly defects than a production unit.
When the prototype arrives, a test fixture for the ICT is not available and, therefore,
manufacturing defects cannot be easily detected and isolated.
Small-size products do not have test points, making it difficult or impossible to probe
suspected nodes.
Many Complex Programmable Logic Devices (CPLDs) and flash memory devices (in
BGA packages) are not socketed and are soldered directly to the board.
Every time a new processor or a different flash device is selected, the engineer has to
learn from scratch how to program the flash memory.
When a design includes CPLDs from different vendors, the engineer must use different
in-circuit programmers to program the CPLDs.
JTAG technology is the only cost-effective solution that can deal with the above problems. In
recent years, the number of devices that include JTAG has grown dramatically. Almost every
new microprocessor that is being introduced includes JTAG circuitry for testing and in-circuit
emulation. Most of the CPLD and field programmable array (FPGA) manufacturers, such as
Altera, Lattice and Xilinx, to mention a few, have incorporated JTAG logic into their
components, including additional circuitry that uses the JTAG four-wire interface to program
their
devices
in-system.
As the acceptance of JTAG as the main technology for interconnect testing and in-system
programming (ISP) has increased, the various JTAG test and ISP tools have matured as well. The
increased number of JTAG components and mature JTAG tools, as well as other factors that will
be described later, provide engineers with the following benefits:
Easy to implement Design-For- Testability (DFT) rules. A list of basic DFT rules is
provided later in this article.
Quick diagnosis (with high resolution) of interconnection problems without writing any
functional test code.
A typical digital board with JTAG devices includes the following main components:
Various JTAG components such as CPLDs, FPGAs, Processors, etc., chained together via
the boundary-scan path.
Most of the boundary-scan test systems are comprised of two basic elements: Test Program
Generation and Test Execution. Generally, a Test Program Generator (TPG) requires the netlist of
the Unit Under Test (UUT) and the BSDL files of the JTAG components. The TPG automatically
generates test patterns that allow fault detection and isolation for all JTAG testable nets of the
PCB. A good TPG can be used to create a thorough test pattern for a wide range of designs. For
example, ScanExpress TPG typically achieves net coverage of more than 60%, even though the
majority of the PCB designs are not optimized for boundary-scan testing. The TPG also creates
test vectors to detect faults on the pins of non-scannable components, such as clusters and
memories
that
are
surrounded
by
scannable
devices.
Some TPGs also generate a test coverage report that allows the user to focus on the non-testable
nets and determine what additional means are needed to increase the test coverage.
Test programs are generated in seconds. For example, when Corelis ScanExpress TPG was
used, it took a 3.0 GHz Pentium 4 PC 23 seconds to generate an interconnect test for a UUT with
5,638 nets (with 19,910 pins). This generation time includes netlist and all other input files
processing
as
well
as
test
pattern
file
generation.
Test execution tools from various vendors provide means for executing JTAG tests and
performing in-system programming in a pre-planned specific order, called a test plan. Test
vectors files, which have been generated using the TPG, are automatically applied to the UUT
and the results are compared to the expected values. In case of a detected fault, the system
diagnoses the fault and lists the failures as depicted in Figure 5. Figure 5 shows the main window
of the Corelis test execution tool, ScanExpress Runner. ScanExpress Runner gives the user an
overview of all test steps and the results of executed tests. These results are displayed both for
individual tests as well as for the total test runs executed. ScanExpress Runner provides the
ability to add or delete various test steps from a test plan, or re-arrange the order of the test steps
in a plan. Tests can also be enabled or disabled and the test execution can be stopped upon the
failure
of
any
particular
test.
Different test plans may be constructed for different UUTs. Tests within a test plan may be reordered, enabled or disabled, and unlimited different tests can be combined into a test plan.
ScanExpress Runner can be used to develop a test sequence or test plan from various
independent sub-tests. These sub-tests can then be executed sequentially as many times as
specified or continuously if desired. A sub-test can also program CPLDs and flash memories. For
ISP, other formats, such as SVF, JAM, and STAPL, are also supported.
To test the board depicted in Figure 4, the user must execute a test plan that consists of various
test steps as shown in Figure 5.
The first and most important test is the scan chain infrastructure integrity test. The scan chain
must work correctly prior to proceeding to other tests and ISP. Following a successful test of the
scan chain, the user can proceed to testing all the interconnections between the JTAG
components. If the interconnect test fails, ScanExpress Runner displays a diagnostic screen that
identifies the type of failure (such as stuck-at, Bridge, Open) and lists the failing nets and pins as
shown in Figure 6. Once the interconnect test passes, including the testing of transparent
components, it makes sense to continue testing the clusters and the memory devices. At this
stage, the system is ready for in-system programming, which typically takes more time as
compared to testing.
During the design phase of a product, some JTAG vendors will provide design assistance in
selecting JTAG-compliant components, work with the developers to ensure that the proper BSDL
files are used, and provide advice in designing the product for testability.
Loss of physical access to fine pitch components, such as SMTs and BGAs, reduces bedof-nails ICT fault isolation.
Development of test fixtures for ICTs becomes longer and more expensive.
Development of test procedures for ICTs becomes longer and more expensive due to
more complex ICs.
Designers are forced to bring out a large number of test points, which is in direct conflict
with the goal to miniaturize the design.
Assembling boards with BGAs is difficult and subject to numerous defects, such as
solder smearing.
As a stand-alone application at a separate test station or test bench to test all the
interconnects and perform ISP of on-board flash and other memories. JTAG embedded
functional test (JET) may be integrated with boundary-scan.
Integrated into the ICT system, where the JTAG control hardware is embedded in the ICT
system and the boundary-scan (and possibly JET) software is a module called from the
ICT software system.
In the first two cases, the test flow is sometimes augmented with a separate ICT stage after the
JTAG-based testing is completed, although it is becoming more common for ICT to be skipped
altogether or at least to be limited to analog or special purpose functional testing.
The following are major benefits in using JTAG test and in-system programming in production:
Preproduction testing can start the next day when prototype is released to production.
Production test is an obvious area in which the use of boundary-scan yields tremendous returns.
Automatic test program generation and fault diagnostics using JTAG software products and the
lack of expensive fixturing requirements can make the entire test process very economical. For
products that contain edge connectors and digital interfaces that are not visible from the
boundary-scan chain, JTAG vendors offer a family of boundary-scan controllable I/Os that
provide a low cost alternative to expensive digital pin electronics.
If there are programmable components in a chain, such as FPGAs, CPLDs, etc., group
them together in the chain order and place the group at either end of the chain. It is
recommended that you provide access to Test Data In (TDI) and Test Data Out (TDO)
signals where the programmable group connects to the non-programmable devices.
All parts in the boundary-scan chain should have 1149.1-compliant test access ports
(TAPs).
Use simple buffering for the Test Clock (TCK) and Test Mode Select (TMS) signals to
simplify test considerations for the boundary-scan TAP. The TAP signals should be
buffered to prevent clocking and drive problems.
Group similar device families and have a single level converter interface between them,
TCK, TMS, TDI, TDO, and system pins.
TCK should be properly routed to prevent skew and noise problems.
Use the standard JTAG connector on your board as depicted in Corelis documentation.
Ensure that BSDL files are available for each JTAG component that is used on your
board and that the files are validated.
Design for interconnect testing requires board-level system understanding to ensure higher test
coverage and elimination of signal level conflicts.
Determine which JTAG components are on the board. Change as many non-JTAG
components to IEEE 1149.1-compliant devices as possible in order to maximize test
coverage.
Check non-JTAG devices on the board and design disabling methods for the outputs of
those devices in order to prevent signal level conflicts. Connect the enable pins of the
conflicting devices to JTAG controllable outputs. Corelis tools will keep the
enable/disable outputs at a fixed disabling value during the entire test.
Ensure that your memory devices are surrounded by JTAG components. This will allow
you to use a test program generator, such as ScanExpress TPG, to test the interconnects
of the memory devices.
Check the access to the non-boundary-scan clusters. Make sure that the clusters are
surrounded by JTAG components. By surrounding the non-boundary-scan clusters with
JTAG devices, the clusters can then be tested using a JTAG test tool.
If your design includes transparent components, such as series resistors or non-inverting
buffers, your test coverage can be increased by testing through these components using
ScanExpress TPG.
Connect all I/Os to JTAG controllable devices. This will enable the use of JTAG, digital
I/O module, such as the ScanIO-300LV, to test all your I/O pins, thus increasing test
coverage.
Summary
JTAG is a widely practiced test methodology that is reducing costs, speeding
development, and improving product quality for electronics manufacturers around the
world. By relying on an industry standard, IEEE 1149.1, it is relatively quick, easy, and
inexpensive to deploy a highly effective test procedure. Indeed, for many of today's
PCBs, there is little alternative because of limited access to board-level circuitry. This
paper highlights just some of the potential applications of the JTAG standard in various
stages of the product life cycle, each contributing to the overall effect of significantly
reduced product development and support costs.