ARM Processors 11
ARM Processors 11
ARM Processors 11
Architecture:
Flash Patch:
3 stage
pipelined
Harvard
Programmers Model:
Addressing Modes:
o Refer to Appendix- C
Operating Modes: Thread Mode (entered on reset) and Handler Mode (entered
on exception)
Operating States: Thumb State (Normal Execution) and Debug State (Halt
during Debug)
Two types of stack: Main Stack and Process Stack
13 General Purpose Registers (32- bit)
Stack point alias of banked registers, SP_process, SP_main
Link Register r14
Program Counter r15
Program Status Register xPSR
o Application Program Status Register (APSR) Consists current state of
condition flags
o InterruptProgram Status Register (IPSR) Consists ISR number [D8-D0] of
current exception activation
o ExecutionProgram Status Register (EPSR) Consists Interruptible
Continuous Instruction (ICI) field, Execution Status Field for If-Then (IT)
Instruction and Thumb Status Bit (T- bit)
Instruction Set:
All Thumb Instructions (Refer to Appendix- A) except BLX(1) and SETEND.
All Thumb 2 instructions (Refer to Appendix- B).
Special Features:
Programmers Model:
Addressing Modes:
o Refer to Appendix- C
Operating modes: Thread mode (application software enters thread mode
after reset) and Handle mode (handles exceptions)
Privilege levels: Unprivileged (limited access) and Privileged (complete
access)
Stack: Full descending stack; two types- Main stack (privileged) and Process
stack (unprivileged)
13 general purpose registers R0-R12
Banked Stack Pointers: MSP (main stack pointer) and PSP (process stack
pointer)
Link Register (LR) R14
Program Counter (PC) R15
Program Status Register (xPSR)
Figure 5: Processor core registers (Ref: ARM Cortex M0+ Technical Reference
MAnual )
Instruction Set:
Special Features:
Programmers Model:
Addressing Modes
o Refer to Appendix- C
Modes of operation: User Mode (in which all the applications run), System
Mode (provides privileged access to memory and coprocessors), Supervisor
Mode (entered in it when CPU is reset or SVC is executed), Abort Mode
(entered in it on Prefetch Abort or Data Abort eception), Undefined Mode
(entered during undefined instruction exception), IRQ Mode (entered on IRQ
execution), FIQ Mode (entered when processor handles FIQ interrupt), Hyp
Privilege Levels: PL0 (executes User Mode), PL1 (executes in all modes other
than User Mode and Hyp Mode), PL2 (executes in Hyp Mode)
16 ARM Core registers including R0 to R12, Stack Pointer (SP), Link Register
and Program Counter (PC).
Registers are selected from a large set of registers, that includes Banked
copies of some registers.
Banked copies of stack pointer are SP_irq and SP_hyp.
CPSR (- Current Program Status Register) holds the processor status and
control information.
o APSR- Application Program status resister
o ISATSTATE- Instruction Set status register
o ITSTATE- IT (If-Then) block status register
o ENDIANSTATE- Endianness mapping register
SPSR- Saved Program Status Register (to record pre- execution value of
CPSR)
Instruction Set:
Specifications:
Architecture: ARM v7-A Cortex
Performance Efficiency: 2.50 DMIPS/MHz per core
Optimized Level 1 Cache
Optional Level 2 Cache Controller
8 to 11 stages pipeline
Clock rate- 800 MHz to 2GHz
NEON Media and Floating Point Processing Engine
TrustZone Technology(Provides support for secured wide array of client
and server computing)
ARM A1176JZF-S
Architecture:
Programmers Model:
Addressing Modes
o Refer to Appendix- C
Modes of operation: User Mode (in which all the applications run), System
Mode (provides privileged access to memory and coprocessors), Supervisor
Figure 12: Processor Core registers (Ref: ARM A1176JZF-S Reference Manual)
Instruction Set:
Specifications:
ARM v6 Instruction Set Architecture
ARM DSP Extension
SIMD (Single Instruction Multiple Data) media processing extensions deliver
up to 2x performance for video processing
APPENDIX-A
Thumb Instruction Set:
Rd is the destination register.
Rn is the register holding the data for the first operand.
Rm is the register holding the data for the second operand.
shift is an optional shift to be applied to Rm.
immedis the immediate operand.
PCis the program counter.
SP is the stack pointer.
reglistis the non- empty list of registers.
<opcode>Rd, #<immed>
MOV, ADD, SUB, CMP
<opcode>Rd, Rm
MOV, CPY, ADD, ADC, SBC, NEG, MUL, AND, EOR, ORR, BIC, MVN, REV, REV16,
REVSH, SXTH, SXTB, UXTH, UXTB
<opcode>Rd, Rn, #<immed>
ADD, SUB
<opcode> Rd, Rn, Rm
ADD, SUB
<opcode>SP, #<immed>
ADD, SUB
<opcode>Rd, SP, #<immed>
ADD
<opcode> Rd, PC, #<immed>
ADD
<opcode>Rn, Rm
CMP, CMN, TST
<opcode> Rd, Rm, #<shift>
LSL, LSR, ASR
<opcode>Rd, Rs
LSL, LSR, ASR
<opcode>Rd, [Rn, #<immed>]
LDR, LDRH, LDRB, STR, STRH, STRB
<opcode> Rd, [Rn, Rm]
LDR, LDRH, LDRSH, LDRB, LDRSB, STR, STRH, STRB
<opcode> Rd, [PC, #<immed>]
LDR
APPENDIX-B
<opcode>Rn, <Operand2>
o
o
MOV, MVN
MOVT, MOV
APPENDIX-C
Addressing Modes: