41639A

PIC16(L)F1454/5/9
Data Sheet
14/20-Pin Flash, 8-Bit USB Microcontrollers
with XLP Technology
2012 Microchip Technology Inc.
Preliminary
DS41639A
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device

applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyers risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
2012, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620763476
QUALITY MANAGEMENT SYSTEM

CERTIFIED BY DNV
== ISO/TS 16949 ==
DS41639A-page 2
Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Companys quality system processes and procedures
are for its PIC MCUs and dsPIC DSCs, KEELOQ code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchips quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
Preliminary
PIC16(L)F1454/5/9
14/20-Pin, 8-Bit Flash USB Microcontroller with
XLP Technology
High-Performance RISC CPU:
Extreme Low-Power Management

PIC16LF145X with XLP:
C Compiler Optimized Architecture

Only 49 Instructions
14 Kbytes Linear Program Memory Addressing
1024 Bytes Linear Data Memory Addressing
Operating Speed:
- DC 48 MHz clock input
- DC 83 ns instruction cycle
- Selectable 3x or 4x PLL for specific frequencies
Interrupt Capability with Automatic Context
Saving
16-Level Deep Hardware Stack with Optional
Overflow/Underflow Reset
Direct, Indirect and Relative Addressing modes:
- Two full 16-bit File Select Registers (FSRs)
capable of accessing both data or program
memory
- FSRs can read program and data memory
Flexible Oscillator Structure:
Special Microcontroller Features:

Operating Voltage Range:
- 1.8V to 3.6V (PIC16LF145X)
- 2.3V to 5.5V (PIC16F145X)
Self-Programmable under Software Control
Power-on Reset (POR)
Power-up Timer (PWRT)
Programmable Brown-Out Reset (BOR)
Low-Power BOR (LPBOR)
Extended Watchdog Timer (WDT):
- Programmable period from 1 ms to 256s
Programmable Code Protection
In-Circuit Serial Programming (ICSP) via Two
Pins
Enhanced Low-Voltage Programming (LVP)
Power-Saving Sleep mode:
Universal Serial Bus (USB) Features:

Self-Tuning from USB Host
(eliminates need for external crystal)
USB V2.0 Compliant SIE
Low Speed (1.5 Mb/s) and Full Speed (12 Mb/s)
Supports Control, Interrupt, Isochronous and Bulk
Transfers
Supports up to Eight Bidirectional Endpoints
512-Byte Dual Access RAM for USB
Interrupt-on-Change (IOC) on D+/D- for USB Host
Detection
Configurable Internal Pull-up Resistors for use
with USB
Sleep mode: 25 nA @ 1.8V, typical

Watchdog Timer Current: 290 nA @ 1.8V, typical
Timer1 Oscillator: 600 nA @ 32 kHz, typical
Operating Current: 25 A/MHz @ 1.8V, typical
16 MHz Internal Oscillator Block:

- Factory calibrated to 0.25%, typical
- Software selectable frequency range from
16 MHz to 31 kHz
- Tunable to 0.25% across temperature range
- 48 MHz with 3x PLL
31 kHz Low-Power Internal Oscillator
Clock Switching with run from:
- Primary Oscillator
- Secondary Oscillator (SOSC)
- Internal Oscillator
Clock Reference Output:
- Clock Prescaler
- CLKOUT
Analog Features(1):
Analog-to-Digital Converter (ADC):
- 10-bit resolution
- Up to nine external channels
- Two internal channels:
- Fixed Voltage Reference channel
- DAC output channel
- Auto acquisition capability
- Conversion available during Sleep
Two Comparators:
- Rail-to-rail inputs
- Power mode control
- Software controllable hysteresis
Voltage Reference module:
- Fixed Voltage Reference (FVR) with 1.024V,
2.048V and 4.096V output levels
Up to One Rail-to-Rail Resistive 5-Bit DAC with
Positive Reference Selection
Note 1:
Preliminary
Analog features are not available on

PIC16(L)F1454 devices.
DS41639A-page 3
PIC16(L)F145X
Peripheral Features:
Up to 14 I/O Pins and Three Input-only Pins:
- High current sink/source 25 mA/25 mA
- Individually programmable weak pull-ups
- Individually programmable
Interrupt-On-Change (IOC) pins
Timer0: 8-Bit Timer/Counter with 8-Bit
Programmable Prescaler
Enhanced Timer1:
- 16-bit timer/counter with prescaler
- External Gate Input mode
Timer2: 8-Bit Timer/Counter with 8-Bit Period
Register, Prescaler and Postscaler
Two 10-bit PWM modules
Complementary Waveform Generator (CWG)(1):
- Up to four selectable signal sources
- Selectable falling and rising edge dead-band
control
- Polarity control
- Up to four auto-shutdown sources
- Multiple input sources: PWM, Comparators
Master Synchronous Serial Port (MSSP) with SPI
and I2C with:
- 7-bit address masking
- SMBus/PMBus compatibility
Enhanced Universal Synchronous
Asynchronous Receiver Transmitter (EUSART):
- RS-232, RS-485 and LIN compatible
- Auto-baud detect
- Auto-wake-up on Start
Note 1:
Not available on PIC16(L)F1454 devices.
Note:
For other small form-factor package availability and marking

www.microchip.com/packaging or contact your local sales office.
DS41639A-page 4
Preliminary
information,
XLP
PIC16(L)F1454 (1) 8192 1024 11

2/1
2
1
1
1
1
PIC16(L)F1455 (1) 8192 1024 11 5
2
1
2/1
2
1
1
1
1
1
PIC16(L)F1459 (1) 8192 1024 17 9
2
1
2/1
2
1
1
1
1
1
Note 1: I - Debugging, Integrated on Chip; H - Debugging, Available using Debug Header;
E - Emulation, Available using Emulation Header.
2: Three pins are input-only.
Data Sheet Index:
1: DS41639 PIC16(L)F1454/1455/1459 Data Sheet, 14/20-Pin Flash, 8-Bit USB Microcontrollers.
Debug(1)
Clock Reference
USB
CWG
MSSP (I2C/SPI)
EUSART
PWM
Timers
(8/16-bit)
DAC
Comparators
10-bit ADC (ch)
I/Os(2)
Data SRAM
(bytes)
Program Memory
Flash (words)
Device
Data Sheet Index
PIC16(L)F145X Family Types
I/H
I/H
I/H
Y
Y
Y
please
visit
PIC16(L)F145X
FIGURE 1:
14-PIN PDIP, SOIC, TSSOP DIAGRAM FOR PIC16(L)F1454/1455
PDIP, SOIC, TSSOP

1
14
RA5
RA4
13
VSS
RA0/D+/ICSPDAT(1)
12
RA1/D-/ICSPCLK(1)
11
VUSB3V3
10
RC0/ICSPDAT
RC1/ICSPCLK
RC2
MCLR/VPP/RA3
3
4
RC5
RC4
RC3
PIC16(L)F1454
PIC16(L)F1455
VDD
Note 1: LVP support for PIC18(L)F1XK50 legacy designs.

2: See Table 1 and Table 2 for location of all peripheral functions.
FIGURE 2:
16-PIN QFN DIAGRAM FOR PIC16(L)F1454/1455
Vss
NC
NC
VDD
QFN (4x4)
16 15 14 13
RA5 1
RA4 2
MCLR/VPP/RA3 3
12 RA0/D+/ICSPDAT(1)
PIC16(L)F1454
PIC16(L)F1455
RC5 4
11 RA1/D-/ICSPCLK(1)
10 VUSB3V3
RC2
ICSPCLK/RC1
RC4
RC3
RC0/ICSPDAT

2: See Table 1 and Table 2 for location of all peripheral functions.
Preliminary
DS41639A-page 5
PIC16(L)F145X
FIGURE 3:
20-PIN PDIP, SOIC, SSOP DIAGRAM FOR PIC16(L)F1459
PDIP, SOIC, SSOP

VSS
RA0/D+/ICSPDAT(1)
20
RA5
19
RA4
18 RA1/D-/ICSPCLK(1)
MCLR/VPP/RA3
3
4
RC5
RC4
RC3
RC6
RC7
RB7 10
PIC16(L)F1459
VDD
17 VUSB3V3
16 RC0/ICSPDAT
15
RC1/ICSPCLK
14
RC2
13
RB4
12
RB5
11
RB6

2: See Table 3 for location of all peripheral functions.
FIGURE 4:
20-PIN QFN DIAGRAM FOR PIC16(L)F1459
RA4
RA5
VDD
Vss
RA0/D+/ICSPDAT(1)
QFN (4x4)
20 19 18 17 16
MCLR/VPP/RA3
RC5
RC4
RC3
RC6
1
2
3
4
5
PIC16(L)F1459
15
14
13
12
11
RA1/D-/ICSPCLK(1)
VUSB3V3
RC0/ICSPDAT
RC1/ICSPCLK
RC2
RC7
RB7
RB6
RB5
RB4
6 7 8 9 10

2: See Table 3 for location of all peripheral functions.
DS41639A-page 6
Preliminary
PIC16(L)F145X
14-Pin PDIP/SOIC/TSSOP
16-Pin QFN
ADC
Reference
Comparator
Timer
CWG
USB
EUSART
PWM
MSSP
Interrupt
Basic
14-PIN ALLOCATION TABLE (PIC16(L)F1454)
I/O
TABLE 1:
RA0
13
12
D+
IOC
ICSPDAT(3)
RA1
12
11
D-
IOC
ICSPCLK(3)
RA2
RA3
T1G(2)
SS(2)
IOC
MCLR
VPP
RA4
SOSCO
T1G(1)
SDO(2)
IOC
CLKOUT
OSC2
CLKR(1)
RA5
SOSCI
T1CKI
PWM2(2)
IOC
CLKIN
OSC1
RC0
10
SCL
SCK
ICSPDAT
RC1
SDA
SDI
INT
ICSPCLK
RC2
SDO(1)
SS(1)
CLKR(2)
PWM2
(1)
RC3
RC4
TK
CK
RC5
T0CKI
RX
DT
PWM1
VDD
16
VDD
VSS
14
13
VSS
VUSB3V3
11
10
VUSB3V3
Note
1:
2:
3:
Default location for peripheral pin function. Alternate location can be selected using the APFCON register.
Alternate location for peripheral pin function selected by the APFCON register.
LVP support for PIC18(L)F1XK50 legacy designs.
Preliminary
DS41639A-page 7
PIC16(L)F145X
14-Pin PDIP/SOIC/TSSOP
16-Pin QFN
ADC
Reference
Comparator
Timer
CWG
USB
EUSART
PWM
MSSP
Interrupt
Basic
I/O
TABLE 2:
RA0
13
12
D+
IOC
ICSPDAT(3)
RA1
12
11
D-
IOC
ICSPCLK(3)
RA2
RA3
T1G(2)
SS(2)
IOC
MCLR
VPP
RA4
AN3
SOSCO
T1G(1)
SDO(2)
IOC
CLKOUT
OSC2
CLKR(1)
RA5
SOSCI
T1CKI
PWM2(2)
IOC
CLKIN
OSC1
RC0
10
AN4
VREF+
C1IN+
C2IN+
SCL
SCK
ICSPDAT
RC1
AN5
C1IN1C2IN1-
CWGFLT
SDA
SDI
INT
ICSPCLK
RC2
AN6
DACOUT1
C1IN2C2IN2-
SDO(1)
RC3
AN7
DACOUT2
C1IN3C2IN3-
PWM2(1)
SS(1)
CLKR(2)
RC4
C1OUT
C2OUT
CWG1B
TK
CK
RC5
T0CKI
CWG1A
RX
DT
PWM1
VDD
16
VDD
VSS
14
13
VSS
VUSB3V3
11
10
VUSB3V3
Note
1:
2:
3:
DS41639A-page 8
Preliminary
PIC16(L)F145X
20-Pin PDIP/SOIC/SSOP
20-Pin QFN
ADC
Reference
Comparator
Timer
CWG
USB
EUSART
PWM
MSSP
Interrupt
Basic
I/O
TABLE 3:
RA0
19
16
D+
IOC
ICSPDAT(3)
RA1
18
15
D-
IOC
ICSPCLK(3)
RA2
RA3
T1G(2)
SS(2)
IOC
MCLR
VPP
RA4
20
AN3
SOSCO
T1G(1)
IOC
OSC2
CLKOUT
CLKR(1)
RA5
19
SOSCI
T1CKI
IOC
OSC1
CLKIN
RB4
13
10
AN10
SDA
SDI
IOC
RB5
12
AN11
RX
DX
IOC
RB6
11
SCL
SCK
IOC
RB7
10
TX
CK
IOC
RC0
16
13
AN4
VREF+
C1IN+
C2IN+
ICSPDAT
RC1
15
12
AN5
C1IN1C2IN1-
CWGFLT
INT
ICSPCLK
RC2
14
11
AN6
DACOUT1
C1IN2C2IN2-
RC3
AN7
DACOUT2
C1IN3C2IN3-
CLKR(2)
RC4
C1OUT
C2OUT
CWG1B
RC5
T0CKI
CWG1A
PWM1
RC6
AN8
PWM2
RC7
AN9
SDO
VDD
18
VDD
VSS
20
17
VSS
VUSB3V3
17
14
VUSB3V3
Note
1:
2:
3:
SS
(1)
Preliminary
DS41639A-page 9
PIC16(L)F145X
Table of Contents
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0
12.0
13.0
14.0
15.0
16.0
Device Overview ........................................................................................................................................................................ 13

Enhanced Mid-Range CPU ........................................................................................................................................................ 21
Memory Organization ................................................................................................................................................................. 23
Device Configuration .................................................................................................................................................................. 51
Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 57
Resets ........................................................................................................................................................................................ 79
Reference Clock Module ............................................................................................................................................................ 87
Interrupts .................................................................................................................................................................................... 91
Power-Down Mode (Sleep) ...................................................................................................................................................... 103
Watchdog Timer (WDT) ........................................................................................................................................................... 107
Flash Program Memory Control ............................................................................................................................................... 112
I/O Ports ................................................................................................................................................................................... 129
Interrupt-On-Change ................................................................................................................................................................ 143
Fixed Voltage Reference (FVR) (PIC16(L)F1455/9 only)......................................................................................................... 149
Temperature Indicator Module (PIC16(L)F1455/9 only)........................................................................................................... 151
Analog-to-Digital Converter (ADC) Module
(PIC16(L)F1455/9 only) ............................................................................................................................................................. 153
17.0 Digital-to-Analog Converter (DAC) Module
(PIC16(L)F1455/9 only) ............................................................................................................................................................. 169
18.0 Comparator Module
(PIC16(L)F1455/9 only) ............................................................................................................................................................. 173
19.0 Timer0 Module ......................................................................................................................................................................... 183
20.0 Timer1 Module with Gate Control............................................................................................................................................. 187
21.0 Timer2 Module ......................................................................................................................................................................... 199
22.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 203
23.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 257
24.0 Pulse Width Modulation (PWM) Module................................................................................................................................... 287
25.0 Complementary Waveform Generator (CWG) Module
(PIC16(L)F1455/9 only)293
26.0 Universal Serial Bus (USB) ...................................................................................................................................................... 309
27.0 In-Circuit Serial Programming (ICSP) ............................................................................................................................... 337
28.0 Instruction Set Summary .......................................................................................................................................................... 339
29.0 Electrical Specifications............................................................................................................................................................ 353
30.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 383
31.0 Development Support............................................................................................................................................................... 385
32.0 Packaging Information.............................................................................................................................................................. 389
Appendix A: Data Sheet Revision History.......................................................................................................................................... 407
Index .................................................................................................................................................................................................. 409
The Microchip Web Site ..................................................................................................................................................................... 415
Customer Change Notification Service .............................................................................................................................................. 415
Customer Support .............................................................................................................................................................................. 415
Reader Response .............................................................................................................................................................................. 416
Product Identification System............................................................................................................................................................. 417
DS41639A-page 10
Preliminary
PIC16(L)F145X
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
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welcome your feedback.
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To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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Preliminary
DS41639A-page 11
PIC16(L)F145X
NOTES:
DS41639A-page 12
Preliminary
PIC16(L)F1454/5/9
1.0
DEVICE OVERVIEW
The PIC16(L)F1454/5/9 are described within this data

sheet. They are available in 14/20-pin packages.
Figure 1-1 shows a block diagram of the
PIC16(L)F1454/5/9 devices. Tables 1-2, 1-3 and 1-4
show the pinout descriptions.
Reference Table 1-1 for peripherals available per
device.
Analog-to-Digital Converter (ADC)

Clock Reference
Complementary Wave Generator (CWG)

Digital-to-Analog Converter (DAC)
PIC16F1459
PIC16LF1459
Peripheral
PIC16F1455
PIC16LF1455
DEVICE PERIPHERAL SUMMARY

PIC16F1454
PIC16LF1454
TABLE 1-1:
Fixed Voltage Reference (FVR)
Temperature Indicator
C1
C2
Enhanced Universal Synchronous/Asynchronous Receiver/Transmitter

(EUSART)
Universal Serial Bus (USB)
Comparators
Master Synchronous Serial Ports

MSSP1
PWM1
PWM2
Timer0
Timer1
Timer2
PWM Modules
Timers
Preliminary
DS41639A-page 13
PIC16(L)F1454/5/9
FIGURE 1-1:
PIC16(L)F1454/5/9 BLOCK DIAGRAM
Program
Flash Memory
RAM
OSC2/CLKOUT
OSC1/CLKIN
Timing
Generation
PORTA
CPU
INTRC
Oscillator
PORTB(2)
(Figure 2-1)
MCLR
USB
EUSART
Note
DS41639A-page 14
1:
2:
CLKR
Temp.
Indicator(1)
PORTC
C1(1)
C2(1)
ADC
10-Bit(1)
Timer0
Timer1
Timer2
CWG1(1)
FVR(1)
PWM1
PWM2
MSSP1
DAC(1)
PIC16(L)F1455/9 only.
PIC16(L)F1459 only.
Preliminary
PIC16(L)F1454/5/9
TABLE 1-2:
PIC16(L)F1454 PINOUT DESCRIPTION
Name
RA0/D+/ICSPDAT(3)
RA1/D-/ICSPCLK(3)
RA3/VPP/T1G(2)/SS(2)/MCLR
RA4/SOSCO/CLKOUT/
T1G(1)/SDO(2)/CLKR(1)/OSC2
RA5/CLKIN/SOSCI/T1CKI/
PWM2(2)/OSC1
RC0/SCL/SCK/ICSPDAT
RC1/SDA/SDI/INT/ICSPCLK
RC2/SDO(1)
RC3/PWM2(1)/SS(1)/CLKR(2)
Function
Input
Type
RA0
TTL
D+
XTAL
Output
Type
Description
CMOS General purpose I/O.

XTAL
USB differential plus line.
ICSPDAT
ST
CMOS ICSP Data I/O.
RA1
TTL
D-
XTAL
XTAL
USB differential minus line.
ICSPCLK
ST
ICSP Programming Clock.
RA3
TTL
General purpose input with IOC and WPU.
VPP
HV
Programming voltage.
T1G
ST
Timer1 Gate input.
SS
ST
Slave Select input.
Master Clear with internal pull-up.
MCLR
ST
RA4
TTL
SOSCO
XTAL
CLKOUT
XTAL
T1G
ST
SDO
CMOS SPI data output.
CLKR
CMOS Clock reference output.
OSC2
XTAL
XTAL
RA5
TTL
CLKIN
CMOS
SOSCI
XTAL
XTAL
T1CKI
ST
PWM2
OSC1
XTAL
RC0
TTL
SCL
I2C
Secondary Oscillator Connection.
CMOS FOSC/4 output.

Timer1 Gate input.
Primary Oscillator connection.

External clock input (EC mode).
Timer1 clock input.
CMOS PWM output.

XTAL
Primary Oscillator Connection.

OD
I2C clock.
SCK
ST
ICSPDAT
ST
CMOS ICSP Data I/O.
RC1
TTL
SDA
I2C
SDI
CMOS
SPI data input.
INT
ST
External input.
ICSPCLK
ST
RC2
TTL
SDO
RC3
TTL
PWM2
SS
ST
CLKR
CMOS SPI clock.
OD
I2C data input/output.

CMOS PWM output.
Slave Select input.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output

OD = Open Drain
TTL = TTL compatible input ST
= Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage
XTAL = Crystal
levels
Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.
2: Alternate location for peripheral pin function selected by the APFCON register.
3: LVP support for PIC18(L)F1XK50 legacy designs.
Preliminary
DS41639A-page 15
PIC16(L)F1454/5/9
TABLE 1-2:
PIC16(L)F1454 PINOUT DESCRIPTION (CONTINUED)
Name
RC4/TX/CK
RC5/T0CKI/RX/DT/PWM1
VDD
VSS
VUSB3V3
Function
Input
Type
RC4
TTL
Output
Type
Description
TX
CK
ST
CMOS USART asynchronous transmit.

CMOS USART synchronous clock.
RC5
TTL
T0CKI
ST
RX
ST
DT
ST
CMOS USART synchronous data.
PWM1
CMOS PWM output.
VDD
Power
VSS
Power
Ground reference.
VUSB3V3
Power
Positive supply for USB transceiver.
Timer0 clock input.
USART asynchronous input.
Positive supply.

OD = Open Drain
HV = High Voltage
XTAL = Crystal
levels
DS41639A-page 16
Preliminary
PIC16(L)F1454/5/9
TABLE 1-3:
Name
RA0/D+/ICSPDAT(3)
RA1/D-/ICSPCLK(3)
RA4/AN3/SOSCO/CLKOUT/
T1G(1)/SDO(2)/CLKR(1)/OSC2
PWM2(2)/OSC1
RC0/AN4/VREF+/C1IN+/C2IN+/
SCL/SCK/ICSPDAT
Function
Input
Type
RA0
TTL
D+
XTAL
Output
Type
Description

XTAL
ICSPDAT
ST
CMOS ICSP Data I/O.
RA1
TTL
D-
XTAL
XTAL
ICSPCLK
ST
RA3
TTL
VPP
HV
T1G
ST
Timer1 Gate input.
SS
ST
Slave Select input.
MCLR
ST
RA4
TTL
AN3
AN
SOSCO
XTAL
XTAL
A/D Channel input.

CMOS FOSC/4 output.
CLKOUT
T1G
ST
SDO
CLKR
OSC2
XTAL
RA5
TTL
XTAL
CLKIN
CMOS
XTAL
XTAL
T1CKI
ST
OSC1
XTAL
RC0
TTL
SOSCI
PWM2
Timer1 Gate input.

Timer1 clock input.
CMOS PWM output.

XTAL
AN4
AN
VREF+
AN
A/D Channel input.

Positive Voltage Reference input.
C1IN+
AN
Comparator positive input.
C2IN+
AN
SCL
I C
OD
I2C clock.
SCK
ST
CMOS SPI clock.
ICSPDAT
ST
CMOS ICSP Data I/O.

OD = Open Drain
HV = High Voltage
XTAL = Crystal
levels
Preliminary
DS41639A-page 17
PIC16(L)F1454/5/9
TABLE 1-3:
Name
RC1/AN5/C1IN1-/
C2IN1-/CWGFLT/SDA/
SDI/INT/ICSPCLK
RC2/AN6/DACOUT1/
C1IN2-/C2IN2-/SDO(1)
RC3/AN7/DACOUT2/
C1IN3-/C2IN3-/PWM2(1)/
SS(1)/CLKR(2)
RC4/C1OUT/C2OUT/
CWG1B/TX/CK
RC5/T0CKI/CWG1A/RX/DT/
PWM1
Function
Input
Type
RC1
TTL
Output
Type
Description
AN5
AN
A/D Channel input.
C1IN1-
AN
Comparator negative input.
C2IN1-
AN
CWGFLT
ST
Complementary Waveform Generator Fault input.
SDA
I C
OD
SDI
CMOS
SPI data input.
INT
ST
External input.
ICSPCLK
ST
RC2
TTL
AN6
AN
A/D Channel input.
DACOUT1
AN
Digital-to-Analog Converter output.
C1IN2-
AN
C2IN2-
AN
SDO
RC3
TTL
AN7
AN
A/D Channel input.
DACOUT2
AN
C1IN3-
AN
C2IN3-
AN
PWM2
CLC2IN0
ST
CLKR
RC4
TTL
C1OUT

CMOS PWM output.
Configurable Logic Cell source input.

CMOS Comparator output.
C2OUT
CWG1B
CMOS CWG complementary output.
TX
CK
ST

RC5
TTL
T0CKI
ST
CWG1A
RX
ST
Timer0 clock input.
DT
ST
PWM1
CMOS PWM output.
VDD
VDD
Power
Positive supply.
VSS
VSS
Power
Ground reference.
VUSB3V3
Power
VUSB3V3

OD = Open Drain
HV = High Voltage
XTAL = Crystal
levels
DS41639A-page 18
Preliminary
PIC16(L)F1454/5/9
TABLE 1-4:
Name
RA0/D+/ICSPDAT(3)
RA1/D-/ICSPCLK(3)
RA4/AN3/SOSCO/CLKOUT/
T1G(1)/CLKR(1)/OSC2
OSC1
RB4/AN10/SDA/SDI
RB5/AN11/RX/DT
RB6/SCL/SCK
RB7/TX/CK
Function
Input
Type
RA0
TTL
D+
XTAL
Output
Type
Description

XTAL
ICSPDAT
ST
CMOS ICSP Data I/O.
RA1
TTL
D-
XTAL
XTAL
ICSPCLK
ST
RA3
TTL
VPP
HV
T1G
ST
Timer1 Gate input.
SS
ST
Slave Select input.
MCLR
ST
RA4
TTL
AN3
AN
SOSCO
XTAL
XTAL
CLKOUT
T1G
ST
CLKR
OSC2
XTAL
A/D Channel input.

CMOS FOSC/4 output.
Timer1 Gate input.

XTAL
RA5
TTL
CLKIN
CMOS
SOSCI
XTAL
XTAL
T1CKI
ST
OSC1
XTAL
RB4
TTL
XTAL

Timer1 clock input.
AN10
AN
A/D Channel input.
SDA
I2C
OD
SPI data input.
SDI
CMOS
RB5
TTL
AN11
AN
A/D Channel input.
RX
ST
DT
ST
RB6
TTL
SCL
I2C
SCK
ST
RB7
TTL
TX
CK
ST
OD
I2C clock.
CMOS SPI clock.


OD = Open Drain
HV = High Voltage
XTAL = Crystal
levels
Preliminary
DS41639A-page 19
PIC16(L)F1454/5/9
TABLE 1-4:
Name
RC0/AN4/VREF+/C1IN+/C2IN+/
ICSPDAT
RC1/AN5/C1IN1-/C2IN1-/
CWGFLT/INT/ICSPCLK
RC2/AN6/DACOUT1/
C1IN2-/C2IN2-
RC3/AN7/DACOUT2/
C1IN3-/C2IN3-/CLKR(2)
RC4/C1OUT/C2OUT/
CWG1B
RC5/T0CKI/CWG1A/PWM1
RC6/AN8/SS(1)/PWM2
RC7/AN9/SDO
Function
Input
Type
RC0
TTL
Output
Type
Description
AN4
AN
VREF+
AN
A/D Channel input.

Positive Voltage Reference input.
C1IN+
AN
C2IN+
AN
ICSPDAT
ST
CMOS ICSP Data I/O.
RC1
TTL
AN5
AN
A/D Channel input.
C1IN1-
AN

C2IN1-
AN
CWGFLT
ST
Complementary Waveform Generator Fault input.
INT
ST
External input.
ICSPCLK
ST
RC2
TTL
AN6
AN
A/D Channel input.
DACOUT1
AN
C1IN2-
AN
C2IN2-
AN
RC3
TTL
AN7
AN
A/D Channel input.
DACOUT2
AN
C1IN3-
AN
C2IN3-
AN
CLKR
RC4
TTL
C1OUT
C2OUT
CWG1B
RC5
TTL
T0CKI
ST
CWG1A

Timer0 clock input.
PWM1
RC6
TTL
CMOS PWM output.
AN8
AN
A/D Channel input.
SS
ST
Slave Select input.
PWM2
RC7
TTL
CMOS PWM output.

AN9
AN
SDO
VDD
VDD
Power
Positive supply.
VSS
VSS
Power
Ground reference.
VUSB3V3
Power
VUSB3V3
A/D Channel input.

OD = Open Drain
HV = High Voltage
XTAL = Crystal
levels
DS41639A-page 20
Preliminary
PIC16(L)F1454/5/9
2.0
ENHANCED MID-RANGE CPU
Relative Addressing modes are available. Two File

Select Registers (FSRs) provide the ability to read
program and data memory.
This family of devices contain an enhanced mid-range

8-bit CPU core. The CPU has 49 instructions. Interrupt
capability includes automatic context saving. The
hardware stack is 16 levels deep and has Overflow and
Underflow Reset capability. Direct, Indirect, and
FIGURE 2-1:
Automatic Interrupt Context Saving

16-level Stack with Overflow and Underflow
File Select Registers
Instruction Set
CORE BLOCK DIAGRAM
15
Configuration
15
MUX
Flash
Program
Memory
Program
Bus
16-Level
8 Level Stack
Stack
(13-bit)
(15-bit)
14
Instruction
Instruction Reg
reg
Data Bus
Program Counter
RAM
Program Memory
Read (PMR)
12
RAM Addr
Addr MUX
Indirect
Addr
12
12
Direct Addr 7
5
BSR
FSR Reg
reg
15
FSR0reg
Reg
FSR
FSR1
Reg
FSR reg
15
STATUS Reg
reg
STATUS
8
3
OSC1/CLKIN
OSC2/CLKOUT
Instruction
Decodeand
&
Decode
Control
Timing
Generation
Internal
Oscillator
Block
MUX
Power-up
Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
VDD
ALU
8
W Reg
VSS
Preliminary
DS41639A-page 21
PIC16(L)F1454/5/9
2.1
Automatic Interrupt Context

Saving
During interrupts, certain registers are automatically

saved in shadow registers and restored when returning
from the interrupt. This saves stack space and user
code. See Section 8.5 Automatic Context Saving,
for more information.
2.2
16-Level Stack with Overflow and

Underflow
These devices have an external stack memory 15 bits

wide and 16 words deep. A Stack Overflow or Underflow will set the appropriate bit (STKOVF or STKUNF)
in the PCON register, and if enabled will cause a software Reset. See section Section 3.5 Stack for more
details.
2.3
File Select Registers
There are two 16-bit File Select Registers (FSR). FSRs

can access all file registers and program memory,
which allows one Data Pointer for all memory. When an
FSR points to program memory, there is one additional
instruction cycle in instructions using INDF to allow the
data to be fetched. General purpose memory can now
also be addressed linearly, providing the ability to
access contiguous data larger than 80 bytes. There are
also new instructions to support the FSRs. See
Section 3.6 Indirect Addressing for more details.
2.4
Instruction Set
There are 49 instructions for the enhanced mid-range

CPU to support the features of the CPU. See
Section 28.0 Instruction Set Summary for more
details.
DS41639A-page 22
Preliminary
PIC16(L)F1454/5/9
3.0
MEMORY ORGANIZATION
These devices contain the following types of memory:

Program Memory
- Configuration Words
- Device ID
- User ID
- Flash Program Memory
Data Memory
- Core Registers
- Special Function Registers
- Dual-Port General Purpose RAM
- General Purpose RAM
- Common RAM
TABLE 3-1:
The following features are associated with access and

control of program memory and data memory:
PCL and PCLATH
Stack
Indirect Addressing
3.1
Program Memory Organization
The enhanced mid-range core has a 15-bit program

counter capable of addressing a 32K x 14 program
memory space. Table 3-1 shows the memory sizes
implemented. Accessing a location above these
boundaries will cause a wrap-around within the
implemented memory space. The Reset vector is at
0000h and the interrupt vector is at 0004h (See
Figure 3-1).
DEVICE SIZES AND ADDRESSES

Program Memory
Space (Words)
Last Program Memory

Address
High-Endurance Flash
Memory Address Range (1)
PIC16F1454
PIC16LF1454
8,192
1FFFh
1F80h-1FFFh
PIC16F1455
PIC16LF1455
8,192
1FFFh
1F80h-1FFFh
PIC16F1459
PIC16LF1459
8,192
1FFFh
1F80h-1FFFh
Device
Note 1: High-endurance Flash applies to low byte of each address in the range.
Preliminary
DS41639A-page 23
PIC16(L)F1454/5/9
FIGURE 3-1:
PROGRAM MEMORY MAP

AND STACK FOR
PIC16(L)F1454/5/9
PC<14:0>
CALL, CALLW
RETURN, RETLW
Interrupt, RETFIE
15
3.1.1
There are two methods of accessing constants in program memory. The first method is to use tables of
RETLW instructions. The second method is to set an
FSR to point to the program memory.
3.1.1.1
The RETLW instruction can be used to provide access

to tables of constants. The recommended way to create
such a table is shown in Example 3-1.
Stack Level 15
EXAMPLE 3-1:
Reset Vector
0000h
Interrupt Vector
0004h
0005h
constants
BRW
RETLW
RETLW
RETLW
RETLW
07FFh
0800h
Page 1
0FFFh
1000h
Page 2
Page 3
Rollover to Page 0
Rollover to Page 3
DS41639A-page 24
RETLW Instruction
Stack Level 0
Stack Level 1
Page 0
On-chip
Program
Memory
READING PROGRAM MEMORY AS

DATA
17FFh
1800h
1FFFh
2000h
DATA0
DATA1
DATA2
DATA3
RETLW INSTRUCTION
;Add Index in W to
;program counter to
;select data
;Index0 data
;Index1 data
my_function
; LOTS OF CODE
MOVLW
DATA_INDEX
call constants
; THE CONSTANT IS IN W
The BRW instruction makes this type of table very simple to implement. If your code must remain portable
with previous generations of microcontrollers, then the
BRW instruction is not available so the older table read
method must be used.
7FFFh
Preliminary
PIC16(L)F1454/5/9
3.1.1.2
Indirect Read with FSR
The program memory can be accessed as data by setting bit 7 of the FSRxH register and reading the matching INDFx register. The MOVIW instruction will place the
lower eight bits of the addressed word in the W register.
Writes to the program memory cannot be performed via
the INDF registers. Instructions that access the program memory via the FSR require one extra instruction
cycle to complete. Example 3-2 demonstrates accessing the program memory via an FSR.
The High directive will set bit<7> if a label points to a
location in program memory.
EXAMPLE 3-2:
ACCESSING PROGRAM
MEMORY VIA FSR
constants
RETLW DATA0
;Index0 data
RETLW DATA1
;Index1 data
RETLW DATA2
RETLW DATA3
my_function
; LOTS OF CODE
MOVLW
LOW constants
MOVWF
FSR1L
MOVLW
HIGH constants
MOVWF
FSR1H
MOVIW
0[FSR1]
;THE PROGRAM MEMORY IS IN W
Preliminary
DS41639A-page 25
PIC16(L)F1454/5/9
3.2
Data Memory Organization
3.2.1
The data memory is partitioned in 32 memory banks

with 128 bytes in a bank. Each bank consists of
(Figure 3-2):
12 core registers
20 Special Function Registers (SFR)
Up to 80 bytes of General Purpose RAM (GPR)
Up to 80 bytes of Dual-Port General Purpose
RAM (DPR)
16 bytes of common RAM
The core registers contain the registers that directly

affect the basic operation. The core registers occupy
the first 12 addresses of every data memory bank
(addresses x00h/x08h through x0Bh/x8Bh). These
registers are listed below in Table 3-2. For detailed
information, see Table 3-11.
TABLE 3-2:
The active bank is selected by writing the bank number

into the Bank Select Register (BSR). Unimplemented
memory will read as 0. All data memory can be
accessed either directly (via instructions that use the
file registers) or indirectly via the two File Select
Registers (FSR). See Section 3.6 Indirect
Addressing for more information.
Data memory uses a 12-bit address. The upper 7-bits
of the address define the Bank address and the lower
5-bits select the registers/RAM in that bank.
DS41639A-page 26
CORE REGISTERS
Preliminary
CORE REGISTERS
Addresses
BANKx
x00h or x80h
x01h or x81h
x02h or x82h
x03h or x83h
x04h or x84h
x05h or x85h
x06h or x86h
x07h or x87h
x08h or x88h
x09h or x89h
x0Ah or x8Ah
x0Bh or x8Bh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
PIC16(L)F1454/5/9
3.2.1.1
STATUS Register
The STATUS register, shown in Register 3-1, contains:

the arithmetic status of the ALU
the Reset status
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
3.3
For example, CLRF STATUS will clear the upper three

bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not
affecting any Status bits (Refer to Section 28.0
Instruction Set Summary).
Note 1: The C and DC bits operate as Borrow
and Digit Borrow out bits, respectively, in
subtraction.
Register Definitions: Status
REGISTER 3-1:
U-0
STATUS: STATUS REGISTER

U-0
U-0
R-1/q
TO
R-1/q
PD
R/W-0/u
R/W-0/u
R/W-0/u
DC(1)
C(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as 0
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set
0 = Bit is cleared
q = Value depends on condition
bit 7-5
Unimplemented: Read as 0
bit 4
TO: Time-Out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 3
PD: Power-Down bit

1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0
C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)

1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1:
For Borrow, the polarity is reversed. A subtraction is executed by adding the twos complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.
Preliminary
DS41639A-page 27
PIC16(L)F1454/5/9
3.3.1
SPECIAL FUNCTION REGISTER
3.3.3
The Special Function Registers are registers used by

the application to control the desired operation of
peripheral functions in the device. The Special Function
Registers occupy the 20 bytes after the core registers of
every data memory bank (addresses x0Ch/x8Ch
through x1Fh/x9Fh). The registers associated with the
operation of the peripherals are described in the appropriate peripheral chapter of this data sheet.
3.3.2
GENERAL PURPOSE RAM
There are up to 80 bytes of GPR in each data memory

bank. The Special Function Registers occupy the 20
bytes after the core registers of every data memory
bank (addresses x0Ch/x8Ch through x1Fh/x9Fh).
3.3.2.1
Linear Access to GPR
The general purpose RAM can be accessed in a

non-banked method via the FSRs. This can simplify
access to large memory structures. See Section 3.6.2
Linear Data Memory for more information.
Refer to Table 3-3 for Dual Port and USB addressing
information.
TABLE 3-3:
DUAL-PORT RAM
Part of the data memory is mapped to a special dual

access RAM. When the USB module is disabled, the
GPRs in these banks are used like any other GPR in
the data memory space.
When the USB module is enabled, the memory in these
banks is allocated as buffer RAM for USB operation.
This area is shared between the microcontroller core
and the USB Serial Interface Engine (SIE) and is used
to transfer data directly between the two.
It is theoretically possible to use the areas of USB RAM
that are not allocated as USB buffers for normal
scratchpad memory or other variable storage. In practice,
the dynamic nature of buffer allocation makes this risky at
best. Additional information on USB RAM and buffer
operation is provided in Section 26.0 Universal Serial
Bus (USB).
3.3.4
COMMON RAM
There are 16 bytes of common RAM accessible from all

banks.
DUAL PORT RAM ADDRESSING

Port 0
Port 1
CPU Banked Address
CPU Linear Address
Note 1:
USB Banked Address
USB Linear Address
020 - 06F
2000 - 204F
020 - 06F
2000 - 204F
0A0 - 0EF
2050 - 209F
0A0 - 0EF
2050 - 209F
120 - 16F
20A0 - 20EF
120 - 16F
20A0 - 20EF
1A0 - 1EF
20F0 - 213F
1A0 - 1EF
20F0 - 213F
220 - 26F
2140 - 218F
220 - 26F
2140 - 218F
2A0 - 2EF
2190 - 21DF
2A0 - 2EF
2190 - 21DF
320 - 32F
21E0 - 21EF
320 - 32F
21E0 - 21EF
370 - 37F
(1)
370 - 37F
(1)
Accessible from banked memory only.
DS41639A-page 28
Preliminary
PIC16(L)F1454/5/9
FIGURE 3-2:
7-bit Bank Offset
BANKED MEMORY
PARTITIONING
3.3.5
DEVICE MEMORY MAPS
The memory maps for PIC16(L)F1454/5/9 are as

shown in Table 3-8 and Table 3-9.
Memory Region
00h
0Bh
0Ch
Core Registers
(12 bytes)
Special Function Registers

(20 bytes maximum)
1Fh
20h
(1)
Dual Port RAM

(80 bytes maximum)
OR
General Purpose RAM
(80 bytes maximum)
6Fh
70h
Common RAM
(16 bytes)
7Fh
Note 1:
If the USB module is disabled, data

memory is GPR. If enabled, data
memory can be DPR. Refer to Memory Map for RAM type details.
Preliminary
DS41639A-page 29
PIC16(L)F1454 MEMORY MAP, BANK 0-7
BANK 0
000h
BANK 1
080h
Core Registers
(Table 3-2)
Preliminary
00Bh
00Ch
00Dh
00Eh
00Fh
010h
011h
012h
013h
014h
015h
016h
017h
018h
019h
01Ah
01Bh
01Ch
01Dh
01Eh
01Fh
020h
PORTA
PORTC
PIR1
PIR2
TMR0
TMR1L
TMR1H
T1CON
T1GCON
TMR2
PR2
T2CON
Core Registers
(Table 3-2)
08Bh
08Ch
08Dh
08Eh
08Fh
090h
091h
092h
093h
094h
095h
096h
097h
098h
099h
09Ah
09Bh
09Ch
09Dh
09Eh
09Fh
0A0h
Dual-Port
General
Purpose
Register
80 Bytes
Dual-Port
Common RAM
07Fh
Legend:
TRISA
TRISC
PIE1
PIE2
OPTION_REG
PCON
WDTCON
OSCTUNE
OSCCON
OSCSTAT
0FFh
Common RAM
(Accesses
70h 7Fh)
BANK 3
180h
Core Registers
(Table 3-2)
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
120h
Dual-Port
General
Purpose
Register
80 Bytes
0EFh
0F0h
06Fh
070h
BANK 2
100h
LATA
LATC
BORCON
APFCON
Core Registers
(Table 3-2)
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
1A0h
Dual-Port
General
Purpose
Register
80 Bytes
16Fh
170h
17Fh
Common RAM
(Accesses
70h 7Fh)
= Unimplemented data memory locations, read as 0.
BANK 4
200h
PMADRL
PMADRH
PMDATL
PMDATH
PMCON1
PMCON2
VREGCON
RCREG
TXREG
SPBRG
SPBRGH
RCSTA
TXSTA
BAUDCON
Core Registers
(Table 3-2)
20Bh
20Ch
20Dh
20Eh
20Fh
210h
211h
212h
213h
214h
215h
216h
217h
218h
219h
21Ah
21Bh
21Ch
21Dh
21Eh
21Fh
220h
Dual-Port
General
Purpose
Register
80 Bytes
1EFh
1F0h
1FFh
Common RAM
(Accesses
70h 7Fh)
BANK 5
280h
WPUA
SSP1BUF
SSP1ADD
SSP1MSK
SSP1STAT
SSP1CON1
SSP1CON2
SSP1CON3
Core Registers
(Table 3-2)
28Bh
28Ch
28Dh
28Eh
28Fh
290h
291h
292h
293h
294h
295h
296h
297h
298h
299h
29Ah
29Bh
29Ch
29Dh
29Eh
29Fh
2A0h
Dual-Port
General
Purpose
Register
80 Bytes
26Fh
270h
27Fh
Common RAM
(Accesses
70h 7Fh)
BANK 6
300h
Dual-Port
General
Purpose
Register
80 Bytes
2EFh
2F0h
2FFh
Common RAM
(Accesses
70h 7Fh)
BANK 7
380h
Core Registers
(Table 3-2)
30Bh
30Ch
30Dh
30Eh
30Fh
310h
311h
312h
313h
314h
315h
316h
317h
318h
319h
31Ah
31Bh
31Ch
31Dh
31Eh
31Fh
320h
32Fh
330h
36Fh
370h
37Fh
Dual-Port
General
Purpose
Register
16Bytes
General
Purpose
Register
64 Bytes
Common RAM
(Accesses
70h 7Fh)
Core Registers
(Table 3-2)
38Bh
38Ch
38Dh
38Eh
38Fh
390h
391h
392h
393h
394h
395h
396h
397h
398h
399h
39Ah
39Bh
39Ch
39Dh
39Eh
39Fh
3A0h
IOCAP
IOCAN
IOCAF
CLKRCON
CRCON
General
Purpose
Register
80 Bytes
3EFh
3F0h
3FFh
Common RAM
(Accesses
70h 7Fh)
PIC16(L)F1454/5/9
DS41639A-page 30
TABLE 3-4:
TABLE 3-5:
BANK 0
000h
BANK 1
080h
Core Registers
(Table 3-2)
Preliminary
00Bh
00Ch
00Dh
00Eh
00Fh
010h
011h
012h
013h
014h
015h
016h
017h
018h
019h
01Ah
01Bh
01Ch
01Dh
01Eh
01Fh
020h
PORTA
PORTC
PIR1
PIR2
TMR0
TMR1L
TMR1H
T1CON
T1GCON
TMR2
PR2
T2CON
Core Registers
(Table 3-2)
08Bh
08Ch
08Dh
08Eh
08Fh
090h
091h
092h
093h
094h
095h
096h
097h
098h
099h
09Ah
09Bh
09Ch
09Dh
09Eh
09Fh
0A0h
Legend:
ADCON0
ADCON1
ADCON2
Core Registers
(Table 3-2)
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
120h
Dual-Port
General
Purpose
Register
80 Bytes
0EFh
0F0h
Dual-Port
Common RAM
07Fh
TRISA
TRISC
PIE1
PIE2
OPTION_REG
PCON
WDTCON
OSCTUNE
OSCCON
OSCSTAT
ADRESL
ADRESH
0FFh
Common RAM
(Accesses
70h 7Fh)
BANK 3
180h
LATA
LATC
CM1CON0
CM1CON1
CM2CON0
CM2CON1
CMOUT
BORCON
FVRCON
DACCON0
DACCON1
APFCON
Core Registers
(Table 3-2)
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
1A0h
Dual-Port
General
Purpose
Register
80 Bytes
16Fh
170h
17Fh
Common RAM
(Accesses
70h 7Fh)
BANK 4
200h
ANSELA
ANSELC
PMADRL
PMADRH
PMDATL
PMDATH
PMCON1
PMCON2
VREGCON
RCREG
TXREG
SPBRG
SPBRGH
RCSTA
TXSTA
BAUDCON
Core Registers
(Table 3-2)
20Bh
20Ch
20Dh
20Eh
20Fh
210h
211h
212h
213h
214h
215h
216h
217h
218h
219h
21Ah
21Bh
21Ch
21Dh
21Eh
21Fh
220h
Dual-Port
General
Purpose
Register
80 Bytes
1EFh
1F0h
1FFh
Common RAM
(Accesses
70h 7Fh)
BANK 5
280h
WPUA
SSP1BUF
SSP1ADD
SSP1MSK
SSP1STAT
SSP1CON1
SSP1CON2
SSP1CON3
Core Registers
(Table 3-2)
28Bh
28Ch
28Dh
28Eh
28Fh
290h
291h
292h
293h
294h
295h
296h
297h
298h
299h
29Ah
29Bh
29Ch
29Dh
29Eh
29Fh
2A0h
Dual-Port
General
Purpose
Register
80 Bytes
26Fh
270h
27Fh
Common RAM
(Accesses
70h 7Fh)
BANK 6
300h
Dual-Port
General
Purpose
Register
80 Bytes
2EFh
2F0h
2FFh
Common RAM
(Accesses
70h 7Fh)
BANK 7
380h
Core Registers
(Table 3-2)
30Bh
30Ch
30Dh
30Eh
30Fh
310h
311h
312h
313h
314h
315h
316h
317h
318h
319h
31Ah
31Bh
31Ch
31Dh
31Eh
31Fh
320h
32Fh
330h
36Fh
370h
37Fh
Dual-Port
General
Purpose
Register
16Bytes
General
Purpose
Register
64 Bytes
Common RAM
(Accesses
70h 7Fh)
Core Registers
(Table 3-2)
38Bh
38Ch
38Dh
38Eh
38Fh
390h
391h
392h
393h
394h
395h
396h
397h
398h
399h
39Ah
39Bh
39Ch
39Dh
39Eh
39Fh
3A0h
IOCAP
IOCAN
IOCAF
CLKRCON
CRCON
General
Purpose
Register
80 Bytes
3EFh
3F0h
3FFh
Common RAM
(Accesses
70h 7Fh)
DS41639A-page 31
PIC16(L)F1454/5/9
Dual-Port
General
Purpose
Register
80 Bytes
06Fh
070h
BANK 2
100h
BANK 0
000h
BANK 1
080h
Core Registers
(Table 3-2)
Preliminary
00Bh
00Ch
00Dh
00Eh
00Fh
010h
011h
012h
013h
014h
015h
016h
017h
018h
019h
01Ah
01Bh
01Ch
01Dh
01Eh
01Fh
020h
PORTA
PORTB
PORTC
PIR1
PIR2
TMR0
TMR1L
TMR1H
T1CON
T1GCON
TMR2
PR2
T2CON
Core Registers
(Table 3-2)
08Bh
08Ch
08Dh
08Eh
08Fh
090h
091h
092h
093h
094h
095h
096h
097h
098h
099h
09Ah
09Bh
09Ch
09Dh
09Eh
09Fh
0A0h
Dual-Port
General
Purpose
Register
80 Bytes
06Fh
070h
Legend:
TRISA
TRISB
TRISC
PIE1
PIE2
OPTION_REG
PCON
WDTCON
OSCTUNE
OSCCON
OSCSTAT
ADRESL
ADRESH
ADCON0
ADCON1
ADCON2
0EFh
0F0h
0FFh
Common RAM
(Accesses
70h 7Fh)
BANK 3
180h
Core Registers
(Table 3-2)
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
120h
Dual-Port
General
Purpose
Register
80 Bytes
Dual-Port
Common RAM
07Fh
BANK 2
100h
LATA
LATB
LATC
CM1CON0
CM1CON1
CM2CON0
CM2CON1
CMOUT
BORCON
FVRCON
DACCON0
DACCON1
APFCON
Core Registers
(Table 3-2)
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
1A0h
Dual-Port
General
Purpose
Register
80 Bytes
16Fh
170h
17Fh
Common RAM
(Accesses
70h 7Fh)
BANK 4
200h
ANSELA
ANSELB
ANSELC
PMADRL
PMADRH
PMDATL
PMDATH
PMCON1
PMCON2
VREGCON
RCREG
TXREG
SPBRG
SPBRGH
RCSTA
TXSTA
BAUDCON
Core Registers
(Table 3-2)
20Bh
20Ch
20Dh
20Eh
20Fh
210h
211h
212h
213h
214h
215h
216h
217h
218h
219h
21Ah
21Bh
21Ch
21Dh
21Eh
21Fh
220h
Dual-Port
General
Purpose
Register
80 Bytes
1EFh
1F0h
1FFh
Common RAM
(Accesses
70h 7Fh)
BANK 5
280h
WPUA
WPUB
SSP1BUF
SSP1ADD
SSP1MSK
SSP1STAT
SSP1CON1
SSP1CON2
SSP1CON3
Core Registers
(Table 3-2)
28Bh
28Ch
28Dh
28Eh
28Fh
290h
291h
292h
293h
294h
295h
296h
297h
298h
299h
29Ah
29Bh
29Ch
29Dh
29Eh
29Fh
2A0h
Dual-Port
General
Purpose
Register
80 Bytes
26Fh
270h
27Fh
Common RAM
(Accesses
70h 7Fh)
BANK 6
300h
Dual-Port
General
Purpose
Register
80 Bytes
2EFh
2F0h
2FFh
Common RAM
(Accesses
70h 7Fh)
BANK 7
380h
Core Registers
(Table 3-2)
30Bh
30Ch
30Dh
30Eh
30Fh
310h
311h
312h
313h
314h
315h
316h
317h
318h
319h
31Ah
31Bh
31Ch
31Dh
31Eh
31Fh
320h
32Fh
330h
36Fh
370h
37Fh
Dual-Port
General
Purpose
Register
16Bytes
General
Purpose
Register
64 Bytes
Common RAM
(Accesses
70h 7Fh)
Core Registers
(Table 3-2)
38Bh
38Ch
38Dh
38Eh
38Fh
390h
391h
392h
393h
394h
395h
396h
397h
398h
399h
39Ah
39Bh
39Ch
39Dh
39Eh
39Fh
3A0h
IOCAP
IOCAN
IOCAF
IOCBP
IOCBN
IOCBF
CLKRCON
CRCON
General
Purpose
Register
80 Bytes
3EFh
3F0h
3FFh
Common RAM
(Accesses
70h 7Fh)
PIC16(L)F1454/5/9
DS41639A-page 32
TABLE 3-6:
TABLE 3-7:
BANK 8
400h
BANK 9
480h
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Preliminary
40Bh
40Ch
40Dh
40Eh
40Fh
410h
411h
412h
413h
414h
415h
416h
417h
418h
419h
41Ah
41Bh
41Ch
41Dh
41Eh
41Fh
420h
48Bh
48Ch
48Dh
48Eh
48Fh
490h
491h
492h
493h
494h
495h
496h
497h
498h
499h
49Ah
49Bh
49Ch
49Dh
49Eh
49Fh
4A0h
General
Purpose
Register
80 Bytes
Common RAM
(Accesses
70h 7Fh)
47Fh
4FFh
BANK 16
Common RAM
(Accesses
70h 7Fh)
DS41639A-page 33
86Fh
870h
87Fh
Legend:
Common RAM
(Accesses
70h 7Fh)
56Fh
570h
57Fh
8FFh
General
Purpose
Register
80 Bytes
5EFh
5F0h
5FFh
64Fh
650h
66Fh
670h
67Fh
9FFh
Unimplemented
Read as 0
Common RAM
(Accesses
70h 7Fh)
Common RAM
(Accesses
70h 7Fh)
68Bh
68Ch
68Dh
68Eh
68Fh
690h
691h
692h
693h
694h
695h
696h
697h
698h
699h
69Ah
69Bh
69Ch
69Dh
69Eh
69Fh
6A0h
6EFh
6F0h
6FFh
76Fh
770h
77Fh
78Bh
78Ch
78Dh
78Eh
78Fh
790h
791h
792h
793h
794h
795h
796h
797h
798h
799h
79Ah
79Bh
79Ch
79Dh
79Eh
79Fh
7A0h
7EFh
7F0h
7FFh
BANK 23
Core Registers
(Table 3-2)
B8Bh
B8Ch
Unimplemented
Read as 0
B7Fh
Common RAM
(Accesses
70h 7Fh)
B80h
Core Registers
(Table 3-2)
B6Fh
B70h
Unimplemented
Read as 0
BANK 22
Unimplemented
Read as 0
AFFh
Common RAM
(Accesses
70h 7Fh)
B0Bh
B0Ch
Common RAM
(Accesses
70h 7Fh)
Core Registers
(Table 3-2)
Unimplemented
Read as 0
Core Registers
(Table 3-2)
AEFh
AF0h
B00h
A8Bh
A8Ch
Common RAM
(Accesses
70h 7Fh)
70Bh
70Ch
70Dh
70Eh
70Fh
710h
711h
712h
713h
714h
715h
716h
717h
718h
719h
71Ah
71Bh
71Ch
71Dh
71Eh
71Fh
720h
BANK 21
Unimplemented
Read as 0
A7Fh
Common RAM
(Accesses
70h 7Fh)
BANK 15
780h
Core Registers
(Table 3-2)
Unimplemented
Read as 0
Core Registers
(Table 3-2)
A6Fh
A70h
A80h
A0Bh
A0Ch
BANK 14
700h
Core Registers
(Table 3-2)
BANK 20
Unimplemented
Read as 0
9EFh
9F0h
PWM1DCL
PWM1DCH
PWM1CON
PWM2DCL
PWM2DCH
PWM2CON
General
Purpose
Register
48 Bytes
A00h
98Bh
98Ch
Common RAM
(Accesses
70h 7Fh)
60Bh
60Ch
60Dh
60Eh
60Fh
610h
611h
612h
613h
614h
615h
616h
617h
618h
619h
61Ah
61Bh
61Ch
61Dh
61Eh
61Fh
620h
Core Registers
(Table 3-2)
Unimplemented
Read as 0
97Fh
Common RAM
(Accesses
70h 7Fh)
BANK 13
680h
Core Registers
(Table 3-2)
BANK 19
Core Registers
(Table 3-2)
96Fh
970h
980h
90Bh
90Ch
Common RAM
(Accesses
70h 7Fh)
58Bh
58Ch
58Dh
58Eh
58Fh
590h
591h
592h
593h
594h
595h
596h
597h
598h
599h
59Ah
59Bh
59Ch
59Dh
59Eh
59Fh
5A0h
BANK 18
Unimplemented
Read as 0
8EFh
8F0h
Common RAM
(Accesses
70h 7Fh)
900h
88Bh
88Ch
Unimplemented
Read as 0
BANK 12
600h
Core Registers
(Table 3-2)
General
Purpose
Register
80 Bytes
Core Registers
(Table 3-2)
Core Registers
(Table 3-2 )
80Bh
80Ch
50Bh
50Ch
50Dh
50Eh
50Fh
510h
511h
512h
513h
514h
515h
516h
517h
518h
519h
51Ah
51Bh
51Ch
51Dh
51Eh
51Fh
520h
BANK 17
880h
800h
Core Registers
(Table 3-2)
General
Purpose
Register
80 Bytes
4EFh
4F0h
BANK 11
580h
Common RAM
(Accesses
70h 7Fh)
Unimplemented
Read as 0
BEFh
BF0h
BFFh
Common RAM
(Accesses
70h 7Fh)
PIC16(L)F1454/5/9
46Fh
470h
BANK 10
500h
PIC16(L)F1455/9 MEMORY MAP, BANK 8-23
BANK 8
400h
BANK 9
480h
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Preliminary
40Bh
40Ch
40Dh
40Eh
40Fh
410h
411h
412h
413h
414h
415h
416h
417h
418h
419h
41Ah
41Bh
41Ch
41Dh
41Eh
41Fh
420h
48Bh
48Ch
48Dh
48Eh
48Fh
490h
491h
492h
493h
494h
495h
496h
497h
498h
499h
49Ah
49Bh
49Ch
49Dh
49Eh
49Fh
4A0h
General
Purpose
Register
80 Bytes
46Fh
470h
Common RAM
(Accesses
70h 7Fh)
47Fh
4EFh
4F0h
4FFh
Common RAM
(Accesses
70h 7Fh)
86Fh
870h
87Fh
Legend:
Common RAM
(Accesses
70h 7Fh)
56Fh
570h
57Fh
8FFh
General
Purpose
Register
80 Bytes
5EFh
5F0h
5FFh
64Fh
650h
66Fh
670h
67Fh
9FFh
Unimplemented
Read as 0
Common RAM
(Accesses
70h 7Fh)
Common RAM
(Accesses
70h 7Fh)
68Bh
68Ch
68Dh
68Eh
68Fh
690h
691h
692h
693h
694h
695h
696h
697h
698h
699h
69Ah
69Bh
69Ch
69Dh
69Eh
69Fh
6A0h
6EFh
6F0h
6FFh
76Fh
770h
77Fh
78Bh
78Ch
78Dh
78Eh
78Fh
790h
791h
792h
793h
794h
795h
796h
797h
798h
799h
79Ah
79Bh
79Ch
79Dh
79Eh
79Fh
7A0h
7EFh
7F0h
7FFh
BANK 23
Core Registers
(Table 3-2)
B8Bh
B8Ch
Unimplemented
Read as 0
B7Fh
Common RAM
(Accesses
70h 7Fh)
B80h
Core Registers
(Table 3-2)
B6Fh
B70h
Unimplemented
Read as 0
BANK 22
Unimplemented
Read as 0
AFFh
Common RAM
(Accesses
70h 7Fh)
B0Bh
B0Ch
Common RAM
(Accesses
70h 7Fh)
Core Registers
(Table 3-2)
Unimplemented
Read as 0
Core Registers
(Table 3-2)
AEFh
AF0h
B00h
A8Bh
A8Ch
Common RAM
(Accesses
70h 7Fh)
70Bh
70Ch
70Dh
70Eh
70Fh
710h
711h
712h
713h
714h
715h
716h
717h
718h
719h
71Ah
71Bh
71Ch
71Dh
71Eh
71Fh
720h
BANK 21
Unimplemented
Read as 0
A7Fh
Common RAM
(Accesses
70h 7Fh)
BANK 15
780h
Core Registers
(Table 3-2)
Unimplemented
Read as 0
Core Registers
(Table 3-2)
A6Fh
A70h
CWG1DBR
CWG1DBF
CWG1CON0
CWG1CON1
CWG1CON2
A80h
A0Bh
A0Ch
BANK 14
700h
Core Registers
(Table 3-2)
BANK 20
Unimplemented
Read as 0
9EFh
9F0h
PWM1DCL
PWM1DCH
PWM1CON
PWM2DCL
PWM2DCH
PWM2CON
General
Purpose
Register
48 Bytes
A00h
98Bh
98Ch
Common RAM
(Accesses
70h 7Fh)
60Bh
60Ch
60Dh
60Eh
60Fh
610h
611h
612h
613h
614h
615h
616h
617h
618h
619h
61Ah
61Bh
61Ch
61Dh
61Eh
61Fh
620h
Core Registers
(Table 3-2)
Unimplemented
Read as 0
97Fh
Common RAM
(Accesses
70h 7Fh)
BANK 13
680h
Core Registers
(Table 3-2)
BANK 19
Core Registers
(Table 3-2)
96Fh
970h
980h
90Bh
90Ch
Common RAM
(Accesses
70h 7Fh)
58Bh
58Ch
58Dh
58Eh
58Fh
590h
591h
592h
593h
594h
595h
596h
597h
598h
599h
59Ah
59Bh
59Ch
59Dh
59Eh
59Fh
5A0h
BANK 18
Unimplemented
Read as 0
8EFh
8F0h
Common RAM
(Accesses
70h 7Fh)
900h
88Bh
88Ch
Unimplemented
Read as 0
BANK 12
600h
Core Registers
(Table 3-2)
General
Purpose
Register
80 Bytes
Core Registers
(Table 3-2)
Core Registers
(Table 3-2 )
80Bh
80Ch
50Bh
50Ch
50Dh
50Eh
50Fh
510h
511h
512h
513h
514h
515h
516h
517h
518h
519h
51Ah
51Bh
51Ch
51Dh
51Eh
51Fh
520h
BANK 17
880h
BANK 11
580h
Core Registers
(Table 3-2)
General
Purpose
Register
80 Bytes
BANK 16
800h
BANK 10
500h
Common RAM
(Accesses
70h 7Fh)
Unimplemented
Read as 0
BEFh
BF0h
BFFh
Common RAM
(Accesses
70h 7Fh)
PIC16(L)F1454/5/9
DS41639A-page 34
TABLE 3-8:
TABLE 3-9:
PIC16(L)F1454/5/9 MEMORY MAP, BANK 24-31
BANK 24
C00h
BANK 25
C80h
Core Registers
(Table 3-2)
Preliminary
C0Bh
C0Ch
C0Dh
C0Eh
C0Fh
C10h
C11h
C12h
C13h
C14h
C15h
C16h
C17h
C18h
C19h
C1Ah
C1Bh
C1Ch
C1Dh
C1Eh
C1Fh
C20h
Core Registers
(Table 3-2)
C8Bh
C8Ch
C8Dh
C8Eh
C8Fh
C90h
C91h
C92h
C93h
C94h
C95h
C96h
C97h
C98h
C99h
C9Ah
C9Bh
C9Ch
C9Dh
C9Eh
C9Fh
CA0h
CFFh
Legend:
Common RAM
(Accesses
70h 7Fh)
Core Registers
(Table 3-2)
D0Bh
D0Ch
D0Dh
D0Eh
D0Fh
D10h
D11h
D12h
D13h
D14h
D15h
D16h
D17h
D18h
D19h
D1Ah
D1Bh
D1Ch
D1Dh
D1Eh
D1Fh
D20h
Unimplemented
Read as 0
CEFh
CF0h
CFFh
Common RAM
(Accesses
70h 7Fh)
BANK 27
D80h
Core Registers
(Table 3-2)
D8Bh
D8Ch
D8Dh
D8Eh
D8Fh
D90h
D91h
D92h
D93h
D94h
D95h
D96h
D97h
D98h
D99h
D9Ah
D9Bh
D9Ch
D9Dh
D9Eh
D9Fh
DA0h
Unimplemented
Read as 0
D6Fh
D70h
D7Fh
Common RAM
(Accesses
70h 7Fh)
BANK 28
E00h
Core Registers
(Table 3-2)
E0Bh
E0Ch
E0Dh
E0Eh
E0Fh
E10h
E11h
E12h
E13h
E14h
E15h
E16h
E17h
E18h
E19h
E1Ah
E1Bh
E1Ch
E1Dh
E1Eh
E1Fh
E20h
Unimplemented
Read as 0
DEFh
DF0h
DFFh
Common RAM
(Accesses
70h 7Fh)
BANK 29
E80h
Core Registers
(Table 3-2)
E8Bh
E8Ch
E8Dh
E8Eh
E8Fh
E90h
E91h
E92h
E93h
E94h
E95h
E96h
E97h
E98h
E99h
E9Ah
E9Bh
E9Ch
E9Dh
E9Eh
E9Fh
EA0h
Unimplemented
Read as 0
E6Fh
E70h
E7Fh
Common RAM
(Accesses
70h 7Fh)
BANK 30
F00h
UCON
USTAT
UIR
UCFG
UIE
UEIR
UFRMH
UFRML
UADDR
UEIE
UEP0
UEP1
UEP2
UEP3
UEP4
UEP5
UEP6
UEP7
Core Registers
(Table 3-2)
F0Bh
F0Ch
F0Dh
F0Eh
F0Fh
F10h
F11h
F12h
F13h
F14h
F15h
F16h
F17h
F18h
F19h
F1Ah
F1Bh
F1Ch
F1Dh
F1Eh
F1Fh
F20h
Unimplemented
Read as 0
EEFh
EF0h
EFFh
Common RAM
(Accesses
70h 7Fh)
BANK 31
F80h
Core Registers
(Table 3-2)
F8Bh
F8Ch
F8Dh
F8Eh
F8Fh
F90h
F91h
F92h
F93h
F94h
F95h
F96h
F97h
See Table 3-10
F98h for register mapF99h
ping details
F9Ah
F9Bh
F9Ch
F9Dh
F9Eh
F9Fh
FA0h
Unimplemented
Read as 0
F6Fh
F70h
F7Fh
Common RAM
(Accesses
70h 7Fh)
FEFh
FF0h
FFFh
Common RAM
(Accesses
70h 7Fh)
DS41639A-page 35
PIC16(L)F1454/5/9
Unimplemented
Read as 0
C6Fh
C70h
BANK 26
D00h
PIC16(L)F1454/5/9
TABLE 3-10:
PIC16(L)F1454/5/9 MEMORY
MAP, BANK 30-31
Bank 31
F8Ch
Unimplemented
Read as 0
FE3h
FE4h
FE5h
FE6h
FE7h
FE8h
FE9h
FEAh
FEBh
FECh
FEDh
FEEh
FEFh
Legend:
STATUS_SHAD
WREG_SHAD
BSR_SHAD
PCLATH_SHAD
FSR0L_SHAD
FSR0H_SHAD
FSR1L_SHAD
FSR1H_SHAD
STKPTR
TOSL
TOSH
= Unimplemented data memory locations,

read as 0.
DS41639A-page 36
Preliminary
PIC16(L)F1454/5/9
3.3.6
CORE FUNCTION REGISTERS

SUMMARY
The Core Function registers listed in Table 3-11 can be

addressed from any Bank.
TABLE 3-11:
Addr
Name
CORE FUNCTION REGISTERS SUMMARY

Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other Resets
Bank 0-31
x00h or
INDF0
x80h
Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)
xxxx xxxx
uuuu uuuu
x01h or
INDF1
x81h
Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register)
xxxx xxxx
uuuu uuuu
x02h or
PCL
x82h
Program Counter (PC) Least Significant Byte
0000 0000
0000 0000
---1 1000
---q quuu
x03h or
STATUS
x83h
TO
PD
DC
x04h or
FSR0L
x84h
Indirect Data Memory Address 0 Low Pointer
0000 0000
uuuu uuuu
x05h or
FSR0H
x85h
Indirect Data Memory Address 0 High Pointer
0000 0000
0000 0000
x06h or
FSR1L
x86h
Indirect Data Memory Address 1 Low Pointer
0000 0000
uuuu uuuu
x07h or
FSR1H
x87h
Indirect Data Memory Address 1 High Pointer
0000 0000
0000 0000
---0 0000
---0 0000
0000 0000
uuuu uuuu
-000 0000
-000 0000
0000 0000
0000 0000
x08h or
BSR
x88h
x09h or
WREG
x89h
BSR<4:0>
Working Register
x0Ah or
PCLATH
x8Ah
x0Bh or
INTCON
x8Bh
GIE
Legend:
Write Buffer for the upper 7 bits of the Program Counter

PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as 0, r = reserved.

Shaded locations are unimplemented, read as 0.
Preliminary
DS41639A-page 37
PIC16(L)F1454/5/9
TABLE 3-12:
Addres
s
SPECIAL FUNCTION REGISTER SUMMARY
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bank 0
00Ch
PORTA
00Dh
PORTB(1)
RA5
RA4
RA3
RA1
RA0
--xx x-xx --xx x-xx
RB7
RB6
RB5
RB4
xxxx ---- xxxx ----
00Eh
PORTC
RC7(1)
RC6(1)
00Fh
Unimplemented
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx xxxx xxxx
010h
Unimplemented
011h
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSP1IF
TMR2IF
TMR1IF
0000 0-00 0000 0-00
OSFIF
C2IF
C1IF
BCL1IF
USBIF
ACTIF
000- 000- 000- 000-
012h
PIR2
013h
Unimplemented
014h
Unimplemented
015h
TMR0
Holding Register for the 8-bit Timer0 Count
xxxx xxxx uuuu uuuu
016h
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Count
xxxx xxxx uuuu uuuu
017h
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Count
018h
T1CON
019h
T1GCON
01Ah
TMR2
Timer2 Module Register
01Bh
PR2
Timer2 Period Register
01Ch
T2CON
01Dh
Unimplemented
01Eh
Unimplemented
01Fh
Unimplemented
TMR1CS<1:0>
TMR1GE
T1CKPS<1:0>
T1GPOL
T1GTM
T1GSPM
T1OSCEN
T1SYNC
T1GGO/
DONE
T1GVAL
xxxx xxxx uuuu uuuu
TMR1ON
T1GSS<1:0>
0000 00-0 uuuu uu-u

0000 0x00 uuuu uxuu
0000 0000 0000 0000
1111 1111 1111 1111
T2OUTPS<3:0>
TMR2ON
T2CKPS<1:0>
-000 0000 -000 0000
Bank 1
08Ch
TRISA
(1)
TRISA5
TRISA4
(2)
(2)
(2)
--11 ---- --11 ----
08Dh
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
1111 ---- 1111 ----
08Eh
TRISC
TRISC7(1)
TRISC6(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111 1111 1111
08Fh
Unimplemented
090h
Unimplemented
091h
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSP1IE
TMR2IE
TMR1IE
0000 0-00 0000 0-00
OSFIE
C2IE
C1IE
BCL1IE
USBIE
ACTIE
000- 000- 000- 000-
092h
PIE2
093h
Unimplemented
094h
Unimplemented
095h
OPTION_REG
WPUEN
INTEDG
TMR0CS
TMR0SE
STKOVF
STKUNF
RWDT
PSA
PS<2:0>
096h
PCON
097h
WDTCON
098h
OSCTUNE
099h
OSCCON
SPLLEN
SPLLMULT
09Ah
OSCSTAT
SOSCR
PLLRDY
09Bh
ADRESL(2)
A/D Result Register Low
09Ch
ADRESH(2)
A/D Result Register High
09Dh
ADCON0(2)
09Eh
ADCON1(2)
ADFM
ADCS<2:0>
09Fh
ADCON2(2)
TRIGSEL<2:0>
RMCLR
RI
POR
WDTPS<4:0>
1111 1111 1111 1111

BOR
00-1 11qq qq-q qquu
SWDTEN
--01 0110 --01 0110
TUN<6:0>
-000 0000 -uuu uuuu
IRCF<3:0>
OSTS
HFIOFR
SCS<1:0>
LFIOFR
0011 1100 0011 1100
HFIOFS
00q0 --00 qqqq --qq

xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CHS<4:0>
GO/DONE
ADON
ADPREF<1:0>
-000 0000 -000 0000

0000 --00 0000 --00
-000 ---- -000 ----
Legend:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as 0.
Note 1:
PIC16(L)F1459 only.
2:
3:
Unimplemented, read as 1.
DS41639A-page 38
Preliminary
PIC16(L)F1454/5/9
TABLE 3-12:
Addres
s
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bank 2
10Ch
LATA
10Dh
LATB(1)
LATA5
LATA4
--xx ---- --uu ----
LATB7
LATB6
LATB5
LATB4
10Eh
LATC
xxxx ---- uuuu ----
LATC7(1)
LATC6(1)
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0
10Fh
Unimplemented
xxxx xxxx uuuu uuuu
110h
Unimplemented
111h
CM1CON0(2)
C1ON
C1OUT
112h
CM1CON1(2)
C1INTP
C1INTN
113h
CM2CON0(2)
C2ON
C2OUT
114h
CM2CON1(2)
C2INTP
C2INTN
115h
CMOUT(2)
C1OE
C1POL
C1PCH<1:0>
C2OE
C2POL
C2PCH<1:0>
C1SP
C1SYNC
C1NCH<2:0>
C2SP
C2HYS
116h
BORCON
SBOREN
BORFS
FVRCON(2)
FVREN
FVRRDY
TSEN
TSRNG
CDAFVR<1:0>
118h
DACCON0(2)
DACEN
DACOE1
DACOE2
DACPSS<1:0>
119h
DACCON1(2)
MC2OUT
0000 -000 0000 -000

0000 -100 0000 -100
MC1OUT
---- --00 ---- --00
BORRDY
10-- ---q uu-- ---u
0000 -000 0000 -000
ADFVR<1:0>
0000 -100 0000 -100
C2SYNC
C2NCH<2:0>
117h
11Ah
to
11Ch
C1HYS
0q00 0000 0q00 0000
0-00 00-- 0-00 00--
DACR<4:0>
---0 0000 ---0 0000
Unimplemented
11Dh
APFCON
CLKRSEL SDOSEL(1)
11Eh
Unimplemented
11Fh
Unimplemented
SSSEL
T1GSEL
P2SEL(1)
000- --00 000- --00
Bank 3
18Ch
ANSELA(2)
ANSA4
---1 ---- ---1 ----
18Dh
ANSELB(1)
ANSB5
ANSB4
--11 ---- --11 ----
18Eh
ANSELC(2)
ANSC7(1)
ANSC6(1)
ANSC3
ANSC2
ANSC1
ANSC0
11-- 1111 11-- 1111
18Fh
Unimplemented
190h
Unimplemented
191h
PMADRL
Flash Program Memory Address Register Low Byte
192h
PMADRH
193h
PMDATL
194h
PMDATH
195h
PMCON1
(2)
CFGS
196h
PMCON2
197h
VREGCON(1)
(2)
0000 0000 0000 0000
Flash Program Memory Address Register High Byte
1000 0000 1000 0000
Flash Program Memory Read Data Register Low Byte
xxxx xxxx uuuu uuuu
Flash Program Memory Read Data Register High Byte

LWLO
FREE
--xx xxxx --uu uuuu
WRERR
WREN
WR
RD
1000 x000 1000 q000
VREGPM
Reserved
---- --01 ---- --01
Flash Program Memory Control Register 2
0000 0000 0000 0000
198h
Unimplemented
199h
RCREG
USART Receive Data Register
0000 0000 0000 0000
19Ah
TXREG
USART Transmit Data Register
0000 0000 0000 0000
19Bh
SPBRGL
Baud Rate Generator Data Register Low
0000 0000 0000 0000
19Ch
SPBRGH
Baud Rate Generator Data Register High
19Dh
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x 0000 000x
19Eh
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
0000 0010 0000 0010
19Fh
BAUDCON
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
01-0 0-00 01-0 0-00
0000 0000 0000 0000
Legend:
Note 1:
PIC16(L)F1459 only.
2:
3:
Preliminary
DS41639A-page 39
PIC16(L)F1454/5/9
TABLE 3-12:
Addres
s
Name

Bit 7
Value on
POR, BOR
Value on all
other
Resets
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WPUA5
WPUA4
WPUA3
--11 1--- --11 1---
WPUB7
WPUB6
WPUB5
WPUB4
1111 ---- 1111 ----
Bank 4
20Ch
WPUA
20Dh
WPUB(1)
20Eh
to
210h
Unimplemented
211h
SSP1BUF
Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx uuuu uuuu
212h
SSP1ADD
ADD<7:0>
0000 0000 0000 0000
213h
SSP1MSK
MSK<7:0>
214h
SSP1STAT
SMP
CKE
D/A
215h
SSP1CON1
WCOL
SSPOV
SSPEN
CKP
216h
SSP1CON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
0000 0000 0000 0000
217h
SSP1CON3
ACKTIM
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
0000 0000 0000 0000
218h
to
21Fh
1111 1111 1111 1111

R/W
UA
BF
SSPM<3:0>
0000 0000 0000 0000

0000 0000 0000 0000
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Bank 5
28Ch
to
29Fh
Bank 6
30Ch
to
31Fh
Bank 7
38Ch
to
390h
391h
IOCAP
IOCAP5
IOCAP4
IOCAP3
IOCAP1
IOCAP0
--00 0-00 --00 0-00
392h
IOCAN
IOCAN5
IOCAN4
IOCAN3
IOCAN1
IOCAN0
--00 0-00 --00 0-00
393h
IOCAF
IOCAF5
IOCAF4
IOCAF3
IOCAF1
IOCAF0
--00 0-00 --00 0-00
394h
IOCBP(1)
IOCBP7
IOCBP6
IOCBP5
IOCBP4
0000 ---- 0000 ----
395h
IOCBN(1)
IOCBN7
IOCBN6
IOCBN5
IOCBN4
0000 ---- 0000 ----
396h
IOCBF(1)
IOCBF7
IOCBF6
IOCBF5
IOCBF4
0000 ---- 0000 ----
397h
to
399h
39Ah
CLKRCON
39Bh
ACTCON
39Ch
to
39Fh
Unimplemented
CLKREN
CLKROE
CLKRSLR
ACTEN
ACTUD
CLKRDC<1:0>
ACTSRC
ACTLOCK
CLKRDIV<2:0>
ACTORS
0011 0000 0011 0000
00-0 0-0- 00-0 0-0-
Unimplemented
Unimplemented
Unimplemented
Bank 8
40Ch
to
41Fh
Bank 9
48Ch
to
49Fh
Legend:
Note 1:
PIC16(L)F1459 only.
2:
3:
DS41639A-page 40
Preliminary
PIC16(L)F1454/5/9
TABLE 3-12:
Addres
s
Name
Value on
POR, BOR
Value on all
other
Resets
Unimplemented
Unimplemented
Unimplemented
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 10
50Ch
to
51Fh
Bank 11
58Ch
to
59Fh
Bank 12
60Ch
to
610h
611h
PWM1DCL
612h
PWM1DCH
613h
PWM1CON0
614h
PWM2DCL
615h
PWM2DCH
616h
PWM2CON0
617h
to
61Fh
PWM1DCL<7:6>
00-- ---- 00-- ----
PWM1DCH<7:0>
PWM1EN
xxxx xxxx uuuu uuuu
PWM1OE PWM1OUT PWM1POL
0000 ---- 0000 ----
00-- ---- 00-- ----
PWM2DCL<7:6>
PWM2DCH<7:0>
PWM2EN
PWM2OE PWM2OUT PWM2POL
xxxx xxxx uuuu uuuu

0000 ---- 0000 ----
Unimplemented
Unimplemented
Bank 13
68Ch
to
690h
691h
CWG1DBR(2)
CWG1DBR<5:0>
692h
CWG1DBF(2)
CWG1DBF<5:0>
693h
CWG1CON0(2)
G1EN
G1OEB
694h
CWG1CON1(2)
695h
CWG1CON2(2)
696h
to
69Fh
G1ASDLB<1:0>
G1ASE
G1ARSEN
G1OEA
G1POLB
G1ASDLA<1:0>
G1POLA
G1ASDC2
--00 0000 --00 0000

--xx xxxx --xx xxxx
G1CS0
G1IS<1:0>
G1ASDC1 G1ASDSFLT
0000 0--0 0000 0--0

0000 --00 0000 --00
00-- 0001 00-- 000-
Unimplemented
Unimplemented
Banks 14-28
x0Ch/
x8Ch
x1Fh/
x9Fh
Legend:
Note 1:
PIC16(L)F1459 only.
2:
3:
Preliminary
DS41639A-page 41
PIC16(L)F1454/5/9
TABLE 3-12:
Addres
s
Name

Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bank 29
E8Ch
Unimplemented
E8Dh
Unimplemented
E8Eh
UCON
E8Fh
USTAT
E90h
UIR
SOFIF
STALLIF
IDLEIF
E91h
UCFG
UTEYE
Reserved
SOFIE
BTSEF
E92h
UIE
E93h
UEIR
E94h
UFRMH
E95h
RESUME
SUSPND
DIR
PPBI
-xxx xxx- -uuu uuu-
TRNIF
ACTVIF
UERRIF
URSTIF
-000 0000 -000 0000
UPUEN
Reserved
FSEN
STALLIE
IDLEIE
TRNIE
ACTVIE
UERRIE
URSTIE
-000 0000 -000 0000
BTOEF
DFN8EF
CRC16EF
CRC5EF
PIDEF
0--0 -000 0--0 -000
FRM10
FRM9
FRM8
---- -xxx ---- -uuu
FRM6
FRM5
FRM4
FRM3
FRM2
FRM1
FRM0
xxxx xxxx uuuu uuuu

-000 0000 -000 0000
PPBRST
SE0
PKTDIS
USBEN
ENDP<3:0>
PPB<1:0>
-0x0 000- -0u0 000-
00-0 -000 00-0 -000
UFRML
FRM7
E96h
UADDR
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
E97h
UEIE
BTSEE
BTOEE
DFN8EE
CRC16EE
CRC5EE
PIDEE
0--0 0000 0--0 0000
E98h
UEP7
EPHSHK
EPCONDIS EPOUTEN
EPINEN
EPSTALL
---0 0000 ---0 0000
E99h
UEP6
EPHSHK
EPCONDIS EPOUTEN
EPINEN
EPSTALL
---0 0000 ---0 0000
E9Ah
UEP5
EPHSHK
EPCONDIS EPOUTEN
EPINEN
EPSTALL
---0 0000 ---0 0000
E9Bh
UEP4
EPHSHK
EPCONDIS EPOUTEN
EPINEN
EPSTALL
---0 0000 ---0 0000
E9Ch
UEP3
EPHSHK
EPCONDIS EPOUTEN
EPINEN
EPSTALL
---0 0000 ---0 0000
E9Dh
UEP2
EPHSHK
EPCONDIS EPOUTEN
EPINEN
EPSTALL
---0 0000 ---0 0000
E9Eh
UEP1
EPHSHK
EPCONDIS EPOUTEN
EPINEN
EPSTALL
---0 0000 ---0 0000
E9Fh
UEP0
EPHSHK
EPCONDIS EPOUTEN
EPINEN
EPSTALL
---0 0000 ---0 0000
Bank 30
F0Ch
F1Fh
Unimplemented
Legend:
Note 1:
PIC16(L)F1459 only.
2:
3:
DS41639A-page 42
Preliminary
PIC16(L)F1454/5/9
TABLE 3-12:
Addres
s
Name

Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bank 31
F8Ch
FE3h
FE4h
STATUS_
Unimplemented
Z_SHAD
DC_SHAD
C_SHAD
---- -xxx ---- -uuu
SHAD
FE5h
WREG_
Working Register Shadow
xxxx xxxx uuuu uuuu
SHAD
FE6h
BSR_
Bank Select Register Shadow
---x xxxx ---u uuuu
SHAD
FE7h
PCLATH_
Program Counter Latch High Register Shadow
-xxx xxxx uuuu uuuu
SHAD
FE8h
FSR0L_
Indirect Data Memory Address 0 Low Pointer Shadow
xxxx xxxx uuuu uuuu
Indirect Data Memory Address 0 High Pointer Shadow
xxxx xxxx uuuu uuuu
Indirect Data Memory Address 1 Low Pointer Shadow
xxxx xxxx uuuu uuuu
Indirect Data Memory Address 1 High Pointer Shadow
xxxx xxxx uuuu uuuu
SHAD
FE9h
FSR0H_
SHAD
FEAh
FSR1L_
SHAD
FEBh
FSR1H_
SHAD
FECh
FEDh
STKPTR
FEEh
TOSL
FEFh
TOSH
Unimplemented
Current Stack Pointer
Top-of-Stack Low byte
---1 1111 ---1 1111

xxxx xxxx uuuu uuuu
Top-of-Stack High byte
-xxx xxxx -uuu uuuu
Legend:
Note 1:
PIC16(L)F1459 only.
2:
3:
Preliminary
DS41639A-page 43
PIC16(L)F1454/5/9
3.4
PCL and PCLATH
3.4.2
The Program Counter (PC) is 15 bits wide. The low byte

comes from the PCL register, which is a readable and
writable register. The high byte (PC<14:8>) is not directly
readable or writable and comes from PCLATH. On any
Reset, the PC is cleared. Figure 3-3 shows the five
situations for the loading of the PC.
FIGURE 3-3:
14
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
PC
6
PCLATH
Instruction with
PCL as
Destination
ALU Result
14
PCH
PCL
PC
6 4
PCLATH
GOTO, CALL
PCH
PCL
PCLATH
CALLW
PCH
PCL
BRW
15
PC + W
14
PCH
PCL
PC
If using BRW, load the W register with the desired

unsigned address and execute BRW. The entire PC will
be loaded with the address PC + 1 + W.
BRA
15
PC + OPCODE <8:0>
3.4.1
BRANCHING
The branching instructions add an offset to the PC.

This allows relocatable code and code that crosses
page boundaries. There are two forms of branching,
BRW and BRA. The PC will have incremented to fetch
the next instruction in both cases. When using either
branching instruction, a PCL memory boundary may be
crossed.
PC
COMPUTED FUNCTION CALLS
A computed function CALL allows programs to maintain

tables of functions and provide another way to execute
state machines or look-up tables. When performing a
table read using a computed function CALL, care
should be exercised if the table location crosses a PCL
memory boundary (each 256-byte block).
3.4.4
14
3.4.3
The CALLW instruction enables computed calls by combining PCLATH and W to form the destination address.
A computed CALLW is accomplished by loading the W
register with the desired address and executing CALLW.
The PCL register is loaded with the value of W and
PCH is loaded with PCLATH.
OPCODE <10:0>
14
A computed GOTO is accomplished by adding an offset to

the program counter (ADDWF PCL). When performing a
table read using a computed GOTO method, care should
be exercised if the table location crosses a PCL memory
boundary (each 256-byte block). Refer to Application
Note AN556, Implementing a Table Read (DS00556).
If using the CALL instruction, the PCH<2:0> and PCL

registers are loaded with the operand of the CALL
instruction. PCH<6:3> is loaded with PCLATH<6:3>.
11
PC
COMPUTED GOTO
If using BRA, the entire PC will be loaded with PC + 1 +,

the signed value of the operand of the BRA instruction.
MODIFYING PCL
Executing any instruction with the PCL register as the

destination simultaneously causes the Program Counter PC<14:8> bits (PCH) to be replaced by the contents
of the PCLATH register. This allows the entire contents
of the program counter to be changed by writing the
desired upper seven bits to the PCLATH register. When
the lower eight bits are written to the PCL register, all
15 bits of the program counter will change to the values
contained in the PCLATH register and those being written to the PCL register.
DS41639A-page 44
Preliminary
PIC16(L)F1454/5/9
3.5
Stack
3.5.1
The stack is available through the TOSH, TOSL and

STKPTR registers. STKPTR is the current value of the
Stack Pointer. TOSH:TOSL register pair points to the
TOP of the stack. Both registers are read/writable. TOS
is split into TOSH and TOSL due to the 15-bit size of the
PC. To access the stack, adjust the value of STKPTR,
which will position TOSH:TOSL, then read/write to
TOSH:TOSL. STKPTR is five bits to allow detection of
overflow and underflow.
All devices have a 16-level x 15-bit wide hardware

stack (refer to Figures 3-4 through 3-7). The stack
space is not part of either program or data space. The
PC is PUSHed onto the stack when CALL or CALLW
instructions are executed or an interrupt causes a
branch. The stack is POPed in the event of a RETURN,
RETLW or a RETFIE instruction execution. PCLATH is
not affected by a PUSH or POP operation.
The stack operates as a circular buffer if the STVREN
bit is programmed to 0(Configuration Words). This
means that after the stack has been PUSHed sixteen
times, the seventeenth PUSH overwrites the value that
was stored from the first PUSH. The eighteenth PUSH
overwrites the second PUSH (and so on). The
STKOVF and STKUNF flag bits will be set on an Overflow/Underflow, regardless of whether the Reset is
enabled.
Note:
Care should be taken when modifying the

STKPTR while interrupts are enabled.
During normal program operation, CALL, CALLW and

Interrupts will increment STKPTR while RETLW,
RETURN, and RETFIE will decrement STKPTR. At any
time STKPTR can be inspected to see how much stack
is left. The STKPTR always points at the currently used
place on the stack. Therefore, a CALL or CALLW will
increment the STKPTR and then write the PC, and a
return will unload the PC and then decrement the
STKPTR.
Note 1: There are no instructions/mnemonics

called PUSH or POP. These are actions
that occur from the execution of the
CALL, CALLW, RETURN, RETLW and
RETFIE instructions or the vectoring to
an interrupt address.
FIGURE 3-4:
ACCESSING THE STACK
Reference Figure 3-4 through Figure 3-7 for examples

of accessing the stack.
ACCESSING THE STACK EXAMPLE 1
TOSH:TOSL
0x0F
STKPTR = 0x1F
Stack Reset Disabled

(STVREN = 0)
0x0E
0x0D
0x0C
0x0B
0x0A
Initial Stack Configuration:
0x09
After Reset, the stack is empty. The

empty stack is initialized so the Stack
Pointer is pointing at 0x1F. If the Stack
Overflow/Underflow Reset is enabled, the
TOSH/TOSL registers will return 0. If
the Stack Overflow/Underflow Reset is
disabled, the TOSH/TOSL registers will
return the contents of stack address 0x0F.
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
TOSH:TOSL
0x1F
0x0000
Preliminary
STKPTR = 0x1F
Stack Reset Enabled

(STVREN = 1)
DS41639A-page 45
PIC16(L)F1454/5/9
FIGURE 3-5:

0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
This figure shows the stack configuration

after the first CALL or a single interrupt.
If a RETURN instruction is executed, the
return address will be placed in the
Program Counter and the Stack Pointer
decremented to the empty state (0x1F).
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
TOSH:TOSL
FIGURE 3-6:
0x00
Return Address
STKPTR = 0x00
0x0F
0x0E
0x0D
0x0C
After seven CALLs or six CALLs and an

interrupt, the stack looks like the figure
on the left. A series of RETURN instructions
will repeatedly place the return addresses
into the Program Counter and pop the stack.
0x0B
0x0A
0x09
0x08
0x07
TOSH:TOSL
DS41639A-page 46
0x06
Return Address
0x05
Return Address
0x04
Return Address
0x03
Return Address
0x02
Return Address
0x01
Return Address
0x00
Return Address
Preliminary
STKPTR = 0x06
PIC16(L)F1454/5/9
FIGURE 3-7:
TOSH:TOSL
3.5.2
0x0F
Return Address
0x0E
Return Address
0x0D
Return Address
0x0C
Return Address
0x0B
Return Address
0x0A
Return Address
0x09
Return Address
0x08
Return Address
0x07
Return Address
0x06
Return Address
0x05
Return Address
0x04
Return Address
0x03
Return Address
0x02
Return Address
0x01
Return Address
0x00
Return Address
When the stack is full, the next CALL or

an interrupt will set the Stack Pointer to
0x10. This is identical to address 0x00
so the stack will wrap and overwrite the
return address at 0x00. If the Stack
Overflow/Underflow Reset is enabled, a
Reset will occur and location 0x00 will
not be overwritten.
STKPTR = 0x10
OVERFLOW/UNDERFLOW RESET
If the STVREN bit in Configuration Words is

programmed to 1, the device will be reset if the stack
is PUSHed beyond the sixteenth level or POPed
beyond the first level, setting the appropriate bits
(STKOVF or STKUNF, respectively) in the PCON
register.
3.6
Indirect Addressing
The INDFn registers are not physical registers. Any

instruction that accesses an INDFn register actually
accesses the register at the address specified by the
File Select Registers (FSR). If the FSRn address
specifies one of the two INDFn registers, the read will
return 0 and the write will not occur (though Status bits
may be affected). The FSRn register value is created
by the pair FSRnH and FSRnL.
The FSR registers form a 16-bit address that allows an
addressing space with 65536 locations. These locations
are divided into three memory regions:
Traditional Data Memory
Linear Data Memory
Program Flash Memory
Preliminary
DS41639A-page 47
PIC16(L)F1454/5/9
FIGURE 3-8:
INDIRECT ADDRESSING
0x0000
0x0000
Traditional
Data Memory
0x0FFF
0x0FFF
0x1000
Reserved
0x1FFF
0x2000
Linear
Data Memory
0x29AF
0x29B0
FSR
Address
Range
Reserved
0x7FFF
0x8000
0x0000
Program
Flash Memory
0xFFFF
Note:
0x7FFF
Not all memory regions are completely implemented. Consult device memory tables for memory limits.
DS41639A-page 48
Preliminary
PIC16(L)F1454/5/9
3.6.1
TRADITIONAL DATA MEMORY
The traditional data memory is a region from FSR

address 0x000 to FSR address 0xFFF. The addresses
correspond to the absolute addresses of all SFR, GPR,
DPR and common registers.
FIGURE 3-9:
TRADITIONAL DATA MEMORY MAP

Direct Addressing
BSR
Indirect Addressing
From Opcode
7
0
Bank Select
Location Select
0x00
FSRxH
0
FSRxL
0
Bank Select
00000 00001 00010
11111
Bank 0 Bank 1 Bank 2
Bank 31
Location Select
0x7F
Preliminary
DS41639A-page 49
PIC16(L)F1454/5/9
3.6.2
3.6.3
LINEAR DATA MEMORY
The linear data memory is the region from FSR

address 0x2000 to FSR address 0x29AF. This region is
a virtual region that points back to the 80-byte blocks of
DPR or GPR memory in all the banks.
Unimplemented memory reads as 0x00. Use of the
linear data memory region allows buffers to be larger
than 80 bytes because incrementing the FSR beyond
one bank will go directly to the DPR or GPR memory of
the next bank.
The 16 bytes of common memory are not included in
the linear data memory region.
FIGURE 3-10:
7
FSRnH
0 0 1
LINEAR DATA MEMORY

MAP
0
FSRnL
To make constant data access easier, the entire

program Flash memory is mapped to the upper half of
the FSR address space. When the MSB of FSRnH is
set, the lower 15 bits are the address in program
memory which will be accessed through INDF. Only the
lower eight bits of each memory location is accessible
via INDF. Writing to the program Flash memory cannot
be accomplished via the FSR/INDF interface. All
instructions that access program Flash memory via the
FSR/INDF interface will require one additional
instruction cycle to complete.
FIGURE 3-11:
7
1
PROGRAM FLASH MEMORY
FSRnH
PROGRAM FLASH
MEMORY MAP
0
Location Select
Location Select
0x2000
FSRnL
0x8000
0x0000
0x020
Bank 0
0x06F
0x0A0
Bank 1
0x0EF
0x120
Program
Flash
Memory
(low 8
bits)
Bank 2
0x16F
0xF20
Bank 30
0x29AF
DS41639A-page 50
0xF6F
Preliminary
0xFFFF
0x7FFF
PIC16(L)F1454/5/9
4.0
DEVICE CONFIGURATION
Device configuration consists of Configuration Words,

Code Protection and Device ID.
4.1
Configuration Words
There are several Configuration Word bits that allow

different oscillator and memory protection options.
These are implemented as Configuration Word 1 at
8007h and Configuration Word 2 at 8008h.
Note:
The DEBUG bit in Configuration Words is

managed
automatically
by
device
development tools including debuggers
and programmers. For normal device
operation, this bit should be maintained as
a '1'.
Preliminary
DS41639A-page 51
PIC16(L)F1454/5/9
4.2
Register Definitions: Configuration Words
REGISTER 4-1:
CONFIG1: CONFIGURATION WORD 1

R/P-1
R/P-1
R/P-1
FCMEN
IESO
CLKOUTEN
R/P-1
R/P-1
BOREN<1:0>
bit 13
R/P-1
R/P-1
R/P-1
CP
MCLRE
PWRTE
U-1
bit 8
R/P-1
R/P-1
R/P-1
WDTE<1:0>
R/P-1
R/P-1
FOSC<2:0>
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
0 = Bit is cleared
1 = Bit is set
-n = Value when blank or after Bulk Erase
bit 13
FCMEN: Fail-Safe Clock Monitor Enable bit

1 = Fail-Safe Clock Monitor is enabled
0 = Fail-Safe Clock Monitor is disabled
bit 12
IESO: Internal External Switchover bit

1 = Internal/External Switchover mode is enabled
0 = Internal/External Switchover mode is disabled
bit 11
CLKOUTEN: Clock Out Enable bit

1 = CLKOUT function is disabled. I/O or oscillator function on the CLKOUT pin
0 = CLKOUT function is enabled on the CLKOUT pin
bit 10-9
BOREN<1:0>: Brown-out Reset Enable bits(1)

11 = BOR enabled
10 = BOR enabled during operation and disabled in Sleep
01 = BOR controlled by SBOREN bit of the BORCON register
00 = BOR disabled
bit 8
bit 7
CP: Code Protection bit(2)

1 = Program memory code protection is disabled
0 = Program memory code protection is enabled
bit 6
MCLRE: MCLR/VPP Pin Function Select bit

If LVP bit = 1:
This bit is ignored.
If LVP bit = 0:
1 = MCLR/VPP pin function is MCLR; Weak pull-up enabled.
0 = MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of
WPUA register.
bit 5
PWRTE: Power-Up Timer Enable bit

1 = PWRT disabled
0 = PWRT enabled
bit 4-3
WDTE<1:0>: Watchdog Timer Enable bits

11 = WDT enabled
10 = WDT enabled while running and disabled in Sleep
01 = WDT controlled by the SWDTEN bit in the WDTCON register
00 = WDT disabled
DS41639A-page 52
Preliminary
PIC16(L)F1454/5/9
REGISTER 4-1:
bit 2-0
Note 1:
2:
CONFIG1: CONFIGURATION WORD 1 (CONTINUED)
FOSC<2:0>: Oscillator Selection bits

111 = ECH: External clock, High-Power mode: on CLKIN pin
110 = ECM: External clock, Medium-Power mode: on CLKIN pin
101 = ECL: External clock, Low-Power mode: on CLKIN pin
100 = INTOSC oscillator: I/O function on OSC1 pin
011 = EXTRC oscillator: RC function connected to CLKIN pin
010 = HS oscillator: High-speed crystal/resonator on OSC1 and OSC2 pins
001 = XT oscillator: Crystal/resonator on OSC1 and OSC2 pins
000 = LP oscillator: Low-power crystal on OSC1 and OSC2 pins
Enabling Brown-out Reset does not automatically enable Power-up Timer.
Once enabled (CP = 0), code-protect can only be disabled by bulk erasing the device.
Preliminary
DS41639A-page 53
PIC16(L)F1454/5/9
REGISTER 4-2:
CONFIG2: CONFIGURATION WORD 2

R/P-1
LVP
R/P-1
DEBUG
(3)
R/P-1
R/P-1
R/P-1
R/P-1
LPBOR
BORV
STVREN
PLLEN
bit 13
R/P-1
R/P-1
PLLMULT
USBLSCLK
bit 8
R/P-1
R/P-1
CPUDIV<1:0>
U-1
U-1
R/P-1
R/P-1
WRT<1:0>
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
0 = Bit is cleared
1 = Bit is set
-n = Value when blank or after Bulk Erase
bit 13
LVP: Low-Voltage Programming Enable bit(1)

1 = Low-voltage programming enabled
0 = High-voltage on MCLR must be used for programming
bit 12
DEBUG: In-Circuit Debugger Mode bit(3)

1 = In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins
0 = In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger
bit 11
LPBOR: Low-Power BOR Enable bit

1 = Low-Power Brown-out Reset is disabled
0 = Low-Power Brown-out Reset is enabled
bit 10
BORV: Brown-out Reset Voltage Selection bit(2)

1 = Brown-out Reset voltage (Vbor), low trip point selected
0 = Brown-out Reset voltage (Vbor, high trip point selected
bit 9
STVREN: Stack Overflow/Underflow Reset Enable bit

1 = Stack Overflow or Underflow will cause a Reset
0 = Stack Overflow or Underflow will not cause a Reset
bit 8
PLLEN: PLL Enable bit

1 = PLL is enabled
0 = PLL is disabled
bit 7
PLLMULT: PLL Multiplier Selection bit

1 = 3x PLL Output Frequency is selected
0 = 4x PLL Output Frequency is selected
bit 6
USBLSCLK: USB Low-Speed Clock Selection bit

1 = USB Clock divide-by 8 (48 MHz system input clock expected)
0 = USB Clock divide-by 4 (24 MHz system input clock expected)
bit 5-4
CPUDIV<1:0>: CPU System Clock Selection bits

11 = CPU system clock divided by 6
00 = No CPU system clock divide
bit 3-2
bit 1-0
WRT<1:0>: Flash Memory Self-Write Protection bits

8 kW Flash memory:
11 = Write protection off
10 = 000h to 01FFh write-protected, 0200h to 1FFFh may be modified
01 = 000h to 0FFFh write-protected, 1000h to 1FFFh may be modified
00 = 000h to 1FFFh write-protected, no addresses may be modified
Note 1:
2:
3:
The LVP bit cannot be programmed to 0 when Programming mode is entered via LVP.
See Vbor parameter for specific trip point voltages.
The DEBUG bit in Configuration Words is managed automatically by device development tools including
debuggers and programmers. For normal device operation, this bit should be maintained as a '1'.
DS41639A-page 54
Preliminary
PIC16(L)F1454/5/9
4.3
Code Protection
Code protection allows the device to be protected from

unauthorized access. Internal access to the program
memory is unaffected by any code protection setting.
4.3.1
PROGRAM MEMORY PROTECTION
The entire program memory space is protected from

external reads and writes by the CP bit in Configuration
Words. When CP = 0, external reads and writes of
program memory are inhibited and a read will return all
0s. The CPU can continue to read program memory,
regardless of the protection bit settings. Writing the
program memory is dependent upon the write
protection
setting.
See
Section 4.4
Write
Protection for more information.
4.4
Write Protection
Write protection allows the device to be protected from

unintended self-writes. Applications, such as
bootloader software, can be protected while allowing
other regions of the program memory to be modified.
The WRT<1:0> bits in Configuration Words define the
size of the program memory block that is protected.
4.5
User ID
Four memory locations (8000h-8003h) are designated as

ID locations where the user can store checksum or other
code identification numbers. These locations are
readable and writable during normal execution. See
Section 11.4 User ID, Device ID and Configuration
Word Access for more information on accessing these
memory locations. For more information on checksum
calculation, see the PIC16(L)F1454/5/9 Memory
Programming Specification (DS41620).
Preliminary
DS41639A-page 55
PIC16(L)F1454/5/9
4.6
Device ID and Revision ID
The memory location 8005h and 8006h are where the

Device ID and Revision ID are stored. See
Section 11.4 User ID, Device ID and Configuration
Word Access for more information on accessing
these memory locations.
Development tools, such as device programmers and
debuggers, may be used to read the Device ID and
Revision ID.
4.7
Register Definitions: Revision and Device
REGISTER 4-3:
DEVID: DEVICE ID REGISTER

R
DEV<13:8>
bit 13
R
bit 8
R
DEV<7:0>
bit 7
bit 0
Legend:
R = Readable bit
1 = Bit is set
bit 13-0
0 = Bit is cleared
DEV<13:0>: Device ID bits
Device
DEVICEID<13:0> Values
PIC16F1454
11 0000 0010 0000 (3020h)
PIC16LF1454
11 0000 0010 0100 (3024h)
PIC16F1455
11 0000 0010 0001 (3021h)
PIC16LF1455
11 0000 0010 0101 (3025h)
PIC16F1459
11 0000 0010 0011 (3023h)
PIC16LF1459
11 0000 0010 0111 (3027h)
REGISTER 4-4:
REVID: REVISION ID REGISTER

R
REV<13:8>
bit 13
R
bit 8
R
REV<7:0>
bit 7
bit 0
Legend:
R = Readable bit
1 = Bit is set
bit 13-0
0 = Bit is cleared
REV<13:0>: Revision ID bits
DS41639A-page 56
Preliminary
PIC16(L)F1454/5/9
5.0
OSCILLATOR MODULE (WITH

FAIL-SAFE CLOCK MONITOR)
5.1
Overview
The oscillator module has a wide variety of clock

sources and selection features that allow it to be used
in a wide range of applications while maximizing performance and minimizing power consumption. Figure 5-1
illustrates a block diagram of the oscillator module.
Clock sources can be supplied from external oscillators,
quartz crystal resonators, ceramic resonators and
Resistor-Capacitor (RC) circuits. In addition, the system
clock source can be supplied from one of two internal
oscillators, with a choice of speeds selectable via
software. Additional clock features include:
Selectable system clock source between external
or internal sources via software.
Two-Speed Start-up mode, which minimizes
latency between external oscillator start-up and
code execution.
Fail-Safe Clock Monitor (FSCM) designed to
detect a failure of the external clock source (LP,
XT, HS, EC or RC modes) and switch
automatically to the internal oscillator.
Oscillator Start-up Timer (OST) ensures stability
of crystal oscillator sources
Fast start-up oscillator allows internal circuits to
power up and stabilize before switching to the 16
MHz HFINTOSC
3x/4x selectable Phase Lock Frequency Multiplier
allows operation at 24, 32 or 48 MHz.
USB with configurable Full/Low speed operation.
The oscillator module can be configured in one of eight

clock modes.
1.
2.
3.
4.
5.
6.
7.
8.
ECL External Clock Low-Power mode

(0 MHz to 0.5 MHz)
ECM External Clock Medium-Power mode
(0.5 MHz to 4 MHz)
ECH External Clock High-Power mode
(4 MHz to 20 MHz)
LP 32 kHz Low-Power Crystal mode.
XT Medium Gain Crystal or Ceramic Resonator
Oscillator mode (up to 4 MHz)
HS High Gain Crystal or Ceramic Resonator
mode (4 MHz to 20 MHz)
RC External Resistor-Capacitor (RC).
INTOSC Internal oscillator (31 kHz to 16 MHz).
Clock Source modes are selected by the FOSC<2:0>

bits in the Configuration Words. The FOSC bits
determine the type of oscillator that will be used when
the device is first powered.
The EC clock mode relies on an external logic level
signal as the device clock source. The LP, XT, and HS
clock modes require an external crystal or resonator to
be connected to the device. Each mode is optimized for
a different frequency range. The RC clock mode
requires an external resistor and capacitor to set the
oscillator frequency.
The INTOSC internal oscillator block produces a low
and high-frequency clock source, designated
LFINTOSC and HFINTOSC. (see Internal Oscillator
Block, Figure 5-1). A wide selection of device clock
frequencies may be derived from these two clock
sources.
Preliminary
DS41639A-page 57
PIC16(L)F1454/5/9
FIGURE 5-1:
SIMPLIFIED PIC MCU CLOCK SOURCE BLOCK DIAGRAM
FOSC<2:0>
3
SPLLMULT
PLLMULT
INTOSC
CLKIN/ OSC1/
SOSCI/ T1CKI
(16 or 8 MHz)
Secondary
Oscillator
(SOSC)
SOSC_clk
Secondary Clock
IRCF<3:0>
Postscaler
HFINTOSC
Start-up
Control Logic
DS41639A-page 58
1
0
Start-Up
OSC
31 kHz
Source
CPU
Divider
Primary Clock
Active Clock
Tuning
16 MHz
Internal OSC
CPUDIV<1:0>
3x/4x PLL
Primary
Oscillator
(OSC)
CLKOUT / OSC2
SOSCO/ T1G
SPLLEN
PLLEN
FSEN
48 MHz
INTOSC
USB
Divider
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
250 kHz
125 kHz
62.5 kHz
31.25 kHz
31 kHz
LFINTOSC
6 MHz
1
0
USB
Clock
Source
USBLSCLK
Clock
Control
Sleep
2
3
LFINTOSC
Preliminary
FOSC
to
CPU and
Peripherals
SCS<1:0>
FOSC<2:0>
to WDT, PWRT
and other Modules
PIC16(L)F1454/5/9
5.2
Clock Source Types
Clock sources can be classified as external or internal.

External clock sources rely on external circuitry for the
clock source to function. Examples are: oscillator modules (EC mode), quartz crystal resonators or ceramic
resonators (LP, XT and HS modes) and Resistor-Capacitor (RC) mode circuits.
Internal clock sources are contained within the oscillator
module. The internal oscillator block has two internal
oscillators that are used to generate the internal system
clock sources: the 16 MHz High-Frequency Internal
Oscillator and the 31 kHz Low-Frequency Internal
Oscillator (LFINTOSC).
The Oscillator Start-up Timer (OST) is disabled when

EC mode is selected. Therefore, there is no delay in
operation after a Power-on Reset (POR) or wake-up
from Sleep. Because the PIC MCU design is fully
static, stopping the external clock input will have the
effect of halting the device while leaving all data intact.
Upon restarting the external clock, the device will
resume operation as if no time had elapsed.
FIGURE 5-2:
5.2.1
An external clock source can be used as the device

system clock by performing one of the following
actions:
Program the FOSC<2:0> bits in the Configuration
Words to select an external clock source that will
be used as the default system clock upon a
device Reset.
Write the SCS<1:0> bits in the OSCCON register
to switch the system clock source to:
- Secondary oscillator during run-time, or
- An external clock source determined by the
value of the FOSC bits.
See Section 5.3 CPU Clock Dividerfor more information.
5.2.1.1
EC Mode
The External Clock (EC) mode allows an externally

generated logic level signal to be the system clock
source. When operating in this mode, an external clock
source is connected to the OSC1 input.
OSC2/CLKOUT is available for general purpose I/O or
CLKOUT. Figure 5-2 shows the pin connections for EC
mode.
EC mode has three power modes to select from through
Configuration Words:
PIC MCU
FOSC/4 or I/O(1)
Note 1:
EXTERNAL CLOCK SOURCES
OSC1/CLKIN
Clock from
Ext. System
The system clock can be selected between external or

internal clock sources via the System Clock Select
(SCS) bits in the OSCCON register. See Section 5.3
CPU Clock Divider for additional information.
5.2.1.2
EXTERNAL CLOCK (EC)

MODE OPERATION
OSC2/CLKOUT
Output depends upon CLKOUTEN bit of the

Configuration Words.
LP, XT, HS Modes
The LP, XT and HS modes support the use of quartz

crystal resonators or ceramic resonators connected to
OSC1 and OSC2 (Figure 5-3). The three modes select
a low, medium or high gain setting of the internal
inverter-amplifier to support various resonator types
and speed.
LP Oscillator mode selects the lowest gain setting of the
internal inverter-amplifier. LP mode current consumption
is the least of the three modes. This mode is designed to
drive only 32.768 kHz tuning-fork type crystals (watch
crystals).
XT Oscillator mode selects the intermediate gain
setting of the internal inverter-amplifier. XT mode
current consumption is the medium of the three modes.
This mode is best suited to drive resonators with a
medium drive level specification.
HS Oscillator mode selects the highest gain setting of the
internal inverter-amplifier. HS mode current consumption
is the highest of the three modes. This mode is best
suited for resonators that require a high drive setting.
Figure 5-3 and Figure 5-4 show typical circuits for
quartz crystal and ceramic resonators, respectively.
High power, 4-20 MHz (FOSC = 111)

Medium power, 0.5-4 MHz (FOSC = 110)
Low power, 0-0.5 MHz (FOSC = 101)
Preliminary
DS41639A-page 59
PIC16(L)F1454/5/9
FIGURE 5-3:
QUARTZ CRYSTAL
OPERATION (LP, XT OR
HS MODE)
FIGURE 5-4:
CERAMIC RESONATOR
OPERATION
(XT OR HS MODE)
PIC MCU
PIC MCU
OSC1/CLKIN
C1
C1
To Internal
Logic
Quartz
Crystal
C2
OSC1/CLKIN
RS(1)
RF(2)
Sleep
RP(3)
OSC2/CLKOUT
A series resistor (RS) may be required for

quartz crystals with low drive level.
2:
The value of RF varies with the Oscillator mode

selected (typically between 2 M to 10 M.
Note 1: Quartz
crystal
characteristics
vary
according to type, package and
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application.
2: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
3: For oscillator design assistance, reference
the following Microchip Applications Notes:
DS41639A-page 60
RF(2)
C2 Ceramic
RS(1)
Resonator
Note 1:
AN826, Crystal Oscillator Basics and

Crystal Selection for rfPIC and PIC
Devices (DS00826)
AN849, Basic PIC Oscillator Design
(DS00849)
AN943, Practical PIC Oscillator
Analysis and Design (DS00943)
AN949, Making Your Oscillator Work
(DS00949)
To Internal
Logic
Note 1:
Sleep
OSC2/CLKOUT
A series resistor (RS) may be required for

ceramic resonators with low drive level.
2: The value of RF varies with the Oscillator mode

selected (typically between 2 M to 10 M.
3: An additional parallel feedback resistor (RP)
may be required for proper ceramic resonator
operation.
5.2.1.3
Oscillator Start-up Timer (OST)
If the oscillator module is configured for LP, XT or HS

modes, the Oscillator Start-up Timer (OST) counts 1024
oscillations from OSC1. This occurs following a
Power-on Reset (POR) and when the Power-up Timer
(PWRT) has expired (if configured), or a wake-up from
Sleep. During this time, the program counter does not
increment and program execution is suspended unless
either FSCM or Two-Speed Start-Up are enabled. In this
case, code will continue to execute at the selected
INTOSC frequency while the OST is counting . The OST
ensures that the oscillator circuit, using a quartz crystal
resonator or ceramic resonator, has started and is
providing a stable system clock to the oscillator module.
In order to minimize latency between external oscillator
start-up and code execution, the Two-Speed Clock
Start-up mode can be selected (see Section 5.6
Two-Speed Clock Start-up Mode).
Preliminary
PIC16(L)F1454/5/9
5.2.1.4
3x PLL or 4x PLL
The oscillator module contains a PLL that can be used

with both external and internal clock sources to provide a
system clock source. By setting the SPLLMULT bit of the
OSCCON register, 3x PLL is selected. By clearing the
SPLLMULT bit of the OSCCON register, 4x PLL is
selected. The input frequency for the PLL must fall within
specifications. See the PLL Clock Timing Specifications in
Section 29.0 Electrical Specifications.
Note 1: Quartz
crystal
characteristics
vary
according to type, package and
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application.
The PLL may be enabled for use by one of two methods:

1.
2.
Program the PLLEN bit in Configuration Words

to a 1.
Write the SPLLEN bit in the OSCCON register to
a 1. If the PLLEN bit in Configuration Words is
programmed to a 1, then the value of SPLLEN
is ignored.
HFINTOSC
(MHz)
ECH/HS
(MHz)
System
Clock (MHz)
4x
8 - 12
32 - 48
3x
16, 8
8 - 16
24 - 48
PLL
5.2.1.5
Secondary Oscillator
The secondary oscillator is a separate crystal oscillator

that is associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz
crystal connected between the SOSCO and SOSCI
device pins.
2: Always verify oscillator performance over

the VDD and temperature range that is
expected for the application.
3: For oscillator design assistance, reference
the following Microchip Applications Notes:
AN826, Crystal Oscillator Basics and
Crystal Selection for rfPIC and PIC
Devices (DS00826)
AN849, Basic PIC Oscillator Design
(DS00849)
AN943, Practical PIC Oscillator
Analysis and Design (DS00943)
AN949, Making Your Oscillator Work
(DS00949)
TB097, Interfacing a Micro Crystal
MS1V-T1K 32.768 kHz Tuning Fork
Crystal to a PIC16F690/SS (DS91097)
AN1288, Design Practices for
Low-Power External Oscillators
(DS01288)
The secondary oscillator can be used as an alternate

system clock source and can be selected during
run-time using clock switching. Refer to Section 5.3
CPU Clock Divider for more information.
FIGURE 5-5:
QUARTZ CRYSTAL
OPERATION
(SECONDARY
OSCILLATOR)
PIC MCU
SOSCI
C1
To Internal
Logic
32.768 kHz
Quartz
Crystal
C2
SOSCO
Preliminary
DS41639A-page 61
PIC16(L)F1454/5/9
5.2.1.6
External RC Mode
5.2.2
The external Resistor-Capacitor (RC) modes support

the use of an external RC circuit. This allows the
designer maximum flexibility in frequency choice while
keeping costs to a minimum when clock accuracy is not
required.
The RC circuit connects to OSC1. OSC2/CLKOUT is
available for general purpose I/O or CLKOUT. The
function of the OSC2/CLKOUT pin is determined by the
CLKOUTEN bit in Configuration Words.
Figure 5-6 shows the external RC mode connections.
FIGURE 5-6:
VDD
EXTERNAL RC MODES
Program the FOSC<2:0> bits in Configuration

Words to select the INTOSC clock source, which
will be used as the default system clock upon a
device Reset.
Write the SCS<1:0> bits in the OSCCON register
to switch the system clock source to the internal
oscillator during run-time. See Section 5.3 CPU
Clock Dividerfor more information.
The function of the OSC2/CLKOUT pin is determined

by the CLKOUTEN bit in Configuration Words.
REXT
Internal
Clock
CEXT
The internal oscillator block has two independent

oscillators that provides the internal system clock
source.
1.
VSS
FOSC/4 or I/O(1)
OSC2/CLKOUT
Recommended values: 10 k REXT 100 k, <3V

3 k REXT 100 k, 3-5V
CEXT > 20 pF, 2-5V
Note 1:
The device may be configured to use the internal oscillator block as the system clock by performing one of the
following actions:
In INTOSC mode, OSC1/CLKIN is available for general

purpose I/O. OSC2/CLKOUT is available for general
purpose I/O or CLKOUT.
PIC MCU
OSC1/CLKIN
INTERNAL CLOCK SOURCES
2.
Output depends upon CLKOUTEN bit of the

The RC oscillator frequency is a function of the supply

voltage, the resistor (REXT) and capacitor (CEXT) values
and the operating temperature. Other factors affecting
the oscillator frequency are:
threshold voltage variation
component tolerances
packaging variations in capacitance
The user also needs to take into account variation due
to tolerance of the external RC components used.
The HFINTOSC (High-Frequency Internal

Oscillator) is factory calibrated and operates at
16 MHz. The frequency of the HFINTOSC can be
user-adjusted via software using the OSCTUNE
register (Register 5-3).
The LFINTOSC (Low-Frequency Internal
Oscillator) is uncalibrated and operates at
31 kHz.
5.2.2.1
HFINTOSC
The High-Frequency Internal Oscillator (HFINTOSC) is

a factory calibrated 16 MHz internal clock source. The
frequency of the HFINTOSC can be altered via
software using the OSCTUNE register (Register 5-3).
The output of the HFINTOSC connects to a postscaler
and multiplexer (see Figure 5-1). The frequency derived
from the HFINTOSC can be selected via software using
the IRCF<3:0> bits of the OSCCON register. See
Section 5.2.2.4 Internal Oscillator Frequency
Selection for more information.
The HFINTOSC is enabled by:
Configure the IRCF<3:0> bits of the OSCCON
register for the desired HF frequency, and
FOSC<2:0> = 100, or
Set the System Clock Source (SCS) bits of the
OSCCON register to 1x.
A fast start-up oscillator allows internal circuits to
power-up and stabilize before switching to HFINTOSC.
The High-Frequency Internal Oscillator Ready bit
(HFIOFR) of the OSCSTAT register indicates when the
HFINTOSC is running.
The High-Frequency Internal Oscillator Stable bit
(HFIOFS) of the OSCSTAT register indicates when the
HFINTOSC is running within 0.5% of its final value.
DS41639A-page 62
Preliminary
PIC16(L)F1454/5/9
5.2.2.2
Internal Oscillator Frequency

Adjustment
5.2.2.4
The 16 MHz internal oscillator is factory calibrated.

This internal oscillator can be adjusted in software by
writing to the OSCTUNE register (Register 5-3). Since
all HFINTOSC clock sources are derived from the
16 MHz internal oscillator a change in the OSCTUNE
register value will apply to all HFINTOSC frequencies.
The default value of the OSCTUNE register is 0. The
value is a 7-bit twos complement number. A value of
3Fh will provide an adjustment to the maximum
frequency. A value of 40h will provide an adjustment to
the minimum frequency.
When the OSCTUNE register is modified, the oscillator
frequency will begin shifting to the new frequency. Code
execution continues during this shift. There is no
indication that the shift has occurred.
OSCTUNE does not affect the LFINTOSC frequency.
Operation of features that depend on the LFINTOSC
clock source frequency, such as the Power-up Timer
(PWRT), Watchdog Timer (WDT), Fail-Safe Clock
Monitor (FSCM) and peripherals, are not affected by the
change in frequency.
5.2.2.3
LFINTOSC
The Low-Frequency Internal Oscillator (LFINTOSC) is

an uncalibrated 31 kHz internal clock source.
The output of the LFINTOSC connects to a postscaler
and multiplexer (see Figure 5-1). Select 31 kHz, via
software, using the IRCF<3:0> bits of the OSCCON
register. See Section 5.2.2.4 Internal Oscillator
Frequency Selection for more information. The
LFINTOSC is also the frequency for the Power-up Timer
(PWRT), Watchdog Timer (WDT) and Fail-Safe Clock
Monitor (FSCM).
The LFINTOSC is enabled by selecting 31 kHz
(IRCF<3:0> bits of the OSCCON register = 000) as the
system clock source (SCS bits of the OSCCON
register = 1x), or when any of the following are
enabled:
Configure the IRCF<3:0> bits of the OSCCON
register for the desired LF frequency, and
FOSC<2:0> = 100, or
Set the System Clock Source (SCS) bits of the
OSCCON register to 1x

Selection
The system clock speed can be selected via software

using the Internal Oscillator Frequency Select bits
IRCF<3:0> of the OSCCON register.
The output of the 16 MHz HFINTOSC and 31 kHz
LFINTOSC connects to a postscaler and multiplexer
(see Figure 5-1). The Internal Oscillator Frequency
Select bits IRCF<3:0> of the OSCCON register select
the frequency output of the internal oscillators. One of
the following frequencies can be selected via software:
HFINTOSC
- 48 MHz (requires 3x PLL)
- 16 MHz
- 8 MHz
- 4 MHz
- 2 MHz
- 1 MHz
- 500 kHz (Default after Reset)
- 250 kHz
- 125 kHz
- 62.5 kHz
- 31.25 kHz
LFINTOSC
- 31 kHz
Note:
Following any Reset, the IRCF<3:0> bits

of the OSCCON register are set to 0111
and the frequency selection is set to
500 kHz. The user can modify the IRCF
bits to select a different frequency.
The IRCF<3:0> bits of the OSCCON register allow

duplicate selections for some frequencies. These duplicate choices can offer system design trade-offs. Lower
power consumption can be obtained when changing
oscillator sources for a given frequency. Faster transition times can be obtained between frequency changes
that use the same oscillator source.
Peripherals that use the LFINTOSC are:

Power-up Timer (PWRT)
Watchdog Timer (WDT)
Fail-Safe Clock Monitor (FSCM)
The Low-Frequency Internal Oscillator Ready bit
(LFIOFR) of the OSCSTAT register indicates when the
LFINTOSC is running.
Preliminary
DS41639A-page 63
PIC16(L)F1454/5/9
5.2.2.5

Selection Using the PLL
5.2.2.6
The Internal Oscillator Block can be used with the PLL

associated with the External Oscillator Block to
produce a 24 MHz, 32 MHz or 48 MHz internal system
clock source. The following settings are required to use
the PLL internal clock sources:
The FOSC bits of the Configuration Words must
be set to use the INTOSC source as the device
system clock (FOSC<2:0> = 100).
The SCS bits of the OSCCON register must be
cleared to use the clock determined by
FOSC<2:0> in Configuration Words
(SCS<1:0> = 00).
For 24 MHz or 32 MHz, the IRCF bits of the
OSCCON register must be set to the 8 MHz
HFINTOSC set to use (IRCF<3:0> = 1110).
For 48 MHz, the IRCF bits of the OSCCON register must be set to the 16 MHz HFINTOSC set to
use (IRCF<3:0> = 1111).
For 24 MHz or 48 MHz, the 3x PLL is required.
The SPLLMULT of the OSCCON register must be
set to use (SPLLMULT = 1).
For 32 MHz, the 4x PLL is required. The
SPLLMULT of the OSCCON register must be
clear to use (SPLLMULT = 0).
The SPLLEN bit of the OSCCON register must be
set to enable the PLL, or the PLLEN bit of the
Configuration Words must be programmed to a
'1'.
Note:
When using the PLLEN bit of the

Configuration Words, the PLL cannot be
disabled by software. The 8 MHz and 16
MHz HFINTOSC options will no longer be
available.
Internal Oscillator Clock Switch

Timing
When switching between the HFINTOSC and the

LFINTOSC, the new oscillator may already be shut
down to save power (see Figure 5-7). If this is the case,
there is a delay after the IRCF<3:0> bits of the
OSCCON register are modified before the frequency
selection takes place. The OSCSTAT register will
reflect the current active status of the HFINTOSC and
LFINTOSC oscillators. The sequence of a frequency
selection is as follows:
1.
2.
3.
4.
5.
6.
7.
IRCF<3:0> bits of the OSCCON register are

modified.
If the new clock is shut down, a clock start-up
delay is started.
Clock switch circuitry waits for a falling edge of
the current clock.
The current clock is held low and the clock
switch circuitry waits for a rising edge in the new
clock.
The new clock is now active.
The OSCSTAT register is updated as required.
Clock switch is complete.
See Figure 5-7 for more details.

If the internal oscillator speed is switched between two
clocks of the same source, there is no start-up delay
before the new frequency is selected. Clock switching
time delays are shown in Table 5-3.
Start-up delay specifications are located in the
oscillator tables of Section 29.0 Electrical
Specifications.
The PLL is not available for use with the internal oscillator when the SCS bits of the OSCCON register are
set to '1x'. The SCS bits must be set to '00' to use the
PLL with the internal oscillator.
DS41639A-page 64
Preliminary
PIC16(L)F1454/5/9
FIGURE 5-7:
HFINTOSC
INTERNAL OSCILLATOR SWITCH TIMING
LFINTOSC (FSCM and WDT disabled)
HFINTOSC
Start-up Time
2-cycle Sync
Running
LFINTOSC
IRCF <3:0>
System Clock
HFINTOSC
LFINTOSC (Either FSCM or WDT enabled)
HFINTOSC
2-cycle Sync
Running
LFINTOSC
IRCF <3:0>
System Clock
LFINTOSC
HFINTOSC
LFINTOSC turns off unless WDT or FSCM is enabled
LFINTOSC
Start-up Time
2-cycle Sync
Running
HFINTOSC
IRCF <3:0>
=0
System Clock
Preliminary
DS41639A-page 65
PIC16(L)F1454/5/9
5.3
CPU Clock Divider
5.4.1
For low-speed USB Operation, a 24 MHz clock is

required for the USB module. To generate the 24 MHz
clock, the following Oscillator modes are allowed:
The CPU Clock divider allows the system clock to run

at a slower speed than the Low/Full-Speed USB
module clock, while sharing the same clock source.
Only the oscillator defined by the settings of the FOSC
bits of the Configuration Words may be used with the
CPU clock divider. the CPU clock divider is controlled
by the CPUDIV<1:0> bits of the Configuration Words.
HFINTOSC with PLL

ECH mode
HS mode
Table 5-1 shows the recommended Clock mode for
low-speed operation.
Setting the CPUDIV bits will set the system clock to:
Equal the clock speed of the USB module

Half the clock speed of the USB module
One third the clock speed of the USB Module
One sixth clock speed of the USB module
5.4.2
HIGH-SPEED OPERATION
For full-speed USB operation, a 48 MHz clock is

required for the USB module. To generate the 48 MHz
clock, the following oscillator modes are allowed:
For more information on the CPU Clock Divider, see

Figure 5-1 and Configuration Words.
5.4
LOW-SPEED OPERATION
HFINTOSC with PLL

ECH mode
HS mode
USB Operation
Table 5-1 shows the recommended Clock mode for

full-speed operation.
The USB module is designed to operate in two different

modes:
Low Speed
Full Speed
To achieve the timing requirements imposed by the
USB specifications, the internal oscillator or the primary
external oscillator are required for the USB module.
The FOSC bits of the Configuration Words must be set
to INTOSC, ECH or HS mode with a clock frequency of
6, 12, or 16 MHz.
TABLE 5-1:
LOW-SPEED USB CLOCK SETTINGS
Clock Mode
Clock
Frequency
16 MHz
PLL Value
3x
USBLSCLK
CPUDIV<1:0>
System Clock
Frequency
(MHz)
11
10
01
00
8
16
24
48
11
10
01
00
4
8
12
24
11
10
01
00
8
16
24
48
11
10
01
00
8
16
24
48
11
10
01
00
4
8
12
24
HFINTOSC
8 MHz
16 MHz
ECH or HS mode
12 MHz
8 MHz
DS41639A-page 66
3x
3x
4x
3x
Preliminary
PIC16(L)F1454/5/9
TABLE 5-2:
HIGH-SPEED USB CLOCK SETTINGS
Clock Mode
HFINTOSC
Clock
Frequency
16 MHz
16 MHz
PLL Value
3x
3x
USBLSCLK
CPUDIV<1:0>
System Clock
Frequency
(MHz)
11
10
01
00
8
16
24
48
11
10
01
00
8
16
24
48
11
10
01
00
8
16
24
48
ECH or HS mode
12 MHz
4x
Preliminary
DS41639A-page 67
PIC16(L)F1454/5/9
5.5
Clock Switching
5.5.3
SECONDARY OSCILLATOR
The system clock source can be switched between

external and internal clock sources via software using
the System Clock Select (SCS) bits of the OSCCON
register. The following clock sources can be selected
using the SCS bits:
The secondary oscillator is a separate crystal oscillator

associated with the Timer1 peripheral. It is optimized
for timekeeping operations with a 32.768 kHz crystal
connected between the SOSCO and SOSCI device
pins.
Default system oscillator determined by FOSC

bits in Configuration Words
Secondary oscillator 32 kHz crystal
Internal Oscillator Block (INTOSC)
The secondary oscillator is enabled using the

T1OSCEN control bit in the T1CON register. See
Section 20.0 Timer1 Module with Gate Control for
more information about the Timer1 peripheral.
5.5.1
5.5.4
SYSTEM CLOCK SELECT (SCS)

BITS
The System Clock Select (SCS) bits of the OSCCON

register selects the system clock source that is used for
the CPU and peripherals.
When the SCS bits of the OSCCON register = 00,
the system clock source is determined by value of
the FOSC<2:0> bits in the Configuration Words.
When the SCS bits of the OSCCON register = 01,
the system clock source is the secondary
oscillator.
When the SCS bits of the OSCCON register = 1x,
the system clock source is chosen by the internal
oscillator frequency selected by the IRCF<3:0>
bits of the OSCCON register. After a Reset, the
SCS bits of the OSCCON register are always
cleared.
Note:
SECONDARY OSCILLATOR READY

(SOSCR) BIT
The user must ensure that the secondary oscillator is

ready to be used before it is selected as a system clock
source. The Secondary Oscillator Ready (SOSCR) bit
of the OSCSTAT register indicates whether the
secondary oscillator is ready to be used. After the
SOSCR bit is set, the SCS bits can be configured to
select the secondary oscillator.
Any automatic clock switch, which may

occur from Two-Speed Start-up or
Fail-Safe Clock Monitor, does not update
the SCS bits of the OSCCON register. The
user can monitor the OSTS bit of the
OSCSTAT register to determine the current
system clock source.
When switching between clock sources, a delay is

required to allow the new clock to stabilize. These oscillator delays are shown in Table 5-3.
5.5.2
OSCILLATOR START-UP TIMER

STATUS (OSTS) BIT
The Oscillator Start-up Timer Status (OSTS) bit of the

OSCSTAT register indicates whether the system clock
is running from the external clock source, as defined by
the FOSC<2:0> bits in the Configuration Words, or
from the internal clock source. In particular, OSTS
indicates that the Oscillator Start-up Timer (OST) has
timed out for LP, XT or HS modes. The OST does not
reflect the status of the secondary oscillator.
DS41639A-page 68
Preliminary
PIC16(L)F1454/5/9
5.6
Two-Speed Clock Start-up Mode
5.6.1
Two-Speed Start-up mode provides additional power

savings by minimizing the latency between external
oscillator start-up and code execution. In applications
that make heavy use of the Sleep mode, Two-Speed
Start-up will remove the external oscillator start-up
time from the time spent awake and can reduce the
overall power consumption of the device. This mode
allows the application to wake-up from Sleep, perform
a few instructions using the INTOSC internal oscillator
block as the clock source and go back to Sleep without
waiting for the external oscillator to become stable.
Two-Speed Start-up provides benefits when the oscillator module is configured for LP, XT, or HS modes.
The Oscillator Start-up Timer (OST) is enabled for
these modes and must count 1024 oscillations before
the oscillator can be used as the system clock source.
TWO-SPEED START-UP MODE

CONFIGURATION
Two-Speed Start-up mode is configured by the

following settings:
IESO (of the Configuration Words) = 1; Internal/External Switchover bit (Two-Speed Start-up
mode enabled).
SCS (of the OSCCON register) = 00.
FOSC<2:0> bits in the Configuration Words
configured for LP, XT or HS mode.
Two-Speed Start-up mode is entered after:
Power-on Reset (POR) and, if enabled, after
Power-up Timer (PWRT) has expired, or
Wake-up from Sleep.
If the oscillator module is configured for any mode

other than LP, XT or HS mode, then Two-Speed
Start-up is disabled. This is because the external clock
oscillator does not require any stabilization time after
POR or an exit from Sleep.
Note:
When FSCM is enabled, Two-Speed

Start-Up will automatically be enabled.
If the OST count reaches 1024 before the device

enters Sleep mode, the OSTS bit of the OSCSTAT register is set and program execution switches to the
external oscillator. However, the system may never
operate from the external oscillator if the time spent
awake is very short.
Note:
Executing a SLEEP instruction will abort

the oscillator start-up time and will cause
the OSTS bit of the OSCSTAT register to
remain clear.
TABLE 5-3:
OSCILLATOR SWITCHING DELAYS
Switch From
Switch To
(1)
Frequency
Oscillator Delay
Sleep/POR
LFINTOSC
HFINTOSC
31 kHz
31.25 kHz-16 MHz
Oscillator Warm-up Delay (TWARM)
Sleep/POR
EC, RC
DC 20 MHz
2 cycles
LFINTOSC
EC, RC
DC 20 MHz
1 cycle of each
Sleep/POR
Secondary Oscillator,
32 kHz-20 MHz
LP, XT, HS(1)
1024 Clock Cycles (OST)
Any clock source
HFINTOSC(1)
31.25 kHz-16 MHz
2 s (approx.)
Any clock source
LFINTOSC(1)
31 kHz
1 cycle of each
Any clock source
Secondary Oscillator 32 kHz
1024 Clock Cycles (OST)
PLL Inactive
PLL Active
2 ms (approx.)
Note 1:
24-48 MHz
PLL inactive.
Preliminary
DS41639A-page 69
PIC16(L)F1454/5/9
5.6.2
1.
2.
3.
4.
5.
6.
7.
TWO-SPEED START-UP
SEQUENCE
5.6.3
Wake-up from Power-on Reset or Sleep.

Instructions begin execution by the internal
oscillator at the frequency set in the IRCF<3:0>
bits of the OSCCON register.
OST enabled to count 1024 clock cycles.
OST timed out, wait for falling edge of the
internal oscillator.
OSTS is set.
System clock held low until the next falling edge
of new clock (LP, XT or HS mode).
System clock is switched to external clock
source.
FIGURE 5-8:
CHECKING TWO-SPEED CLOCK

STATUS
Checking the state of the OSTS bit of the OSCSTAT

register will confirm if the microcontroller is running
from the external clock source, as defined by the
FOSC<2:0> bits in the Configuration Words, or the
internal oscillator.
TWO-SPEED START-UP
INTOSC
TOST
OSC1
1022 1023
OSC2
Program Counter
PC - N
PC + 1
PC
System Clock
DS41639A-page 70
Preliminary
PIC16(L)F1454/5/9
5.7
Fail-Safe Clock Monitor
5.7.3
The Fail-Safe Clock Monitor (FSCM) allows the device

to continue operating should the external oscillator fail.
The FSCM can detect oscillator failure any time after
the Oscillator Start-up Timer (OST) has expired. The
FSCM is enabled by setting the FCMEN bit in the
Configuration Words. The FSCM is applicable to all
external Oscillator modes (LP, XT, HS, EC, RC and
secondary oscillator).
FIGURE 5-9:
FSCM BLOCK DIAGRAM

Clock Monitor
Latch
External
Clock
LFINTOSC
Oscillator
64
31 kHz
(~32 s)
488 Hz
(~2 ms)
Sample Clock
5.7.1
The Fail-Safe condition is cleared after a Reset,

executing a SLEEP instruction or changing the SCS bits
of the OSCCON register. When the SCS bits are
changed, the OST is restarted. While the OST is
running, the device continues to operate from the
INTOSC selected in OSCCON. When the OST times
out, the Fail-Safe condition is cleared after successfully
switching to the external clock source. The OSFIF bit
should be cleared prior to switching to the external
clock source. If the Fail-Safe condition still exists, the
OSFIF flag will again become set by hardware.
5.7.4
Clock
Failure
Detected
RESET OR WAKE-UP FROM SLEEP
The FSCM is designed to detect an oscillator failure

after the Oscillator Start-up Timer (OST) has expired.
The OST is used after waking up from Sleep and after
any type of Reset. The OST is not used with the EC or
RC Clock modes so that the FSCM will be active as
soon as the Reset or wake-up has completed. When
the FSCM is enabled, the Two-Speed Start-up is also
enabled. Therefore, the device will always be executing
code while the OST is operating.
Note:
FAIL-SAFE DETECTION
The FSCM module detects a failed oscillator by

comparing the external oscillator to the FSCM sample
clock. The sample clock is generated by dividing the
LFINTOSC by 64. See Figure 5-9. Inside the fail
detector block is a latch. The external clock sets the
latch on each falling edge of the external clock. The
sample clock clears the latch on each rising edge of the
sample clock. A failure is detected when an entire
half-cycle of the sample clock elapses before the
external clock goes low.
5.7.2
FAIL-SAFE CONDITION CLEARING
Due to the wide range of oscillator start-up

times, the Fail-Safe circuit is not active
during oscillator start-up (i.e., after exiting
Reset or Sleep). After an appropriate
amount of time, the user should check the
Status bits in the OSCSTAT register to
verify the oscillator start-up and that the
system clock switchover has successfully
completed.
FAIL-SAFE OPERATION
When the external clock fails, the FSCM switches the

device clock to an internal clock source and sets the bit
flag OSFIF of the PIR2 register. Setting this flag will
generate an interrupt if the OSFIE bit of the PIE2
register is also set. The device firmware can then take
steps to mitigate the problems that may arise from a
failed clock. The system clock will continue to be
sourced from the internal clock source until the device
firmware successfully restarts the external oscillator
and switches back to external operation.
The internal clock source chosen by the FSCM is
determined by the IRCF<3:0> bits of the OSCCON
register. This allows the internal oscillator to be
configured before a failure occurs.
Preliminary
DS41639A-page 71
PIC16(L)F1454/5/9
FIGURE 5-10:
FSCM TIMING DIAGRAM
Sample Clock
Oscillator
Failure
System
Clock
Output
Clock Monitor Output
(Q)
Failure
Detected
OSCFIF
Test
Note:
DS41639A-page 72
Test
Test
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
Preliminary
PIC16(L)F1454/5/9
5.8
Active Clock Tuning (ACT)
5.8.2
The Active Clock Tuning (ACT) continuously adjusts

the 16 MHz Internal Oscillator, using an available
external reference, to achieve 0.20% accuracy. This
eliminates the need for a high-speed, high-accuracy
external crystal when the system has an available
lower speed, lower power, high-accuracy clock source
available.
Systems implementing a Real-Time Clock Calendar
(RTCC) or a full-speed USB application can take full
advantage of the ACT.
5.8.1
ACTIVE CLOCK TUNING

OPERATION
The ACT defaults to the disabled state after any Reset.

When the ACT is disabled, the user can write to the
TUN<6:0> bits in the OSCTUNE register to manually
adjust the 16 MHz Internal Oscillator.
The ACT is enabled by setting the ACTEN bit of the
ACTCON register. When enabled, the ACT takes
control of the OSCTUNE register. The ACT uses the
selected ACT reference clock to tune the 16 MHz
Internal Oscillator to an accuracy of 16MHz 0.2%.
The tuning automatically adjusts the OSCTUNE
register every reference clock cycle.
Note 1: When the ACT is enabled, the
OSCTUNE register is only updated by
the ACT. Writes to the OSCTUNE register by the user are inhibited, but reading
the register is permitted.
2: After disabling the ACT, the user should
wait three instructions before writing to
the OSCTUNE register.
FIGURE 5-11:
ACTIVE CLOCK TUNING SOURCE

SELECTION
The ACT reference clock is selected with the ACTSRC

bit of the ACTCON register. The reference clock
sources are provided by the:
USB module in full-speed operation (ACT_clk)
Secondary clock at 32.768 kHz (SOSC_clk)
5.8.3
ACT LOCK STATUS
The ACTLOCK bit will be set to '1', when the 16 MHz

Internal Oscillator is successfully tuned.
The bit will be cleared by the following conditions:
Out of Lock condition
Device Reset
ACT is disabled
5.8.4
ACT OUT-OF-RANGE STATUS
If the ACT requires an OSCTUNE value outside the

range to achieve 0.20% accuracy, then
the ACT Out-of-Range (ACTOR) Status bit will be set
to '1'.
An out-of-range status can occur:
When the 16 MHz internal oscillator is tuned to its
lowest frequency and the next ACT_clk event
requests a lower frequency.
When the 16 MHz internal oscillator is tuned to its
highest frequency and the next ACT_clk event
requests a higher frequency.
When the ACT out-of-range event occurs, the 16 MHz
internal oscillator will continue to use the last written
OSCTUNE value. When the OSCTUNE value moves
back within the tunable range and ACTLOCK is
established, the ACTOR bit is cleared to '0'.
ACTIVE CLOCK TUNING BLOCK DIAGRAM

ACTEN
ACTSRC
FSUSB_clk
SOSC_clk
ACT_clk
Enable
Active
Clock
Tuning
16 MHz
Internal OSC
ACT data
7
ACTUD
ACTEN
sfr data
7
OSCTUNE<6:0>
Preliminary
Write
OSCTUNE
ACTEN
DS41639A-page 73
PIC16(L)F1454/5/9
5.8.5
ACTIVE CLOCK TUNING UPDATE

DISABLE
When the ACT is enabled, the OSCTUNE register is

continuously updated every ACT_clk period. Setting
the ACT Update Disable bit can be used to suspend
updates to the OSCTUNE register, without disabling
the ACT. If the 16 MHz internal oscillator drifts out of the
accuracy range, the ACT Status bits will change and an
interrupt can be generated to notify the application.
Clearing the ACTUD bit will engage the ACT updates
to OSCTUNE and an interrupt can be generated to
notify the application.
5.8.6
INTERRUPTS
The ACT will set the ACT Interrupt Flag, (ACTIF) when
either of the ACT Status bits (ACTLOCK or ACTORS)
change state, regardless if the interrupt is enabled,
(ACTIE = 1). The ACTIF and ACTIE bits are in the PIRx
and PIEx registers, respectively. When ACTIE = 1, an
interrupt will be generated whenever the ACT Status
bits change.
The ACTIF bit must be cleared in software, regardless
of the interrupt enable setting.
5.8.7
OPERATION DURING SLEEP
This ACT does not run during Sleep and will not generate interrupts during Sleep.
DS41639A-page 74
Preliminary
PIC16(L)F1454/5/9
5.9
Register Definitions: Oscillator Control
REGISTER 5-1:
OSCCON: OSCILLATOR CONTROL REGISTER
R/W-0/0
R/W-0/0
SPLLEN
SPLLMULT
R/W-0/0
R/W-1/1
R/W-1/1
R/W-1/1
R/W-0/0
IRCF<3:0>
bit 7
R/W-0/0
SCS<1:0>
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
SPLLEN: Software PLL Enable bit

If PLLEN in Configuration Words = 1:
SPLLEN bit is ignored. PLL is always enabled (subject to oscillator requirements)
If PLLEN in Configuration Words = 0:
1 = PLL is enabled
0 = PLL is disabled
bit 6
SPLLMULT: Software PLL Multiplier Select bit

1 = 3x PLL is enabled
0 = 4x PLL is enabled
bit 5-2
IRCF<3:0>: Internal Oscillator Frequency Select bits

1111 = 16 MHz or 48 MHz HF (see Section 5.2.2.1 HFINTOSC)
1110 = 8 MHz or 24 MHz HF (3x PLL) or 32 MHz HF (4x PLL) (see Section 5.2.2.1 HFINTOSC)
1101 = 4 MHz
1100 = 2 MHz
1011 = 1 MHz
1010 = 500 kHz(1)
1001 = 250 kHz(1)
1000 = 125 kHz(1)
0111 = 500 kHz (default upon Reset)
0110 = 250 kHz
0101 = 125 kHz
0100 = 62.5 kHz
001x = 31.25 kHz(1)
000x = 31 kHz LF
bit 1-0
SCS<1:0>: System Clock Select bits

1x = Internal oscillator block
01 = Secondary oscillator
00 = Clock determined by FOSC<2:0> in Configuration Words.
Note 1:
Duplicate frequency derived from HFINTOSC.
Preliminary
DS41639A-page 75
PIC16(L)F1454/5/9
REGISTER 5-2:
OSCSTAT: OSCILLATOR STATUS REGISTER
R-1/q
R-0/q
R-q/q
R-0/q
U-0
U-0
R-0/q
R-0/q
SOSCR
PLLRDY
OSTS
HFIOFR
LFIOFR
HFIOFS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
q = Conditional
bit 7
SOSCR: Secondary Oscillator Ready bit

If T1OSCEN = 1:
1 = Secondary oscillator is ready
0 = Secondary oscillator is not ready
If T1OSCEN = 0:
1 = Timer1 clock source is always ready
bit 6
PLLRDY: PLL Ready bit

1 = PLL is ready
0 = PLL is not ready
bit 5
OSTS: Oscillator Start-up Timer Status bit

1 = Running from the clock defined by the FOSC<2:0> bits of the Configuration Words
0 = Running from an internal oscillator (FOSC<2:0> = 100)
bit 4
HFIOFR: High-Frequency Internal Oscillator Ready bit

1 = HFINTOSC is ready
0 = HFINTOSC is not ready
bit 3-2
bit 1
LFIOFR: Low-Frequency Internal Oscillator Ready bit

1 = LFINTOSC is ready
0 = LFINTOSC is not ready
bit 0
HFIOFS: High-Frequency Internal Oscillator Stable bit

1 = HFINTOSC 16 MHz Oscillator is stable and is driving the INTOSC
0 = HFINTOSC 16 MHz is not stable, the Start-up Oscillator is driving INTOSC
DS41639A-page 76
Preliminary
PIC16(L)F1454/5/9
OSCTUNE: OSCILLATOR TUNING REGISTER(1,2)
REGISTER 5-3:
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
TUN<6:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-0
TUN<6:0>: Frequency Tuning bits

1000000 = Minimum frequency
1111111 =
0000000 = Oscillator module is running at the factory-calibrated frequency.
0000001 =
0111110 =
0111111 = Maximum frequency
Note 1:
2:
When active clock tuning is enabled (ACTSEL = 1) the oscillator is tuned automatically, the user cannot
write to OSCTUNE.
Oscillator is tuned monotonically.
Preliminary
DS41639A-page 77
PIC16(L)F1454/5/9
REGISTER 5-4:
ACTCON: ACTIVE CLOCK TUNING (ACT) CONTROL REGISTER
R/W-0/0
R/W-0/0
U-0
R/W-0/0
R-0/0
U-0
R-0/0
U-0
ACTEN
ACTUD
ACTSRC(1)
ACTLOCK
ACTORS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
ACTEN: Active Clock Tuning Selection bit

1 = ACT is enabled, updates to OSCTUNE are exclusive to the ACT
0 = ACT is disabled
bit 6
ACTUD: Active Clock Tuning Update Disable bit

1 = Updates to the OSCTUNE register from ACT are disabled
0 = Updates to the OSCTUNE register from ACT are enabled
bit 5
bit 4
ACTSRC: Active Clock Tuning Source Selection bit

1 = The HFINTOSC oscillator is tuned using Fll-speed USB events
0 = The HFINTOSC oscillator is tuned using the 32.768 kHz oscillator (SOSC) clock source
bit 3
ACTLOCK: Active Clock Tuning Lock Status bit

1 = Locked; 16 MHz internal oscillator is within 0.20%.Locked
0 = Not locked; 16 MHz internal oscillator tuning has not stabilized within 0.20%
bit 2
bit 1
ACTORS: Active Clock Tuning Out-of-Range Status bit

1 = Out-of-range; oscillator frequency is outside of the OSCTUNE range
0 = In-range; oscillator frequency is within the OSCTUNE range
bit 0
Note 1:
The ACTSRC bit should only be changed when ACTEN = 0.
TABLE 5-4:
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ACTCON
ACTEN
ACTUD
ACTSRC
ACTLOCK
ACTORS
75
OSCCON
SPLLEN
SPLLMULT
OSCSTAT
SOSCR
PLLRDY
OSTS
HFIOFR
LFIOFR
HFIOFS
76
Name
IRCF<3:0>
OSCTUNE
SCS<1:0>
75
TUNE<6:0>
77
PIR2
OSFIF
C2IF
C1IF
BCL1IF
USBIF
ACTIF
PIE2
OSFIE
C2IE
C1IE
BCL1IE
USBIE
ACTIE
100
T1OSCEN
T1SYNC
TMR1ON
195
TMR1CS<1:0>
T1CON
Legend:
= unimplemented location, read as 0. Shaded cells are not used by clock sources.
TABLE 5-5:
Name
CONFIG1
Legend:
T1CKPS<1:0>
98
Bits
SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES

Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
IESO
CLKOUTEN
13:8
FCMEN
7:0
CP
MCLRE
PWRTE
Bit 10/2
Bit 9/1
BOREN<1:0>
WDTE<1:0>
FOSC<2:0>
Bit 8/0
Register
on Page
52
= unimplemented location, read as 0. Shaded cells are not used by clock sources.
DS41639A-page 78
Preliminary
PIC16(L)F1454/5/9
6.0
RESETS
There are multiple ways to reset this device:

Brown-out Reset (BOR)
Low-Power Brown-out Reset (LPBOR)
MCLR Reset
WDT Reset
RESET instruction
Stack Overflow
Stack Underflow
Programming mode exit
To allow VDD to stabilize, an optional Power-up Timer

can be enabled to extend the Reset time after a BOR
or POR event.
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 6-1.
FIGURE 6-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
ICSP Programming Mode Exit

RESET Instruction
Stack
Pointer
MCLRE
MCLR
Sleep
WDT
Time-out
Device
Reset
Power-on
Reset
VDD
Brown-out
Reset
PWRT
Done
LPBOR
Reset
PWRTE
LFINTOSC
BOR
Active(1)
Note 1:
See Table 6-1 for BOR active conditions.
Preliminary
DS41639A-page 79
PIC16(L)F1454/5/9
6.1
Power-On Reset (POR)
6.2
Brown-Out Reset (BOR)
The POR circuit holds the device in Reset until VDD has
reached an acceptable level for minimum operation.
Slow rising VDD, fast operating speeds or analog
performance may require greater than minimum VDD.
The PWRT, BOR or MCLR features can be used to
extend the start-up period until all device operation
conditions have been met.
The BOR circuit holds the device in Reset when VDD

reaches a selectable minimum level. Between the
POR and BOR, complete voltage range coverage for
execution protection can be implemented.
6.1.1
POWER-UP TIMER (PWRT)
The Power-up Timer provides a nominal 64 ms timeout on POR or Brown-out Reset.

The device is held in Reset as long as PWRT is active.
The PWRT delay allows additional time for the VDD to
rise to an acceptable level. The Power-up Timer is
enabled by clearing the PWRTE bit in Configuration
Words.
The Power-up Timer starts after the release of the POR
and BOR.
For additional information, refer to Application Note
AN607, Power-up Trouble Shooting (DS00607).
TABLE 6-1:
The Brown-out Reset module has four operating

modes controlled by the BOREN<1:0> bits in Configuration Words. The four operating modes are:
BOR is always on
BOR is off when in Sleep
BOR is controlled by software
BOR is always off
Refer to Table 6-1 for more information.

The Brown-out Reset voltage level is selectable by
configuring the BORV bit in Configuration Words.
A VDD noise rejection filter prevents the BOR from triggering on small events. If VDD falls below VBOR for a
duration greater than parameter TBORDC, the device
will reset. See Figure 6-2 for more information.
BOR OPERATING MODES

Instruction Execution upon:
Release of POR or Wake-up from Sleep
BOREN<1:0>
SBOREN
Device Mode
BOR Mode
11
Active
Waits for BOR ready(1)

(BORRDY = 1)
10
Awake
Active
Sleep
Disabled
Waits for BOR ready

(BORRDY = 1)
1
01
00
Active
Waits for BOR ready(1)

(BORRDY = 1)
Begins immediately
(BORRDY = x)
Disabled
Disabled
Note 1: In these specific cases, release of POR and wake-up from Sleep, there is no delay in start-up. The BOR
ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR
circuit is forced on by the BOREN<1:0> bits.
6.2.1
BOR IS ALWAYS ON
When the BOREN bits of Configuration Words are programmed to 11, the BOR is always on. The device
start-up will be delayed until the BOR is ready and VDD
is higher than the BOR threshold.
BOR protection is active during Sleep. The BOR does
not delay wake-up from Sleep.
6.2.2
BOR IS OFF IN SLEEP
When the BOREN bits of Configuration Words are programmed to 10, the BOR is on, except in Sleep. The
device start-up will be delayed until the BOR is ready
and VDD is higher than the BOR threshold.
DS41639A-page 80
BOR protection is not active during Sleep. The device

wake-up will be delayed until the BOR is ready.
6.2.3
BOR CONTROLLED BY SOFTWARE
When the BOREN bits of Configuration Words are

programmed to 01, the BOR is controlled by the
SBOREN bit of the BORCON register. The device
start-up is not delayed by the BOR ready condition or
the VDD level.
BOR protection begins as soon as the BOR circuit is
ready. The status of the BOR circuit is reflected in the
BORRDY bit of the BORCON register.
BOR protection is unchanged by Sleep.
Preliminary
PIC16(L)F1454/5/9
FIGURE 6-2:
BROWN-OUT SITUATIONS
VDD
VBOR
Internal
Reset
TPWRT(1)
VDD
VBOR
Internal
Reset
< TPWRT
TPWRT(1)
VDD
VBOR
Internal
Reset
Note 1:
6.3
TPWRT(1)
TPWRT delay only if PWRTE bit is programmed to 0.
Register Definitions: BOR Control
REGISTER 6-1:
BORCON: BROWN-OUT RESET CONTROL REGISTER
R/W-1/u
R/W-0/u
U-0
U-0
U-0
U-0
U-0
R-q/u
SBOREN
BORFS
BORRDY
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
SBOREN: Software Brown-out Reset Enable bit

If BOREN <1:0> in Configuration Words = 01:
1 = BOR Enabled
0 = BOR Disabled
If BOREN <1:0> in Configuration Words 00:
SBOREN is read/write, but has no effect on the BOR.
bit 6
BORFS: Brown-out Reset Fast Start bit(1)

If BOREN <1:0> = 10 (Disabled in Sleep) or BOREN<1:0> = 01 (Under software control):
1 = Band gap is forced on always (covers sleep/wake-up/operating cases)
0 = Band gap operates normally, and may turn off
If BOREN<1:0> = 11 (Always on) or BOREN<1:0> = 00 (Always off)
BORFS is Read/Write, but has no effect.
bit 5-1
bit 0
BORRDY: Brown-out Reset Circuit Ready Status bit

1 = The Brown-out Reset circuit is active
0 = The Brown-out Reset circuit is inactive
Note 1:
BOREN<1:0> bits are located in Configuration Words.
Preliminary
DS41639A-page 81
PIC16(L)F1454/5/9
6.4
Low-Power Brown-out Reset

(LPBOR)
6.6
The Low-Power Brown-Out Reset (LPBOR) is an

essential part of the Reset subsystem. Refer to
Figure 6-1 to see how the BOR interacts with other
modules.
The LPBOR is used to monitor the external VDD pin.
When too low of a voltage is detected, the device is
held in Reset. When this occurs, a register bit (BOR) is
changed to indicate that a BOR Reset has occurred.
The same bit is set for both the BOR and the LPBOR.
Refer to Register 6-2.
6.4.1
ENABLING LPBOR
The LPBOR is controlled by the LPBOR bit of

Configuration Words. When the device is erased, the
LPBOR module defaults to disabled.
6.4.1.1
LPBOR Module Output
The output of the LPBOR module is a signal indicating

whether or not a Reset is to be asserted. This signal is
ORd together with the Reset signal of the BOR module to provide the generic BOR signal which goes to
the PCON register and to the power control block.
6.5
MCLR
Watchdog Timer (WDT) Reset
The Watchdog Timer generates a Reset if the firmware

does not issue a CLRWDT instruction within the time-out
period. The TO and PD bits in the STATUS register are
changed to indicate the WDT Reset. See Section 10.0
Watchdog Timer (WDT) for more information.
6.7
RESET Instruction
A RESET instruction will cause a device Reset. The RI

bit in the PCON register will be set to 0. See Table 6-4
for default conditions after a RESET instruction has
occurred.
6.8
Stack Overflow/Underflow Reset
The device can reset when the Stack Overflows or

Underflows. The STKOVF or STKUNF bits of the PCON
register indicate the Reset condition. These Resets are
enabled by setting the STVREN bit in Configuration
Words. See Section 3.5.2 Overflow/Underflow
Reset for more information.
6.9
Programming Mode Exit
Upon exit of Programming mode, the device will

behave as if a POR had just occurred.
The MCLR is an optional external input that can reset

the device. The MCLR function is controlled by the
MCLRE bit of Configuration Words and the LVP bit of
Configuration Words (Table 6-2).
6.10
TABLE 6-2:
The Power-up Timer is controlled by the PWRTE bit of

MCLR CONFIGURATION
MCLRE
LVP
MCLR
Disabled
Enabled
Enabled
6.5.1
MCLR ENABLED
A Reset does not drive the MCLR pin low.
MCLR DISABLED
When MCLR is disabled, the pin functions as a general

purpose input and the internal weak pull-up is under
software control. See Section 12.3 PORTA Registers for more information.
DS41639A-page 82
Start-up Sequence
Upon the release of a POR or BOR, the following must

occur before the device will begin executing:
The device has a noise filter in the MCLR Reset path.

The filter will detect and ignore small pulses.
6.5.2
The Power-up Timer optionally delays device execution

after a BOR or POR event. This timer is typically used to
allow VDD to stabilize before allowing the device to start
running.
6.11
When MCLR is enabled and the pin is held low, the

device is held in Reset. The MCLR pin is connected to
VDD through an internal weak pull-up.
Note:
Power-Up Timer
1.
2.
Power-up Timer runs to completion (if enabled).

MCLR must be released (if enabled).
The total time-out will vary based on oscillator configuration and Power-up Timer configuration. See
Section 6.0 Active Clock Tuning (ACT) Module for
more information.
The Power-up Timer runs independently of MCLR
Reset. If MCLR is kept low long enough, the Power-up
Timer will expire. Upon bringing MCLR high, the device
will begin execution immediately (see Figure 6-3). This
is useful for testing purposes or to synchronize more
than one device operating in parallel.
Preliminary
PIC16(L)F1454/5/9
FIGURE 6-3:
RESET START-UP SEQUENCE
VDD
Internal POR
TPWRT
Power-Up Timer
MCLR
TMCLR
Internal RESET
Internal Oscillator
Oscillator
FOSC
External Clock (EC)

CLKIN
FOSC
Preliminary
DS41639A-page 83
PIC16(L)F1454/5/9
6.12
Determining the Cause of a Reset
Upon any Reset, multiple bits in the STATUS and

PCON registers are updated to indicate the cause of
the Reset. Table 6-3 and Table 6-4 show the Reset
conditions of these registers.
TABLE 6-3:
RESET STATUS BITS AND THEIR SIGNIFICANCE
STKOVF STKUNF RWDT
RMCLR
RI
POR
BOR
TO
PD
Condition
Power-on Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
Brown-out Reset
WDT Reset
WDT Wake-up from Sleep
Interrupt Wake-up from Sleep
MCLR Reset during normal operation
MCLR Reset during Sleep
RESET Instruction Executed
Stack Overflow Reset (STVREN = 1)
Stack Underflow Reset (STVREN = 1)
TABLE 6-4:
RESET CONDITION FOR SPECIAL REGISTERS(2)

Program
Counter
STATUS
Register
PCON
Register
Power-on Reset
0000h
---1 1000
00-- 110x
MCLR Reset during normal operation
0000h
---u uuuu
uu-- 0uuu
MCLR Reset during Sleep
0000h
---1 0uuu
uu-- 0uuu
WDT Reset
0000h
---0 uuuu
uu-- uuuu
WDT Wake-up from Sleep
PC + 1
---0 0uuu
uu-- uuuu
Brown-out Reset
0000h
---1 1uuu
00-- 11u0
---1 0uuu
uu-- uuuu
---u uuuu
uu-- u0uu
Condition
Interrupt Wake-up from Sleep

RESET Instruction Executed
PC + 1
(1)
0000h
Stack Overflow Reset (STVREN = 1)
0000h
---u uuuu
1u-- uuuu
Stack Underflow Reset (STVREN = 1)
0000h
---u uuuu
u1-- uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as 0.

Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit (GIE) is set, the return address is
pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.
2: If a Status bit is not implemented, that bit will be read as 0.
DS41639A-page 84
Preliminary
PIC16(L)F1454/5/9
6.13
Power Control (PCON) Register
The Power Control (PCON) register contains flag bits

to differentiate between a:

Reset Instruction Reset (RI)
MCLR Reset (RMCLR)
Watchdog Timer Reset (RWDT)
Stack Underflow Reset (STKUNF)
Stack Overflow Reset (STKOVF)
The PCON register bits are shown in Register 6-2.
6.14
Register Definitions: Power Control
REGISTER 6-2:
PCON: POWER CONTROL REGISTER
R/W/HS-0/q
R/W/HS-0/q
U-0
STKOVF
STKUNF
R/W/HC-1/q R/W/HC-1/q
RWDT
R/W/HC-1/q
R/W/HC-q/u
R/W/HC-q/u
RI
POR
BOR
RMCLR
bit 7
bit 0
Legend:
HC = Bit is cleared by hardware
HS = Bit is set by hardware
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
STKOVF: Stack Overflow Flag bit

1 = A Stack Overflow occurred
0 = A Stack Overflow has not occurred or cleared by firmware
bit 6
STKUNF: Stack Underflow Flag bit

1 = A Stack Underflow occurred
0 = A Stack Underflow has not occurred or cleared by firmware
bit 5
bit 4
RWDT: Watchdog Timer Reset Flag bit

1 = A Watchdog Timer Reset has not occurred or set by firmware
0 = A Watchdog Timer Reset has occurred (cleared by hardware)
bit 3
RMCLR: MCLR Reset Flag bit

1 = A MCLR Reset has not occurred or set by firmware
0 = A MCLR Reset has occurred (cleared by hardware)
bit 2
RI: RESET Instruction Flag bit

1 = A RESET instruction has not been executed or set by firmware
0 = A RESET instruction has been executed (cleared by hardware)
bit 1
POR: Power-on Reset Status bit

1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit

1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset
occurs)
Preliminary
DS41639A-page 85
PIC16(L)F1454/5/9
TABLE 6-5:
SUMMARY OF REGISTERS ASSOCIATED WITH RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
BORCON
SBOREN
BORFS
BORRDY
81
PCON
STKOVF
STKUNF
RWDT
RMCLR
RI
POR
BOR
85
STATUS
TO
PD
DC
27
WDTCON
SWDTEN
110
WDTPS<4:0>
Legend: = unimplemented bit, reads as 0. Shaded cells are not used by Resets.
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
TABLE 6-6:
Name
CONFIG1
CONFIG2
Legend:
SUMMARY OF CONFIGURATION WORD WITH RESETS
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
IESO
CLKOUTEN
13:8
FCMEN
7:0
CP
MCLRE
PWRTE
LVP
13:8
7:0
PLLMULT USBLSCLK
Bit 10/2
BOREN<1:0>
WDTE<1:0>
DEBUG
CPUDIV<1:0>
Bit 9/1
Bit 8/0
FOSC<2:0>
LPBOR
BORV
STVREN
PLLEN
WRT<1:0>
Register
on Page
52
54
= unimplemented location, read as 0. Shaded cells are not used by Resets.
DS41639A-page 86
Preliminary
PIC16(L)F1454/5/9
7.0
REFERENCE CLOCK MODULE
The reference clock module provides the ability to send

a divided clock to the clock output pin of the device
(CLKR). This module is available in all oscillator configurations and allows the user to select a greater range
of clock submultiples to drive external devices in the
application. The reference clock module includes the
following features:
System clock is the source

Available in all oscillator configurations
Programmable clock divider
Output enable to a port pin
Selectable duty cycle
Slew rate control
Note 1: If the base clock rate is selected without

a divider, the output clock will always
have a duty cycle equal to that of the
source clock, unless a 0% duty cycle is
selected. If the clock divider is set to base
clock/2, then 25% and 75% duty cycle
accuracy will be dependent upon the
source clock.
Conflicts with the CLKR Pin
There are two cases when the reference clock output

signal cannot be output to the CLKR pin, if:
LP, XT or HS Oscillator mode is selected.
CLKOUT function is enabled.
7.3.1
OSCILLATOR MODES
If LP, XT or HS Oscillator modes are selected, the

OSC2/CLKR pin must be used as an oscillator input pin
and the CLKR output cannot be enabled. See
Section 5.2 Clock Source Types for more information on different oscillator modes.
7.3.2
The reference clock module is controlled by the

CLKRCON register (Register 7-1) and is enabled when
setting the CLKREN bit. To output the divided clock signal to the CLKR port pin, the CLKROE bit must be set.
The CLKRDIV<2:0> bits enable the selection of eight
different clock divider options. The CLKRDC<1:0> bits
can be used to modify the duty cycle of the output
clock(1). The CLKRSLR bit controls slew rate limiting.
7.1
7.3
CLKOUT FUNCTION
The CLKOUT function has a higher priority than the reference clock module. Therefore, if the CLKOUT function is enabled by the CLKOUTEN bit in Configuration
Words, FOSC/4 will always be output on the port pin.
Reference Section 4.0 Device Configuration for
more information.
7.4
Operation During Sleep
As the reference clock module relies on the system

clock as its source, and the system clock is disabled in
Sleep, the module does not function in Sleep, even if
an external clock source or the Timer1 clock source is
configured as the system clock. The module outputs
will remain in their current state until the device exits
Sleep.
Slew Rate
The slew rate limitation on the output port pin can be

disabled. The slew rate limitation can be removed by
clearing the CLKRSLR bit in the CLKRCON register.
7.2
Effects of a Reset
Upon any device Reset, the reference clock module is

disabled. The user's firmware is responsible for
initializing the module before enabling the output. The
registers are reset to their default values.
Preliminary
DS41639A-page 87
PIC16(L)F1454/5/9
7.5
Register Definition: Reference Clock Control
REGISTER 7-1:
CLKRCON: REFERENCE CLOCK CONTROL REGISTER
R/W-0/0
R/W-0/0
R/W-1/1
CLKREN
CLKROE
CLKRSLR
R/W-1/1
R/W-0/0
R/W-0/0
CLKRDC<1:0>
R/W-0/0
R/W-0/0
CLKRDIV<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
CLKREN: Reference Clock Module Enable bit

1 = Reference clock module is enabled
0 = Reference clock module is disabled
bit 6
CLKROE: Reference Clock Output Enable bit(3)

1 = Reference clock output is enabled on CLKR pin
0 = Reference clock output disabled on CLKR pin
bit 5
CLKRSLR: Reference Clock Slew Rate Control limiting enable bit

1 = Slew rate limiting is enabled
0 = Slew rate limiting is disabled
bit 4-3
CLKRDC<1:0>: Reference Clock Duty Cycle bits

11 = Clock outputs duty cycle of 75%
bit 2-0
CLKRDIV<2:0> Reference Clock Divider bits

111 = Base clock value divided by 128
001 = Base clock value divided by 2(1)
000 = Base clock value(2)
Note 1: In this mode, the 25% and 75% duty cycle accuracy will be dependent on the source clock duty cycle.
2: In this mode, the duty cycle will always be equal to the source clock duty cycle, unless a duty cycle of 0%
is selected.
3: To route CLKR to pin, CLKOUTEN of Configuration Words = 1 is required. CLKOUTEN of Configuration
Words = 0 will result in FOSC/4. See Section 7.3 Conflicts with the CLKR Pin for details.
DS41639A-page 88
Preliminary
PIC16(L)F1454/5/9
TABLE 7-1:
SUMMARY OF REGISTERS ASSOCIATED WITH REFERENCE CLOCK SOURCES
Name
CLKRCON
Legend:
Bit 7
Bit 6
Bit 5
CLKREN
CLKROE
CLKRSLR
CONFIG1
Legend:
Bit 3
CLKRDC<1:0>
Bit 2
Bit 1
Bit 0
Register
on Page
88
CLKRDIV<2:0>
= unimplemented locations read as 0. Shaded cells are not used by reference clock sources.
TABLE 7-2:
Name
Bit 4
Bits
SUMMARY OF CONFIGURATION WORD WITH REFERENCE CLOCK SOURCES

Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
IESO
CLKOUTEN
13:8
FCMEN
7:0
CP
MCLRE
PWRTE
WDTE<1:0>
Bit 10/2
Bit 9/1
BOREN<1:0>
FOSC<2:0>
Bit 8/0
CPD
Register
on Page
52
= unimplemented locations read as 0. Shaded cells are not used by reference clock sources.
Preliminary
DS41639A-page 89
PIC16(L)F1454/5/9
NOTES:
DS41639A-page 90
Preliminary
PIC16(L)F1454/5/9
8.0
INTERRUPTS
The interrupt feature allows certain events to preempt

normal program flow. Firmware is used to determine
the source of the interrupt and act accordingly. Some
interrupts can be configured to wake the MCU from
Sleep mode.
This chapter contains the following information for
Interrupts:
Operation
Interrupt Latency
Interrupts During Sleep
INT Pin
Automatic Context Saving
Many peripherals produce interrupts. Refer to the

corresponding chapters for details.
A block diagram of the interrupt logic is shown in
Figure 8-1.
FIGURE 8-1:
INTERRUPT LOGIC
TMR0IF
TMR0IE
Peripheral Interrupts
(TMR1IF) PIR1<0>
(TMR1IF) PIR1<0>
Wake-up
(If in Sleep mode)
INTF
INTE
IOCIF
IOCIE
Interrupt
to CPU
PEIE
PIRn<7>
PIEn<7>
GIE
Preliminary
DS41639A-page 91
PIC16(L)F1454/5/9
8.1
Operation
8.2
Interrupts are disabled upon any device Reset. They

are enabled by setting the following bits:
GIE bit of the INTCON register
Interrupt Enable bit(s) for the specific interrupt
event(s)
PEIE bit of the INTCON register (if the Interrupt
Enable bit of the interrupt event is contained in the
PIE1 and PIE2 registers)
Interrupt Latency
Interrupt latency is defined as the time from when the

interrupt event occurs to the time code execution at the
interrupt vector begins. The latency for synchronous
interrupts is three or four instruction cycles. For asynchronous interrupts, the latency is three to five instruction cycles, depending on when the interrupt occurs.
See Figure 8-2 and Figure 8.3 for more details.
The INTCON, PIR1 and PIR2 registers record individual interrupts via interrupt flag bits. Interrupt flag bits will
be set, regardless of the status of the GIE, PEIE and
individual interrupt enable bits.
The following events happen when an interrupt event
occurs while the GIE bit is set:
Current prefetched instruction is flushed
GIE bit is cleared
Current Program Counter (PC) is pushed onto the
stack
Critical registers are automatically saved to the
shadow registers (See Section 8.5 Automatic
Context Saving.)
PC is loaded with the interrupt vector 0004h
The firmware within the Interrupt Service Routine (ISR)
should determine the source of the interrupt by polling
the interrupt flag bits. The interrupt flag bits must be
cleared before exiting the ISR to avoid repeated
interrupts. Because the GIE bit is cleared, any interrupt
that occurs while executing the ISR will be recorded
through its interrupt flag, but will not cause the
processor to redirect to the interrupt vector.
The RETFIE instruction exits the ISR by popping the
previous address from the stack, restoring the saved
context from the shadow registers and setting the GIE
bit.
For additional information on a specific interrupts
operation, refer to its peripheral chapter.
Note 1: Individual interrupt flag bits are set,
regardless of the state of any other
enable bits.
2: All interrupts will be ignored while the GIE
bit is cleared. Any interrupt occurring
while the GIE bit is clear will be serviced
when the GIE bit is set again.
DS41639A-page 92
Preliminary
PIC16(L)F1454/5/9
FIGURE 8-2:
INTERRUPT LATENCY
Fosc
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKR
Interrupt Sampled
during Q1
Interrupt
GIE
PC
Execute
PC-1
PC
1 Cycle Instruction at PC
PC+1
0004h
0005h
Inst(PC)
NOP
NOP
Inst(0004h)
PC+1/FSR
ADDR
New PC/
PC+1
0004h
0005h
Inst(PC)
NOP
NOP
Inst(0004h)
FSR ADDR
PC+1
PC+2
0004h
0005h
INST(PC)
NOP
NOP
NOP
Inst(0004h)
Inst(0005h)
FSR ADDR
PC+1
0004h
0005h
INST(PC)
NOP
NOP
Inst(0004h)
Interrupt
GIE
PC
Execute
PC-1
PC
Interrupt
GIE
PC
Execute
PC-1
PC
Interrupt
GIE
PC
Execute
PC-1
PC
Preliminary
PC+2
NOP
NOP
DS41639A-page 93
PIC16(L)F1454/5/9
FIGURE 8-3:
INT PIN INTERRUPT TIMING

Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKOUT (3)
(4)
INT pin
(1)
(1)
INTF
Interrupt Latency (2)
(5)
GIE
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
Note 1:
PC
Inst (PC)
Inst (PC 1)
PC + 1
Inst (PC + 1)
PC + 1
Forced NOP
Inst (PC)
0004h
Inst (0004h)
Forced NOP
0005h
Inst (0005h)
Inst (0004h)
INTF flag is sampled here (every Q1).
2:
Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3:
CLKOUT not available in all oscillator modes.
4:
For minimum width of INT pulse, refer to AC specifications in Section 29.0 Electrical Specifications
5:
INTF is enabled to be set any time during the Q4-Q1 cycles.
DS41639A-page 94
Preliminary
PIC16(L)F1454/5/9
8.3
Interrupts During Sleep
Some interrupts can be used to wake from Sleep. To

wake from Sleep, the peripheral must be able to
operate without the system clock. The interrupt source
must have the appropriate Interrupt Enable bit(s) set
prior to entering Sleep.
On waking from Sleep, if the GIE bit is also set, the
processor will branch to the interrupt vector. Otherwise,
the processor will continue executing instructions after
the SLEEP instruction. The instruction directly after the
SLEEP instruction will always be executed before
branching to the ISR. Refer to Section 9.0 PowerDown Mode (Sleep) for more details.
8.4
INT Pin
The INT pin can be used to generate an asynchronous

edge-triggered interrupt. This interrupt is enabled by
setting the INTE bit of the INTCON register. The
INTEDG bit of the OPTION_REG register determines on
which edge the interrupt will occur. When the INTEDG
bit is set, the rising edge will cause the interrupt. When
the INTEDG bit is clear, the falling edge will cause the
interrupt. The INTF bit of the INTCON register will be set
when a valid edge appears on the INT pin. If the GIE and
INTE bits are also set, the processor will redirect
program execution to the interrupt vector.
8.5
Automatic Context Saving
Upon entering an interrupt, the return PC address is

saved on the stack. Additionally, the following registers
are automatically saved in the shadow registers:
W register
STATUS register (except for TO and PD)
BSR register
FSR registers
PCLATH register
Upon exiting the Interrupt Service Routine, these registers are automatically restored. Any modifications to
these registers during the ISR will be lost. If modifications to any of these registers are desired, the corresponding shadow register should be modified and the
value will be restored when exiting the ISR. The
shadow registers are available in Bank 31 and are
readable and writable. Depending on the users application, other registers may also need to be saved.
Preliminary
DS41639A-page 95
PIC16(L)F1454/5/9
8.6
Register Definitions: Interrupt Control
REGISTER 8-1:
INTCON: INTERRUPT CONTROL REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R-0/0
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
GIE: Global Interrupt Enable bit

1 = Enables all active interrupts
0 = Disables all interrupts
bit 6
PEIE: Peripheral Interrupt Enable bit

1 = Enables all active peripheral interrupts
0 = Disables all peripheral interrupts
bit 5
TMR0IE: Timer0 Overflow Interrupt Enable bit

1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt
bit 4
INTE: INT External Interrupt Enable bit

1 = Enables the INT external interrupt
0 = Disables the INT external interrupt
bit 3
IOCIE: Interrupt-on-Change Enable bit

1 = Enables the interrupt-on-change
0 = Disables the interrupt-on-change
bit 2
TMR0IF: Timer0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed
0 = TMR0 register did not overflow
bit 1
INTF: INT External Interrupt Flag bit

1 = The INT external interrupt occurred
0 = The INT external interrupt did not occur
bit 0
IOCIF: Interrupt-on-Change Interrupt Flag bit(1)

1 = When at least one of the interrupt-on-change pins changed state
0 = None of the interrupt-on-change pins have changed state
Note 1:
Note:
The IOCIF Flag bit is read-only and cleared when all the interrupt-on-change flags in the IOCBF register
have been cleared by software.
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE, of the INTCON
register. User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
DS41639A-page 96
Preliminary
PIC16(L)F1454/5/9
REGISTER 8-2:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
R/W-0/0
TMR1GIE
ADIE(1)
RCIE
TXIE
SSP1IE
TMR2IE
TMR1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
TMR1GIE: Timer1 Gate Interrupt Enable bit

1 = Enables the Timer1 gate acquisition interrupt
0 = Disables the Timer1 gate acquisition interrupt
bit 6
ADIE: A/D Converter (ADC) Interrupt Enable bit

1 = Enables the ADC interrupt
0 = Disables the ADC interrupt
bit 5
RCIE: USART Receive Interrupt Enable bit

1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4
TXIE: USART Transmit Interrupt Enable bit

1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3
SSP1IE: Synchronous Serial Port (MSSP) Interrupt Enable bit

1 = Enables the MSSP interrupt
0 = Disables the MSSP interrupt
bit 2
bit 1
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the Timer2 to PR2 match interrupt
0 = Disables the Timer2 to PR2 match interrupt
bit 0
TMR1IE: Timer1 Overflow Interrupt Enable bit

1 = Enables the Timer1 overflow interrupt
0 = Disables the Timer1 overflow interrupt
Note 1:
Note:
Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.
Preliminary
DS41639A-page 97
PIC16(L)F1454/5/9
REGISTER 8-3:
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0/0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
OSFIE
C2IE
C1IE
BCL1IE
USBIE
ACTIE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
OSFIE: Oscillator Fail Interrupt Enable bit

1 = Enables the Oscillator Fail interrupt
0 = Disables the Oscillator Fail interrupt
bit 6
C2IE: Comparator C2 Interrupt Enable bit

1 = Enables the Comparator C2 interrupt
0 = Disables the Comparator C2 interrupt
bit 5
C1IE: Comparator C1 Interrupt Enable bit

1 = Enables the Comparator C1 interrupt
0 = Disables the Comparator C1 interrupt
bit 4
bit 3
BCL1IE: MSSP Bus Collision Interrupt Enable bit

1 = Enables the MSSP Bus Collision Interrupt
0 = Disables the MSSP Bus Collision Interrupt
bit 2
USBIE: USB Interrupt Enable bit

1 = Enables the USB interrupt
0 = Disables the USB interrupt
bit 1
ACTIE: Active Clock Tuning Interrupt Enable bit

1 = Enables the Active Clock Tuning interrupt
0 = Disables the Active Clock Tuning interrupt
bit 0
Note:
Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.
DS41639A-page 98
Preliminary
PIC16(L)F1454/5/9
REGISTER 8-4:
PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
R/W-0/0
TMR1GIF
ADIF(1)
RCIF
TXIF
SSP1IF
TMR2IF
TMR1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
TMR1GIF: Timer1 Gate Interrupt Flag bit

1 = Interrupt is pending
0 = Interrupt is not pending
bit 6
ADIF: A/D Converter Interrupt Flag bit

bit 5
RCIF: USART Receive Interrupt Flag bit

bit 4
TXIF: USART Transmit Interrupt Flag bit

bit 3
SSP1IF: Synchronous Serial Port (MSSP) Interrupt Flag bit

bit 2
bit 1
TMR2IF: Timer2 to PR2 Interrupt Flag bit

bit 0
TMR1IF: Timer1 Overflow Interrupt Flag bit

Note 1:
Note:

appropriate interrupt flag bits are clear prior
to enabling an interrupt.
Preliminary
DS41639A-page 99
PIC16(L)F1454/5/9
REGISTER 8-5:
PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
R/W-0/0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
OSFIF
C2IF
C1IF
BCL1IF
USBIF
ACTIF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
OSFIF: Oscillator Fail Interrupt Flag bit

bit 6
C2IF: Numerically Controlled Oscillator Flag bit

bit 5
C1IF: Numerically Controlled Oscillator Flag bit

bit 4
bit 3
BCL1IF: MSSP Bus Collision Interrupt Flag bit

bit 2
USBIF: USB Flag bit

bit 1
ACTIF: Active Clock Tuning Interrupt Flag bit

bit 0
Note:

appropriate interrupt flag bits are clear prior
to enabling an interrupt.
DS41639A-page 100
Preliminary
PIC16(L)F1454/5/9
TABLE 8-1:
Name
INTCON
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS

Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
96
OPTION_REG WPUEN
PIE1
TMR1GIE
INTEDG TMR0CS TMR0SE

(1)
ADIE
RCIE
PSA
PS<2:0>
TXIE
SSP1IE
TMR2IE
185
TMR1IE
97
PIE2
OSFIE
C2IE
C1IE
BCL1IE
USBIE
ACTIE
98
PIR1
TMR1GIF
ADIF(1)
RCIF
TXIF
SSP1IF
TMR2IF
TMR1IF
99
PIR2
OSFIF
C2IF
C1IF
BCL1IF
USBIF
ACTIF
100
Legend: = unimplemented location, read as 0. Shaded cells are not used by interrupts.
Note 1: PIC16(L)F1455/9 only.
Preliminary
DS41639A-page 101
PIC16(L)F1454/5/9
NOTES:
DS41639A-page 102
Preliminary
PIC16(L)F1454/5/9
9.0
POWER-DOWN MODE (SLEEP)
The Power-Down mode is entered by executing a

SLEEP instruction.
Upon entering Sleep mode, the following conditions exist:
1.
2.
3.
4.
5.
6.
7.
8.
WDT will be cleared but keeps running, if

enabled for operation during Sleep.
PD bit of the STATUS register is cleared.
TO bit of the STATUS register is set.
CPU clock is disabled.
31 kHz LFINTOSC is unaffected and peripherals
that operate from it may continue operation in
Sleep.
ADC is unaffected, if the dedicated FRC clock is
selected.
I/O ports maintain the status they had before
SLEEP was executed (driving high, low or highimpedance).
Resets other than WDT are not affected by
Sleep mode.
Refer to individual chapters for more details on

peripheral operation during Sleep.
To minimize current consumption, the following
conditions should be considered:
I/O pins should not be floating

External circuitry sinking current from I/O pins
Internal circuitry sourcing current from I/O pins
Current draw from pins with internal weak pull-ups
Modules using 31 kHz LFINTOSC
CWG module using HFINTOSC
9.1
Wake-up from Sleep
The device can wake-up from Sleep through one of the

following events:
1. External Reset input on MCLR pin, if enabled
2. BOR Reset, if enabled
3. POR Reset
4. Watchdog Timer, if enabled
5. Any external interrupt
6. Interrupts by peripherals capable of running during Sleep (see individual peripheral for more
information)
The first three events will cause a device Reset. The
last three events are considered a continuation of program execution. To determine whether a device Reset
or wake-up event occurred, refer to Section 6.12
Determining the Cause of a Reset.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be enabled. Wake-up will
occur regardless of the state of the GIE bit. If the GIE
bit is disabled, the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
enabled, the device executes the instruction after the
SLEEP instruction, the device will then call the Interrupt
Service Routine. In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOP after the SLEEP instruction.
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
I/O pins that are high-impedance inputs should be

pulled to VDD or VSS externally to avoid switching
currents caused by floating inputs.
Examples of internal circuitry that might be sourcing
current include the FVR module. See Section 14.0
Fixed Voltage Reference (FVR) (PIC16(L)F1455/9
only) for more information on this module.
Preliminary
DS41639A-page 103
PIC16(L)F1454/5/9
9.1.1
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
If the interrupt occurs before the execution of a
SLEEP instruction
- SLEEP instruction will execute as a NOP.
- WDT and WDT prescaler will not be cleared
- TO bit of the STATUS register will not be set
- PD bit of the STATUS register will not be
cleared.
If the interrupt occurs during or after the execution of a SLEEP instruction
- SLEEP instruction will be completely executed
- Device will immediately wake-up from Sleep
- WDT and WDT prescaler will be cleared
- TO bit of the STATUS register will be set
- PD bit of the STATUS register will be cleared
FIGURE 9-1:
Even if the flag bits were checked before executing a

SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKIN(1)
T1OSC(3)
CLKOUT(2)
Interrupt Latency (4)
Interrupt flag
GIE bit
(INTCON reg.)
Processor in
Sleep
Instruction Flow
PC
Instruction
Fetched
Instruction
Executed
Note
1:
2:
3:
4:
PC
Inst(PC) = Sleep
Inst(PC - 1)
PC + 1
PC + 2
PC + 2
Inst(PC + 1)
Inst(PC + 2)
Sleep
Inst(PC + 1)
PC + 2
Forced NOP
0004h
0005h
Inst(0004h)
Inst(0005h)
Forced NOP
Inst(0004h)
External clock. High, Medium, Low mode assumed.

CLKOUT is shown here for timing reference.
T1OSC; See Section 29.0 Electrical Specifications.
GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.
DS41639A-page 104
Preliminary
PIC16(L)F1454/5/9
9.2
Low-Power Sleep Mode
9.2.2
The PIC16F1454/5/9 device contains an internal Low

Dropout (LDO) voltage regulator, which allows the
device I/O pins to operate at voltages up to 5.5V while
the internal device logic operates at a lower voltage.
The LDO and its associated reference circuitry must
remain active when the device is in Sleep mode. The
PIC16F1454/5/9 allows the user to optimize the
operating current in Sleep, depending on the
application requirements.
A Low-Power Sleep mode can be selected by setting
the VREGPM bit of the VREGCON register. With this
bit set, the LDO and reference circuitry are placed in a
low-power state when the device is in Sleep.
9.2.1
SLEEP CURRENT VS. WAKE-UP

TIME
In the default operating mode, the LDO and reference

circuitry remain in the normal configuration while in
Sleep. The device is able to exit Sleep mode quickly
since all circuits remain active. In Low-Power Sleep
mode, when waking up from Sleep, an extra delay time
is required for these circuits to return to the normal configuration and stabilize.
Some peripherals that can operate in Sleep mode will

not operate properly with the Low-Power Sleep mode
selected. The LDO will remain in the Normal-Power
mode when those peripherals are enabled. The LowPower Sleep mode is intended for use with these
peripherals:
Brown-Out Reset (BOR)

Watchdog Timer (WDT)
External interrupt pin/Interrupt-on-change pins
Timer1 (with external clock source)
The Complementary Waveform Generator (CWG)

module can utilize the HFINTOSC oscillator as either
a clock source or as an input source. Under certain
conditions, when the HFINTOSC is selected for use
with the CWG module, the HFINTOSC will remain
active during Sleep. This will have a direct effect on
the Sleep mode current.
Please refer to section 25.10 Operation During
Sleep for more information.
Note:
The Low-Power Sleep mode is beneficial for applications that stay in Sleep mode for long periods of time.
The Normal mode is beneficial for applications that
need to wake from Sleep quickly and frequently.
PERIPHERAL USAGE IN SLEEP
Preliminary
The PIC16LF1454/5/9 does not have a

configurable Low-Power Sleep mode.
PIC16LF1454/5/9 is an unregulated
device and is always in the lowest power
state when in Sleep, with no wake-up time
penalty. This device has a lower maximum
VDD and I/O voltage than the
PIC16LF1454/5/9. See Section 29.0
Electrical Specifications for more
information.
DS41639A-page 105
PIC16(L)F1454/5/9
9.3
Register Definitions: Voltage Regulator Control

VREGCON: VOLTAGE REGULATOR CONTROL REGISTER(1)
REGISTER 9-1:
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0/0
R/W-1/1
VREGPM
Reserved
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-2
bit 1
VREGPM: Voltage Regulator Power Mode Selection bit

1 = Low-Power Sleep mode enabled in Sleep(2)
Draws lowest current in Sleep, slower wake-up
0 = Normal-Power mode enabled in Sleep(2)
Draws higher current in Sleep, faster wake-up
bit 0
Reserved: Read as 1. Maintain this bit set.
Note 1:
2:
PIC16LF1454/5/9 only.
See Section 29.0 Electrical Specifications.
TABLE 9-1:
SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register on
Page
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
96
IOCAF
IOCAF5
IOCAF4
IOCAF3
IOCAF1
IOCAF0
146
IOCAN
IOCAN5
IOCAN4
IOCAN3
IOCAN1
IOCAN0
145
IOCAP
IOCAP5
IOCAP4
IOCAP3
IOCAP1
IOCAP0
145
IOCBF(2)
IOCBF7
IOCBF6
IOCBF5
IOCBF4
147
IOCBN(2)
IOCBN7
IOCBN6
IOCBN5
IOCBN4
147
IOCBP(2)
IOCBP7
IOCBP6
IOCBP5
IOCBP4
146
PIE1
TMR1GIE
ADIE(1)
RCIE
TXIE
SSP1IE
TMR2IE
TMR1IE
97
PIE2
OSFIE
C2IE
C1IE
BCL1IE
USBIE
ACTIE
98
RCIF
TXIF
SSP1IF
TMR2IF
TMR1IF
99
PIR1
TMR1GIF
PIR2
(1)
ADIF
OSFIF
C2IF
C1IF
BCL1IF
USBIF
ACTIF
100
STATUS
TO
PD
DC
27
WDTCON
SWDTEN
110
WDTPS<4:0>
Legend: = unimplemented, read as 0. Shaded cells are not used in Power-Down mode.
Note 1: PIC16(L)F1455/9 only.
2: PIC16(L)F1459 only.
DS41639A-page 106
Preliminary
PIC16(L)F1454/5/9
10.0
WATCHDOG TIMER (WDT)
The Watchdog Timer is a system timer that generates

a Reset if the firmware does not issue a CLRWDT
instruction within the time-out period. The Watchdog
Timer is typically used to recover the system from
unexpected events.
The WDT has the following features:
Independent clock source
Multiple operating modes
- WDT is always on
- WDT is off when in Sleep
- WDT is controlled by software
- WDT is always off
Configurable time-out period is from 1 ms to 256
seconds (nominal)
Multiple Reset conditions
Operation during Sleep
FIGURE 10-1:
WATCHDOG TIMER BLOCK DIAGRAM
WDTE<1:0> = 01
SWDTEN
WDTE<1:0> = 11
LFINTOSC
23-bit Programmable
Prescaler WDT
WDT Time-out
WDTE<1:0> = 10
Sleep
WDTPS<4:0>
Preliminary
DS41639A-page 107
PIC16(L)F1454/5/9
10.1
Independent Clock Source
10.4
The WDT derives its time base from the 31 kHz

LFINTOSC internal oscillator. Time intervals in this
chapter are based on a nominal interval of 1 ms. See
Section 29.0 Electrical Specifications for the
LFINTOSC tolerances.
10.2
WDT Operating Modes
The Watchdog Timer module has four operating modes

controlled by the WDTE<1:0> bits in Configuration
Words. See Table 10-1.
10.2.1
WDT protection is active during Sleep.
WDT IS OFF IN SLEEP
When the WDTE bits of Configuration Words are set to

10, the WDT is on, except in Sleep.
WDT protection is not active during Sleep.
10.2.3
WDT CONTROLLED BY SOFTWARE

01, the WDT is controlled by the SWDTEN bit of the
WDTCON register.
WDT protection is unchanged
Table 10-1 for more details.
TABLE 10-1:
by
Sleep.
See
WDT OPERATING MODES
WDTE<1:0>
SWDTEN
Device
Mode
WDT
Mode
11
Active
10
Awake
Active
Sleep
Disabled
01
00
10.3
1
0
X
The WDT is cleared when any of the following conditions occur:
Any Reset
CLRWDT instruction is executed
Device enters Sleep
Device wakes up from Sleep
Oscillator fail
WDT is disabled
Oscillator Start-up Timer (OST) is running
See Table 10-2 for more information.
WDT IS ALWAYS ON

11, the WDT is always on.
10.2.2
Clearing the WDT
X
X
10.5
When the device enters Sleep, the WDT is cleared. If

the WDT is enabled during Sleep, the WDT resumes
counting.
When the device exits Sleep, the WDT is cleared
again. The WDT remains clear until the OST, if
enabled, completes. See Section 5.0 Oscillator
Module (With Fail-Safe Clock Monitor) for more
information on the OST.
The WDT remains clear until the OST, if enabled, completes. See Section 5.0 Oscillator Module (With
Fail-Safe Clock Monitor) for more information on the
OST. (add with start-up timer oscillators)
When a WDT time-out occurs while the device is in
Sleep, no Reset is generated. Instead, the device
wakes up and resumes operation. The TO and PD bits
in the STATUS register are changed to indicate the
event. The RWDT bit in the PCON register can also be
used. See Section 3.0 Memory Organization for
more information.
Active
Disabled
Disabled
Time-Out Period
The WDTPS bits of the WDTCON register set the

time-out period from 1 ms to 256 seconds (nominal).
After a Reset, the default time-out period is two
seconds.
DS41639A-page 108
Preliminary
PIC16(L)F1454/5/9
TABLE 10-2:
WDT CLEARING CONDITIONS

Conditions
WDT
WDTE<1:0> = 00
WDTE<1:0> = 01 and SWDTEN = 0
WDTE<1:0> = 10 and enter Sleep
Cleared
CLRWDT Command
Oscillator Fail Detected
Exit Sleep + System Clock = EXTRC, INTOSC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP
Cleared until the end of OST
Change INTOSC divider (IRCF bits)
Unaffected
Preliminary
DS41639A-page 109
PIC16(L)F1454/5/9
10.6
Register Definitions: Watchdog Control
REGISTER 10-1:
WDTCON: WATCHDOG TIMER CONTROL REGISTER
U-0
U-0
R/W-0/0
R/W-1/1
R/W-0/0
R/W-1/1
R/W-1/1
WDTPS<4:0>
R/W-0/0
SWDTEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-1
WDTPS<4:0>: Watchdog Timer Period Select bits(1)

Bit Value = Prescale Rate
00000 = 1:32 (Interval 1 ms nominal)
01010 = 1:32768 (Interval 1s nominal)
01011 = 1:65536 (Interval 2s nominal) (Reset value)
01100 = 1:131072 (217) (Interval 4s nominal)
10011 = Reserved. Results in minimum interval (1:32)
11111 = Reserved. Results in minimum interval (1:32)
bit 0
Note 1:
SWDTEN: Software Enable/Disable for Watchdog Timer bit

If WDTE<1:0> = 00:
If WDTE<1:0> = 01:
1 = WDT is turned on
0 = WDT is turned off
If WDTE<1:0> = 1x:
Times are approximate. WDT time is based on 31 kHz LFINTOSC.
DS41639A-page 110
Preliminary
PIC16(L)F1454/5/9
TABLE 10-3:
SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER
Name
Bit 7
Bit 6
OSCCON
SPLLEN
SPLLMULT
PCON
STKOVF
STKUNF
RWDT
STATUS
TO
WDTCON
Legend:
CONFIG1
Legend:
Bit 4
Bit 3
Bit 2
Bit 1
IRCF<3:0>
Bit 0
SCS<1:0>
RMCLR
RI
POR
PD
DC
WDTPS<4:0>
Register
on Page
75
BOR
85
27
SWDTEN
110
x = unknown, u = unchanged, = unimplemented locations read as 0. Shaded cells are not used by Watchdog Timer.
TABLE 10-4:
Name
Bit 5
SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
13:8
FCMEN
IESO
CLKOUTEN
7:0
CP
MCLRE
PWRTE
WDTE<1:0>
Bit 10/2
Bit 9/1
BOREN<1:0>
FOSC<2:0>
Bit 8/0
Register
on Page
52
= unimplemented location, read as 0. Shaded cells are not used by Watchdog Timer.
Preliminary
DS41639A-page 111
PIC16(L)F1454/5/9
11.0
FLASH PROGRAM MEMORY

CONTROL
11.1.1
The Flash program memory is readable and writable

during normal operation over the full VDD range.
Program memory is indirectly addressed using Special
Function Registers (SFRs). The SFRs used to access
program memory are:
PMCON1
PMCON2
PMDATL
PMDATH
PMADRL
PMADRH
When accessing the program memory, the

PMDATH:PMDATL register pair forms a 2-byte word
that holds the 14-bit data for read/write, and the
PMADRH:PMADRL register pair forms a 2-byte word
that holds the 15-bit address of the program memory
location being read.
The write time is controlled by an on-chip timer. The write/
erase voltages are generated by an on-chip charge pump
rated to operate over the operating voltage range of the
device.
The Flash program memory can be protected in two
ways; by code protection (CP bit in Configuration Words)
and write protection (WRT<1:0> bits in Configuration
Words).
Code protection (CP = 0)(1), disables access, reading
and writing, to the Flash program memory via external
device programmers. Code protection does not affect
the self-write and erase functionality. Code protection
can only be reset by a device programmer performing
a Bulk Erase to the device, clearing all Flash program
memory, Configuration bits and User IDs.
Write protection prohibits self-write and erase to a
portion or all of the Flash program memory as defined
by the bits WRT<1:0>. Write protection does not affect
a device programmers ability to read, write or erase the
device.
PMCON1 is the control register for Flash program

memory accesses.
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set, in
software. They are cleared by hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.
The WREN bit, when set, will allow a write operation to
occur. On power-up, the WREN bit is clear. The
WRERR bit is set when a write operation is interrupted
by a Reset during normal operation. In these situations,
following Reset, the user can check the WRERR bit
and execute the appropriate error handling routine.
The PMCON2 register is a write-only register. Attempting
to read the PMCON2 register will return all 0s.
To enable writes to the program memory, a specific
pattern (the unlock sequence), must be written to the
PMCON2 register. The required unlock sequence
prevents inadvertent writes to the program memory
write latches and Flash program memory.
11.2
After a row has been erased, the user can reprogram

all or a portion of this row. Data to be written into the
program memory row is written to 14-bit wide data write
latches. These write latches are not directly accessible
to the user, but may be loaded via sequential writes to
the PMDATH:PMDATL register pair.
Note:
PMADRL and PMADRH Registers
The PMADRH:PMADRL register pair can address up

to a maximum of 32K words of program memory. When
selecting a program address value, the MSB of the
address is written to the PMADRH register and the LSB
is written to the PMADRL register.
DS41639A-page 112
Flash Program Memory Overview
It is important to understand the Flash program memory

structure for erase and programming operations. Flash
program memory is arranged in rows. A row consists of
a fixed number of 14-bit program memory words. A row
is the minimum size that can be erased by user software.
Note 1: Code protection of the entire Flash

program memory array is enabled by
clearing the CP bit of Configuration Words.
11.1
PMCON1 AND PMCON2

REGISTERS
If the user wants to modify only a portion

of a previously programmed row, then the
contents of the entire row must be read
and saved in RAM prior to the erase.
Then, new data and retained data can be
written into the write latches to reprogram
the row of Flash program memory. However, any unprogrammed locations can be
written without first erasing the row. In this
case, it is not necessary to save and
rewrite the other previously programmed
locations.
See Table 11-1 for Erase Row size and the number of
write latches for Flash program memory.
Preliminary
PIC16(L)F1454/5/9
TABLE 11-1:
FLASH MEMORY
ORGANIZATION BY DEVICE
Device
PIC16(L)F1454/5/9
11.2.1
Row Erase
(words)
Write
Latches
(words)
32
32
FIGURE 11-1:
READING THE FLASH PROGRAM

MEMORY
FLASH PROGRAM
MEMORY READ
FLOWCHART
Start
Read Operation
Select
Program or Configuration Memory
(CFGS)
To read a program memory location, the user must:

1.
2.
3.
Write
the
desired
address
to
the
PMADRH:PMADRL register pair.
Clear the CFGS bit of the PMCON1 register.
Then, set control bit RD of the PMCON1 register.
Once the read control bit is set, the program memory

Flash controller will use the second instruction cycle to
read the data. This causes the second instruction
immediately following the BSF PMCON1,RD instruction
to be ignored. The data is available in the very next cycle,
in the PMDATH:PMDATL register pair; therefore, it can
be read as two bytes in the following instructions.
PMDATH:PMDATL register pair will hold this value until
another read or until it is written to by the user.
Note:
The two instructions following a program

memory read are required to be NOPs.
This prevents the user from executing a
two-cycle instruction on the next
instruction after the RD bit is set.
Select
Word Address
(PMADRH:PMADRL)
Initiate Read operation

(RD = 1)
Instruction Fetched ignored

NOP execution forced

Data read now in

PMDATH:PMDATL
End
Read Operation
Preliminary
DS41639A-page 113
PIC16(L)F1454/5/9
FIGURE 11-2:
FLASH PROGRAM MEMORY READ CYCLE EXECUTION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
Flash ADDR
Flash Data
PC + 1
INSTR (PC)
INSTR(PC - 1)
executed here
PC
+3
PC+3
PMADRH,PMADRL
INSTR (PC + 1)
BSF PMCON1,RD
executed here
PMDATH,PMDATL
INSTR(PC + 1)
instruction ignored
Forced NOP
executed here
PC + 4
INSTR (PC + 3)
INSTR(PC + 2)
instruction ignored
Forced NOP
executed here
PC + 5
INSTR (PC + 4)
INSTR(PC + 3)
executed here
INSTR(PC + 4)
executed here
RD bit
PMDATH
PMDATL
Register
EXAMPLE 11-1:
FLASH PROGRAM MEMORY READ
* This code block will read 1 word of program

* memory at the memory address:
PROG_ADDR_HI: PROG_ADDR_LO
*
data will be returned in the variables;
*
PROG_DATA_HI, PROG_DATA_LO
BANKSEL
MOVLW
MOVWF
MOVLW
MOVWF
PMADRL
PROG_ADDR_LO
PMADRL
PROG_ADDR_HI
PMADRH
; Select Bank for PMCON registers

;
; Store LSB of address
;
; Store MSB of address
BCF
BSF
NOP
NOP
PMCON1,CFGS
PMCON1,RD
;
;
;
;
Do not select Configuration Space

Initiate read
Ignored (Figure 11-2)
Ignored (Figure 11-2)
MOVF
MOVWF
MOVF
MOVWF
PMDATL,W
PROG_DATA_LO
PMDATH,W
PROG_DATA_HI
;
;
;
;
Get LSB of word

Store in user location
Get MSB of word
DS41639A-page 114
Preliminary
PIC16(L)F1454/5/9
11.2.2
FLASH MEMORY UNLOCK

SEQUENCE
FIGURE 11-3:
The unlock sequence is a mechanism that protects the

Flash program memory from unintended self-write programming or erasing. The sequence must be executed
and completed without interruption to successfully
complete any of the following operations:
Row Erase
Load program memory write latches
Write of program memory write latches to program memory
Write of program memory write latches to User
IDs
FLASH PROGRAM
MEMORY UNLOCK
SEQUENCE FLOWCHART
Start
Unlock Sequence
Write 055h to
PMCON2
The unlock sequence consists of the following steps:
Write 0AAh to
PMCON2
1. Write 55h to PMCON2

Initiate
Write or Erase operation
(WR = 1)
2. Write AAh to PMCON2

3. Set the WR bit in PMCON1
4. NOP instruction
5. NOP instruction
Once the WR bit is set, the processor will always force
two NOP instructions. When an Erase Row or Program
Row operation is being performed, the processor will stall
internal operations (typical 2 ms), until the operation is
complete and then resume with the next instruction.
When the operation is loading the program memory write
latches, the processor will always force the two NOP
instructions and continue uninterrupted with the next
instruction.


End
Unlock Sequence
Since the unlock sequence must not be interrupted,

global interrupts should be disabled prior to the unlock
sequence and re-enabled after the unlock sequence is
completed.
Preliminary
DS41639A-page 115
PIC16(L)F1454/5/9
11.2.3
ERASING FLASH PROGRAM

MEMORY
FIGURE 11-4:
While executing code, program memory can only be

erased by rows. To erase a row:
1.
2.
3.
4.
5.
Load the PMADRH:PMADRL register pair with

any address within the row to be erased.
Set the FREE and WREN bits of the PMCON1
register.
Write 55h, then AAh, to PMCON2 (Flash
programming unlock sequence).
Set control bit WR of the PMCON1 register to
begin the erase operation.
See Example 11-2.

After the BSF PMCON1,WR instruction, the processor
requires two cycles to set up the erase operation. The
user must place two NOP instructions immediately following the WR bit set instruction. The processor will
halt internal operations for the typical 2 ms erase time.
This is not Sleep mode as the clocks and peripherals
will continue to run. After the erase cycle, the processor
will resume operation with the third instruction after the
PMCON1 write instruction.
FLASH PROGRAM
MEMORY ERASE
FLOWCHART
Start
Erase Operation
Disable Interrupts
(GIE = 0)
Select
Program or Configuration Memory
(CFGS)
Select Row Address

(PMADRH:PMADRL)
Select Erase Operation

(FREE = 1)
Enable Write/Erase Operation

(WREN = 1)
Unlock Sequence
Figure 11-3
(FIGURE
x-x)
CPU stalls while

Erase operation completes
(2ms typical)
Disable Write/Erase Operation

(WREN = 0)
Re-enable Interrupts
(GIE = 1)
End
Erase Operation
DS41639A-page 116
Preliminary
PIC16(L)F1454/5/9
EXAMPLE 11-2:
ERASING ONE ROW OF PROGRAM MEMORY
Required
Sequence
; This row erase routine assumes the following:

; 1. A valid address within the erase row is loaded in ADDRH:ADDRL
; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)
BCF
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
BCF
BSF
BSF
INTCON,GIE
PMADRL
ADDRL,W
PMADRL
ADDRH,W
PMADRH
PMCON1,CFGS
PMCON1,FREE
PMCON1,WREN
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
NOP
55h
PMCON2
0AAh
PMCON2
PMCON1,WR
BCF
BSF
PMCON1,WREN
INTCON,GIE
; Disable ints so required sequences will execute properly

; Load lower 8 bits of erase address boundary
; Load upper 6 bits of erase address boundary
; Not configuration space
; Specify an erase operation
; Enable writes
;
;
;
;
;
;
;
;
;
;
Start of required sequence to initiate erase

Write 55h
Write AAh
Set WR bit to begin erase
NOP instructions are forced as processor starts
row erase of program memory.
The processor stalls until the erase process is complete
after erase processor continues with 3rd instruction
; Disable writes
; Enable interrupts
Preliminary
DS41639A-page 117
PIC16(L)F1454/5/9
11.2.4
WRITING TO FLASH PROGRAM

MEMORY
Program memory is programmed using the following

steps:
1.
2.
3.
4.
Load the address in PMADRH:PMADRL of the

row to be programmed.
Load each write latch with data.
Initiate a programming operation.
Repeat steps 1 through 3 until all data is written.
The following steps should be completed to load the

write latches and program a row of program memory.
These steps are divided into two parts. First, each write
latch is loaded with data from the PMDATH:PMDATL
using the unlock sequence with LWLO = 1. When the
last word to be loaded into the write latch is ready, the
LWLO bit is cleared and the unlock sequence
executed. This initiates the programming operation,
writing all the latches into Flash program memory.
Note:
Before writing to program memory, the word(s) to be

written must be erased or previously unwritten. Program memory can only be erased one row at a time. No
automatic erase occurs upon the initiation of the write.
Program memory can be written one or more words at
a time. The maximum number of words written at one
time is equal to the number of write latches. See
Figure 11-5 (row writes to program memory with 32
write latches) for more details.
The write latches are aligned to the Flash row address
boundary defined by the upper 10-bits of
PMADRH:PMADRL, (PMADRH<6:0>:PMADRL<7:5>)
with the lower 5-bits of PMADRL, (PMADRL<4:0>)
determining the write latch being loaded. Write operations do not cross these boundaries. At the completion
of a program memory write operation, the data in the
write latches is reset to contain 0x3FFF.
The special unlock sequence is required

to load a write latch with data or initiate a
Flash programming operation. If the
unlock sequence is interrupted, writing to
the latches or program memory will not be
initiated.
1.
2.
3.
Set the WREN bit of the PMCON1 register.

Set the LWLO bit of the PMCON1 register.
When the LWLO bit of the PMCON1 register is
1, the write sequence will only load the write
latches and will not initiate the write to Flash
program memory.
4. Load the PMADRH:PMADRL register pair with
the address of the location to be written.
5. Load the PMDATH:PMDATL register pair with
the program memory data to be written.
6. Execute the unlock sequence (Section 11.2.2
Flash Memory Unlock Sequence). The write
latch is now loaded.
7. Increment the PMADRH:PMADRL register pair
to point to the next location.
8. Repeat steps 5 through 7 until all but the last
write latch has been loaded.
9. Clear the LWLO bit of the PMCON1 register.
When the LWLO bit of the PMCON1 register is
0, the write sequence will initiate the write to
Flash program memory.
10. Load the PMDATH:PMDATL register pair with
the program memory data to be written.
11. Execute the unlock sequence (Section 11.2.2
Flash Memory Unlock Sequence). The
entire program memory latch content is now
written to Flash program memory.
Note:
The program memory write latches are

reset to the blank state (0x3FFF) at the
completion of every write or erase
operation. As a result, it is not necessary
to load all the program memory write
latches. Unloaded latches will remain in
the blank state.
An example of the complete write sequence is shown in

Example 11-3. The initial address is loaded into the
PMADRH:PMADRL register pair; the data is loaded
using indirect addressing.
DS41639A-page 118
Preliminary
r10
BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES
0 7
5 4
PMADRH
r9
r8
r7
r6
PMADRL
r5
r4
r3
r2
r1
r0
c3
c2
c1
PMDATH
6
c0
0
PMDATL
8
14
10
Program Memory Write Latches
14
Write Latch #0
00h
PMADRL<4:0>
14
Write Latch #1
01h
Preliminary
14
CFGS = 0
PMADRH<6:0>
:PMADRL<7:4>
Row
Address
Decode
14
14
Write Latch #30 Write Latch #31

1Eh
1Fh
14
14
14
Row
Addr
Addr
Addr
Addr
000h
0000h
0001h
001Eh
001Fh
001h
0010h
0011h
003Eh
003Fh
002h
0020h
0021h
005Eh
005Fh
7FEh
7FE0h
7FE1h
7FDEh
7FDFh
7FFh
7FF0h
7FF1h
7FFEh
7FFFh
Flash Program Memory
800h
8000h - 8003h
USER ID 0 - 3
CFGS = 1
8004h
reserved
8005h
REVID
8006h
8007h 8008h
8009h - 801Fh
DEVID
Configuration
Words
reserved
Configuration Memory
PIC16(L)F1454/5/9
DS41639A-page 119
FIGURE 11-5:
PIC16(L)F1454/5/9
FIGURE 11-6:
FLASH PROGRAM MEMORY WRITE FLOWCHART
Start
Write Operation
Determine number of words

to be written into Program or
Configuration Memory.
The number of words cannot
exceed the number of words
per row.
(word_cnt)
Disable Interrupts
(GIE = 0)
Select
Program or Config. Memory
(CFGS)
Select Row Address

(PMADRH:PMADRL)
Enable Write/Erase
Operation (WREN = 1)
Load the value to write

(PMDATH:PMDATL)
Update the word counter

(word_cnt--)
Last word to
write ?
Yes
No
Unlock Sequence
(Figure11-3
x-x)
Figure
Select Write Operation

(FREE = 0)
No delay when writing to
Program Memory Latches
Load Write Latches Only
(LWLO = 1)
Increment Address
(PMADRH:PMADRL++)
Write Latches to Flash

(LWLO = 0)
Unlock Sequence
(Figure11-3
x-x)
Figure
CPU stalls while Write

operation completes
(2ms typical)
Disable
Write/Erase Operation
(WREN = 0)
Re-enable Interrupts
(GIE = 1)
End
Write Operation
DS41639A-page 120
Preliminary
PIC16(L)F1454/5/9
EXAMPLE 11-3:
;
;
;
;
;
;
;
WRITING TO FLASH PROGRAM MEMORY
This write routine assumes the following:

1. 64 bytes of data are loaded, starting at the address in DATA_ADDR
2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR,
stored in little endian format
3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL
4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)
BCF
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BCF
BSF
BSF
INTCON,GIE
PMADRH
ADDRH,W
PMADRH
ADDRL,W
PMADRL
LOW DATA_ADDR
FSR0L
HIGH DATA_ADDR
FSR0H
PMCON1,CFGS
PMCON1,WREN
PMCON1,LWLO
;
;
;
;
;
;
;
;
;
;
;
;
;
Disable ints so required sequences will execute properly

Bank 3
Load initial address
MOVIW
MOVWF
MOVIW
MOVWF
FSR0++
PMDATL
FSR0++
PMDATH
; Load first data byte into lower

;
; Load second data byte into upper
;
MOVF
XORLW
ANDLW
BTFSC
GOTO
PMADRL,W
0x1F
0x1F
STATUS,Z
START_WRITE
; Check if lower bits of address are '00000'

; Check if we're on the last of 32 addresses
;
; Exit if last of 32 words,
;
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
55h
PMCON2
0AAh
PMCON2
PMCON1,WR
;
;
;
;
;
;
;
;
PMADRL,F
LOOP
; Still loading latches Increment address

; Write next latches
PMCON1,LWLO
; No more loading latches - Actually start Flash program

; memory write
55h
PMCON2
0AAh
PMCON2
PMCON1,WR
;
;
;
;
;
;
;
;
;
;
;
;
;
Load initial data address

Load initial data address
Not configuration space
Enable writes
Only Load Write Latches
Required
Sequence
LOOP
NOP
INCF
GOTO
Required
Sequence
START_WRITE
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
NOP
BCF
BSF
PMCON1,WREN
INTCON,GIE
Start of required write sequence:

Write 55h
Write AAh
Set WR bit to begin write
NOP instructions are forced as processor
loads program memory write latches
Start of required write sequence:

Write 55h
Write AAh
Set WR bit to begin write
NOP instructions are forced as processor writes
all the program memory write latches simultaneously
to program memory.
After NOPs, the processor
stalls until the self-write process in complete
after write processor continues with 3rd instruction
Disable writes
Enable interrupts
Preliminary
DS41639A-page 121
PIC16(L)F1454/5/9
11.3
Modifying Flash Program Memory
FIGURE 11-7:
When modifying existing data in a program memory

row, and data within that row must be preserved, it must
first be read and saved in a RAM image. Program
memory is modified using the following steps:
1.
2.
3.
4.
5.
6.
7.
Load the starting address of the row to be

modified.
Read the existing data from the row into a RAM
image.
Modify the RAM image to contain the new data
to be written into program memory.
Load the starting address of the row to be
rewritten.
Erase the program memory row.
Load the write latches with data from the RAM
image.
Initiate a programming operation.
FLASH PROGRAM
MEMORY MODIFY
FLOWCHART
Start
Modify Operation
Read Operation
(Figure11-2
x.x)
Figure
An image of the entire row read

must be stored in RAM
Modify Image
The words to be modified are
changed in the RAM image
Erase Operation
(Figure11-4
x.x)
Figure
WRITE Operation
use RAM image
(Figure11-5
x.x)
Figure
End
Modify Operation
DS41639A-page 122
Preliminary
PIC16(L)F1454/5/9
11.4
User ID, Device ID and

Configuration Word Access
Instead of accessing program memory, the User IDs,

Device ID/Revision ID and Configuration Words can be
accessed when CFGS = 1 in the PMCON1 register.
This is the region that would be pointed to by
PC<15> = 1, but not all addresses are accessible.
Different access may exist for reads and writes. Refer
to Table 11-2.
When read access is initiated on an address outside
the
parameters
listed
in
Table 11-2,
the
PMDATH:PMDATL register pair is cleared, reading
back 0s.
TABLE 11-2:
USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS = 1)
Address
Function
Read Access
Write Access
8000h-8003h
8005h-8006h
8007h-8008h
User IDs
Revision ID-Device ID
Configuration Words 1 and 2
Yes
Yes
Yes
Yes
No
No
EXAMPLE 11-4:
CONFIGURATION WORD AND DEVICE ID ACCESS
* This code block will read 1 word of program memory at the memory address:
*
PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables;
*
PROG_DATA_HI, PROG_DATA_LO
BANKSEL
MOVLW
MOVWF
CLRF
PMADRL
PROG_ADDR_LO
PMADRL
PMADRH
; Select correct Bank

;
; Store LSB of address
; Clear MSB of address
BSF
BCF
BSF
NOP
NOP
BSF
PMCON1,CFGS
INTCON,GIE
PMCON1,RD
INTCON,GIE
;
;
;
;
;
;
Select Configuration Space

Disable interrupts
Initiate read
Executed (See Figure 11-2)
Ignored (See Figure 11-2)
Restore interrupts
MOVF
MOVWF
MOVF
MOVWF
PMDATL,W
PROG_DATA_LO
PMDATH,W
PROG_DATA_HI
;
;
;
;
Get LSB of word

Get MSB of word
Preliminary
DS41639A-page 123
PIC16(L)F1454/5/9
11.5
Write Verify
It is considered good programming practice to verify that

program memory writes agree with the intended value.
Since program memory is stored as a full page then the
stored program memory contents are compared with the
intended data stored in RAM after the last write is
complete.
FIGURE 11-8:
FLASH PROGRAM
MEMORY VERIFY
FLOWCHART
Start
Verify Operation
This routine assumes that the last row

of data written was from an image
saved in RAM. This image will be used
to verify the data currently stored in
Flash Program Memory.
Read Operation
(Figure
x.x)
Figure
11-2
PMDAT =
RAM image
?
Yes
No
No
Fail
Verify Operation
Last
Word ?
Yes
End
Verify Operation
DS41639A-page 124
Preliminary
PIC16(L)F1454/5/9
11.6
Register Definitions: Flash Program Memory Control
REGISTER 11-1:
R/W-x/u
PMDATL: PROGRAM MEMORY DATA LOW BYTE REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
PMDAT<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
PMDAT<7:0>: Read/write value for Least Significant bits of program memory
REGISTER 11-2:
PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER
U-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
PMDAT<13:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-0
PMDAT<13:8>: Read/write value for Most Significant bits of program memory
Preliminary
DS41639A-page 125
PIC16(L)F1454/5/9
REGISTER 11-3:
R/W-0/0
PMADRL: PROGRAM MEMORY ADDRESS LOW BYTE REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PMADR<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
PMADR<7:0>: Specifies the Least Significant bits for program memory address
REGISTER 11-4:
U-1(1)
PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PMADR<14:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-0
Note 1:
PMADR<14:8>: Specifies the Most Significant bits for program memory address
Unimplemented bit, read as 1.
DS41639A-page 126
Preliminary
PIC16(L)F1454/5/9
REGISTER 11-5:
PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER
U-1(1)
R/W-0/0
R/W-0/0
CFGS
LWLO
R/W/HC-0/0 R/W/HC-x/q(2)
FREE
WRERR
R/W-0/0
R/S/HC-0/0
R/S/HC-0/0
WREN
WR
RD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
S = Bit can only be set
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
CFGS: Configuration Select bit

1 = Access Configuration, User ID and Device ID Registers
0 = Access Flash program memory
bit 5
LWLO: Load Write Latches Only bit(3)

1 = Only the addressed program memory write latch is loaded/updated on the next WR command
0 = The addressed program memory write latch is loaded/updated and a write of all program memory
write latches will be initiated on the next WR command
bit 4
FREE: Program Flash Erase Enable bit

1 = Performs an erase operation on the next WR command (hardware cleared upon completion)
0 = Performs a write operation on the next WR command
bit 3
WRERR: Program/Erase Error Flag bit

1 = Condition indicates an improper program or erase sequence attempt or termination (bit is set
automatically on any set attempt (write 1) of the WR bit).
0 = The program or erase operation completed normally.
bit 2
WREN: Program/Erase Enable bit

1 = Allows program/erase cycles
0 = Inhibits programming/erasing of program Flash
bit 1
WR: Write Control bit

1 = Initiates a program Flash program/erase operation.
The operation is self-timed and the bit is cleared by hardware once operation is complete.
The WR bit can only be set (not cleared) in software.
0 = Program/erase operation to the Flash is complete and inactive.
bit 0
RD: Read Control bit

1 = Initiates a program Flash read. Read takes one cycle. RD is cleared in hardware. The RD bit can
only be set (not cleared) in software.
0 = Does not initiate a program Flash read.
Note 1:
2:
3:
Unimplemented bit, read as 1.

The WRERR bit is automatically set by hardware when a program memory write or erase operation is
started (WR = 1).
The LWLO bit is ignored during a program memory erase operation (FREE = 1).
Preliminary
DS41639A-page 127
PIC16(L)F1454/5/9
REGISTER 11-6:
W-0/0
PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER

W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
Program Memory Control Register 2

bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
S = Bit can only be set
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
Flash Memory Unlock Pattern bits

To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the
PMCON1 register. The value written to this register is used to unlock the writes. There are specific
timing requirements on these writes.
TABLE 11-3:
SUMMARY OF REGISTERS ASSOCIATED WITH FLASH PROGRAM MEMORY

Register on
Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
96
CFGS
LWLO
FREE
WRERR
WREN
WR
RD
127
(1)
PMCON1
PMCON2
Program Memory Control Register 2
128
PMADRL
PMADRL<7:0>
126
(1)
PMADRH
PMADRH<6:0>
PMDATL
PMDATH
Legend:
Note 1:
CONFIG1
CONFIG2
Legend:
125
PMDATH<5:0>
125
= unimplemented location, read as 0. Shaded cells are not used by Flash program memory.
TABLE 11-4:
Name
126
PMDATL<7:0>
SUMMARY OF CONFIGURATION WORD WITH FLASH PROGRAM MEMORY
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
IESO
CLKOUTEN
13:8
FCMEN
7:0
CP
MCLRE
PWRTE
13:8
LVP
7:0
PLLMULT USBLSCLK
Bit 10/2
FOSC<2:0>
LPBOR
BORV
CPUDIV<1:0>
Bit 8/0
BOREN<1:0>
WDTE<1:0>
DEBUG
Bit 9/1
STVREN
PLLEN
WRT<1:0>
Register
on Page
52
54
= unimplemented location, read as 0. Shaded cells are not used by Flash program memory.
DS41639A-page 128
Preliminary
PIC16(L)F1454/5/9
12.0
I/O PORTS
FIGURE 12-1:
GENERIC I/O PORT

OPERATION
Each port has three standard registers for its operation.

These registers are:
TRISx registers (data direction)
PORTx registers (reads the levels on the pins of
the device)
LATx registers (output latch)
Read LATx
D
Some ports may have one or more of the following

additional registers. These registers are:
Write LATx
Write PORTx
ANSELx (analog select)

WPUx (weak pull-up)
CK
VDD
Data Register
In general, when a peripheral is enabled on a port pin,

that pin cannot be used as a general purpose output.
However, the pin can still be read.
Data Bus
I/O pin
Read PORTx
To peripherals
ANSELx
PIC16(L)F1454/5
PIC16(L)F1459
PORTC
Device
PORTB
PORT AVAILABILITY PER

DEVICE
PORTA
TABLE 12-1:
TRISx
The Data Latch (LATx registers) is useful for

read-modify-write operations on the value that the I/O
pins are driving.
A write operation to the LATx register has the same
effect as a write to the corresponding PORTx register.
A read of the LATx register reads of the values held in
the I/O PORT latches, while a read of the PORTx
register reads the actual I/O pin value.
EXAMPLE 12-1:
;
;
;
;
VSS
INITIALIZING PORTA
This code example illustrates

initializing the PORTA register. The
other ports are initialized in the same
manner.
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
MOVLW
MOVWF
PORTA
PORTA
LATA
LATA
ANSELA
ANSELA
TRISA
B'00111000'
TRISA
;
;Init PORTA
;Data Latch
;
;
;digital I/O
;
;Set RA<5:3> as inputs
;and set RA<2:0> as
;outputs
Ports that support analog inputs have an associated

ANSELx register. When an ANSEL bit is set, the digital
input buffer associated with that bit is disabled.
Disabling the input buffer prevents analog signal levels
on the pin between a logic high and low from causing
excessive current in the logic input circuitry. A
simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 12-1.
Preliminary
DS41639A-page 129
PIC16(L)F1454/5/9
12.1
Alternate Pin Function
The Alternate Pin Function Control register is used to

steer specific peripheral input and output functions
between different pins. The APFCON register is shown
in Register 12-1. For this device family, the following
functions can be moved between different pins.
CLKR
SDO
SS
T1G
P2
These bits have no effect on the values of any TRIS

register. PORT and TRIS overrides will be routed to the
correct pin. The unselected pin will be unaffected.
12.2
Register Definitions: Alternate Pin Function Control
REGISTER 12-1:
R/W-0/0
CLKRSEL
APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER
R/W-0/0
SDOSEL
(1)
R/W-0/0
SSSEL
U-0
R/W-0/0
R/W-0/0
U-0
U-0
T1GSEL
P2SEL(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
CLKRSEL: Pin Selection bit

1 = CLKR function is on RC3
0 = CLKR function is on RA4
bit 6
SDOSEL: Pin Selection bit(1)

1 = SDO function is on RA4
0 = SDO function is on RC2
bit 5
SSSEL: Pin Selection bit

For 14-Pin Devices (PIC16(L)F1454/5):
1 = SS function is on RA3
0 = SS function is on RC3
For 20-Pin Devices (PIC16(L)F1455/9):
1 = SS function is on RA3
0 = SS function is on RC6
bit 4
bit 3
T1GSEL: Pin Selection bit

1 = T1G function is on RA3
bit 2
P2SEL: Pin Selection bit(1)

0 = T1G function is on RC3
bit 1-0
Note 1:
DS41639A-page 130
Preliminary
PIC16(L)F1454/5/9
12.3
12.3.1
PORTA Registers
EXAMPLE 12-2:
DATA REGISTER
PORTA is a 5-bit wide, bidirectional port. The

corresponding data direction register is TRISA
(Register 12-3). Setting a TRISA bit (= 1) will make the
corresponding PORTA pin an input (i.e., disable the
output driver). Clearing a TRISA bit (= 0) will make the
corresponding PORTA pin an output (i.e., enables
output driver and puts the contents of the output latch
on the selected pin). The exception is RA0, RA1 and
RA3, which are input only and its TRIS bit will always
read as 1. Example 12-2 shows how to initialize an I/O
port.
Reading the PORTA register (Register 12-2) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then
written to the PORT data latch (LATA).
12.3.2
DIRECTION CONTROL
The TRISA register (Register 12-3) controls the

PORTA pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits
in the TRISA register are maintained set when using
them as analog inputs. I/O pins configured as analog
input always read 0.
12.3.3
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
MOVLW
MOVWF
12.3.4
PORTA FUNCTIONS AND OUTPUT

PRIORITIES
Analog input functions, such as ADC and comparator

inputs, are not shown in the priority lists. These inputs
are active when the I/O pin is set for Analog mode using
the ANSELx registers. Digital output functions may
control the pin when it is in Analog mode with the
priority shown below in Table 12-2.
TABLE 12-2:
Pin Name
The state of the ANSELA bits has no effect on digital

output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
The ANSELA bits default to the Analog
mode after Reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSEL bits
must be initialized to 0 by user software.
;
;Init PORTA
;Data Latch
;
;
;digital I/O
;
;Set RA<5:3> as inputs
;and set RA<2:0> as
;outputs
When multiple outputs are enabled, the actual pin

control goes to the peripheral with the highest priority.
ANALOG CONTROL
PORTA
PORTA
LATA
LATA
ANSELA
ANSELA
TRISA
B'00111000'
TRISA
Each PORTA pin is multiplexed with other functions. The

pins, their combined functions and their output priorities
are shown in Table 12-2.
The ANSELA register (Register 12-5) is used to

configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELA bit high will cause all
digital reads on the pin to be read as 0 and allow
analog functions on the pin to operate correctly.
Note:
INITIALIZING PORTA
Note 1:
2:
3:
4:
Preliminary
PORTA OUTPUT PRIORITY

Function Priority(1)
RA0
ICSPDAT(4)
RA1
ICSPCLK(4)
RA2
VUSB3V3
RA3
None
RA4
CLKOUT
SOSCO
CLKR(2)
SDO(3)
RA4
RA5
PWM2(3)
RA5
Priority listed from highest to lowest.

Default pin (see APFCON register).
Alternate pin (see APFCON register).
LVP only.
DS41639A-page 131
PIC16(L)F1454/5/9
12.4
Register Definitions: PORTA
REGISTER 12-2:
PORTA: PORTA REGISTER
U-0
U-0
R/W-x/x
R/W-x/x
R-x/x
U-0
R-x/x
R-x/x
RA5
RA4
RA3
RA1
RA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-3
RA<5:3>: PORTA I/O Value bits(1)

1 = Port pin is > VIH
0 = Port pin is < VIL
bit 2
bit 1-0
RA<1:0>: PORTA I/O Value bits(1)

Note 1:
Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return
of actual I/O pin values.
REGISTER 12-3:
U-0
TRISA: PORTA TRI-STATE REGISTER

U-0
R/W-1/1
TRISA5
R/W-1/1
U-1
TRISA4
(1)
U-0
U-1
U-1
(1)
(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-4
TRISA<5:4>: PORTA Tri-State Control bit

1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
bit 3
bit 2
bit 1-0
Note 1:
DS41639A-page 132
Preliminary
PIC16(L)F1454/5/9
REGISTER 12-4:
LATA: PORTA DATA LATCH REGISTER
U-0
U-0
R/W-x/u
R/W-x/u
U-0
U-0
U-0
U-0
LATA5
LATA4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-4
LATA<5:4>: RA<5:4> Output Latch Value bits(1)
bit 3-0
Note 1:
Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return
of actual I/O pin values.
ANSELA: PORTA ANALOG SELECT REGISTER(2)
REGISTER 12-5:
U-0
U-0
U-0
R/W-1/1
U-0
U-0
U-0
U-0
ANSA4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-5
bit 4
ANSA4: Analog Select between Analog or Digital Function on pins RA4, respectively
1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
0 = Digital I/O. Pin is assigned to port or digital special function.
bit 3-0
Note 1:
2:
When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
Preliminary
DS41639A-page 133
PIC16(L)F1454/5/9
REGISTER 12-6:
WPUA: WEAK PULL-UP PORTA REGISTER
U-0
U-0
R/W-1/1
R/W-1/1
R/W-1/1
U-0
U-0
U-0
WPUA5
WPUA4
WPUA3
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-3
WPUA<5:3>: Weak Pull-up Register bits(3)

1 = Pull-up enabled
0 = Pull-up disabled
bit 2-0
Note 1:
2:
3:
Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
The weak pull-up device is automatically disabled if the pin is configured as an output.
For the WPUA3 bit, when MCLRE = 1, weak pull-up is internally enabled, but not reported here.
TABLE 12-3:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name
Bit 7
ANSELA(3)
APFCON
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSA4
133
CLKRSEL
SDOSEL(2)
SSSEL
T1GSEL
P2SEL(2)
130
LATA5
LATA4
133
LATA
WPUEN
INTEDG
TMR0CS
TMR0SE
PSA
PORTA
RA5
RA4
RA3
RA1
RA0
132
TRISA
TRISA5
TRISA4
(1)
(1)
(1)
132
WPUA
WPUA5
WPUA4
WPUA3
134
OPTION_REG
Legend:
Note 1:
2:
3:
CONFIG1
Legend:
185
x = unknown, u = unchanged, = unimplemented locations read as 0. Shaded cells are not used by PORTA.
TABLE 12-4:
Name
PS<2:0>
SUMMARY OF CONFIGURATION WORD WITH PORTA
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
IESO
CLKOUTEN
13:8
FCMEN
7:0
CP
MCLRE
PWRTE
Bit 10/2
WDTE<1:0>
Bit 9/1
BOREN<1:0>
FOSC<2:0>
Bit 8/0
Register
on Page
52
= unimplemented location, read as 0. Shaded cells are not used by PORTA.
DS41639A-page 134
Preliminary
PIC16(L)F1454/5/9
12.5
12.5.1
PORTB Registers
(PIC16(L)F1455/9 only)
12.5.4
DATA REGISTER
PORTB is a 4-bit wide, bidirectional port. The

corresponding data direction register is TRISB
(Register 12-3). Setting a TRISB bit (= 1) will make the
corresponding PORTB pin an input (i.e., disable the
output driver). Clearing a TRISB bit (= 0) will make the
corresponding PORTB pin an output (i.e., enables
output driver and puts the contents of the output latch
on the selected pin). Example 12-2 shows how to
initialize an I/O port.
Reading the PORTB register (Register 12-2) reads the
port pins are read, this value is modified and then
written to the PORT data latch (LATB).
12.5.2
Each PORTB pin is multiplexed with other functions. The

Analog input functions, such as ADC and comparator
inputs, are not shown in the priority lists. These inputs
are active when the I/O pin is set for Analog mode using
the ANSELx registers. Digital output functions may
control the pin when it is in Analog mode with the
priority shown below in Table 12-2.
TABLE 12-5:
DIRECTION CONTROL
ANALOG CONTROL
The ANSELB register (Register 12-5) is used to

Setting the appropriate ANSELB bit high will cause all
PORTB OUTPUT PRIORITY

Pin Name
The TRISB register (Register 12-3) controls the

PORTB pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits
in the TRISB register are maintained set when using
them as analog inputs. I/O pins configured as analog
input always read 0.
12.5.3
PORTB FUNCTIONS AND OUTPUT

PRIORITIES
RB4
SDA
RB4
RB5
RX
RB5
RB6
SCL
SCK
RB6
RB7
TX
RB7
Note 1:
2:
3:

The state of the ANSELB bits has no effect on digital

output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
Note:
The ANSELB bits default to the Analog

Preliminary
DS41639A-page 135
PIC16(L)F1454/5/9
12.6
Register Definitions: PORTB
REGISTER 12-7:
PORTB: PORTB REGISTER
R/W-x/x
R/W-x/x
R/W-x/x
R/W-x/x
U-0
U-0
U-0
U-0
RB7
RB6
RB5
RB4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
RB<7:4>: PORTB I/O Value bits(1)

bit 3-0
Note 1:
Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is
return of actual I/O pin values.
REGISTER 12-8:
TRISB: PORTB TRI-STATE REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
U-0
U-0
U-0
U-0
TRISB7
TRISB6
TRISB5
TRISB4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
TRISB<7:4>: PORTB Tri-State Control bits

1 = PORTB pin configured as an input (tri-stated)
0 = PORTB pin configured as an output
bit 3-0
DS41639A-page 136
Preliminary
PIC16(L)F1454/5/9
REGISTER 12-9:
LATB: PORTB DATA LATCH REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
U-0
U-0
U-0
U-0
LATB7
LATB6
LATB5
LATB4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
LATB<7:4>: RB<7:4> Output Latch Value bits(1)
bit 3-0
Note 1:
Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is
REGISTER 12-10: ANSELB: PORTB ANALOG SELECT REGISTER

U-0
U-0
R/W-1/1
R/W-1/1
U-0
U-0
U-0
U-0
ANSB5
ANSB4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-4
ANSB<5:4>: Analog Select between Analog or Digital Function on pins RB<5:4>, respectively
bit 3-0
Note 1:
Preliminary
DS41639A-page 137
PIC16(L)F1454/5/9
REGISTER 12-11: WPUB: WEAK PULL-UP PORTB REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
U-0
U-0
U-0
U-0
WPUB7
WPUB6
WPUB5
WPUB4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
WPUB<7:4>: Weak Pull-up Register bits

1 = Pull-up enabled
0 = Pull-up disabled
bit 3-0
Note 1:
2:
Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
The weak pull-up device is automatically disabled if the pin is configured as an output.
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB(1)
TABLE 12-6:
Name
Bit 7
Bit 6
ANSELB
CLKRSEL
APFCON
LATB
OPTION_REG
SDOSEL
(1)
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSB5
ANSB4
137
130
137
SSSEL
T1GSEL
LATB7
LATB6
LATB5
LATB4
WPUEN
INTEDG
TMR0CS
TMR0SE
PSA
P2SEL
(1)
PS<2:0>
185
PORTB
RB7
RB6
RB5
RB4
136
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
136
WPUB7
WPUB6
WPUB5
WPUB4
138
WPUB
Legend:
Note 1:
x = unknown, u = unchanged, = unimplemented locations read as 0. Shaded cells are not used by PORTB.
PIC16(L)F1459 only.
TABLE 12-7:
Name
CONFIG1
Legend:
SUMMARY OF CONFIGURATION WORD WITH PORTB
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
13:8
FCMEN
IESO
CLKOUTEN
7:0
CP
MCLRE
PWRTE
Bit 10/2
WDTE<1:0>
Bit 9/1
BOREN<1:0>
FOSC<2:0>
Bit 8/0
Register
on Page
52
= unimplemented location, read as 0. Shaded cells are not used by PORTB.
DS41639A-page 138
Preliminary
PIC16(L)F1454/5/9
12.7
12.7.1
PORTC Registers
12.7.4
DATA REGISTER
PORTC is a 8-bit wide, bidirectional port. The

corresponding data direction register is TRISC
(Register 12-13). Setting a TRISC bit (= 1) will make
the corresponding PORTC pin an input (i.e., put the
corresponding output driver in a High-Impedance
mode). Clearing a TRISC bit (= 0) will make the
corresponding PORTC pin an output (i.e., enable the
output driver and put the contents of the output latch
on the selected pin). Example 12-2 shows how to
initialize an I/O port.
Reading the PORTC register (Register 12-12) reads the
port pins are read, this value is modified and then written
to the PORT data latch (LATC).
12.7.2
Each PORTC pin is multiplexed with other functions. The

Analog input and some digital input functions are not
included in the output priority list. These input functions
can remain active when the pin is configured as an
output. Certain digital input functions override other
port functions and are included in the output priority list.
TABLE 12-8:
Pin Name
DIRECTION CONTROL
The TRISC register (Register 12-13) controls the

PORTC pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits in
the TRISC register are maintained set when using them
as analog inputs. I/O pins configured as analog input
always read 0.
12.7.3
ANALOG CONTROL
The ANSELC register (Register 12-15) is used to

Setting the appropriate ANSELC bit high will cause all
The state of the ANSELC bits has no effect on digital output functions. A pin with TRIS clear and ANSELC set will
still operate as a digital output, but the Input mode will be
analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected
port.
Note:
The ANSELC bits default to the Analog

PORTC FUNCTIONS AND OUTPUT

PRIORITIES
RC0
ICSPDAT
SCL(4)
SCK(4)
RC1
ICSPCLK
SDA(4)
SDI(4)
RC1
RC2
DACOUT1
SDO(2)
RC2
RC3
DACOUT2
CLKR(3)
PWM2(2)
RC3
RC4
CWG1B
C1OUT
C2OUT
TX(4)
RC4
RC5
CWG1A
PWM1
RX(4)
RC5
RC6
PWM2(5)
RC6
RC7
SDO(5)
RC7
Note 1:
2:
3:
4:
5:
Preliminary
PORTC OUTPUT PRIORITY

DS41639A-page 139
PIC16(L)F1454/5/9
12.8
Register Definitions: PORTC
REGISTER 12-12: PORTC: PORTC REGISTER

R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
RC7(1)
RC6(1)
RC5
RC4
RC3
RC2
RC1
RC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
Note 1:
RC<7:0>: PORTC General Purpose I/O Pin bits

PIC16(L)F1459 only.
REGISTER 12-13: TRISC: PORTC TRI-STATE REGISTER

R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
TRISC7(1)
TRISC6(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
Note 1:
TRISC<7:0>: PORTC Tri-State Control bits

1 = PORTC pin configured as an input (tri-stated)
0 = PORTC pin configured as an output
PIC16(L)F1459 only.
DS41639A-page 140
Preliminary
PIC16(L)F1454/5/9
REGISTER 12-14: LATC: PORTC DATA LATCH REGISTER
R/W-x/u
R/W-x/u
(1)
(1)
LATC7
LATC6
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
LATC<7:0>: PORTC Output Latch Value bits(1)
bit 7-0
Note 1:
2:
Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is
PIC16(L)F1459 only.
REGISTER 12-15: ANSELC: PORTC ANALOG SELECT REGISTER

R/W-1/1
R/W-1/1
U-0
U-0
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
ANSC7(1)
ANSC6(1)
ANSC3
ANSC2
ANSC1
ANSC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
ANSC<7:6>: Analog Select between Analog or Digital Function on pins RC<7:6>, respectively
bit 5-4
bit 3-0
ANSC<3:0>: Analog Select between Analog or Digital Function on pins RC<3:0>, respectively
Note 1:
2:
PIC16(L)F1459 only.
TABLE 12-9:
Name
ANSELC(2)
LATC
PORTC
TRISC
Legend:
Note 1:
2:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSC7(1)
ANSC6(1)
ANSC3
ANSC2
ANSC1
ANSC0
141
(1)
(1)
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0
141
LATC7
RC7
(1)
LATC6
RC6
(1)
TRISC7(1) TRISC6(1)
RC5
RC4
RC3
RC2
RC1
RC0
140
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
140
x = unknown, u = unchanged, - = unimplemented locations read as 0. Shaded cells are not used by PORTC.
PIC16(L)F1459 only.
Preliminary
DS41639A-page 141
PIC16(L)F1454/5/9
NOTES:
DS41639A-page 142
Preliminary
PIC16(L)F1454/5/9
13.0
INTERRUPT-ON-CHANGE
13.3
The PORTA and PORTB pins can be configured to

operate as Interrupt-On-Change (IOC) pins. An interrupt
can be generated by detecting a signal that has either a
rising edge or a falling edge. Any individual port pin, or
combination of port pins, can be configured to generate
an interrupt. The interrupt-on-change module has the
following features:
Interrupt-on-Change enable (Master Switch)

Individual pin configuration
Rising and falling edge detection
Individual pin interrupt flags
The IOCAFx and IOCBFx bits located in the IOCAF and

IOCBF registers, respectively, are status flags that
correspond to the interrupt-on-change pins of the
associated port. If an expected edge is detected on an
appropriately enabled pin, then the status flag for that pin
will be set, and an interrupt will be generated if the IOCIE
bit is set. The IOCIF bit of the INTCON register reflects
the status of all IOCAFx and IOCBFx bits.
13.4
Clearing Interrupt Flags
The individual status flags, (IOCAFx and IOCBFx bits),

can be cleared by resetting them to zero. If another edge
is detected during this clearing operation, the associated
status flag will be set at the end of the sequence,
regardless of the value actually being written.
Figure 13-1 is a block diagram of the IOC module.
13.1
Interrupt Flags
Enabling the Module
To allow individual port pins to generate an interrupt, the

IOCIE bit of the INTCON register must be set. If the
IOCIE bit is disabled, the edge detection on the pin will
still occur, but an interrupt will not be generated.
In order to ensure that no detected edge is lost while

clearing flags, only AND operations masking out known
changed bits should be performed. The following
sequence is an example of what should be performed.
13.2
Individual Pin Configuration
EXAMPLE 13-1:
For each port pin, a rising edge detector and a falling

edge detector are present. To enable a pin to detect a
rising edge, the associated bit of the IOCxP register is
set. To enable a pin to detect a falling edge, the
associated bit of the IOCxN register is set.
MOVLW
XORWF
ANDWF
A pin can be configured to detect rising and falling

edges simultaneously by setting both associated bits of
the IOCxP and IOCxN registers, respectively.
13.5
CLEARING INTERRUPT
FLAGS
(PORTA EXAMPLE)
0xff
IOCAF, W
IOCAF, F
Operation in Sleep
The interrupt-on-change interrupt sequence will wake

the device from Sleep mode, if the IOCIE bit is set.
If an edge is detected while in Sleep mode, the IOCxF
register will be updated prior to the first instruction
executed out of Sleep.
Preliminary
DS41639A-page 143
PIC16(L)F1454/5/9
FIGURE 13-1:
INTERRUPT-ON-CHANGE BLOCK DIAGRAM (PORTA EXAMPLE)
IOCANx
Q4Q1
CK
Edge
Detect
RAx
IOCAPx
Data Bus =
0 or 1
Write IOCAFx
CK
To Data Bus
IOCAFx
CK
IOCIE
R
Q2
From all other
IOCAFx individual
Pin Detectors
Q1
Q2
Q3
Q4
Q4Q1
DS41639A-page 144
Q1
Q1
Q2
Q2
Q3
Q4
Q4Q1
IOC interrupt
to CPU core
Q3
Q4
Q4
Q4Q1
Preliminary
Q4Q1
PIC16(L)F1454/5/9
13.6
Register Definitions: Interrupt-on-change Control
REGISTER 13-1:
IOCAP: INTERRUPT-ON-CHANGE PORTA POSITIVE EDGE REGISTER
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
R/W-0/0
IOCAP5
IOCAP4
IOCAP3
IOCAP1
IOCAP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-3
IOCAP<5:3>: Interrupt-on-Change PORTA Positive Edge Enable bits

1 = Interrupt-on-Change enabled on the pin for a positive going edge. IOCAFx bit and IOCIF flag will
be set upon detecting an edge.
0 = Interrupt-on-Change disabled for the associated pin.
bit 2
bit 1-0
IOCAP<1:0>: Interrupt-on-Change PORTA Positive Edge Enable bits

1 = Interrupt-on-Change enabled on the pin for a positive going edge. IOCAFx bit and IOCIF flag will
REGISTER 13-2:
IOCAN: INTERRUPT-ON-CHANGE PORTA NEGATIVE EDGE REGISTER
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
R/W-0/0
IOCAN5
IOCAN4
IOCAN3
IOCAN1
IOCAN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-3
IOCAN<5:3>: Interrupt-on-Change PORTA Negative Edge Enable bits

1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCAFx bit and IOCIF flag will
bit 2
bit 1-0
IOCAN<1:0>: Interrupt-on-Change PORTA Negative Edge Enable bits

1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCAFx bit and IOCIF flag will
Preliminary
DS41639A-page 145
PIC16(L)F1454/5/9
REGISTER 13-3:
IOCAF: INTERRUPT-ON-CHANGE PORTA FLAG REGISTER
U-0
U-0
R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0

IOCAF5
IOCAF4
IOCAF3
U-0
R/W/HS-0/0
R/W/HS-0/0
IOCAF1
IOCAF0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
HS - Bit is set in hardware
bit 7-6
bit 5-3
IOCAF<5:3>: Interrupt-on-Change PORTA Flag bits

1 = An enabled change was detected on the associated pin.
Set when IOCAPx = 1 and a rising edge was detected on RAx, or when IOCANx = 1 and a falling
edge was detected on RAx.
0 = No change was detected, or the user cleared the detected change.
bit 2
bit 1-0
IOCAF<:0>: Interrupt-on-Change PORTA Flag bits

Set when IOCAPx = 1 and a rising edge was detected on RAx, or when IOCANx = 1 and a falling
edge was detected on RAx.
REGISTER 13-4:
IOCBP: INTERRUPT-ON-CHANGE PORTB POSITIVE EDGE REGISTER(1)
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
U-0
U-0
U-0
IOCBP7
IOCBP6
IOCBP5
IOCBP4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
IOCBP<7:4>: Interrupt-on-Change PORTB Positive Edge Enable bits

1 = Interrupt-on-Change enabled on the pin for a positive going edge. IOCBFx bit and IOCIF flag will
bit 3-0
Note 1:
PIC16(L)F1459 only.
DS41639A-page 146
Preliminary
PIC16(L)F1454/5/9
REGISTER 13-5:
IOCBN: INTERRUPT-ON-CHANGE PORTB NEGATIVE EDGE REGISTER(1)
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
U-0
U-0
U-0
IOCBN7
IOCBN6
IOCBN5
IOCBN4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
IOCBN<7:4>: Interrupt-on-Change PORTB Negative Edge Enable bits

1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCBFx bit and IOCIF flag will
bit 3-0
Note 1:
PIC16(L)F1459 only.
REGISTER 13-6:
IOCBF: INTERRUPT-ON-CHANGE PORTB FLAG REGISTER(1)
R/W/HS-0/0
R/W/HS-0/0
IOCBF7
IOCBF6
R/W/HS-0/0 R/W/HS-0/0
IOCBF5
IOCBF4
U-0
U-0
U-0
U-0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
HS - Bit is set in hardware
bit 7-4
IOCBF<7:4>: Interrupt-on-Change PORTB Flag bits

Set when IOCBPx = 1 and a rising edge was detected on RBx, or when IOCBNx = 1 and a falling
edge was detected on RBx.
bit 3-0
Note 1:
PIC16(L)F1459 only.
Preliminary
DS41639A-page 147
PIC16(L)F1454/5/9
TABLE 13-1:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE

Bit 7
ANSELA(3)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
133
ANSA4
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
96
IOCAF
IOCAF5
IOCAF4
IOCAF3
IOCAF1
IOCAF0
146
IOCAN
IOCAN5
IOCAN4
IOCAN3
IOCAN1
IOCAN0
145
IOCAP
IOCAP5
IOCAP4
IOCAP3
IOCAP1
IOCAP0
145
IOCBF(2)
IOCBF7
IOCBF6
IOCBF5
IOCBF4
147
IOCBN(2)
IOCBN7
IOCBN6
IOCBN5
IOCBN4
147
(2)
IOCBP
IOCBP7
IOCBP6
IOCBP5
IOCBP4
146
TRISA
TRISA5
TRISA4
(1)
(1)
(1)
132
TRISB7
TRISB6
TRISB5
TRISB4
136
INTCON
TRISB(2)
Legend:
Note 1:
2:
3:
= unimplemented location, read as 0. Shaded cells are not used by interrupt-on-change.

PIC16(L)F1459 only.
DS41639A-page 148
Preliminary
PIC16(L)F1454/5/9
14.0
FIXED VOLTAGE REFERENCE

(FVR) (PIC16(L)F1455/9 ONLY)
The Fixed Voltage Reference, or FVR, is a stable

voltage reference, independent of VDD, with 1.024V,
2.048V or 4.096V selectable output levels. The output
of the FVR can be configured to supply a reference
voltage to the following:
ADC input channel

ADC positive reference
DAC input channel
Comparator positive input
Comparator negative input
Independent Gain Amplifier
The output of the FVR supplied to the ADC and

comparators is routed through a programmable gain
amplifier. Each amplifier can be programmed for a gain
of 1x, 2x or 4x, to produce the three possible voltage
levels.
FIGURE 14-1:
The CDAFVR<1:0> bits of the FVRCON register are

used to enable and configure the gain amplifier settings
for the reference supplied to the comparator modules.
Reference Section 18.0 Comparator Module
(PIC16(L)F1455/9 only) for additional information.
14.2
The FVR can be enabled by setting the FVREN bit of

the FVRCON register.
14.1
The ADFVR<1:0> bits of the FVRCON register are

used to enable and configure the gain amplifier settings
for the reference supplied to the ADC module. Reference Section 16.0 Analog-to-Digital Converter
(ADC) Module (PIC16(L)F1455/9 only) for additional
information.
FVR Stabilization Period
When the Fixed Voltage Reference module is enabled, it

requires time for the reference and amplifier circuits to
stabilize. Once the circuits stabilize and are ready for use,
the FVRRDY bit of the FVRCON register will be set. See
Section 29.0 Electrical Specifications for the
minimum delay requirement.
VOLTAGE REFERENCE BLOCK DIAGRAM

ADFVR<1:0>
CDAFVR<1:0>
2
X1
X2
X4
FVR BUFFER1
(To ADC Module)
X1
X2
X4
FVR BUFFER2
(To Comparators, DAC)
FVREN
+
FVRRDY
Any peripheral requiring the

Fixed Reference
(See Table 14-1)
TABLE 14-1:
Peripheral
HFINTOSC
BOR
LDO
PERIPHERALS REQUIRING THE FIXED VOLTAGE REFERENCE (FVR)

Conditions
Description
FOSC<2:0> = 010 and

IRCF<3:0> = 000x
INTOSC is active and device is not in Sleep.
BOREN<1:0> = 11
BOR always enabled.
BOREN<1:0> = 10 and BORFS = 1
BOR disabled in Sleep mode, BOR Fast Start enabled.
BOREN<1:0> = 01 and BORFS = 1
BOR under software control, BOR Fast Start enabled.
All PIC16F1454/5/9 devices, when

VREGPM = 1 and not in Sleep
The device runs off of the Low-Power Regulator when in

Sleep mode.
Preliminary
DS41639A-page 149
PIC16(L)F1454/5/9
14.3
Register Definitions: FVR Control
REGISTER 14-1:
FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER
R/W-0/0
R-q/q
R/W-0/0
R/W-0/0
FVREN
FVRRDY(1)
TSEN
TSRNG
R/W-0/0
R/W-0/0
R/W-0/0
CDAFVR<1:0>
R/W-0/0
ADFVR<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
FVREN: Fixed Voltage Reference Enable bit

1 = Fixed Voltage Reference is enabled
0 = Fixed Voltage Reference is disabled
bit 6
FVRRDY: Fixed Voltage Reference Ready Flag bit(1)

1 = Fixed Voltage Reference output is ready for use
0 = Fixed Voltage Reference output is not ready or not enabled
bit 5
TSEN: Temperature Indicator Enable bit(3)

1 = Temperature Indicator is enabled
0 = Temperature Indicator is disabled
bit 4
TSRNG: Temperature Indicator Range Selection bit(3)

1 = VOUT = VDD - 4VT (High Range)
0 = VOUT = VDD - 2VT (Low Range)
bit 3-2
CDAFVR<1:0>: Comparator Fixed Voltage Reference Selection bits

11 = Comparator Fixed Voltage Reference Peripheral output is 4x (4.096V)(2)
10 = Comparator Fixed Voltage Reference Peripheral output is 2x (2.048V)(2)
01 = Comparator Fixed Voltage Reference Peripheral output is 1x (1.024V)
00 = Comparator Fixed Voltage Reference Peripheral output is off
bit 1-0
ADFVR<1:0>: ADC Fixed Voltage Reference Selection bit

11 = ADC Fixed Voltage Reference Peripheral output is 4x (4.096V)(2)
10 = ADC Fixed Voltage Reference Peripheral output is 2x (2.048V)(2)
01 = ADC Fixed Voltage Reference Peripheral output is 1x (1.024V)
00 = ADC Fixed Voltage Reference Peripheral output is off
Note 1:
2:
3:
FVRRDY is always 1 for the PIC16F1455/9 devices.

Fixed Voltage Reference output cannot exceed VDD.
See Section 15.0 Temperature Indicator Module (PIC16(L)F1455/9 only) for additional information.
TABLE 14-2:
Name
FVRCON
Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH THE FIXED VOLTAGE REFERENCE

Bit 7
Bit 6
Bit 5
Bit 4
FVREN
FVRRDY
TSEN
TSRNG
Bit 3
Bit 2
CDAFVR>1:0>
Bit 1
Bit 0
ADFVR<1:0>
Register
on page
150
Shaded cells are unused by the Fixed Voltage Reference module.
DS41639A-page 150
Preliminary
PIC16(L)F1454/5/9
15.0
TEMPERATURE INDICATOR
MODULE (PIC16(L)F1455/9
ONLY)
FIGURE 15-1:
VDD
This family of devices is equipped with a temperature

circuit designed to measure the operating temperature
of the silicon die. The circuits range of operating
temperature falls between -40C and +85C. The
output is a voltage that is proportional to the device
temperature. The output of the temperature indicator is
internally connected to the device ADC.
The circuit may be used as a temperature threshold
detector or a more accurate temperature indicator,
depending on the level of calibration performed. A onepoint calibration allows the circuit to indicate a
temperature closely surrounding that point. A two-point
calibration allows the circuit to sense the entire range
of temperature more accurately. Reference Application
Note AN1333, Use and Calibration of the Internal
Temperature Indicator (DS01333) for more details
regarding the calibration process.
15.1
Circuit Operation
Figure 15-1 shows a simplified block diagram of the

temperature circuit. The proportional voltage output is
achieved by measuring the forward voltage drop across
multiple silicon junctions.
TEMPERATURE CIRCUIT
DIAGRAM
TSEN
TSRNG
VOUT
15.2
To ADC
Minimum Operating VDD
When the temperature circuit is operated in low range,

the device may be operated at any operating voltage
that is within specifications.
Equation 15-1 describes the output characteristics of

the temperature indicator.
When the temperature circuit is operated in high range,

the device operating voltage, VDD, must be high
enough to ensure that the temperature circuit is correctly biased.
EQUATION 15-1:
Table 15-1 shows the recommended minimum VDD vs.

range setting.
VOUT RANGES
TABLE 15-1:
High Range: VOUT = VDD - 4VT

Low Range: VOUT = VDD - 2VT
The temperature sense circuit is integrated with the

Fixed Voltage Reference (FVR) module. See
Section Register 14-1: FVRCON: Fixed Voltage
Reference Control Register for more information.
The circuit is enabled by setting the TSEN bit of the
FVRCON register. When disabled, the circuit draws no
current.
The circuit operates in either high or low range. The high
range, selected by setting the TSRNG bit of the
FVRCON register, provides a wider output voltage. This
provides more resolution over the temperature range,
but may be less consistent from part to part. This range
requires a higher bias voltage to operate and thus, a
higher VDD is needed.
The low range is selected by clearing the TSRNG bit of
the FVRCON register. The low range generates a lower
voltage drop and thus, a lower bias voltage is needed to
operate the circuit. The low range is provided for low
voltage operation.
RECOMMENDED VDD VS.

RANGE
Min. VDD, TSRNG = 1
Min. VDD, TSRNG = 0
3.6V
1.8V
15.3
Temperature Output
The output of the circuit is measured using the internal

Analog-to-Digital Converter. A channel is reserved for
the temperature circuit output. Refer to Section 16.0
Analog-to-Digital
Converter
(ADC)
Module
(PIC16(L)F1455/9 only) for detailed information.
15.4
ADC Acquisition Time
To ensure accurate temperature measurements, the

user must wait at least 200 s after the ADC input
multiplexer is connected to the temperature indicator
output before the conversion is performed. In addition,
the user must wait 200 s between sequential
conversions of the temperature indicator output.
Preliminary
DS41639A-page 151
PIC16(L)F1454/5/9
TABLE 15-2:
Name
FVRCON
Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR

Bit 7
Bit 6
Bit 5
Bit 4
FVREN
FVRRDY
TSEN
TSRNG
Bit 3
Bit 2
CDAFVR<1:0>
Bit 1
Bit 0
ADFVR<1:0>
Register
on page
118
Shaded cells are unused by the temperature indicator module.
DS41639A-page 152
Preliminary
PIC16(L)F1454/5/9
16.0
ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
(PIC16(L)F1455/9 ONLY)
The Analog-to-Digital Converter (ADC) allows

conversion of an analog input signal to a 10-bit binary
representation of that signal. This device uses analog
inputs, which are multiplexed into a single sample and
hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates a 10-bit binary result via successive
approximation and stores the conversion result into the
ADC result registers (ADRESH:ADRESL register pair).
Figure 16-1 shows the block diagram of the ADC.
The ADC voltage reference is software selectable to be
either internally generated or externally supplied.
The ADC can generate an interrupt upon completion of
a conversion. This interrupt can be used to wake-up the
device from Sleep.
Preliminary
DS41639A-page 153
PIC16(L)F1454/5/9
FIGURE 16-1:
ADC BLOCK DIAGRAM

VDD
ADPREF = 00
VREF+
Reserved
00000
Reserved
00001
Reserved
00010
AN3
00011
VREF+/AN4
00100
AN5
00101
AN6
00110
AN7
AN8
00111
01000
AN9
01001
AN10
01010
AN11
Reserved
01011
01100
Reserved
11100
ADPREF = 10
VREF- = VSS
VREF+
ref+ refADC
10
GO/DONE
ADFM
0 = Left Justify
1 = Right Justify
16
ADON
Temp Indicator
11101
DAC
FVR Buffer1
11110
VSS
ADRESH
ADRESL
11111
CHS<4:0>
Note 1:
When ADON = 0, all multiplexer inputs are disconnected.
DS41639A-page 154
Preliminary
PIC16(L)F1454/5/9
16.1
ADC Configuration
16.1.4
When configuring and using the ADC the following

functions must be considered:
Port configuration
Channel selection
ADC voltage reference selection
ADC conversion clock source
Interrupt control
Result formatting
16.1.1
The ADC can be used to convert both analog and

digital signals. When converting analog signals, the I/O
pin should be configured for analog by setting the
associated TRIS and ANSEL bits. Refer to
Section 12.0 I/O Ports for more information.
Note:
16.1.2
The source of the conversion clock is software selectable via the ADCS bits of the ADCON1 register. There
are seven possible clock options:
PORT CONFIGURATION
Analog voltages on any pin that is defined

as a digital input may cause the input buffer to conduct excess current.
FOSC/2
FOSC/4
FOSC/8
FOSC/16
FOSC/32
FOSC/64
FRC (dedicated internal oscillator)
The time to complete one bit conversion is defined as

TAD. One full 10-bit conversion requires 11.5 TAD periods as shown in Figure 16-2.
For correct conversion, the appropriate TAD specification must be met. Refer to the A/D conversion requirements in Section 29.0 Electrical Specifications for
more information. Table 16-1 gives examples of appropriate ADC clock selections.
Note:
CHANNEL SELECTION
There are 12 channel selections available:
CONVERSION CLOCK
AN<11:3> pins
DAC
FVR (Fixed Voltage Reference) Output
Unless using the FRC, any changes in the

system clock frequency will change the
ADC clock frequency, which may
adversely affect the ADC result.
Refer to Section 14.0 Fixed Voltage Reference (FVR)

(PIC16(L)F1455/9 only) and Section 15.0 Temperature Indicator Module (PIC16(L)F1455/9 only) for
more information on these channel selections.
The CHS bits of the ADCON0 register determine which
channel is connected to the sample and hold circuit.
When changing channels, a delay is required before
starting the next conversion. Refer to Section 16.2
ADC Operation for more information.
16.1.3
ADC VOLTAGE REFERENCE
The ADPREF bits of the ADCON1 register provides

control of the positive voltage reference. The positive
voltage reference can be:
VREF+ pin
VDD
See Section 14.0 Fixed Voltage Reference (FVR)
(PIC16(L)F1455/9 only) for more details on the Fixed
Voltage Reference.
Preliminary
DS41639A-page 155
PIC16(L)F1454/5/9
TABLE 16-1:
ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
ADC Clock Period (TAD)
Device Frequency (FOSC)
ADC
Clock Source
ADCS<2:0>
20 MHz
16 MHz
8 MHz
4 MHz
1 MHz
Fosc/2
000
100 ns(2)
125 ns(2)
250 ns(2)
500 ns(2)
2.0 s
Fosc/4
100
(2)
200 ns
(2)
250 ns
(2)
Fosc/8
001
400 ns(2)
0.5 s(2)
Fosc/16
101
800 ns
1.0 s
Fosc/32
1.6 s
010
2.0 s
Fosc/64
110
3.2 s
4.0 s
FRC
x11
1.0-6.0 s(1,4)
1.0-6.0 s(1,4)
Legend:
Note 1:
2:
3:
4:
1.0 s
4.0 s
1.0 s
2.0 s
8.0 s(3)
2.0 s
4.0 s
16.0 s(3)
500 ns
4.0 s
(3)
8.0 s
1.0-6.0 s(1,4)
(3)
8.0 s
(3)
16.0 s
1.0-6.0 s(1,4)
32.0 s(3)
64.0 s(3)
1.0-6.0 s(1,4)
Shaded cells are outside of recommended range.

The FRC source has a typical TAD time of 1.6 s for VDD.
These values violate the minimum required TAD time.
For faster conversion times, the selection of another clock source is recommended.
The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the
system clock FOSC. However, the FRC clock source must be used when conversions are to be performed with the
device in Sleep mode.
FIGURE 16-2:
ANALOG-TO-DIGITAL CONVERSION TAD CYCLES
TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b4
b1
b0
b6
b7
b2
b8
b3
b9
b5
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
On the following cycle:
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
DS41639A-page 156
Preliminary
PIC16(L)F1454/5/9
16.1.5
INTERRUPTS
16.1.6
The ADC module allows for the ability to generate an

interrupt upon completion of an Analog-to-Digital
conversion. The ADC Interrupt Flag is the ADIF bit in
the PIR1 register. The ADC Interrupt Enable is the
ADIE bit in the PIE1 register. The ADIF bit must be
cleared in software.
RESULT FORMATTING
The 10-bit A/D conversion result can be supplied in two

formats, left justified or right justified. The ADFM bit of
the ADCON1 register controls the output format.
Figure 16-3 shows the two output formats.
Note 1: The ADIF bit is set at the completion of

every conversion, regardless of whether
or not the ADC interrupt is enabled.
2: The ADC operates during Sleep only
when the FRC oscillator is selected.
This interrupt can be generated while the device is

operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to
wake-up from Sleep and resume in-line code execution, the GIE and PEIE bits of the INTCON register
must be disabled. If the GIE and PEIE bits of the
INTCON register are enabled, execution will switch to
the Interrupt Service Routine.
FIGURE 16-3:
10-BIT A/D CONVERSION RESULT FORMAT

ADRESH
(ADFM = 0)
ADRESL
MSB
LSB
bit 7
bit 0
bit 7
10-bit A/D Result

(ADFM = 1)
bit 0
MSB
bit 7
LSB
bit 0
bit 7
bit 0
10-bit A/D Result
Preliminary
DS41639A-page 157
PIC16(L)F1454/5/9
16.2
16.2.1
ADC Operation
16.2.4
STARTING A CONVERSION
To enable the ADC module, the ADON bit of the

ADCON0 register must be set to a 1. Setting the GO/
DONE bit of the ADCON0 register to a 1 will start the
Analog-to-Digital conversion.
Note:
16.2.2
The GO/DONE bit should not be set in the

same instruction that turns on the ADC.
Refer to Section 16.2.6 A/D Conversion Procedure.
COMPLETION OF A CONVERSION
When the conversion is complete, the ADC module will:

Clear the GO/DONE bit
Set the ADIF Interrupt Flag bit
Update the ADRESH and ADRESL registers with
new conversion result
16.2.3
TERMINATING A CONVERSION
If a conversion must be terminated before completion,

the GO/DONE bit can be cleared in software. The
ADRESH and ADRESL registers will be updated with
the partially complete Analog-to-Digital conversion
sample. Incomplete bits will match the last bit
converted.
Note:
A device Reset forces all registers to their

Reset state. Thus, the ADC module is
turned off and any pending conversion is
terminated.
DS41639A-page 158
ADC OPERATION DURING SLEEP
The ADC module can operate during Sleep. This

requires the ADC clock source to be set to the FRC
option. When the FRC clock source is selected, the
ADC waits one additional instruction before starting the
conversion. This allows the SLEEP instruction to be
executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
will wake-up from Sleep when the conversion
completes. If the ADC interrupt is disabled, the ADC
module is turned off after the conversion completes,
although the ADON bit remains set.
When the ADC clock source is something other than
FRC, a SLEEP instruction causes the present conversion to be aborted and the ADC module is turned off,
although the ADON bit remains set.
16.2.5
AUTO-CONVERSION TRIGGER
The auto-conversion trigger allows periodic ADC measurements without software intervention. When a rising
edge of the selected source occurs, the GO/DONE bit
is set by hardware.
The auto-conversion trigger source is selected with the
TRIGSEL<2:0> bits of the ADCON2 register.
Using the auto-conversion trigger does not assure
proper ADC timing. It is the users responsibility to
ensure that the ADC timing requirements are met.
Auto-Conversion sources are:
TMR0
TMR1
TMR2
C1
C2
Preliminary
PIC16(L)F1454/5/9
16.2.6
A/D CONVERSION PROCEDURE
EXAMPLE 16-1:
This is an example procedure for using the ADC to

perform an Analog-to-Digital conversion:
1.
2.
3.
4.
5.
6.
7.
8.
Configure Port:
Disable pin output driver (Refer to the TRIS
register)
Configure pin as analog (Refer to the ANSEL
register)
Configure the ADC module:
Select ADC conversion clock
Configure voltage reference
Select ADC input channel
Turn on ADC module
Configure ADC interrupt (optional):
Clear ADC interrupt flag
Enable ADC interrupt
Enable peripheral interrupt
Enable global interrupt(1)
Wait the required acquisition time(2).
Start conversion by setting the GO/DONE bit.
Wait for ADC conversion to complete by one of
the following:
Polling the GO/DONE bit
Waiting for the ADC interrupt (interrupts
enabled)
Read ADC Result.
Clear the ADC interrupt flag (required if interrupt
is enabled).
A/D CONVERSION
;This code block configures the ADC

;for polling, Vdd and Vss references, Frc
;clock and AN0 input.
;
;Conversion start & polling for completion
; are included.
;
BANKSEL
ADCON1
;
MOVLW
B11110000 ;Right justify, Frc
;clock
MOVWF
ADCON1
;Vdd and Vss Vref+
BANKSEL
TRISA
;
BSF
TRISA,0
;Set RA0 to input
BANKSEL
ANSEL
;
BSF
ANSEL,0
;Set RA0 to analog
BANKSEL
ADCON0
;
MOVLW
B00000001 ;Select channel AN0
MOVWF
ADCON0
;Turn ADC On
CALL
SampleTime
;Acquisiton delay
BSF
ADCON0,ADGO ;Start conversion
BTFSC
ADCON0,ADGO ;Is conversion done?
GOTO
$-1
;No, test again
BANKSEL
ADRESH
;
MOVF
ADRESH,W
;Read upper 2 bits
MOVWF
RESULTHI
;store in GPR space
BANKSEL
ADRESL
;
MOVF
ADRESL,W
;Read lower 8 bits
MOVWF
RESULTLO
;Store in GPR space
Note 1: The global interrupt can be disabled if the

user is attempting to wake-up from Sleep
and resume in-line code execution.
2: Refer to Section 16.4 A/D Acquisition
Requirements.
Preliminary
DS41639A-page 159
PIC16(L)F1454/5/9
16.3
Register Definitions: ADC Control
REGISTER 16-1:
U-0
ADCON0: A/D CONTROL REGISTER 0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
CHS<4:0>
R/W-0/0
R/W-0/0
R/W-0/0
GO/DONE
ADON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-2
CHS<4:0>: Analog Channel Select bits

00000 = Reserved. No channel connected.
00011 = AN3
00100 = AN4
00101 = AN5
00110 = AN6
00111 = AN7
01000 = AN8
01001 = AN9
01010 = AN10
01011 = AN11

11101 = Temperature Indicator(1)
11110 = DAC (Digital-to-Analog Converter)(2)
11111 = FVR (Fixed Voltage Reference) Buffer 1 Output(3)
bit 1
GO/DONE: A/D Conversion Status bit

1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.
This bit is automatically cleared by hardware when the A/D conversion has completed.
0 = A/D conversion completed/not in progress
bit 0
ADON: ADC Enable bit

1 = ADC is enabled
0 = ADC is disabled and consumes no operating current
Note 1:
2:
3:
See Section 15.0 Temperature Indicator Module (PIC16(L)F1455/9 only) for more information.
See Section 17.0 Digital-to-Analog Converter (DAC) Module (PIC16(L)F1455/9 only) for more information.
See Section 14.0 Fixed Voltage Reference (FVR) (PIC16(L)F1455/9 only) for more information.
DS41639A-page 160
Preliminary
PIC16(L)F1454/5/9
REGISTER 16-2:
R/W-0/0
R/W-0/0
ADFM
R/W-0/0
R/W-0/0
ADCS<2:0>
U-0
U-0
R/W-0/0
bit 7
R/W-0/0
ADPREF<1:0>
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
ADFM: A/D Result Format Select bit

1 = Right justified. Six Most Significant bits of ADRESH are set to 0 when the conversion result is
loaded.
0 = Left justified. Six Least Significant bits of ADRESL are set to 0 when the conversion result is
loaded.
bit 6-4
ADCS<2:0>: A/D Conversion Clock Select bits

000 = FOSC/2
001 = FOSC/8
010 = FOSC/32
011 = FRC (clock supplied from a dedicated RC oscillator)
100 = FOSC/4
101 = FOSC/16
110 = FOSC/64
111 = FRC (clock supplied from a dedicated RC oscillator)
bit 3-2
bit 1-0
ADPREF<1:0>: A/D Positive Voltage Reference Configuration bits

00 = VREF+ is connected to VDD
01 = Reserved
10 = VREF+ is connected to external VREF+ pin(1)
11 = VREF+ is connected to internal Fixed Voltage Reference (FVR) module
Note 1:
When selecting the VREF+ pin as the source of the positive reference, be aware that a minimum voltage
specification exists. See Section 29.0 Electrical Specifications for details.
Preliminary
DS41639A-page 161
PIC16(L)F1454/5/9
REGISTER 16-3:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
TRIGSEL<2:0>
U-0
U-0
U-0
U-0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-4
TRIGSEL<2:0>: Auto-Conversion Trigger Selection bits(1)

000 =
No auto-conversion trigger selected
001 =
Reserved
010 =
Reserved
011 =
TMR0 Overflow(2)
100 =
TMR1 Overflow(2)
101 =
TMR2 Match to PR2(2)
110 =
sync_C1OUT
111 =
sync_C2OUT
bit 3-0
Note 1:
2:
This is a rising edge sensitive input for all sources.

Signal also sets its corresponding interrupt flag.
DS41639A-page 162
Preliminary
PIC16(L)F1454/5/9
REGISTER 16-4:
R/W-x/u
ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
ADRES<9:2>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
ADRES<9:2>: ADC Result Register bits

Upper eight bits of 10-bit conversion result
REGISTER 16-5:
R/W-x/u
ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0
R/W-x/u
ADRES<1:0>
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6

Lower two bits of 10-bit conversion result
bit 5-0
Reserved: Do not use.
Preliminary
DS41639A-page 163
PIC16(L)F1454/5/9
REGISTER 16-6:
ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
ADRES<9:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-2
Reserved: Do not use.
bit 1-0

Upper two bits of 10-bit conversion result
REGISTER 16-7:
R/W-x/u
ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
ADRES<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0

Lower eight bits of 10-bit conversion result
DS41639A-page 164
Preliminary
PIC16(L)F1454/5/9
16.4
A/D Acquisition Requirements
For the ADC to meet its specified accuracy, the charge

holding capacitor (CHOLD) must be allowed to fully
charge to the input channel voltage level. The Analog
Input model is shown in Figure 16-4. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD), refer
to Figure 16-4. The maximum recommended
impedance for analog sources is 10 k. As the
EQUATION 16-1:
Assumptions:
source impedance is decreased, the acquisition time

may be decreased. After the analog input channel is
selected (or changed), an A/D acquisition must be
done before the conversion can be started. To calculate
the minimum acquisition time, Equation 16-1 may be
used. This equation assumes that 1/2 LSb error is used
(1,024 steps for the ADC). The 1/2 LSb error is the
maximum error allowed for the ADC to meet its
specified resolution.
ACQUISITION TIME EXAMPLE

Temperature = 50C and external impedance of 10k 5.0V V DD
T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + T C + T COFF
= 2s + T C + Temperature - 25C 0.05s/C
The value for TC can be approximated with the following equations:
1
= V CHOLD
V AP P LI ED 1 -------------------------n+1
2
1
;[1] VCHOLD charged to within 1/2 lsb
TC
----------
RC
V AP P LI ED 1 e = V CHOLD
;[2] VCHOLD charge response to VAPPLIED
Tc
---------
1
RC
;combining [1] and [2]
V AP P LI ED 1 e = V A PP LIE D 1 -------------------------n+1
2
1
Note: Where n = number of bits of the ADC.

Solving for TC:
T C = C HOLD R IC + R SS + R S ln(1/2047)
= 12.5pF 1k + 7k + 10k ln(0.0004885)
= 1.12 s
Therefore:
T A CQ = 5s + 1.12 s + 50C- 25C 0.05 s/C
= 7.37s
Note 1: The reference voltage (VREF+) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
Preliminary
DS41639A-page 165
PIC16(L)F1454/5/9
FIGURE 16-4:
ANALOG INPUT MODEL

VDD
Analog
Input
pin
Rs
VT 0.6V
CPIN
5 pF
VA
RIC 1k
Sampling
Switch
SS Rss
I LEAKAGE(1)
VT 0.6V
CHOLD = 10 pF
VREF-
Legend: CHOLD
CPIN
6V
5V
VDD 4V
3V
2V
= Sample/Hold Capacitance
= Input Capacitance
RSS
I LEAKAGE = Leakage current at the pin due to

various junctions
RIC
= Interconnect Resistance
RSS
= Resistance of Sampling Switch
SS
= Sampling Switch
VT
= Threshold Voltage
Note 1:
FIGURE 16-5:
5 6 7 8 9 10 11
Sampling Switch
(k)
Refer to Section 29.0 Electrical Specifications.
ADC TRANSFER FUNCTION
Full-Scale Range
3FFh
3FEh
ADC Output Code
3FDh
3FCh
3FBh
03h
02h
01h
00h
Analog Input Voltage

0.5 LSB
VREF-
DS41639A-page 166
1.5 LSB
Zero-Scale
Transition
Full-Scale
Transition
Preliminary
VREF+
PIC16(L)F1454/5/9
TABLE 16-2:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH ADC(3)

Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
CHS<4:0>
Bit 1
Bit 0
GO/DONE
ADON
ADCON0
ADCON1
ADFM
ADCS<2:0>
ADPREF<1:0>
ADCON2
TRIGSEL<2:0>
ADRESH
ADRESL
ANSELA(3)
ANSELB
(2)
ANSELC(3)
INTCON
PIE1
PIR1
TRISA
TRISB(2)
TRISC
FVRCON
Legend:
Note 1:
2:
3:
Register
on Page
160
161
162
163, 164
A/D Result Register Low
163, 164
ANSA4
ANSB5
ANSB4
ANSC7(1)
ANSC6(1)
ANSC3
ANSC2
133
137
ANSC1
ANSC0
141
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
96
TMR1GIE
ADIE(3)
RCIE
TXIE
SSP1IE
TMR2IE
TMR1IE
97
TMR1GIF
ADIF(3)
RCIF
TXIF
SSP1IF
TMR2IF
TMR1IF
99
TRISA5
TRISA4
(1)
(1)
(1)
132
TRISB7
TRISB6
TRISB5
TRISB4
136
TRISC7(2)
TRISC6(2)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
140
FVREN
FVRRDY
TSEN
TSRNG
CDAFVR<1:0>
ADFVR<1:0>
150
x = unknown, u = unchanged, = unimplemented read as 0, q = value depends on condition. Shaded cells are not
used for ADC module.
PIC16(L)F1459 only.
Preliminary
DS41639A-page 167
PIC16(L)F1454/5/9
NOTES:
DS41639A-page 168
Preliminary
PIC16(L)F1454/5/9
17.0
DIGITAL-TO-ANALOG
CONVERTER (DAC) MODULE
The Digital-to-Analog Converter supplies a variable

voltage reference, ratiometric with the input source,
with 32 selectable output levels.
17.1
Output Voltage Selection
The DAC has 32 voltage level ranges. The 32 levels

are set with the DACR<4:0> bits of the DACCON1
register.
The DAC output voltage is determined by the following
equations:
The input of the DAC can be connected to:

External VREF+ pin
VDD supply voltage
The output of the DAC can be configured to supply a
reference voltage to the following:
Comparator positive input

ADC input channel
DACOUT1 pin
DACOUT2 pin
The Digital-to-Analog Converter (DAC) can be enabled

by setting the DACEN bit of the DACCON0 register.
EQUATION 17-1:
DAC OUTPUT VOLTAGE
IF DACEN = 1
DACR 4:0
VOUT = VSOURCE+ VSOURCE- ----------------------------+ VSOURCE5
2
IF DACEN = 0 and DACLPS = 1 and DACR[4:0] = 11111
V OUT = V SOURCE +
IF DACEN = 0 and DACLPS = 0 and DACR[4:0] = 00000
V OUT = V SOURCE
VSOURCE+ = VDD, VREF, or FVR BUFFER 2
VSOURCE- = VSS
17.2
Ratiometric Output Level
17.3
The DAC output value is derived using a resistor ladder

with each end of the ladder tied to a positive and
negative voltage reference input source. If the voltage
of either input source fluctuates, a similar fluctuation will
result in the DAC output value.
The value of the individual resistors within the ladder
can be found in Section 29.0 Electrical
Specifications.
DAC Voltage Reference Output
The DAC voltage can be output to the DACOUT1 and

DACOUT2 pins by setting the respective DACOE1 and
DACOE2 pins of the DACCON0 register. Selecting the
DAC reference voltage for output on either DACOUTx
pin automatically overrides the digital output buffer and
digital input threshold detector functions of that pin.
Reading the DACOUTx pin when it has been configured for DAC reference voltage output will always
return a 0.
Due to the limited current drive capability, a buffer must
be used on the DAC voltage reference output for
external connections to either DACOUTx pin.
Figure 17-2 shows an example buffering technique.
Preliminary
DS41639A-page 169
PIC16(L)F1454/5/9
FIGURE 17-1:
DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM
Digital-to-Analog Converter (DAC)
VSOURCE+
VDD
DACR<4:0>
VREF+
R
R
DACPSS
DACEN
R
32
Steps
R
32-to-1 MUX
DAC
(To Comparator and
ADC Module)
DACOUT1
DACOE1
VSOURCE-
DACOUT2
DACOE2
FIGURE 17-2:
VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE

PIC MCU
DAC
Module
R
Voltage
Reference
Output
Impedance
DS41639A-page 170
DACOUTX
Preliminary
Buffered DAC Output
PIC16(L)F1454/5/9
17.4
When the device wakes up from Sleep through an

interrupt or a Watchdog Timer time-out, the contents of
the DACCON0 register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
17.5
Effects of a Reset
A device Reset affects the following:

DAC is disabled.
DAC output voltage is removed from the
DACOUT pin.
The DACR<4:0> range select bits are cleared.
Preliminary
DS41639A-page 171
PIC16(L)F1454/5/9
17.6
Register Definitions: DAC Control
REGISTER 17-1:
DACCON0: VOLTAGE REFERENCE CONTROL REGISTER 0
R/W-0/0
U-0
R/W-0/0
R/W-0/0
DACEN
DACOE1
DACOE2
R/W-0/0
R/W-0/0
DACPSS<1:0>
U-0
U-0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
DACEN: DAC Enable bit

1 = DAC is enabled
0 = DAC is disabled
bit 6
bit 5
DACOE1: DAC Voltage Output Enable bit

1 = DAC voltage level is also an output on the DACOUT1 pin
0 = DAC voltage level is disconnected from the DACOUT1 pin
bit 4
DACOE2: DAC Voltage Output Enable bit

1 = DAC voltage level is also an output on the DACOUT2 pin
0 = DAC voltage level is disconnected from the DACOUT2 pin
bit 3-2
DACPSS<1:0>: DAC Positive Source Select bit

11 = Reserved
10 = Comparator FVR output
01 = VREF+ pin
00 = VDD
bit 1-0
REGISTER 17-2:
DACCON1: VOLTAGE REFERENCE CONTROL REGISTER 1
U-0
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
DACR<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-5
bit 4-0
DACR<4:0>: DAC Voltage Output Select bits
TABLE 17-1:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC MODULE(1)

Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
FVRCON
FVREN
FVRRDY
TSEN
TSRNG
CDAFVR<1:0>
DACCON0
DACEN
DACOE1
DACOE2
DACPSS<1:0>
DACCON1
Legend:
Note 1:
Bit 1
Bit 0
ADFVR<1:0>
DACR<4:0>
Register
on page
356
172
172
= Unimplemented location, read as 0. Shaded cells are not used with the DAC module.
DS41639A-page 172
Preliminary
PIC16(L)F1454/5/9
18.0
COMPARATOR MODULE
FIGURE 18-1:
Comparators are used to interface analog circuits to a

digital circuit by comparing two analog voltages and
providing a digital indication of their relative magnitudes.
Comparators are very useful mixed signal building
blocks because they provide analog functionality
independent of program execution. The analog
comparator module includes the following features:
Independent comparator control

Programmable input selection
Comparator output is available internally/externally
Programmable output polarity
Interrupt-on-change
Wake-up from Sleep
Programmable Speed/Power optimization
PWM shutdown
Programmable and fixed voltage reference
18.1
SINGLE COMPARATOR
VIN+
VIN-
Output
VINVIN+
Output
Note:
The black areas of the output of the

comparator represents the uncertainty
due to input offsets and response time.
Comparator Overview
A single comparator is shown in Figure 18-1 along with

the relationship between the analog input levels and
the digital output. When the analog voltage at VIN+ is
less than the analog voltage at VIN-, the output of the
comparator is a digital low level. When the analog
voltage at VIN+ is greater than the analog voltage at
VIN-, the output of the comparator is a digital high level.
The comparators available for this device are located in
Table 18-1.
TABLE 18-1:
COMPARATOR AVAILABILITY
PER DEVICE
Device
C1
C2
PIC16(L)F1455
PIC16(L)F1459
Preliminary
DS41639A-page 173
PIC16(L)F1454/5/9
FIGURE 18-2:
COMPARATOR MODULES SIMPLIFIED BLOCK DIAGRAM
CxNCH<2:0>
CxON(1)
det
Reserved
CXIN2-
1
MUX
2 (2)
CXIN3-
FVR Buffer2
CXIN1-
Set CxIF
0
MUX
1 (2)
DAC
FVR Buffer2
CxINTN
Interrupt
det
CXPOL
CxVN
Cx
CxVP
CXIN+
CxINTP
Interrupt
CXOUT
MCXOUT
+
EN
Q1
CxHYS
CxSP
async_CxOUT
2
3
CXSYNC
CxON
CXPCH<1:0>
To CWG
CXOE
TRIS bit
CXOUT
0
2
D
(from Timer1)
T1CLK
SYNCCXOUT
Note
1:
2:
When CxON = 0, the Comparator will produce a 0 at the output

When CxON = 0, all multiplexer inputs are disconnected.
DS41639A-page 174
Preliminary
To Timer1,
ADC
PIC16(L)F1454/5/9
18.2
Comparator Control
18.2.3
Each comparator has two control registers: CMxCON0

and CMxCON1.
The CMxCON0 registers (see Register 18-1) contain
Control and Status bits for the following:
Enable
Output selection
Output polarity
Speed/Power selection
Hysteresis enable
Output synchronization
Inverting the output of the comparator is functionally

equivalent to swapping the comparator inputs. The
polarity of the comparator output can be inverted by
setting the CxPOL bit of the CMxCON0 register.
Clearing the CxPOL bit results in a non-inverted output.
Table 18-2 shows the output state versus input
conditions, including polarity control.
TABLE 18-2:
Interrupt enable
Interrupt edge polarity
Positive input channel selection
Negative input channel selection
18.2.1
CxPOL
CxOUT
CxVN > CxVP
CxVN < CxVP
CxVN > CxVP
CxVN < CxVP
18.2.4
COMPARATOR ENABLE
Setting the CxON bit of the CMxCON0 register enables

the comparator for operation. Clearing the CxON bit
disables the comparator resulting in minimum current
consumption.
18.2.2
COMPARATOR OUTPUT
SELECTION
COMPARATOR OUTPUT
STATE VS. INPUT
CONDITIONS
Input Condition
The CMxCON1 registers (see Register 18-2) contain

Control bits for the following:
COMPARATOR OUTPUT POLARITY
COMPARATOR SPEED/POWER
SELECTION
The trade-off between speed or power can be optimized during program execution with the CxSP control
bit. The default state for this bit is 1 which selects the
Normal-Speed mode. Device power consumption can
be optimized at the cost of slower comparator propagation delay by clearing the CxSP bit to 0.
The output of the comparator can be monitored by

reading either the CxOUT bit of the CMxCON0 register
or the MCxOUT bit of the CMOUT register. In order to
make the output available for an external connection,
the following conditions must be true:
CxOE bit of the CMxCON0 register must be set
Corresponding TRIS bit must be cleared
CxON bit of the CMxCON0 register must be set
Note 1: The CxOE bit of the CMxCON0 register
overrides the PORT data latch. Setting
the CxON bit of the CMxCON0 register
has no impact on the port override.
2: The internal output of the comparator is
latched with each instruction cycle.
Unless otherwise specified, external
outputs are not latched.
Preliminary
DS41639A-page 175
PIC16(L)F1454/5/9
18.3
Comparator Hysteresis
18.5
A selectable amount of separation voltage can be

added to the input pins of each comparator to provide a
hysteresis function to the overall operation. Hysteresis
is enabled by setting the CxHYS bit of the CMxCON0
register.
Comparator Interrupt
An interrupt can be generated upon a change in the

output value of the comparator for each comparator, a
rising edge detector and a falling edge detector are
present.
See Section 29.0 Electrical Specifications for

more information.
When either edge detector is triggered and its associated enable bit is set (CxINTP and/or CxINTN bits of
the CMxCON1 register), the Corresponding Interrupt
Flag bit (CxIF bit of the PIR2 register) will be set.
18.4
To enable the interrupt, you must set the following bits:
Timer1 Gate Operation
The output resulting from a comparator operation can

be used as a source for gate control of Timer1. See
Section 20.6 Timer1 Gate for more information.
This feature is useful for timing the duration or interval
of an analog event.
It is recommended that the comparator output be synchronized to Timer1. This ensures that Timer1 does not
increment while a change in the comparator is occurring.
18.4.1
COMPARATOR OUTPUT
SYNCHRONIZATION
The output from either comparator, C1 or C2, can be

synchronized with Timer1 by setting the CxSYNC bit of
the CMxCON0 register.
Once enabled, the comparator output is latched on the
falling edge of the Timer1 source clock. If a prescaler is
used with Timer1, the comparator output is latched after
the prescaling function. To prevent a race condition, the
comparator output is latched on the falling edge of the
Timer1 clock source and Timer1 increments on the
rising edge of its clock source. See the Comparator
Block Diagram (Figure 18-2) and the Timer1 Block
Diagram (Figure 20-1) for more information.
CxON, CxPOL and CxSP bits of the CMxCON0

register
CxIE bit of the PIE2 register
CxINTP bit of the CMxCON1 register (for a rising
edge detection)
CxINTN bit of the CMxCON1 register (for a falling
edge detection)
PEIE and GIE bits of the INTCON register
The associated interrupt flag bit, CxIF bit of the PIR2
register, must be cleared in software. If another edge is
detected while this flag is being cleared, the flag will still
be set at the end of the sequence.
Note:
18.6
Although a comparator is disabled, an

interrupt can be generated by changing
the output polarity with the CxPOL bit of
the CMxCON0 register, or by switching
the comparator on or off with the CxON bit
of the CMxCON0 register.
Comparator Positive Input

Selection
Configuring the CxPCH<1:0> bits of the CMxCON1

register directs an internal voltage reference or an
analog pin to the non-inverting input of the comparator:
CxIN+ analog pin

DAC output
FVR (Fixed Voltage Reference)
VSS (Ground)
See Section 14.0 Fixed Voltage Reference (FVR)

(PIC16(L)F1455/9 only) for more information on the
Fixed Voltage Reference module.
See Section 17.0 Digital-to-Analog Converter
(DAC) Module (PIC16(L)F1455/9 only) for more
information on the DAC input signal.
Any time the comparator is disabled (CxON = 0), all
comparator inputs are disabled.
DS41639A-page 176
Preliminary
PIC16(L)F1454/5/9
18.7
Comparator Negative Input

Selection
18.10 Analog Input Connection

Considerations
The CxNCH<2:0> bits of the CMxCON0 register direct

one of the input sources to the comparator inverting
input.
Note:
18.8
To use CxIN+ and CxINx- pins as analog

input, the appropriate bits must be set in
the ANSEL register and the corresponding TRIS bits must also be set to disable
the output drivers.
Comparator Response Time
The comparator output is indeterminate for a period of

time after the change of an input source or the selection
of a new reference voltage. This period is referred to as
the response time. The response time of the comparator
differs from the settling time of the voltage reference.
Therefore, both of these times must be considered when
determining the total response time to a comparator
input change. See the Comparator and Voltage Reference Specifications in Section 29.0 Electrical Specifications for more details.
18.9
A simplified circuit for an analog input is shown in

Figure 18-3. Since the analog input pins share their
connection with a digital input, they have reverse
biased ESD protection diodes to VDD and VSS. The
analog input, therefore, must be between VSS and VDD.
If the input voltage deviates from this range by more
than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur.
A maximum source impedance of 10 k is recommended
for the analog sources. Also, any external component
connected to an analog input pin, such as a capacitor or
a Zener diode, should have very little leakage current to
minimize inaccuracies introduced.
Note 1: When reading a PORT register, all pins
configured as analog inputs will read as a
0. Pins configured as digital inputs will
convert as an analog input, according to
the input specification.
Interaction with ECCP Logic
2: Analog levels on any pin defined as a

digital input, may cause the input buffer to
consume more current than is specified.
The C1 and C2 comparators can be used as general

purpose comparators. Their outputs can be brought
out to the C1OUT and C2OUT pins. When the ECCP
Auto-Shutdown is active it can use one or both
comparator signals. If auto-restart is also enabled, the
comparators can be configured as a closed loop
analog feedback to the ECCP, thereby, creating an
analog controlled PWM.
Note:
When the comparator module is first

initialized the output state is unknown.
Upon initialization, the user should verify
the output state of the comparator prior to
relying on the result, primarily when using
the result in connection with other
peripheral features, such as the ECCP
Auto-Shutdown mode.
Preliminary
DS41639A-page 177
PIC16(L)F1454/5/9
FIGURE 18-3:
ANALOG INPUT MODEL

VDD
Rs < 10K
Analog
Input
pin
VT 0.6V
RIC
To Comparator
VA
CPIN
5 pF
VT 0.6V
ILEAKAGE(1)
Vss
Legend: CPIN
= Input Capacitance
ILEAKAGE = Leakage Current at the pin due to various junctions
= Interconnect Resistance
RIC
= Source Impedance
RS
= Analog Voltage
VA
= Threshold Voltage
VT
Note 1:
DS41639A-page 178
See Section 29.0 Electrical Specifications.
Preliminary
PIC16(L)F1454/5/9
18.11 Register Definitions: Comparator Control
REGISTER 18-1:
CMxCON0: COMPARATOR Cx CONTROL REGISTER 0
R/W-0/0
R-0/0
R/W-0/0
R/W-0/0
U-0
R/W-1/1
R/W-0/0
R/W-0/0
CxON
CxOUT
CxOE
CxPOL
CxSP
CxHYS
CxSYNC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
CxON: Comparator Enable bit

1 = Comparator is enabled and consumes no active power
0 = Comparator is disabled
bit 6
CxOUT: Comparator Output bit

If CxPOL = 1 (inverted polarity):
1 = CxVP < CxVN
0 = CxVP > CxVN
If CxPOL = 0 (non-inverted polarity):
1 = CxVP > CxVN
0 = CxVP < CxVN
bit 5
CxOE: Comparator Output Enable bit

1 = CxOUT is present on the CxOUT pin. Requires that the associated TRIS bit be cleared to actually
drive the pin. Not affected by CxON.
0 = CxOUT is internal only
bit 4
CxPOL: Comparator Output Polarity Select bit

1 = Comparator output is inverted
0 = Comparator output is not inverted
bit 3
bit 2
CxSP: Comparator Speed/Power Select bit

1 = Comparator operates in Normal-Power, Higher Speed mode
0 = Comparator operates in Low-Power, Low-Speed mode
bit 1
CxHYS: Comparator Hysteresis Enable bit

1 = Comparator hysteresis enabled
0 = Comparator hysteresis disabled
bit 0
CxSYNC: Comparator Output Synchronous Mode bit

1 = Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source.
Output updated on the falling edge of Timer1 clock source.
0 = Comparator output to Timer1 and I/O pin is asynchronous
Preliminary
DS41639A-page 179
PIC16(L)F1454/5/9
REGISTER 18-2:
CMxCON1: COMPARATOR Cx CONTROL REGISTER 1
R/W-0/0
R/W-0/0
CxINTP
CxINTN
R/W-0/0
R/W-0/0
CxPCH<1:0>
U-0
R/W-0/0
R/W-0/0
R/W-0/0
CxNCH<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
CxINTP: Comparator Interrupt on Positive Going Edge Enable bits

1 = The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit
0 = No interrupt flag will be set on a positive going edge of the CxOUT bit
bit 6
CxINTN: Comparator Interrupt on Negative Going Edge Enable bits

1 = The CxIF interrupt flag will be set upon a negative going edge of the CxOUT bit
0 = No interrupt flag will be set on a negative going edge of the CxOUT bit
bit 5-4
CxPCH<1:0>: Comparator Positive Input Channel Select bits

11 = CxVP connects to VSS
10 = CxVP connects to FVR Voltage Reference
01 = CxVP connects to DAC Voltage Reference
00 = CxVP connects to CxIN+ pin
bit 3
bit 2-0
CxNCH<2:0>: Comparator Negative Input Channel Select bits

111 = Reserved
110 = Reserved
101 = Reserved
100 = CxVN connects to FVR Voltage reference
011 = CxVN connects to CxIN3- pin
000 = Reserved
REGISTER 18-3:
U-0
CMOUT: COMPARATOR OUTPUT REGISTER

U-0
U-0
U-0
U-0
U-0
R-0/0
R-0/0
MC2OUT
MC1OUT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-2
bit 1
MC2OUT: Mirror Copy of C2OUT bit
bit 0
MC1OUT: Mirror Copy of C1OUT bit
DS41639A-page 180
Preliminary
PIC16(L)F1454/5/9
TABLE 18-3:
Name
ANSELA
ANSELC
CM1CON0
SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE(3)

Bit 7
Bit 6
ANSC7
(2)
C1ON
ANSC6
(2)
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSA4
133
ANSC3
ANSC2
ANSC1
ANSC0
141
C1OUT
C1OE
C1POL
C1SP
C1HYS
C1SYNC
179
C2OE
C2POL
C2SP
C2HYS
C2SYNC
179
CM2CON0
C2ON
C2OUT
CM1CON1
C1NTP
C1INTN
CM2CON1
C2NTP
C2INTN
DACCON0
DACEN
DACOE1
DACOE2
DACCON1
FVRCON
FVREN
FVRRDY
TSEN
TSRNG
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
96
PIE2
OSFIE
C2IE
C1IE
BCL1IE
USBIE
ACTIE
98
PIR2
OSFIF
C2IF
C1IF
BCL1IF
USBIF
ACTIF
100
RA5
RA4
RA3
RA1
RA0
132
RC5
RC4
RC3
RC2
RC1
RC0
140
LATA5
LATA4
133
CMOUT
PORTA
PORTC
RC7
(2)
RC6
(2)
C1PCH<1:0>
C2PCH<1:0>
C1NCH<2:0>
180
C2NCH<2:0>
DACPSS<1:0>
180
MC2OUT
MC1OUT
180
172
DACR<4:0>
CDAFVR<1:0>
172
ADFVR<1:0>
150
LATA
LATC
LATC7(2)
LATC6(2)
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0
141
TRISA4
(1)
(1)
(1)
132
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
140
TRISA
TRISA5
TRISC
TRISC7(2)
TRISC6(2)
TRISC5
Legend:
Note 1:
2:
3:
= unimplemented location, read as 0. Shaded cells are unused by the comparator module.
PIC16(L)F1459 only.
PIC16(L)F1455/9 only,
Preliminary
DS41639A-page 181
PIC16(L)F1454/5/9
NOTES:
DS41639A-page 182
Preliminary
PIC16(L)F1454/5/9
19.0
TIMER0 MODULE
When TMR0 is written, the increment is inhibited for

two instruction cycles immediately following the write.
The Timer0 module is an 8-bit timer/counter with the

following features:
Note:
8-bit timer/counter register (TMR0)

8-bit prescaler (independent of Watchdog Timer)
Programmable internal or external clock source
Programmable external clock edge selection
Interrupt on overflow
TMR0 can be used to gate Timer1
19.1.2
8-Bit Counter mode using the T0CKI pin is selected by

setting the TMR0CS bit in the OPTION_REG register to
1.
Timer0 Operation
The rising or falling transition of the incrementing edge

for either input source is determined by the TMR0SE bit
in the OPTION_REG register.
The Timer0 module can be used as either an 8-bit timer

or an 8-bit counter.
19.1.1
8-BIT COUNTER MODE
In 8-Bit Counter mode, the Timer0 module will increment

on every rising or falling edge of the T0CKI pin.
Figure 19-1 is a block diagram of the Timer0 module.
19.1
The value written to the TMR0 register

can be adjusted, in order to account for
the two instruction cycle delay when
TMR0 is written.
8-BIT TIMER MODE
The Timer0 module will increment every instruction

cycle, if used without a prescaler. 8-bit Timer mode is
selected by clearing the TMR0CS bit of the
OPTION_REG register.
FIGURE 19-1:
BLOCK DIAGRAM OF THE TIMER0
FOSC/4
Data Bus
0
T0CKI
1
1
8
Sync
2 TCY
TMR0
0
TMR0SE TMR0CS
8-bit
Prescaler
PSA
Set Flag bit TMR0IF

on Overflow
Overflow to Timer1
PS<2:0>
Preliminary
DS41639A-page 183
PIC16(L)F1454/5/9
19.1.3
SOFTWARE PROGRAMMABLE
PRESCALER
A software programmable prescaler is available for

exclusive use with Timer0. The prescaler is enabled by
clearing the PSA bit of the OPTION_REG register.
Note:
The Watchdog Timer (WDT) uses its own

independent prescaler.
There are eight prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are
selectable via the PS<2:0> bits of the OPTION_REG
register. In order to have a 1:1 prescaler value for the
Timer0 module, the prescaler must be disabled by setting the PSA bit of the OPTION_REG register.
The prescaler is not readable or writable. All instructions
writing to the TMR0 register will clear the prescaler.
19.1.4
TIMER0 INTERRUPT
Timer0 will generate an interrupt when the TMR0

register overflows from FFh to 00h. The TMR0IF
interrupt flag bit of the INTCON register is set every
time the TMR0 register overflows, regardless of
whether or not the Timer0 interrupt is enabled. The
TMR0IF bit can only be cleared in software. The Timer0
interrupt enable is the TMR0IE bit of the INTCON
register.
Note:
19.1.5
The Timer0 interrupt cannot wake the

processor from Sleep since the timer is
frozen during Sleep.
8-BIT COUNTER MODE

SYNCHRONIZATION
When in 8-Bit Counter mode, the incrementing edge on

the T0CKI pin must be synchronized to the instruction
clock. Synchronization can be accomplished by
sampling the prescaler output on the Q2 and Q4 cycles
of the instruction clock. The high and low periods of the
external clocking source must meet the timing
requirements as shown in Section 29.0 Electrical
Specifications.
19.1.6
OPERATION DURING SLEEP
Timer0 cannot operate while the processor is in Sleep

mode. The contents of the TMR0 register will remain
unchanged while the processor is in Sleep mode.
DS41639A-page 184
Preliminary
PIC16(L)F1454/5/9
19.2
Register Definitions: Option Register
REGISTER 19-1:
OPTION_REG: OPTION REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
WPUEN
INTEDG
TMR0CS
TMR0SE
PSA
R/W-1/1
R/W-1/1
R/W-1/1
PS<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
WPUEN: Weak Pull-Up Enable bit

1 = All weak pull-ups are disabled (except MCLR, if it is enabled)
0 = Weak pull-ups are enabled by individual WPUx latch values
bit 6
INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
bit 5
TMR0CS: Timer0 Clock Source Select bit

1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (FOSC/4)
bit 4
TMR0SE: Timer0 Source Edge Select bit

1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3
PSA: Prescaler Assignment bit

1 = Prescaler is not assigned to the Timer0 module
0 = Prescaler is assigned to the Timer0 module
bit 2-0
PS<2:0>: Prescaler Rate Select bits
TABLE 19-1:
Name
OPTION_REG
TRISA
Legend:
*
Note 1:
2:
000
001
010
011
100
101
110
111
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
Bit 6
Bit 5
Bit 4
TRIGSEL<2:0>
INTCON
TMR0
Timer0 Rate
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0

Bit 7
ADCON2(2)
Bit Value
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
162
TMR0IF
INTF
IOCIF
96
GIE
PEIE
TMR0IE
INTE
IOCIE
WPUEN
INTEDG
TMR0CS
TMR0SE
PSA
PS<2:0>
185
Holding Register for the 8-bit Timer0 Count
TRISA5
TRISA4
183*
(1)
(1)
(1)
132
= Unimplemented location, read as 0. Shaded cells are not used by the Timer0 module.
Page provides register information.
Preliminary
DS41639A-page 185
PIC16(L)F1454/5/9
NOTES:
DS41639A-page 186
Preliminary
PIC16(L)F1454/5/9
20.0
TIMER1 MODULE WITH GATE

CONTROL
Gate Single-pulse mode

Gate Value Status
Gate Event Interrupt
The Timer1 module is a 16-bit timer/counter with the

following features:
Figure 20-1 is a block diagram of the Timer1 module.
16-bit timer/counter register pair (TMR1H:TMR1L)

Programmable internal or external clock source
2-bit prescaler
Optionally synchronized comparator out
Multiple Timer1 gate (count enable) sources
Interrupt on overflow
Wake-up on overflow (external clock,
Asynchronous mode only)
Auto-conversion Trigger (with CCP)
Selectable Gate Source Polarity
Gate Toggle mode
FIGURE 20-1:
TIMER1 BLOCK DIAGRAM
T1GSS<1:0>
T1GSPM
00
T1G
From Timer0
Overflow
01
sync_C1OUT
10
sync_C2OUT
11
T1GVAL
0
Single-Pulse
TMR1ON
T1GPOL
t1g_in
CK
R
Acq. Control
Q1
Data Bus
D
Q
RD
T1GCON
EN
Interrupt
T1GGO/DONE
Set
TMR1GIF
det
T1GTM
TMR1GE
Set flag bit

TMR1IF on
Overflow
To ADC Auto-Conversion
TMR1ON
To Comparator Module(4)
TMR1(2)
TMR1H
EN
TMR1L
T1CLK
Synchronized
clock input
0
1
TMR1CS<1:0>
T1OSO
LFINTOSC
T1OSC
T1OSI
T1SYNC
OUT
11
Synchronize(3)
Prescaler
1, 2, 4, 8
det
10
EN
0
T1OSCEN
(1)
FOSC
Internal
Clock
01
FOSC/4
Internal
Clock
00
2
T1CKPS<1:0>
FOSC/2
Internal
Clock
Sleep input
T1CKI
To Clock Switching Modules
Note 1:
2:
3:
4:
ST Buffer is high speed type when using T1CKI.

Timer1 register increments on rising edge.
Synchronize does not operate while in Sleep.
Preliminary
DS41639A-page 187
PIC16(L)F1454/5/9
20.1
Timer1 Operation
20.2
The Timer1 module is a 16-bit incrementing counter

which is accessed through the TMR1H:TMR1L register
pair. Writes to TMR1H or TMR1L directly update the
counter.
When used with an internal clock source, the module is
a timer and increments on every instruction cycle.
When used with an external clock source, the module
can be used as either a timer or counter and increments on every selected edge of the external source.
Timer1 is enabled by configuring the TMR1ON and
TMR1GE bits in the T1CON and T1GCON registers,
respectively. Table 20-1 displays the Timer1 enable
selections.
TABLE 20-1:
TIMER1 ENABLE
SELECTIONS
Clock Source Selection
The TMR1CS<1:0> bits of the T1CON register are used

to select the clock source for Timer1. Table 20-2
displays the clock source selections.
20.2.1
INTERNAL CLOCK SOURCE
When the internal clock source is selected, the

TMR1H:TMR1L register pair will increment on multiples
of FOSC as determined by the Timer1 prescaler.
When the FOSC internal clock source is selected, the
Timer1 register value will increment by four counts every
instruction clock cycle. Due to this condition, a two LSB
error in resolution will occur when reading the Timer1
value. To utilize the full resolution of Timer1, an
asynchronous input signal must be used to gate the
Timer1 clock input.
The following asynchronous sources may be used:
Asynchronous event on the T1G pin to Timer1
gate
C1 or C2 comparator input to Timer1 gate
Timer1
Operation
TMR1ON
TMR1GE
Off
Off
20.2.2
Always On
Count Enabled
When the external clock source is selected, the Timer1

module may work as a timer or a counter.
EXTERNAL CLOCK SOURCE
When enabled to count, Timer1 is incremented on the

rising edge of the external clock input T1CKI, The
external clock source can be synchronized to the
microcontroller system clock or it can run
asynchronously.
When used as a timer with a clock oscillator, an
external 32.768 kHz crystal can be used in conjunction
with the dedicated internal oscillator circuit.
Note:
In Counter mode, a falling edge must be

registered by the counter prior to the first
incrementing rising edge after any one or
more of the following conditions:
TABLE 20-2:
Timer1 enabled after POR

Write to TMR1H or TMR1L
Timer1 is disabled
Timer1 is disabled (TMR1ON = 0)
when T1CKI is high then Timer1 is
enabled (TMR1ON=1) when T1CKI is
low.
CLOCK SOURCE SELECTIONS
TMR1CS<1:0>
T1OSCEN
11
LFINTOSC
10
External Clocking on T1CKI Pin
01
System Clock (FOSC)
00
Instruction Clock (FOSC/4)
DS41639A-page 188
Clock Source
Preliminary
PIC16(L)F1454/5/9
20.3
Timer1 Prescaler
20.5.1
Timer1 has four prescaler options allowing 1, 2, 4 or 8

divisions of the clock input. The T1CKPS bits of the
T1CON register control the prescale counter. The
prescale counter is not directly readable or writable;
however, the prescaler counter is cleared upon a write to
TMR1H or TMR1L.
20.4
Timer1 Oscillator
READING AND WRITING TIMER1 IN

ASYNCHRONOUS COUNTER
MODE
Reading TMR1H or TMR1L while the timer is running

from an external asynchronous clock will ensure a valid
read (taken care of in hardware). However, the user
should keep in mind that reading the 16-bit timer in two
8-bit values itself, poses certain problems, since the
timer may overflow between the reads.
A dedicated low-power 32.768 kHz oscillator circuit is

built-in between pins T1OSI (input) and T1OSO
(amplifier output). This internal circuit is to be used in
conjunction with an external 32.768 kHz crystal.
For writes, it is recommended that the user simply stop

the timer and write the desired values. A write
contention may occur by writing to the timer registers,
while the register is incrementing. This may produce an
unpredictable value in the TMR1H:TMR1L register pair.
The oscillator circuit is enabled by setting the

T1OSCEN bit of the T1CON register. The oscillator will
continue to run during Sleep.
20.6
Note:
20.5
The oscillator requires a start-up and

stabilization time before use. Thus,
T1OSCEN should be set and a suitable
delay observed prior to using Timer1. A
suitable delay similar to the OST delay
can be implemented in software by
clearing the TMR1IF bit then presetting
the TMR1H:TMR1L register pair to
FC00h. The TMR1IF flag will be set when
1024 clock cycles have elapsed, thereby
indicating that the oscillator is running and
reasonably stable.
Timer1 Operation in
Asynchronous Counter Mode
If the control bit T1SYNC of the T1CON register is set,

the external clock input is not synchronized. The timer
increments asynchronously to the internal phase
clocks. If the external clock source is selected then the
timer will continue to run during Sleep and can
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in
software are needed to read/write the timer (see
Section 20.5.1 Reading and Writing Timer1 in
Asynchronous Counter Mode).
Note:
Timer1 can be configured to count freely or the count

can be enabled and disabled using Timer1 gate
circuitry. This is also referred to as Timer1 Gate Enable.
Timer1 gate can also be driven by multiple selectable
sources.
20.6.1
TIMER1 GATE ENABLE
The Timer1 Gate Enable mode is enabled by setting

the TMR1GE bit of the T1GCON register. The polarity
of the Timer1 Gate Enable mode is configured using
the T1GPOL bit of the T1GCON register.
When Timer1 Gate Enable mode is enabled, Timer1
will increment on the rising edge of the Timer1 clock
source. When Timer1 Gate Enable mode is disabled,
no incrementing will occur and Timer1 will hold the
current count. See Figure 20-4 for timing details.
TABLE 20-3:
TIMER1 GATE ENABLE

SELECTIONS
T1CLK
T1GPOL
T1G
Counts
Holds Count
Holds Count
Counts
When switching from synchronous to

asynchronous operation, it is possible to
skip an increment. When switching from
asynchronous to synchronous operation,
it is possible to produce an additional
increment.
Timer1 Gate
Preliminary
Timer1 Operation
DS41639A-page 189
PIC16(L)F1454/5/9
20.6.2
TIMER1 GATE SOURCE

SELECTION
20.6.3
Timer1 gate source selections are shown in Table 20-4.

Source selection is controlled by the T1GSS bits of the
T1GCON register. The polarity for each available source
is also selectable. Polarity selection is controlled by the
T1GPOL bit of the T1GCON register.
TABLE 20-4:
TIMER1 GATE SOURCES
T1GSS
Timer1 Gate Pin
01
Overflow of Timer0
(TMR0 increments from FFh to 00h)
10
Comparator 1 Output sync_C1OUT

(optionally Timer1 synchronized output)
11
Comparator 2 Output sync_C2OUT

(optionally Timer1 synchronized output)
20.6.2.1
20.6.4
T1G Pin Gate Operation
Timer0 Overflow Gate Operation
When Timer0 increments from FFh to 00h, a low-tohigh pulse will automatically be generated and internally supplied to the Timer1 gate circuitry.
20.6.2.3
Comparator C1 Gate Operation
The output resulting from a Comparator 1 operation can

be selected as a source for Timer1 gate control. The
Comparator 1 output (sync_C1OUT) can be
synchronized to the Timer1 clock or left asynchronous.
For more information see Section 18.4.1 Comparator
Output Synchronization.
20.6.2.4
The Timer1 gate source is routed through a flip-flop that

changes state on every incrementing edge of the signal. See Figure 20-4 for timing details.
Note:
The T1G pin is one source for Timer1 gate control. It

can be used to supply an external source to the Timer1
gate circuitry.
20.6.2.2
When Timer1 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a Timer1 gate
signal, as opposed to the duration of a single level
pulse.
Timer1 Gate Toggle mode is enabled by setting the

T1GTM bit of the T1GCON register. When the T1GTM
bit is cleared, the flip-flop is cleared and held clear. This
is necessary in order to control which edge is
measured.
Timer1 Gate Source
00
TIMER1 GATE TOGGLE MODE
Comparator C2 Gate Operation
The output resulting from a Comparator 2 operation

can be selected as a source for Timer1 gate control.
The Comparator 2 output (sync_C2OUT) can be
synchronized to the Timer1 clock or left asynchronous.
For more information see Section 18.4.1 Comparator
Output Synchronization
Enabling Toggle mode at the same time

as changing the gate polarity may result in
indeterminate operation.
TIMER1 GATE SINGLE-PULSE

MODE
When Timer1 Gate Single-Pulse mode is enabled, it is

possible to capture a single-pulse gate event. Timer1
Gate Single-Pulse mode is first enabled by setting the
T1GSPM bit in the T1GCON register. Next, the T1GGO/
DONE bit in the T1GCON register must be set. The
Timer1 will be fully enabled on the next incrementing
edge. On the next trailing edge of the pulse, the T1GGO/
DONE bit will automatically be cleared. No other gate
events will be allowed to increment Timer1 until the
T1GGO/DONE bit is once again set in software. See
Figure 20-5 for timing details.
If the Single-Pulse Gate mode is disabled by clearing the
T1GSPM bit in the T1GCON register, the T1GGO/DONE
bit should also be cleared.
Enabling the Toggle mode and the Single-Pulse mode
simultaneously will permit both sections to work
together. This allows the cycle times on the Timer1 gate
source to be measured. See Figure 20-6 for timing
details.
20.6.5
TIMER1 GATE VALUE STATUS
When Timer1 Gate Value Status is utilized, it is possible

to read the most current level of the gate control value.
The value is stored in the T1GVAL bit in the T1GCON
register. The T1GVAL bit is valid even when the Timer1
gate is not enabled (TMR1GE bit is cleared).
20.6.6
TIMER1 GATE EVENT INTERRUPT
When Timer1 Gate Event Interrupt is enabled, it is possible to generate an interrupt upon the completion of a
gate event. When the falling edge of T1GVAL occurs,
the TMR1GIF flag bit in the PIR1 register will be set. If
the TMR1GIE bit in the PIE1 register is set, then an
interrupt will be recognized.
The TMR1GIF flag bit operates even when the Timer1
gate is not enabled (TMR1GE bit is cleared).
DS41639A-page 190
Preliminary
PIC16(L)F1454/5/9
20.7
Timer1 Interrupt
20.8
The Timer1 register pair (TMR1H:TMR1L) increments

to FFFFh and rolls over to 0000h. When Timer1 rolls
over, the Timer1 interrupt flag bit of the PIR1 register is
set. To enable the interrupt on rollover, you must set
these bits:
TMR1ON bit of the T1CON register

TMR1IE bit of the PIE1 register
PEIE bit of the INTCON register
GIE bit of the INTCON register
The interrupt is cleared by clearing the TMR1IF bit in

the Interrupt Service Routine.
Note:
The TMR1H:TMR1L register pair and the

TMR1IF bit should be cleared before
enabling interrupts.
Timer1 Operation During Sleep
Timer1 can only operate during Sleep when setup in

Asynchronous Counter mode. In this mode, an external
crystal or clock source can be used to increment the
counter. To set up the timer to wake the device:
TMR1ON bit of the T1CON register must be set

TMR1IE bit of the PIE1 register must be set
PEIE bit of the INTCON register must be set
T1SYNC bit of the T1CON register must be set
TMR1CS bits of the T1CON register must be
configured
T1OSCEN bit of the T1CON register must be
configured
The device will wake-up on an overflow and execute
the next instructions. If the GIE bit of the INTCON
register is set, the device will call the Interrupt Service
Routine.
Timer1 oscillator will continue to operate in Sleep
regardless of the T1SYNC bit setting.
FIGURE 20-2:
TIMER1 INCREMENTING EDGE
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1:
2:
Arrows indicate counter increments.

In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.
Preliminary
DS41639A-page 191
PIC16(L)F1454/5/9
FIGURE 20-3:
TIMER1 GATE ENABLE MODE
TMR1GE
T1GPOL
t1g_in
T1CKI
T1GVAL
Timer1
FIGURE 20-4:
N+1
N+2
N+3
N+4
TIMER1 GATE TOGGLE MODE
TMR1GE
T1GPOL
T1GTM
t1g_in
T1CKI
T1GVAL
Timer1
DS41639A-page 192
N+1 N+2 N+3
N+4
Preliminary
N+5 N+6 N+7
N+8
PIC16(L)F1454/5/9
FIGURE 20-5:
TIMER1 GATE SINGLE-PULSE MODE
TMR1GE
T1GPOL
T1GSPM
T1GGO/
Cleared by hardware on
falling edge of T1GVAL
Set by software
DONE
Counting enabled on
rising edge of T1G
t1g_in
T1CKI
T1GVAL
Timer1
TMR1GIF
N+1
Set by hardware on
Cleared by software
N+2
Preliminary
Cleared by
software
DS41639A-page 193
PIC16(L)F1454/5/9
FIGURE 20-6:
TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE
TMR1GE
T1GPOL
T1GSPM
T1GTM
T1GGO/
Cleared by hardware on
Set by software
DONE
Counting enabled on
rising edge of T1G
t1g_in
T1CKI
T1GVAL
Timer1
TMR1GIF
DS41639A-page 194
Cleared by software
N+1
N+2
N+3
N+4
Set by hardware on
Preliminary
Cleared by
software
PIC16(L)F1454/5/9
20.9
Register Definitions: Timer1 Control
REGISTER 20-1:
R/W-0/u
T1CON: TIMER1 CONTROL REGISTER
R/W-0/u
TMR1CS<1:0>
R/W-0/u
R/W-0/u
T1CKPS<1:0>
R/W-0/u
R/W-0/u
U-0
R/W-0/u
T1OSCEN
T1SYNC
TMR1ON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
TMR1CS<1:0>: Timer1 Clock Source Select bits

11 = Timer1 clock source is Capacitive Sensing Oscillator (CAPOSC)
10 = Timer1 clock source is pin or oscillator:
If T1OSCEN = 0:
External clock from T1CKI pin (on the rising edge)
If T1OSCEN = 1:
Crystal oscillator on T1OSI/T1OSO pins
01 = Timer1 clock source is system clock (FOSC)
00 = Timer1 clock source is instruction clock (FOSC/4)
bit 5-4
T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits

11 = 1:8 Prescale value
bit 3
T1OSCEN: LP Oscillator Enable Control bit

1 = Dedicated Timer1 oscillator circuit enabled
0 = Dedicated Timer1 oscillator circuit disabled
bit 2
T1SYNC: Timer1 Synchronization Control bit

1 = Do not synchronize asynchronous clock input
0 = Synchronize asynchronous clock input with system clock (FOSC)
bit 1
bit 0
TMR1ON: Timer1 On bit

1 = Enables Timer1
0 = Stops Timer1 and clears Timer1 gate flip-flop
Preliminary
DS41639A-page 195
PIC16(L)F1454/5/9
REGISTER 20-2:
T1GCON: TIMER1 GATE CONTROL REGISTER
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
R/W/HC-0/u
R-x/x
TMR1GE
T1GPOL
T1GTM
T1GSPM
T1GGO/
DONE
T1GVAL
R/W-0/u
R/W-0/u
T1GSS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
TMR1GE: Timer1 Gate Enable bit

If TMR1ON = 0:
This bit is ignored
If TMR1ON = 1:
1 = Timer1 counting is controlled by the Timer1 gate function
0 = Timer1 counts regardless of Timer1 gate function
bit 6
T1GPOL: Timer1 Gate Polarity bit

1 = Timer1 gate is active-high (Timer1 counts when gate is high)
0 = Timer1 gate is active-low (Timer1 counts when gate is low)
bit 5
T1GTM: Timer1 Gate Toggle Mode bit

1 = Timer1 Gate Toggle mode is enabled
0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared
Timer1 gate flip-flop toggles on every rising edge.
bit 4
T1GSPM: Timer1 Gate Single-Pulse Mode bit

1 = Timer1 Gate Single-Pulse mode is enabled and is controlling Timer1 gate
0 = Timer1 Gate Single-Pulse mode is disabled
bit 3
T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit

1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge
0 = Timer1 gate single-pulse acquisition has completed or has not been started
bit 2
T1GVAL: Timer1 Gate Current State bit

Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L.
Unaffected by Timer1 Gate Enable (TMR1GE).
bit 1-0
T1GSS<1:0>: Timer1 Gate Source Select bits

11 = Comparator 2 optionally synchronized output (sync_C2OUT)
10 = Comparator 1 optionally synchronized output (sync_C1OUT)
01 = Timer0 overflow output
00 = Timer1 gate pin
DS41639A-page 196
Preliminary
PIC16(L)F1454/5/9
TABLE 20-5:
Name
ANSELA(3)
APFCON

Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSA4
133
CLKRSEL
SDOSEL(2)
SSSEL
T1GSEL
P2SEL(2)
130
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
96
PIE1
TMR1GIE
ADIE(3)
RCIE
TXIE
SSP1IE
TMR2IE
TMR1IE
97
PIR1
TMR1GIF
ADIF(3)
RCIF
TXIF
SSP1IF
TMR2IF
TMR1IF
INTCON
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Count
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Count
TRISA
T1CON
T1GCON
Legend:
*
Note 1:
2:
3:
TMR1CS<1:0>
TMR1GE
T1GPOL
TRISA5
TRISA4
T1CKPS<1:0>
T1GTM
T1GSPM
99
187*
187*
(1)
(1)
(1)
132
T1OSCEN
T1SYNC
TMR1ON
195
T1GGO/
DONE
T1GVAL
T1GSS<1:0>
196
= unimplemented location, read as 0. Shaded cells are not used by the Timer1 module.
PIC16(L)F1455 only.
Preliminary
DS41639A-page 197
PIC16(L)F1454/5/9
NOTES:
DS41639A-page 198
Preliminary
PIC16(L)F1454/5/9
21.0
TIMER2 MODULE
The Timer2 module incorporates the following features:

8-bit Timer and Period registers (TMR2 and PR2,
respectively)
Readable and writable (both registers)
Software programmable prescaler (1:1, 1:4, 1:16,
and 1:64)
Software programmable postscaler (1:1 to 1:16)
Interrupt on TMR2 match with PR2, respectively
Optional use as the shift clock for the MSSP
module (Timer2 only)
See Figure 21-1 for a block diagram of Timer2.
FIGURE 21-1:
TIMER2 BLOCK DIAGRAM

TMR2
Output
FOSC/4
Prescaler
1:1, 1:4, 1:16, 1:64
2
TMR2
Comparator
Sets Flag
bit TMR2IF
Reset
Postscaler
1:1 to 1:16
EQ
T2CKPS<1:0>
4
PR2
T2OUTPS<3:0>
Preliminary
DS41639A-page 199
PIC16(L)F1454/5/9
21.1
Timer2 Operation
21.3
The clock input to the Timer2 module is the system

instruction clock (FOSC/4).
TMR2 increments from 00h on each clock edge.
A 4-bit counter/prescaler on the clock input allows direct
input, divide-by-4 and divide-by-16 prescale options.
These options are selected by the prescaler control bits,
T2CKPS<1:0> of the T2CON register. The value of
TMR2 is compared to that of the Period register, PR2, on
each clock cycle. When the two values match, the
comparator generates a match signal as the timer
output. This signal also resets the value of TMR2 to 00h
on the next cycle and drives the output counter/
postscaler (see Section 21.2 Timer2 Interrupt).
The TMR2 and PR2 registers are both directly readable
and writable. The TMR2 register is cleared on any
device Reset, whereas the PR2 register initializes to
FFh. Both the prescaler and postscaler counters are
cleared on the following events:
Timer2 Output
The unscaled output of TMR2 is available primarily to

the PWM module, where it is used as a time base for
operation.
Timer2 can be optionally used as the shift clock source
for the MSSP module operating in SPI mode.
Additional information is provided in Section 22.1
Master SSP (MSSP) Module Overview.
21.4
Timer2 Operation During Sleep
Timer2 cannot be operated while the processor is in

Sleep mode. The contents of the TMR2 and PR2
registers will remain unchanged while the processor is
in Sleep mode.
a write to the TMR2 register

a write to the T2CON register
MCLR Reset
Watchdog Timer (WDT) Reset
Stack Overflow Reset
Stack Underflow Reset
RESET Instruction
Note:
21.2
TMR2 is not cleared when T2CON is

written.
Timer2 Interrupt
Timer2 can also generate an optional device interrupt.

The Timer2 output signal (TMR2-to-PR2 match)
provides the input for the 4-bit counter/postscaler. This
counter generates the TMR2 match interrupt flag which
is latched in TMR2IF of the PIR1 register. The interrupt
is enabled by setting the TMR2 Match Interrupt Enable
bit, TMR2IE of the PIE1 register.
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS<3:0>, of the T2CON register.
DS41639A-page 200
Preliminary
PIC16(L)F1454/5/9
21.5
Register Definitions: Timer2 Control
REGISTER 21-1:
U-0
T2CON: TIMER2 CONTROL REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
T2OUTPS<3:0>
R/W-0/0
R/W-0/0
TMR2ON
bit 7
R/W-0/0
T2CKPS<1:0>
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-3
T2OUTPS<3:0>: Timer2 Output Postscaler Select bits

1111 = 1:16 Postscaler
bit 2
TMR2ON: Timer2 On bit

1 = Timer2 is on
0 = Timer2 is off
bit 1-0
T2CKPS<1:0>: Timer2 Clock Prescale Select bits

11 = Prescaler is 64
10 = Prescaler is 16
01 = Prescaler is 4
00 = Prescaler is 1
Preliminary
DS41639A-page 201
PIC16(L)F1454/5/9
TABLE 21-1:
Name
INTCON

Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
96
PIE1
TMR1GIE
ADIE(1)
RCIE
TXIE
SSP1IE
TMR2IE
TMR1IE
97
PIR1
TMR1GIF
ADIF(1)
RCIF
TXIF
SSP1IF
TMR2IF
TMR1IF
PR2
Timer2 Module Period Register
99
199*
PWM1CON
PWM1EN
PWM1OE
PWM1OUT PWM1POL
291
PWM2CON
PWM2EN
PWM2OE
PWM2OUT PWM2POL
291
T2CON
TMR2
Legend:
*
Note 1:
T2OUTPS<3:0>
TMR2ON
T2CKPS<1:0>
Holding Register for the 8-bit TMR2 Count
201
199*
= unimplemented location, read as 0. Shaded cells are not used for Timer2 module.
DS41639A-page 202
Preliminary
PIC16(L)F1454/5/9
22.0
MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
22.1
Master SSP (MSSP) Module

Overview
The Master Synchronous Serial Port (MSSP) module is

a serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSPx module
can operate in one of two modes:
Serial Peripheral Interface (SPI)
Inter-Integrated Circuit (I2C)
The SPI interface supports the following modes and
features:
Master mode
Slave mode
Clock Parity
Slave Select Synchronization (Slave mode only)
Daisy-chain connection of slave devices
Figure 22-1 is a block diagram of the SPI interface

module.
FIGURE 22-1:
MSSP BLOCK DIAGRAM (SPI MODE)

Data Bus
Read
Write
SSPBUF Reg
SDI
SDO_out
SSPSR Reg
SDO
bit 0
SS
SS Control
Enable
Shift
Clock
2 (CKP, CKE)
Clock Select
Edge
Select
SCK_out
SSPM<3:0>
4
SCK
Edge
Select
TRIS bit
Preliminary
( TMR22Output )
Prescaler TOSC
4, 16, 64
Baud Rate
Generator
(SSPADD)
DS41639A-page 203
PIC16(L)F1454/5/9
The I2C interface supports the following modes and
features:
Master mode
Slave mode
Byte NACKing (Slave mode)
Limited Multi-master support
7-bit and 10-bit addressing
Start and Stop interrupts
Interrupt masking
Clock stretching
Bus collision detection
General call address matching
Address masking
Address Hold and Data Hold modes
Selectable SDA hold times
Figure 22-2 is a block diagram of the I2C interface module in Master mode. Figure 22-3 is a diagram of the I2C
interface module in Slave mode.
MSSP BLOCK DIAGRAM (I2C MASTER MODE)

Internal
Data Bus
Read
[SSPM<3:0>]
Write
SSP1BUF
Shift
Clock
SDA in
Receive Enable (RCEN)
SCL
SCL in
Bus Collision
DS41639A-page 204
LSb
Start bit, Stop bit,

Acknowledge
Generate (SSPCON2)
Start bit detect,

Stop bit detect
Write collision detect
Clock arbitration
State counter for
end of XMIT/RCV
Address Match detect
Preliminary
Clock Cntl
SSPSR
MSb
(Hold off clock source)
SDA
Baud Rate
Generator
(SSPADD)
Clock arbitrate/BCOL detect
FIGURE 22-2:
Set/Reset: S, P, SSP1STAT, WCOL, SSPOV

Reset SEN, PEN (SSPCON2)
Set SSPIF, BCLIF
PIC16(L)F1454/5/9
FIGURE 22-3:
MSSP BLOCK DIAGRAM (I2C SLAVE MODE)

Internal
Data Bus
Read
Write
SSPBUF Reg
SCL
Shift
Clock
SSPSR Reg
SDA
MSb
LSb
SSPMSK Reg
Match Detect
Addr Match
SSPADD Reg
Start and
Stop bit Detect
Preliminary
Set, Reset
S, P bits
(SSPSTAT Reg)
DS41639A-page 205
PIC16(L)F1454/5/9
22.2
SPI Mode Overview
The Serial Peripheral Interface (SPI) bus is a

synchronous serial data communication bus that
operates in Full-Duplex mode. Devices communicate
in a master/slave environment where the master device
initiates the communication. A slave device is
controlled through a Chip Select known as Slave
Select.
The SPI bus specifies four signal connections:
its SDO pin) and the slave device is reading this bit and
saving it as the LSb of its shift register, that the slave
device is also sending out the MSb from its shift register
(on its SDO pin) and the master device is reading this
bit and saving it as the LSb of its shift register.
After eight bits have been shifted out, the master and
slave have exchanged register values.
If there is more data to exchange, the shift registers are
loaded with new data and the process repeats itself.
Whether the data is meaningful or not (dummy data),
depends on the application software. This leads to
three scenarios for data transmission:
Serial Clock (SCK)

Serial Data Out (SDO)
Serial Data In (SDI)
Slave Select (SS)
Figure 22-1 shows the block diagram of the MSSP

module when operating in SPI mode.
The SPI bus operates with a single master device and
one or more slave devices. When multiple slave
devices are used, an independent Slave Select connection is required from the master device to each
slave device.
Figure 22-4 shows a typical connection between a
master device and multiple slave devices.
The master selects only one slave at a time. Most slave
devices have tri-state outputs so their output signal
appears disconnected from the bus when they are not
selected.
Master sends useful data and slave sends dummy

data.
Master sends useful data and slave sends useful
data.
Master sends dummy data and slave sends useful
data.
Transmissions may involve any number of clock
cycles. When there is no more data to be transmitted,
the master stops sending the clock signal and it deselects the slave.
Every slave device connected to the bus that has not
been selected through its slave select line must disregard the clock and transmission signals and must not
transmit out any data of its own.
Transmissions involve two shift registers, eight bits in

size, one in the master and one in the slave. With either
the master or the slave device, data is always shifted
out one bit at a time, with the Most Significant bit (MSb)
shifted out first. At the same time, a new Least
Significant bit (LSb) is shifted into the same register.
Figure 22-5 shows a typical connection between two
processors configured as master and slave devices.
Data is shifted out of both shift registers on the programmed clock edge and latched on the opposite edge
of the clock.
The master device transmits information out on its SDO
output pin which is connected to, and received by, the
slave's SDI input pin. The slave device transmits information out on its SDO output pin, which is connected
to, and received by, the master's SDI input pin.
To begin communication, the master device first sends
out the clock signal. Both the master and the slave
devices should be configured for the same clock polarity.
The master device starts a transmission by sending out
the MSb from its shift register. The slave device reads
this bit from that same line and saves it into the LSb
position of its shift register.
During each SPI clock cycle, a full-duplex data
transmission occurs. This means that while the master
device is sending out the MSb from its shift register (on
DS41639A-page 206
Preliminary
PIC16(L)F1454/5/9
FIGURE 22-4:
SPI MASTER AND MULTIPLE SLAVE CONNECTION
SPI Master
SCK
SCK
SDO
SDI
SDI
SDO
General I/O
General I/O
SS
General I/O
SCK
SDI
SDO
SPI Slave
#1
SPI Slave
#2
SS
SCK
SDI
SDO
SPI Slave
#3
SS
22.2.1
SPI MODE REGISTERS
The MSSP module has five registers for SPI mode

operation. These are:
MSSP STATUS register (SSPSTAT)

MSSP Control Register 1 (SSPCON1)
MSSP Control Register 3 (SSPCON3)
MSSP Data Buffer register (SSPBUF)
MSSP Address register (SSPADD)
MSSP Shift register (SSPSR)
(Not directly accessible)
SSPCON1 and SSPSTAT are the control and STATUS

registers in SPI mode operation. The SSPCON1 register is readable and writable. The lower six bits of the
SSPSTAT are read-only. The upper two bits of the
SSPSTAT are read/write.
In one SPI master mode, SSPADD can be loaded with
a value used in the Baud Rate Generator. More information on the Baud Rate Generator is available in
Section 22.7 Baud Rate Generator.
SSPSR is the shift register used for shifting data in and
out. SSPBUF provides indirect access to the SSPSR
register. SSPBUF is the buffer register to which data
bytes are written, and from which data bytes are read.
In receive operations, SSPSR and SSPBUF together
create a buffered receiver. When SSPSR receives a
complete byte, it is transferred to SSPBUF and the
SSPIF interrupt is set.
During transmission, the SSPBUF is not buffered. A
write to SSPBUF will write to both SSPBUF and
SSPSR.
Preliminary
DS41639A-page 207
PIC16(L)F1454/5/9
22.2.2
SPI MODE OPERATION
When initializing the SPI, several options need to be

specified. This is done by programming the appropriate
control bits (SSPCON1<5:0> and SSPSTAT<7:6>).
These control bits allow the following to be specified:
Master mode (SCK is the clock output)

Slave mode (SCK is the clock input)
Clock Polarity (Idle state of SCK)
Data Input Sample Phase (middle or end of data
output time)
Clock Edge (output data on rising/falling edge of
SCK)
Clock Rate (Master mode only)
Slave Select mode (Slave mode only)
To enable the serial port, SSP Enable bit, SSPEN of the
SSPCON1 register, must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the
SSPCONx registers and then set the SSPEN bit. This
configures the SDI, SDO, SCK and SS pins as serial
port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the
TRIS register) appropriately programmed as follows:
SDI must have corresponding TRIS bit set
SDO must have corresponding TRIS bit cleared
SCK (Master mode) must have corresponding
TRIS bit cleared
SCK (Slave mode) must have corresponding
TRIS bit set
SS must have corresponding TRIS bit set
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
FIGURE 22-5:
The MSSP consists of a transmit/receive shift register

(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR
until the received data is ready. Once the eight bits of
data have been received, that byte is moved to the
SSPBUF register. Then, the Buffer Full Detect bit, BF
of the SSPSTAT register, and the interrupt flag bit,
SSPIF, are set. This double-buffering of the received
data (SSPBUF) allows the next byte to start reception
before reading the data that was just received. Any
write
to
the
SSPBUF
register
during
transmission/reception of data will be ignored and the
write collision detect bit WCOL of the SSPCON1
register, will be set. User software must clear the
WCOL bit to allow the following write(s) to the SSPBUF
register to complete successfully.
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. The
Buffer Full bit, BF of the SSPSTAT register, indicates
when SSPBUF has been loaded with the received data
(transmission is complete). When the SSPBUF is read,
the BF bit is cleared. This data may be irrelevant if the
SPI is only a transmitter. Generally, the MSSP interrupt
is used to determine when the transmission/reception
has completed. If the interrupt method is not going to
be used, then software polling can be done to ensure
that a write collision does not occur.
The SSPSR is not directly readable or writable and can
only be accessed by addressing the SSPBUF register.
Additionally, the SSPSTAT register indicates the
various Status conditions.
SPI MASTER/SLAVE CONNECTION
SPI Master SSPM<3:0> = 00xx

= 1010
SPI Slave SSPM<3:0> = 010x

SDO
SDI
Serial Input Buffer

(BUF)
SDI
Shift Register
(SSPSR)
MSb
Serial Input Buffer

(SSPBUF)
LSb
SCK
General I/O
Processor 1
DS41639A-page 208
SDO
Serial Clock
Slave Select
(optional)
Preliminary
Shift Register
(SSPSR)
MSb
LSb
SCK
SS
Processor 2
PIC16(L)F1454/5/9
22.2.3
SPI MASTER MODE
The master can initiate the data transfer at any time

because it controls the SCK line. The master
determines when the slave (Processor 2, Figure 22-5)
is to broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SDO output could be disabled (programmed as an input). The SSPSR register
will continue to shift in the signal present on the SDI pin
at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and Status bits
appropriately set).
The clock polarity is selected by appropriately

programming the CKP bit of the SSPCON1 register
and the CKE bit of the SSPSTAT register. This then,
would give waveforms for SPI communication as
shown in Figure 22-6, Figure 22-8, Figure 22-9 and
Figure 22-10, where the MSB is transmitted first. In
Master mode, the SPI clock rate (bit rate) is user
programmable to be one of the following:
FOSC/4 (or TCY)

FOSC/16 (or 4 * TCY)
FOSC/64 (or 16 * TCY)
Timer2 output/2
Fosc/(4 * (SSPADD + 1))
Figure 22-6 shows the waveforms for Master mode.

When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
data is shown.
FIGURE 22-6:
SPI MODE WAVEFORM (MASTER MODE)
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
Modes
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
SDO
(CKE = 0)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDO
(CKE = 1)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit 0
bit 7
Input
Sample
(SMP = 1)
SSPIF
SSPSR to
SSPBUF
Preliminary
DS41639A-page 209
PIC16(L)F1454/5/9
22.2.4
22.2.5
SPI SLAVE MODE
In Slave mode, the data is transmitted and received as

external clock pulses appear on SCK. When the last
bit is latched, the SSPIF interrupt flag bit is set.
Before enabling the module in SPI Slave mode, the clock
line must match the proper Idle state. The clock line can
be observed by reading the SCK pin. The Idle state is
determined by the CKP bit of the SSPCON1 register.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
While in Sleep mode, the slave can transmit/receive
data. The shift register is clocked from the SCK pin
input and when a byte is received, the device will generate an interrupt. If enabled, the device will wake-up
from Sleep.
22.2.4.1
Daisy-Chain Configuration
The SPI bus can sometimes be connected in a

daisy-chain configuration. The first slave output is connected to the second slave input, the second slave
output is connected to the third slave input, and so on.
The final slave output is connected to the master input.
Each slave sends out, during a second group of clock
pulses, an exact copy of what was received during the
first group of clock pulses. The whole chain acts as
one large communication shift register. The
daisy-chain feature only requires a single Slave Select
line from the master device.
Figure 22-7 shows the block diagram of a typical
daisy-chain connection when operating in SPI Mode.
In a daisy-chain configuration, only the most recent
byte on the bus is required by the slave. Setting the
BOEN bit of the SSPCON3 register will enable writes
to the SSPBUF register, even if the previous byte has
not been read. This allows the software to ignore data
that may not apply to it.
SLAVE SELECT
SYNCHRONIZATION
The Slave Select can also be used to synchronize communication. The Slave Select line is held high until the
master device is ready to communicate. When the
Slave Select line is pulled low, the slave knows that a
new transmission is starting.
If the slave fails to receive the communication properly,
it will be reset at the end of the transmission, when the
Slave Select line returns to a high state. The slave is
then ready to receive a new transmission when the
Slave Select line is pulled low again. If the Slave Select
line is not used, there is a risk that the slave will eventually become out of sync with the master. If the slave
misses a bit, it will always be one bit off in future transmissions. Use of the Slave Select line allows the slave
and master to align themselves at the beginning of
each transmission.
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SS pin control enabled
(SSPCON1<3:0> = 0100).
When the SS pin is low, transmission and reception are
enabled and the SDO pin is driven.
When the SS pin goes high, the SDO pin is no longer
driven, even if in the middle of a transmitted byte and
becomes a floating output. External pull-up/pull-down
resistors may be desirable depending on the application.
Note 1: When the SPI is in Slave mode with SS pin
control enabled (SSPCON1<3:0> =
0100), the SPI module will reset if the SS
pin is set to VDD.
2: When the SPI is used in Slave mode with
CKE set; the user must enable SS pin
control.
3: While operated in SPI Slave mode the
SMP bit of the SSPSTAT register must
remain clear.
When the SPI module resets, the bit counter is forced

to 0. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit.
DS41639A-page 210
Preliminary
PIC16(L)F1454/5/9
FIGURE 22-7:
SPI DAISY-CHAIN CONNECTION
SPI Master
SCK
SCK
SDO
SDI
SDI
SPI Slave
#1
SDO
General I/O
SS
SCK
SDI
SPI Slave
#2
SDO
SS
SCK
SDI
SPI Slave
#3
SDO
SS
FIGURE 22-8:
SLAVE SELECT SYNCHRONOUS WAVEFORM
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
Shift register SSPSR

and bit count are reset
SSPBUF to
SSPSR
SDO
bit 7
bit 6
bit 7
SDI
bit 6
bit 0
bit 0
bit 7
bit 7
Input
Sample
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
Preliminary
DS41639A-page 211
PIC16(L)F1454/5/9
FIGURE 22-9:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
Valid
SDO
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDI
bit 0
bit 7
Input
Sample
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
Write Collision
detection active
FIGURE 22-10:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
Valid
SDO
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDI
bit 0
bit 7
Input
Sample
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
Write Collision
detection active
DS41639A-page 212
Preliminary
PIC16(L)F1454/5/9
22.2.6
SPI OPERATION IN SLEEP MODE
In SPI Master mode, module clocks may be operating

at a different speed than when in full power mode; in
the case of the Sleep mode, all clocks are halted.
Special care must be taken by the user when the MSSP
clock is much faster than the system clock.
In Slave mode, when MSSP interrupts are enabled,
after the master completes sending data, an MSSP
interrupt will wake the controller from Sleep.
If an exit from Sleep mode is not desired, MSSP interrupts should be disabled.
TABLE 22-1:
In SPI Master mode, when the Sleep mode is selected,

all module clocks are halted and the transmission/reception will remain in that state until the device
wakes. After the device returns to Run mode, the module will resume transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in Sleep mode and data
to be shifted into the SPI Transmit/Receive Shift
register. When all eight bits have been received, the
MSSP interrupt flag bit will be set and if enabled, will
wake the device.
SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSELA(3)
ANSA4
133
INTCON
PIE1
PIR1
SSP1BUF
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
96
TMR1GIE
ADIE(3)
RCIE
TXIE
SSP1IE
TMR2IE
TMR1IE
97
TMR1GIF
ADIF(3)
RCIF
TXIF
SSP1IF
TMR2IF
TMR1IF
Synchronous Serial Port Receive Buffer/Transmit Register
SSP1CON1
WCOL
SSPOV
SSPEN
CKP
SSP1CON3
ACKTIM
PCIE
SCIE
BOEN
SSP1STAT
99
207*
SSPM<3:0>
SDAHT
SBCDE
AHEN
253
DHEN
255
SMP
CKE
D/A
R/W
UA
BF
251
TRISA
TRISA5
TRISA4
(1)
(1)
(1)
132
TRISC
TRISC7(2)
TRISC6(2)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
140
Legend:
*
Note 1:
2:
3:
= Unimplemented location, read as 0. Shaded cells are not used by the MSSP in SPI mode.
PIC16(L)F1459 only.
Preliminary
DS41639A-page 213
PIC16(L)F1454/5/9
22.3
I2C MODE OVERVIEW
FIGURE 22-11:
The Inter-Integrated Circuit Bus (IC) is a multi-master

serial data communication bus. Devices communicate
in a master/slave environment where the master
devices initiate the communication. A Slave device is
controlled through addressing.
VDD
SCL
The I2C bus specifies two signal connections:

Serial Clock (SCL)
Serial Data (SDA)
Figure 22-11 shows a typical connection between two

processors configured as master and slave devices.
The I2C bus can operate with one or more master
devices and one or more slave devices.
There are four potential modes of operation for a given
device:
Master Transmit mode
(master is transmitting data to a slave)
Master Receive mode
(master is receiving data from a slave)
Slave Transmit mode
(slave is transmitting data to a master)
Slave Receive mode
(slave is receiving data from the master)
SDA
The Acknowledge bit (ACK) is an active-low signal,

which holds the SDA line low to indicate to the transmitter that the slave device has received the transmitted
data and is ready to receive more.
The transition of a data bit is always performed while
the SCL line is held low. Transitions that occur while the
SCL line is held high are used to indicate Start and Stop
bits.
If the master intends to write to the slave, then it repeatedly sends out a byte of data, with the slave responding
after each byte with an ACK bit. In this example, the
master device is in Master Transmit mode and the
slave is in Slave Receive mode.
If the master intends to read from the slave, then it
repeatedly receives a byte of data from the slave, and
responds after each byte with an ACK bit. In this example, the master device is in Master Receive mode and
the slave is Slave Transmit mode.
To begin communication, a master device starts out in

Master Transmit mode. The master device sends out a
Start bit followed by the address byte of the slave it
intends to communicate with. This is followed by a single Read/Write bit, which determines whether the master intends to transmit to or receive data from the slave
device.
If the requested slave exists on the bus, it will respond
with an Acknowledge bit, otherwise known as an ACK.
The master then continues in either Transmit mode or
Receive mode and the slave continues in the complement, either in Receive mode or Transmit mode,
respectively.
A Start bit is indicated by a high-to-low transition of the
SDA line while the SCL line is held high. Address and
data bytes are sent out, Most Significant bit (MSb) first.
The Read/Write bit is sent out as a logical one when the
master intends to read data from the slave, and is sent
out as a logical zero when it intends to write data to the
slave.
DS41639A-page 214
Slave
SDA
Figure 22-11 shows the block diagram of the MSSP

module when operating in I2C mode.
SCL
VDD
Master
Both the SCL and SDA connections are bidirectional

open-drain lines, each requiring pull-up resistors for the
supply voltage. Pulling the line to ground is considered
a logical zero and letting the line float is considered a
logical one.
I2C MASTER/
SLAVE CONNECTION
On the last byte of data communicated, the master

device may end the transmission by sending a Stop bit.
If the master device is in Receive mode, it sends the
Stop bit in place of the last ACK bit. A Stop bit is indicated by a low-to-high transition of the SDA line while
the SCL line is held high.
In some cases, the master may want to maintain control of the bus and re-initiate another transmission. If
so, the master device may send another Start bit in
place of the Stop bit or last ACK bit when it is in receive
mode.
The I2C bus specifies three message protocols;
Single message where a master writes data to a
slave.
Single message where a master reads data from
a slave.
Combined message where a master initiates a
minimum of two writes, or two reads, or a
combination of writes and reads, to one or more
slaves.
Preliminary
PIC16(L)F1454/5/9
When one device is transmitting a logical one, or letting
the line float, and a second device is transmitting a logical zero, or holding the line low, the first device can
detect that the line is not a logical one. This detection,
when used on the SCL line, is called clock stretching.
Clock stretching gives slave devices a mechanism to
control the flow of data. When this detection is used on
the SDA line, it is called arbitration. Arbitration ensures
that there is only one master device communicating at
any single time.
22.3.1
CLOCK STRETCHING
When a slave device has not completed processing

data, it can delay the transfer of more data through the
process of Clock Stretching. An addressed slave
device may hold the SCL clock line low after receiving
or sending a bit, indicating that it is not yet ready to continue. The master that is communicating with the slave
will attempt to raise the SCL line in order to transfer the
next bit, but will detect that the clock line has not yet
been released. Because the SCL connection is
open-drain, the slave has the ability to hold that line low
until it is ready to continue communicating.
Clock stretching allows receivers that cannot keep up
with a transmitter to control the flow of incoming data.
22.3.2
ARBITRATION
Each master device must monitor the bus for Start and
Stop bits. If the device detects that the bus is busy, it
cannot begin a new message until the bus returns to an
Idle state.
However, two master devices may try to initiate a transmission on or about the same time. When this occurs,
the process of arbitration begins. Each transmitter
checks the level of the SDA data line and compares it
to the level that it expects to find. The first transmitter to
observe that the two levels do not match, loses arbitration, and must stop transmitting on the SDA line.
For example, if one transmitter holds the SDA line to a
logical one (lets it float) and a second transmitter holds
it to a logical zero (pulls it low), the result is that the
SDA line will be low. The first transmitter then observes
that the level of the line is different than expected and
concludes that another transmitter is communicating.
The first transmitter to notice this difference is the one
that loses arbitration and must stop driving the SDA
line. If this transmitter is also a master device, it also
must stop driving the SCL line. It then can monitor the
lines for a Stop condition before trying to reissue its
transmission. In the meantime, the other device that
has not noticed any difference between the expected
and actual levels on the SDA line continues with its
original transmission. It can do so without any complications, because so far, the transmission appears
exactly as expected with no other transmitter disturbing
the message.
Slave Transmit mode can also be arbitrated, when a
master addresses multiple slaves, but this is less common.
If two master devices are sending a message to two different slave devices at the address stage, the master
sending the lower slave address always wins arbitration. When two master devices send messages to the
same slave address, and addresses can sometimes
refer to multiple slaves, the arbitration process must
continue into the data stage.
Arbitration usually occurs very rarely, but it is a necessary process for proper multi-master support.
Preliminary
DS41639A-page 215
PIC16(L)F1454/5/9
22.4
I2C MODE OPERATION
TABLE 22-2:
All MSSP I2C communication is byte oriented and

shifted out MSb first. Six SFR registers and two
interrupt flags interface the module with the PIC
microcontroller and user software. Two pins, SDA and
SCL, are exercised by the module to communicate
with other external I2C devices.
22.4.1
BYTE FORMAT
All communication in I2C is done in 9-bit segments. A

byte is sent from a master to a slave or vice-versa, followed by an Acknowledge bit sent back. After the 8th
falling edge of the SCL line, the device outputting data
on the SDA changes that pin to an input and reads in
an acknowledge value on the next clock pulse.
The clock signal, SCL, is provided by the master. Data
is valid to change while the SCL signal is low, and
sampled on the rising edge of the clock. Changes on
the SDA line while the SCL line is high define special
conditions on the bus, explained below.
22.4.2
DEFINITION OF I2C TERMINOLOGY
There is language and terminology in the description

of I2C communication that have definitions specific to
I2C. That word usage is defined below and may be
used in the rest of this document without explanation.
This table was adapted from the Philips I2C
specification.
22.4.3
SDA AND SCL PINS
Selection of any I2C mode with the SSPEN bit set,

forces the SCL and SDA pins to be open-drain. These
pins should be set by the user to inputs by setting the
appropriate TRIS bits.
Note: Data is tied to output zero when an I2C
mode is enabled.
22.4.4
SDA HOLD TIME
The hold time of the SDA pin is selected by the SDAHT

bit of the SSPCON3 register. Hold time is the time SDA
is held valid after the falling edge of SCL. Setting the
SDAHT bit selects a longer 300 ns minimum hold time
and may help on buses with large capacitance.
DS41639A-page 216
TERM
I2C BUS TERMS

Description
Transmitter
The device which shifts data out

onto the bus.
Receiver
The device which shifts data in
from the bus.
Master
The device that initiates a transfer,
generates clock signals and terminates a transfer.
Slave
The device addressed by the master.
Multi-master
A bus with more than one device
that can initiate data transfers.
Arbitration
Procedure to ensure that only one
master at a time controls the bus.
Winning arbitration ensures that
the message is not corrupted.
Synchronization Procedure to synchronize the
clocks of two or more devices on
the bus.
Idle
No master is controlling the bus,
and both SDA and SCL lines are
high.
Active
Any time one or more master
devices are controlling the bus.
Addressed
Slave device that has received a
Slave
matching address and is actively
being clocked by a master.
Matching
Address byte that is clocked into a
Address
slave that matches the value
stored in SSPADD.
Write Request
Slave receives a matching
address with R/W bit clear, and is
ready to clock in data.
Read Request
Master sends an address byte with
the R/W bit set, indicating that it
wishes to clock data out of the
Slave. This data is the next and all
following bytes until a Restart or
Stop.
Clock Stretching When a device on the bus hold
SCL low to stall communication.
Bus Collision
Any time the SDA line is sampled
low by the module while it is outputting and expected high state.
Preliminary
PIC16(L)F1454/5/9
22.4.5
START CONDITION
22.4.7
The I2C specification defines a Start condition as a

transition of SDA from a high to a low state while SCL
line is high. A Start condition is always generated by
the master and signifies the transition of the bus from
an Idle to an Active state. Figure 22-12 shows wave
forms for Start and Stop conditions.
A bus collision can occur on a Start condition if the
module samples the SDA line low before asserting it
low. This does not conform to the I2C Specification that
states no bus collision can occur on a Start.
22.4.6
STOP CONDITION
A Stop condition is a transition of the SDA line from

low-to-high state while the SCL line is high.
Note: At least one SCL low time must appear
before a Stop is valid, therefore, if the SDA
line goes low then high again while the SCL
line stays high, only the Start condition is
detected.
RESTART CONDITION
A Restart is valid any time that a Stop would be valid.

A master can issue a Restart if it wishes to hold the
bus after terminating the current transfer. A Restart
has the same effect on the slave that a Start would,
resetting all slave logic and preparing it to clock in an
address. The master may want to address the same or
another slave. Figure 22-13 shows wave forms for a
Restart condition.
In 10-bit Addressing Slave mode a Restart is required
for the master to clock data out of the addressed
slave. Once a slave has been fully addressed, matching both high and low address bytes, the master can
issue a Restart and the high address byte with the
R/W bit set. The slave logic will then hold the clock
and prepare to clock out data.
After a full match with R/W clear in 10-bit mode, a prior
match flag is set and maintained. Until a Stop condition, a high address with R/W clear, or high address
match fails.
22.4.8
START/STOP CONDITION INTERRUPT

MASKING
The SCIE and PCIE bits of the SSPCON3 register can

enable the generation of an interrupt in Slave modes
that do not typically support this function. Slave modes
where interrupt on Start and Stop detect are already
enabled, these bits will have no effect.
FIGURE 22-12:
I2C START AND STOP CONDITIONS
SDA
SCL
S
Start
P
Change of
Change of
Data Allowed
Data Allowed
Condition
Stop
Condition
Preliminary
DS41639A-page 217
PIC16(L)F1454/5/9
FIGURE 22-13:
I2C RESTART CONDITION
Sr
Change of
Change of
Data Allowed
Restart
Data Allowed
Condition
DS41639A-page 218
Preliminary
PIC16(L)F1454/5/9
22.4.9
22.5
ACKNOWLEDGE SEQUENCE
The 9th SCL pulse for any transferred byte in I2C is

dedicated as an Acknowledge. It allows receiving
devices to respond back to the transmitter by pulling
the SDA line low. The transmitter must release control
of the line during this time to shift in the response. The
Acknowledge (ACK) is an active-low signal, pulling the
SDA line low indicated to the transmitter that the
device has received the transmitted data and is ready
to receive more.
The result of an ACK is placed in the ACKSTAT bit of
the SSPCON2 register.
Slave software, when the AHEN and DHEN bits are
set, allow the user to set the ACK value sent back to
the transmitter. The ACKDT bit of the SSPCON2 register is set/cleared to determine the response.
Slave hardware will generate an ACK response if the
AHEN and DHEN bits of the SSPCON3 register are
clear.
There are certain conditions where an ACK will not be
sent by the slave. If the BF bit of the SSPSTAT register
or the SSPOV bit of the SSPCON1 register are set
when a byte is received.
When the module is addressed, after the 8th falling
edge of SCL on the bus, the ACKTIM bit of the
SSPCON3 register is set. The ACKTIM bit indicates
the acknowledge time of the active bus. The ACKTIM
Status bit is only active when the AHEN bit or DHEN
bit is enabled.
I2C SLAVE MODE OPERATION
The MSSP Slave mode operates in one of four modes

selected in the SSPM bits of SSPCON1 register. The
modes can be divided into 7-bit and 10-bit Addressing
mode. 10-bit Addressing modes operate the same as
7-bit with some additional overhead for handling the
larger addresses.
Modes with Start and Stop bit interrupts operated the
same as the other modes with SSPIF additionally getting set upon detection of a Start, Restart, or Stop
condition.
22.5.1
SLAVE MODE ADDRESSES
The SSPADD register (Register 22-6) contains the

Slave mode address. The first byte received after a
Start or Restart condition is compared against the
value stored in this register. If the byte matches, the
value is loaded into the SSPBUF register and an interrupt is generated. If the value does not match, the
module goes idle and no indication is given to the software that anything happened.
The SSP Mask register (Register 22-5) affects the
address matching process. See Section 22.5.9 SSP
Mask Register for more information.
22.5.1.1
I2C Slave 7-bit Addressing Mode
In 7-bit Addressing mode, the LSb of the received data

byte is ignored when determining if there is an address
match.
22.5.1.2
I2C Slave 10-bit Addressing Mode
In 10-bit Addressing mode, the first received byte is

compared to the binary value of 1 1 1 1 0 A9 A8 0. A9
and A8 are the two MSb of the 10-bit address and
stored in bits 2 and 1 of the SSPADD register.
After the acknowledge of the high byte the UA bit is set
and SCL is held low until the user updates SSPADD
with the low address. The low address byte is clocked
in and all eight bits are compared to the low address
value in SSPADD. Even if there is not an address
match; SSPIF and UA are set, and SCL is held low
until SSPADD is updated to receive a high byte again.
When SSPADD is updated the UA bit is cleared. This
ensures the module is ready to receive the high
address byte on the next communication.
A high and low address match as a write request is
required at the start of all 10-bit addressing communication. A transmission can be initiated by issuing a
Restart once the slave is addressed, and clocking in
the high address with the R/W bit set. The slave hardware will then acknowledge the read request and prepare to clock out data. This is only valid for a slave
after it has received a complete high and low address
byte match.
Preliminary
DS41639A-page 219
PIC16(L)F1454/5/9
22.5.2
22.5.2.2
SLAVE RECEPTION
When the R/W bit of a matching received address byte

is clear, the R/W bit of the SSPSTAT register is cleared.
The received address is loaded into the SSPBUF register and acknowledged.
When the overflow condition exists for a received
address, then not Acknowledge is given. An overflow
condition is defined as either bit BF of the SSPSTAT
register is set, or bit SSPOV of the SSPCON1 register
is set. The BOEN bit of the SSPCON3 register modifies
this operation. For more information see Register 22-4.
An MSSP interrupt is generated for each transferred
data byte. Flag bit, SSPIF, must be cleared by software.
When the SEN bit of the SSPCON2 register is set, SCL
will be held low (clock stretch) following each received
byte. The clock must be released by setting the CKP
bit of the SSPCON1 register, except sometimes in
10-bit mode. See Section 22.2.3 SPI Master Mode
for more detail.
22.5.2.1
7-bit Addressing Reception
This section describes a standard sequence of events

for the MSSP module configured as an I2C Slave in
7-bit Addressing mode. All decisions made by hardware or software and their effect on reception.
Figure 22-14 and Figure 22-15 is used as a visual
reference for this description.
This is a step by step process of what typically must
be done to accomplish I2C communication.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
Start bit detected.

S bit of SSPSTAT is set; SSPIF is set if interrupt
on Start detect is enabled.
Matching address with R/W bit clear is received.
The slave pulls SDA low sending an ACK to the
master, and sets SSPIF bit.
Software clears the SSPIF bit.
Software reads received address from SSPBUF
clearing the BF flag.
If SEN = 1; Slave software sets CKP bit to
release the SCL line.
The master clocks out a data byte.
Slave drives SDA low sending an ACK to the
master, and sets SSPIF bit.
Software clears SSPIF.
Software reads the received byte from SSPBUF
clearing BF.
Steps 8-12 are repeated for all received bytes
from the master.
Master sends Stop condition, setting P bit of
SSPSTAT, and the bus goes idle.
DS41639A-page 220
7-bit Reception with AHEN and DHEN
Slave device reception with AHEN and DHEN set

operate the same as without these options with extra
interrupts and clock stretching added after the 8th falling edge of SCL. These additional interrupts allow the
slave software to decide whether it wants to ACK the
receive address or data byte, rather than the hardware. This functionality adds support for PMBus that
was not present on previous versions of this module.
This list describes the steps that need to be taken by
slave software to use these options for I2C communcation. Figure 22-16 displays a module using both
address and data holding. Figure 22-17 includes the
operation with the SEN bit of the SSPCON2 register
set.
1.
S bit of SSPSTAT is set; SSPIF is set if interrupt

2. Matching address with R/W bit clear is clocked
in. SSPIF is set and CKP cleared after the 8th
falling edge of SCL.
3. Slave clears the SSPIF.
4. Slave can look at the ACKTIM bit of the
SSPCON3 register to determine if the SSPIF
was after or before the ACK.
5. Slave reads the address value from SSPBUF,
6. Slave sets ACK value clocked out to the master
by setting ACKDT.
7. Slave releases the clock by setting CKP.
8. SSPIF is set after an ACK, not after a NACK.
9. If SEN = 1 the slave hardware will stretch the
clock after the ACK.
10. Slave clears SSPIF.
Note: SSPIF is still set after the 9th falling edge of
SCL even if there is no clock stretching and
BF has been cleared. Only if NACK is sent
to Master is SSPIF not set
11. SSPIF set and CKP cleared after 8th falling

edge of SCL for a received data byte.
12. Slave looks at ACKTIM bit of SSPCON3 to
determine the source of the interrupt.
13. Slave reads the received data from SSPBUF
clearing BF.
14. Steps 7-14 are the same for each received data
byte.
15. Communication is ended by either the slave
sending an ACK = 1, or the master sending a
Stop condition. If a Stop is sent and Interrupt on
Stop Detect is disabled, the slave will only know
by polling the P bit of the SSTSTAT register.
Preliminary
Preliminary
SSPOV
BF
SSPIF
A7
A6
A5
A4
A3
Receiving Address
A2
A1
ACK
D7
D6
D3
D2
D1
SSPBUF is read
Cleared by software
D4
Receiving Data
D5
D6
First byte
of data is
available
in SSPBUF
D0 ACK D7
D3
D2
D1
SSPOV set because

SSPBUF is still full.
ACK is not sent.
Cleared by software
D4
Receiving Data
D5
D0
SSPIF set on 9th

falling edge of
SCL
ACK = 1
FIGURE 22-14:
SCL
SDA
From Slave to Master
Bus Master sends

Stop condition
PIC16(L)F1454/5/9
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0)
DS41639A-page 221
DS41639A-page 222
Preliminary
CKP
SSPOV
BF
SSPIF
SCL
A7
A6
A5
A4
A3
A2
A1
R/W=0 ACK
SEN
2
D6
D5
D4
D3
D2
D1
D0
CKP is written to 1 in software,

releasing SCL
SSPBUF is read
Cleared by software
Clock is held low until CKP is set to 1
D7
Receive Data
ACK
SEN
3
D5
D4
D3
First byte
of data is
available
in SSPBUF
D2
D1
SSPOV set because

SSPBUF is still full.
ACK is not sent.
Cleared by software
D6
CKP is written to 1 in software,

releasing SCL
D7
Receive Data
D0
ACK
SCL is not held

low because
ACK= 1
SSPIF set on 9th

falling edge of SCL
FIGURE 22-15:
SDA
Receive Address
Bus Master sends

Stop condition
PIC16(L)F1454/5/9
Preliminary
ACKTIM
CKP
ACKDT
BF
SSPIF
Receiving Address
ACK the received

byte
Slave software
clears ACKDT to
Address is
read from
SSBUF
If AHEN = 1:
SSPIF is set
ACKTIM set by hardware

on 8th falling edge of SCL
When AHEN=1:
CKP is cleared by hardware
and SCL is stretched
A7 A6 A5 A4 A3 A2 A1
Receiving Data
9
2
ACKTIM cleared by
hardware in 9th
rising edge of SCL
When DHEN=1:
CKP is cleared by
hardware on 8th falling
edge of SCL
SSPIF is set on
9th falling edge of
SCL, after ACK
ACK D7 D6 D5 D4 D3 D2 D1 D0
Received Data
ACKTIM set by hardware

CKP set by software,

SCL is released
Slave software
sets ACKDT to
not ACK
Cleared by software
D7 D6 D5 D4 D3 D2 D1 D0
Data is read from SSPBUF
ACK
No interrupt
after not ACK
from Slave
ACK=1
Master sends
Stop condition
FIGURE 22-16:
SCL
SDA
Master Releases SDA

to slave for ACK sequence
PIC16(L)F1454/5/9
DS41639A-page 223
DS41639A-page 224
Preliminary
ACKTIM
CKP
ACKDT
BF
SSPIF
Receiving Address
4
5
6 7
When AHEN = 1;
on the 8th falling edge
of SCL of an address
byte, CKP is cleared
Slave software clears

ACKDT to ACK
the received byte
Received
address is loaded into
SSPBUF
2 3
ACKTIM is set by hardware

A7 A6 A5 A4 A3 A2 A1
ACK
Receive Data
2 3
6 7
ACKTIM is cleared by hardware

on 9th rising edge of SCL
When DHEN = 1;
of SCL of a received
data byte, CKP is cleared
Received data is
available on SSPBUF
Cleared by software
D7 D6 D5 D4 D3 D2 D1 D0
ACK
Receive Data
1
3 4
6 7
Set by software,
release SCL
Slave sends
not ACK
SSPBUF can be
read any time before
next byte is loaded
D7 D6 D5 D4 D3 D2 D1 D0
ACK
CKP is not cleared

if not ACK
No interrupt after
if not ACK
from Slave
Master sends
Stop condition
FIGURE 22-17:
SCL
SDA
R/W = 0
Master releases
SDA to slave for ACK sequence
PIC16(L)F1454/5/9
PIC16(L)F1454/5/9
22.5.3
SLAVE TRANSMISSION
22.5.3.2
7-bit Transmission
When the R/W bit of the incoming address byte is set

and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register, and an ACK pulse is
sent by the slave on the ninth bit.
A master device can transmit a read request to a

slave, and then clock data out of the slave. The list
below outlines what software for a slave will need to
do to accomplish a standard transmission.
Figure 22-18 can be used as a reference to this list.
Following the ACK, slave hardware clears the CKP bit

and the SCL pin is held low (see Section 22.5.6
Clock Stretching for more detail). By stretching the
clock, the master will be unable to assert another clock
pulse until the slave is done preparing the transmit
data.
1.
The transmit data must be loaded into the SSPBUF

register which also loads the SSPSR register. Then the
SCL pin should be released by setting the CKP bit of
the SSPCON1 register. The eight data bits are shifted
out on the falling edge of the SCL input. This ensures
that the SDA signal is valid during the SCL high time.
The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCL input pulse. This ACK
value is copied to the ACKSTAT bit of the SSPCON2
register. If ACKSTAT is set (not ACK), then the data
transfer is complete. In this case, when the not ACK is
latched by the slave, the slave goes idle and waits for
another occurrence of the Start bit. If the SDA line was
low (ACK), the next transmit data must be loaded into
the SSPBUF register. Again, the SCL pin must be
released by setting bit CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared by software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
22.5.3.1
Master sends a Start condition on SDA and

SCL.
2. S bit of SSPSTAT is set; SSPIF is set if interrupt
3. Matching address with R/W bit set is received by
the Slave setting SSPIF bit.
4. Slave hardware generates an ACK and sets
SSPIF.
5. SSPIF bit is cleared by user.
6. Software reads the received address from
SSPBUF, clearing BF.
7. R/W is set so CKP was automatically cleared
after the ACK.
8. The slave software loads the transmit data into
SSPBUF.
9. CKP bit is set releasing SCL, allowing the master to clock the data out of the slave.
10. SSPIF is set after the ACK response from the
master is loaded into the ACKSTAT register.
11. SSPIF bit is cleared.
12. The slave software checks the ACKSTAT bit to
see if the master wants to clock out more data.
Note 1: If the master ACKs the clock will be
stretched.
2: ACKSTAT is the only bit updated on the
rising edge of SCL (9th) rather than the
falling.
Slave Mode Bus Collision
A slave receives a read request and begins shifting

data out on the SDA line. If a bus collision is detected
and the SBCDE bit of the SSPCON3 register is set, the
BCLIF bit of the PIR register is set. Once a bus collision
is detected, the slave goes idle and waits to be
addressed again. User software can use the BCLIF bit
to handle a slave bus collision.
13. Steps 9-13 are repeated for each transmitted

byte.
14. If the master sends a not ACK; the clock is not
held, but SSPIF is still set.
15. The master sends a Restart condition or a Stop.
16. The slave is no longer addressed.
Preliminary
DS41639A-page 225
DS41639A-page 226
Preliminary
D/A
R/W
ACKSTAT
CKP
BF
SSPIF
Received address
is read from SSPBUF
Indicates an address
has been received
R/W is copied from the

matching address byte
When R/W is set

SCL is always
held low after 9th SCL
falling edge
Automatic
Set by software
Data to transmit is
loaded into SSPBUF
Cleared by software
D7 D6 D5 D4 D3 D2 D1 D0 ACK
Transmitting Data
CKP is not
held for not
ACK
Masters not ACK

is copied to
ACKSTAT
BF is automatically
cleared after 8th falling
edge of SCL
D7 D6 D5 D4 D3 D2 D1 D0
Transmitting Data
ACK
FIGURE 22-18:
SCL
SDA
R/W = 1 Automatic
A7 A6 A5 A4 A3 A2 A1
ACK
Receiving Address
Master sends
Stop condition
PIC16(L)F1454/5/9
I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0)
PIC16(L)F1454/5/9
22.5.3.3
7-bit Transmission with Address

Hold Enabled
Setting the AHEN bit of the SSPCON3 register

enables additional clock stretching and interrupt generation after the 8th falling edge of a received matching address. Once a matching address has been
clocked in, CKP is cleared and the SSPIF interrupt is
set.
Figure 22-19 displays a standard waveform of a 7-bit
Address Slave Transmission with AHEN enabled.
1.
2.
Bus starts Idle.

Master sends Start condition; the S bit of
SSPSTAT is set; SSPIF is set if interrupt on Start
detect is enabled.
3. Master sends matching address with R/W bit
set. After the 8th falling edge of the SCL line the
CKP bit is cleared and SSPIF interrupt is generated.
4. Slave software clears SSPIF.
5. Slave software reads ACKTIM bit of SSPCON3
register, and R/W and D/A of the SSPSTAT register to determine the source of the interrupt.
6. Slave reads the address value from the
SSPBUF register clearing the BF bit.
7. Slave software decides from this information if it
wishes to ACK or not ACK and sets ACKDT bit
of the SSPCON2 register accordingly.
8. Slave sets the CKP bit releasing SCL.
9. Master clocks in the ACK value from the slave.
10. Slave hardware automatically clears the CKP bit
and sets SSPIF after the ACK if the R/W bit is
set.
11. Slave software clears SSPIF.
12. Slave loads value to transmit to the master into
SSPBUF setting the BF bit.
Note: SSPBUF cannot be loaded until after the
ACK.
13. Slave sets CKP bit releasing the clock.

14. Master clocks out the data from the slave and
sends an ACK value on the 9th SCL pulse.
15. Slave hardware copies the ACK value into the
ACKSTAT bit of the SSPCON2 register.
16. Steps 10-15 are repeated for each byte transmitted to the master from the slave.
17. If the master sends a not ACK the slave
releases the bus allowing the master to send a
Stop and end the communication.
Note: Master must send a not ACK on the last byte
to ensure that the slave releases the SCL
line to receive a Stop.
Preliminary
DS41639A-page 227
DS41639A-page 228
Preliminary
D/A
R/W
ACKTIM
CKP
ACKSTAT
ACKDT
BF
SSPIF
Receiving Address
Slave clears
ACKDT to ACK
address
ACKTIM is set on 8th falling

edge of SCL
ACK
When R/W = 1;
CKP is always
cleared after ACK
R/W = 1
Received address
is read from SSPBUF
When AHEN = 1;
CKP is cleared by hardware
after receiving matching
address.
A7 A6 A5 A4 A3 A2 A1
3
Cleared by software
Set by software,
releases SCL
Data to transmit is
loaded into SSPBUF
Transmitting Data
Automatic
ACKTIM is cleared
on 9th rising edge of SCL
Automatic
Transmitting Data
after not ACK
CKP not cleared
Masters ACK
response is copied
to SSPSTAT
BF is automatically
cleared after 8th falling
edge of SCL
D7 D6 D5 D4 D3 D2 D1 D0
9
ACK
Master sends
Stop condition
FIGURE 22-19:
SCL
SDA
Master releases SDA

to slave for ACK sequence
PIC16(L)F1454/5/9
I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1)
PIC16(L)F1454/5/9
22.5.4
SLAVE MODE 10-BIT ADDRESS

RECEPTION
22.5.5
This section describes a standard sequence of events

for the MSSP module configured as an I2C slave in
10-bit Addressing mode.
Figure 22-20 is used as a visual reference for this
description.
This is a step by step process of what must be done by
slave software to accomplish I2C communication.
1.
2.
3.
4.
5.
6.
7.
8.
Bus starts Idle.

Master sends Start condition; S bit of SSPSTAT
is set; SSPIF is set if interrupt on Start detect is
enabled.
Master sends matching high address with R/W
bit clear; UA bit of the SSPSTAT register is set.
Slave sends ACK and SSPIF is set.
Software clears the SSPIF bit.
Software reads received address from SSPBUF
Slave loads low address into SSPADD,
releasing SCL.
Master sends matching low address byte to the
slave; UA bit is set.
10-BIT ADDRESSING WITH ADDRESS OR

DATA HOLD
Reception using 10-bit addressing with AHEN or

DHEN set is the same as with 7-bit modes. The only
difference is the need to update the SSPADD register
using the UA bit. All functionality, specifically when the
CKP bit is cleared and SCL line is held low are the
same. Figure 22-21 can be used as a reference of a
slave in 10-bit addressing with AHEN set.
Figure 22-22 shows a standard waveform for a slave
transmitter in 10-bit Addressing mode.
Note: Updates to the SSPADD register are not

allowed until after the ACK sequence.
9.
Slave sends ACK and SSPIF is set.

Note: If the low address does not match, SSPIF
and UA are still set so that the slave software can set SSPADD back to the high
address. BF is not set because there is no
match. CKP is unaffected.

11. Slave reads the received matching address
from SSPBUF clearing BF.
12. Slave loads high address into SSPADD.
13. Master clocks a data byte to the slave and
clocks out the slaves ACK on the 9th SCL pulse;
SSPIF is set.
14. If SEN bit of SSPCON2 is set, CKP is cleared by
hardware and the clock is stretched.
16. Slave reads the received byte from SSPBUF
clearing BF.
17. If SEN is set the slave sets CKP to release the
SCL.
18. Steps 13-17 repeat for each received byte.
19. Master sends Stop to end the transmission.
Preliminary
DS41639A-page 229
DS41639A-page 230
Preliminary
CKP
UA
BF
SSPIF
1
5
0 A9 A8
Set by hardware
on 9th falling edge
When UA = 1;
SCL is held low
If address matches
SSPADD it is loaded into
SSPBUF
Receive First Address Byte
ACK
Software updates SSPADD

and releases SCL
A7 A6 A5 A4 A3 A2 A1 A0 ACK
Receive Second Address Byte
9
1
Data is read
from SSPBUF
SCL is held low

while CKP = 0
Receive Data
Set by software,
When SEN = 1;
releasing SCL
CKP is cleared after
9th falling edge of received byte
Receive address is
read from SSPBUF
Cleared by software
Receive Data
FIGURE 22-20:
SCL
SDA
Master sends
Stop condition
PIC16(L)F1454/5/9
Preliminary
ACKTIM
CKP
UA
ACKDT
BF
A9
A8
Set by hardware
on 9th falling edge
R/W = 0
ACKTIM is set by hardware

If when AHEN = 1;
of SCL of an address
byte, CKP is cleared
Slave software clears

ACKDT to ACK
the received byte
ACK
UA
2
A5
A4
A2
A1
Update to SSPADD is
not allowed until 9th
falling edge of SCL
SSPBUF can be
read anytime before
the next received byte
A3
Receive Second Address Byte

A6
Cleared by software
A7
A0
ACK
UA
D6
D5
D4
D2
Set CKP with software

releases SCL
D1
Update of SSPADD,
clears UA and releases
SCL
D3
Receive Data
Cleared by software
D7
Received data
is read from
SSPBUF
D6 D5
Receive Data
D0 ACK D7
FIGURE 22-21:
SSPIF
SCL
SDA
PIC16(L)F1454/5/9
DS41639A-page 231
DS41639A-page 232
Preliminary
D/A
R/W
ACKSTAT
CKP
UA
BF
SSPIF
Set by hardware
Indicates an address
has been received
UA indicates SSPADD
must be updated
SSPBUF loaded
with received address
SCL
Receiving Address R/W = 0

1 1 1 1 0 A9 A8
ACK
1
3
7 8
After SSPADD is
updated, UA is cleared
and SCL is released
Cleared by software
A7 A6 A5 A4 A3 A2 A1 A0 ACK
Receiving Second Address Byte
1
4
7 8
Set by hardware
2 3
R/W is copied from the

matching address byte
When R/W = 1;
CKP is cleared on
9th falling edge of SCL
High address is loaded

back into SSPADD
Received address is
read from SSPBUF
Sr
1 1 1 1 0 A9 A8
ACK
Masters not ACK

is copied
Set by software
releases SCL
Data to transmit is
loaded into SSPBUF
D7 D6 D5 D4 D3 D2 D1 D0
Transmitting Data Byte
Master sends
Stop condition
ACK = 1
Master sends
not ACK
FIGURE 22-22:
SDA
Master sends
Restart event
PIC16(L)F1454/5/9
I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0)
PIC16(L)F1454/5/9
22.5.6
22.5.6.2
CLOCK STRETCHING
Clock stretching occurs when a device on the bus

holds the SCL line low effectively pausing communication. The slave may stretch the clock to allow more
time to handle data or prepare a response for the master device. A master device is not concerned with
stretching as anytime it is active on the bus and not
transferring data it is stretching. Any stretching done
by a slave is invisible to the master software and handled by the hardware that generates SCL.
The CKP bit of the SSPCON1 register is used to control stretching in software. Any time the CKP bit is
cleared, the module will wait for the SCL line to go low
and then hold it. Setting CKP will release SCL and
allow more communication.
22.5.6.1
Normal Clock Stretching
Following an ACK if the R/W bit of SSPSTAT is set, a

read request, the slave hardware will clear CKP. This
allows the slave time to update SSPBUF with data to
transfer to the master. If the SEN bit of SSPCON2 is
set, the slave hardware will always stretch the clock
after the ACK sequence. Once the slave is ready; CKP
is set by software and communication resumes.
Note 1: The BF bit has no effect on if the clock will
be stretched or not. This is different than
previous versions of the module that
would not stretch the clock, clear CKP, if
SSPBUF was read before the 9th falling
edge of SCL.
2: Previous versions of the module did not
stretch the clock for a transmission if SSPBUF was loaded before the 9th falling
edge of SCL. It is now always cleared for
read requests.
FIGURE 22-23:
10-bit Addressing Mode
In 10-bit Addressing mode, when the UA bit is set the

clock is always stretched. This is the only time, the
SCL is stretched without CKP being cleared. SCL is
released immediately after a write to SSPADD.
Note: Previous versions of the module did not
stretch the clock if the second address byte
did not match.
22.5.6.3
Byte NACKing
When AHEN bit of SSPCON3 is set; CKP is cleared by

hardware after the 8th falling edge of SCL for a
received matching address byte. When DHEN bit of
SSPCON3 is set; CKP is cleared after the 8th falling
edge of SCL for received data.
Stretching after the 8th falling edge of SCL allows the
slave to look at the received address or data and
decide if it wants to ACK the received data.
22.5.7
CLOCK SYNCHRONIZATION AND

THE CKP BIT
Any time the CKP bit is cleared, the module will wait
for the SCL line to go low and then hold it. However,
clearing the CKP bit will not assert the SCL output low
until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an
external I2C master device has already asserted the
SCL line. The SCL output will remain low until the CKP
bit is set and all other devices on the I2C bus have
released SCL. This ensures that a write to the CKP bit
will not violate the minimum high time requirement for
SCL (see Figure 22-23).
CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
DX 1
DX
SCL
CKP
Master device
asserts clock
Master device
releases clock
WR
SSPCON1
Preliminary
DS41639A-page 233
PIC16(L)F1454/5/9
22.5.8
In 10-bit Address mode, the UA bit will not be set on

the reception of the general call address. The slave
will prepare to receive the second byte as data, just as
it would in 7-bit mode.
GENERAL CALL ADDRESS SUPPORT
The addressing procedure for the I2C bus is such that

the first byte after the Start condition usually determines which device will be the slave addressed by the
master device. The exception is the general call
address which can address all devices. When this
address is used, all devices should, in theory, respond
with an acknowledge.
If the AHEN bit of the SSPCON3 register is set, just as

with any other address reception, the slave hardware
will stretch the clock after the 8th falling edge of SCL.
The slave must then set its ACKDT value and release
the clock with communication progressing as it would
normally.
The general call address is a reserved address in the

I2C protocol, defined as address 0x00. When the
GCEN bit of the SSPCON2 register is set, the slave
module will automatically ACK the reception of this
address regardless of the value stored in SSPADD.
After the slave clocks in an address of all zeros with
the R/W bit clear, an interrupt is generated and slave
software can read SSPBUF and respond.
Figure 22-24 shows a general call reception
sequence.
FIGURE 22-24:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE

Address is compared to General Call Address
after ACK, set interrupt
R/W = 0
ACK D7
General Call Address
SDA
SCL
S
Receiving Data
ACK
D6
D5
D4
D3
D2
D1
D0
SSPIF
BF (SSPSTAT<0>)
Cleared by software
SSPBUF is read
GCEN (SSPCON2<7>)
22.5.9
SSP MASK REGISTER
An SSP Mask (SSPMSK) register (Register 22-5) is

available in I2C Slave mode as a mask for the value
held in the SSPSR register during an address
comparison operation. A zero (0) bit in the SSPMSK
register has the effect of making the corresponding bit
of the received address a dont care.
This register is reset to all 1s upon any Reset
condition and, therefore, has no effect on standard
SSP operation until written with a mask value.
The SSP Mask register is active during:
7-bit Address mode: address compare of A<7:1>.
10-bit Address mode: address compare of A<7:0>
only. The SSP mask has no effect during the
reception of the first (high) byte of the address.
DS41639A-page 234
Preliminary
PIC16(L)F1454/5/9
22.6
I2C MASTER MODE
22.6.1
I2C MASTER MODE OPERATION
Master mode is enabled by setting and clearing the

appropriate SSPM bits in the SSPCON1 register and
by setting the SSPEN bit. In Master mode, the SDA and
SCK pins must be configured as inputs. The MSSP
peripheral hardware will override the output driver TRIS
controls when necessary to drive the pins low.
The master device generates all of the serial clock

pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I2C bus will
not be released.
Master mode of operation is supported by interrupt

generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from
a Reset or when the MSSP module is disabled. Control
of the I 2C bus may be taken when the P bit is set, or the
bus is Idle.
In Master Transmitter mode, serial data is output

through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic 0. Serial data is
transmitted eight bits at a time. After each byte is transmitted, an Acknowledge bit is received. Start and Stop
conditions are output to indicate the beginning and the
end of a serial transfer.
In Firmware Controlled Master mode, user code

conducts all I 2C bus operations based on Start and
Stop bit condition detection. Start and Stop condition
detection is the only active circuitry in this mode. All
other communication is done by the user software
directly manipulating the SDA and SCL lines.
The following events will cause the SSP Interrupt Flag
bit, SSPIF, to be set (SSP interrupt, if enabled):
Start condition detected

Stop condition detected
Data transfer byte transmitted/received
Acknowledge transmitted/received
Repeated Start generated
Note 1: The MSSP module, when configured in
I2C Master mode, does not allow queueing of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPBUF register to
initiate transmission before the Start condition is complete. In this case, the SSPBUF will not be written to and the WCOL
bit will be set, indicating that a write to the
SSPBUF did not occur
In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic 1. Thus, the first byte transmitted is a 7-bit slave
address followed by a 1 to indicate the receive bit.
Serial data is received via SDA, while SCL outputs the
serial clock. Serial data is received eight bits at a time.
After each byte is received, an Acknowledge bit is
transmitted. Start and Stop conditions indicate the
beginning and end of transmission.
A Baud Rate Generator is used to set the clock
frequency output on SCL. See Section 22.7 Baud
Rate Generator for more detail.
2: When in Master mode, Start/Stop detection is masked and an interrupt is generated when the SEN/PEN bit is cleared and
the generation is complete.
Preliminary
DS41639A-page 235
PIC16(L)F1454/5/9
22.6.2
CLOCK ARBITRATION
Clock arbitration occurs when the master, during any

receive, transmit or Repeated Start/Stop condition,
releases the SCL pin (SCL allowed to float high). When
the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL
pin is actually sampled high. When the SCL pin is sampled high, the Baud Rate Generator is reloaded with
the contents of SSPADD<7:0> and begins counting.
This ensures that the SCL high time will always be at
least one BRG rollover count in the event that the clock
is held low by an external device (Figure 22-25).
FIGURE 22-25:
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
DX 1
DX
SCL deasserted but slave holds
SCL low (clock arbitration)
SCL allowed to transition high
SCL
BRG decrements on
Q2 and Q4 cycles
BRG
Value
03h
02h
01h
00h (hold off)
03h
02h
SCL is sampled high, reload takes

place and BRG starts its count
BRG
Reload
22.6.3
WCOL STATUS FLAG
If the user writes the SSPBUF when a Start, Restart,

Stop, Receive or Transmit sequence is in progress, the
WCOL is set and the contents of the buffer are
unchanged (the write does not occur). Any time the
WCOL bit is set it indicates that an action on SSPBUF
was attempted while the module was not idle.
Note:
Because queueing of events is not

allowed, writing to the lower five bits of
SSPCON2 is disabled until the Start
condition is complete.
DS41639A-page 236
Preliminary
PIC16(L)F1454/5/9
22.6.4
I2C MASTER MODE START
ister will be automatically cleared by hardware; the

Baud Rate Generator is suspended, leaving the SDA
line held low and the Start condition is complete.
CONDITION TIMING
To initiate a Start condition (Figure 22-26), the user

sets the Start Enable bit, SEN bit of the SSPCON2
register. If the SDA and SCL pins are sampled high,
the Baud Rate Generator is reloaded with the contents
of SSPADD<7:0> and starts its count. If SCL and SDA
are both sampled high when the Baud Rate Generator
times out (TBRG), the SDA pin is driven low. The action
of the SDA being driven low while SCL is high is the
Start condition and causes the S bit of the SSPSTAT1
register to be set. Following this, the Baud Rate Generator is reloaded with the contents of SSPADD<7:0>
and resumes its count. When the Baud Rate Generator times out (TBRG), the SEN bit of the SSPCON2 reg-
FIGURE 22-26:
Note 1: If at the beginning of the Start condition,

the SDA and SCL pins are already sampled low, or if during the Start condition,
the SCL line is sampled low before the
SDA line is driven low, a bus collision
occurs, the Bus Collision Interrupt Flag,
BCLIF, is set, the Start condition is
aborted and the I2C module is reset into
its Idle state.
2: The Philips I2C Specification states that
a bus collision cannot occur on a Start.
FIRST START BIT TIMING

Set S bit (SSPSTAT<3>)
Write to SEN bit occurs here
At completion of Start bit,

hardware clears SEN bit
and sets SSPIF bit
SDA = 1,
SCL = 1
TBRG
TBRG
Write to SSPBUF occurs here
SDA
1st bit
2nd bit
TBRG
SCL
S
Preliminary
TBRG
DS41639A-page 237
PIC16(L)F1454/5/9
22.6.5
I2C MASTER MODE REPEATED
SSPCON2 register will be automatically cleared and

the Baud Rate Generator will not be reloaded, leaving
the SDA pin held low. As soon as a Start condition is
detected on the SDA and SCL pins, the S bit of the
SSPSTAT register will be set. The SSPIF bit will not be
set until the Baud Rate Generator has timed out.
START CONDITION TIMING
A Repeated Start condition (Figure 22-27) occurs when

the RSEN bit of the SSPCON2 register is programmed
high and the Master state machine is no longer active.
When the RSEN bit is set, the SCL pin is asserted low.
When the SCL pin is sampled low, the Baud Rate Generator is loaded and begins counting. The SDA pin is
released (brought high) for one Baud Rate Generator
count (TBRG). When the Baud Rate Generator times
out, if SDA is sampled high, the SCL pin will be deasserted (brought high). When SCL is sampled high, the
Baud Rate Generator is reloaded and begins counting.
SDA and SCL must be sampled high for one TBRG.
This action is then followed by assertion of the SDA pin
(SDA = 0) for one TBRG while SCL is high. SCL is
asserted low. Following this, the RSEN bit of the
FIGURE 22-27:
Note 1: If RSEN is programmed while any other

event is in progress, it will not take effect.
2: A bus collision during the Repeated Start
condition occurs if:
SDA is sampled low when SCL

goes from low-to-high.
SCL goes low before SDA is
asserted low. This may indicate
that another master is attempting to
transmit a data 1.
REPEAT START CONDITION WAVEFORM

S bit set by hardware
Write to SSPCON2
occurs here
SDA = 1,
SCL (no change)
At completion of Start bit,

hardware clears RSEN bit
and sets SSPIF
SDA = 1,
SCL = 1
TBRG
TBRG
TBRG
1st bit
SDA
Write to SSPBUF occurs here

TBRG
SCL
Sr
TBRG
Repeated Start
DS41639A-page 238
Preliminary
PIC16(L)F1454/5/9
22.6.6
I2C MASTER MODE TRANSMISSION
22.6.6.3
Transmission of a data byte, a 7-bit address or the

other half of a 10-bit address is accomplished by simply
writing a value to the SSPBUF register. This action will
set the Buffer Full flag bit, BF and allow the Baud Rate
Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out
onto the SDA pin after the falling edge of SCL is
asserted. SCL is held low for one Baud Rate Generator
rollover count (TBRG). Data should be valid before SCL
is released high. When the SCL pin is released high, it
is held that way for TBRG. The data on the SDA pin
must remain stable for that duration and some hold
time after the next falling edge of SCL. After the eighth
bit is shifted out (the falling edge of the eighth clock),
the BF flag is cleared and the master releases SDA.
This allows the slave device being addressed to
respond with an ACK bit during the ninth bit time if an
address match occurred, or if data was received properly. The status of ACK is written into the ACKSTAT bit
on the rising edge of the ninth clock. If the master
receives an Acknowledge, the Acknowledge Status bit,
ACKSTAT, is cleared. If not, the bit is set. After the ninth
clock, the SSPIF bit is set and the master clock (Baud
Rate Generator) is suspended until the next data byte
is loaded into the SSPBUF, leaving SCL low and SDA
unchanged (Figure 22-28).
After the write to the SSPBUF, each bit of the address
will be shifted out on the falling edge of SCL until all
seven address bits and the R/W bit are completed. On
the falling edge of the eighth clock, the master will
release the SDA pin, allowing the slave to respond with
an Acknowledge. On the falling edge of the ninth clock,
the master will sample the SDA pin to see if the address
was recognized by a slave. The status of the ACK bit is
loaded into the ACKSTAT Status bit of the SSPCON2
register. Following the falling edge of the ninth clock
transmission of the address, the SSPIF is set, the BF
flag is cleared and the Baud Rate Generator is turned
off until another write to the SSPBUF takes place, holding SCL low and allowing SDA to float.
22.6.6.1
ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit of the SSPCON2

register is cleared when the slave has sent an Acknowledge (ACK = 0) and is set when the slave does not
Acknowledge (ACK = 1). A slave sends an Acknowledge when it has recognized its address (including a
general call), or when the slave has properly received
its data.
22.6.6.4
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
BF Status Flag
Typical transmit sequence:
The user generates a Start condition by setting

the SEN bit of the SSPCON2 register.
SSPIF is set by hardware on completion of the
Start.
SSPIF is cleared by software.
The MSSP module will wait the required start
time before any other operation takes place.
The user loads the SSPBUF with the slave
address to transmit.
Address is shifted out the SDA pin until all eight
bits are transmitted. Transmission begins as
soon as SSPBUF is written to.
The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
The user loads the SSPBUF with eight bits of
data.
Data is shifted out the SDA pin until all eight bits
are transmitted.
Steps 8-11 are repeated for all transmitted data
bytes.
The user generates a Stop or Restart condition
by setting the PEN or RSEN bits of the
SSPCON2 register. Interrupt is generated once
the Stop/Restart condition is complete.
In Transmit mode, the BF bit of the SSPSTAT register

is set when the CPU writes to SSPBUF and is cleared
when all eight bits are shifted out.
22.6.6.2
WCOL Status Flag
If the user writes the SSPBUF when a transmit is

already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the buffer are unchanged (the write does not occur).
WCOL must be cleared by software before the next
transmission.
Preliminary
DS41639A-page 239
DS41639A-page 240
S
Preliminary
R/W
PEN
SEN
BF (SSPSTAT<0>)
SSPIF
SCL
SDA
A6
A5
A4
A3
A2
A1
Cleared by software
After Start condition, SEN cleared by hardware
SSPBUF written
D7
1
SCL held low
while CPU
responds to SSPIF
ACK = 0
R/W = 0
SSPBUF written with 7-bit address and R/W

start transmit
A7
Transmit Address to Slave
D5
D4
D3
D2
D1
D0
SSPBUF is written by software
Cleared by software service routine

from SSP interrupt
D6
Transmitting Data or Second Half

of 10-bit Address
From slave, clear ACKSTAT bit SSPCON2<6>
Cleared by software
ACK
ACKSTAT in
SSPCON2 = 1
FIGURE 22-28:
SEN = 0
Write SSPCON2<0> SEN = 1

Start condition begins
PIC16(L)F1454/5/9
I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
PIC16(L)F1454/5/9
22.6.7
I2C MASTER MODE RECEPTION
22.6.7.4
Master mode reception (Figure 22-29) is enabled by

programming the Receive Enable bit, RCEN bit of the
SSPCON2 register.
Note:
The MSSP module must be in an Idle

state before the RCEN bit is set or the
RCEN bit will be disregarded.
The Baud Rate Generator begins counting and on each

rollover, the state of the SCL pin changes
(high-to-low/low-to-high) and data is shifted into the
SSPSR. After the falling edge of the eighth clock, the
receive enable flag is automatically cleared, the contents of the SSPSR are loaded into the SSPBUF, the
BF flag bit is set, the SSPIF flag bit is set and the Baud
Rate Generator is suspended from counting, holding
SCL low. The MSSP is now in Idle state awaiting the
next command. When the buffer is read by the CPU,
the BF flag bit is automatically cleared. The user can
then send an Acknowledge bit at the end of reception
by setting the Acknowledge Sequence Enable, ACKEN
bit of the SSPCON2 register.
22.6.7.1
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
BF Status Flag
In receive operation, the BF bit is set when an address

or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.
11.
22.6.7.2
12.
SSPOV Status Flag
In receive operation, the SSPOV bit is set when eight

bits are received into the SSPSR and the BF flag bit is
already set from a previous reception.
13.
14.
22.6.7.3
15.
WCOL Status Flag
If the user writes the SSPBUF when a receive is

already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write does not occur).
Preliminary
Typical Receive Sequence:
The user generates a Start condition by setting

the SEN bit of the SSPCON2 register.
SSPIF is set by hardware on completion of the
Start.
SSPIF is cleared by software.
User writes SSPBUF with the slave address to
transmit and the R/W bit set.
Address is shifted out the SDA pin until all eight
bits are transmitted. Transmission begins as
soon as SSPBUF is written to.
The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
User sets the RCEN bit of the SSPCON2 register
and the master clocks in a byte from the slave.
After the 8th falling edge of SCL, SSPIF and BF
are set.
Master clears SSPIF and reads the received
byte from SSPUF, clears BF.
Master sets ACK value sent to slave in ACKDT
bit of the SSPCON2 register and initiates the
ACK by setting the ACKEN bit.
Masters ACK is clocked out to the slave and
SSPIF is set.
User clears SSPIF.
Steps 8-13 are repeated for each received byte
from the slave.
Master sends a not ACK or Stop to end
communication.
DS41639A-page 241
DS41639A-page 242
Preliminary
RCEN
ACKEN
SSPOV
BF
(SSPSTAT<0>)
SDA = 0, SCL = 1
while CPU
responds to SSPIF
SSPIF
A7
4
5
Cleared by software
A6 A5 A4 A3 A2
Transmit Address to Slave
7
8
ACK
D0
ACK
RCEN cleared
automatically
5
6
Cleared by software
Set SSPIF interrupt

at end of Acknowledge
sequence
Data shifted in on falling edge of CLK
ACK from Master

SDA = ACKDT = 0
Cleared in
software
Set SSPIF at end

of receive
ACK is not sent
ACK
P
Set SSPIF interrupt
at end of Acknowledge sequence
Bus master
terminates
transfer
Set P bit
(SSPSTAT<4>)
and SSPIF
PEN bit = 1
written here
SSPOV is set because

SSPBUF is still full
D0
RCEN cleared
automatically
D7 D6 D5 D4 D3 D2 D1
RCEN cleared
automatically
Set ACKEN, start Acknowledge sequence

SDA = ACKDT = 1
Receiving Data from Slave
RCEN = 1, start
next receive
ACK from Master

SDA = ACKDT = 0
Last bit is shifted into SSPSR and

contents are unloaded into SSPBUF
Cleared by software
Set SSPIF interrupt

at end of receive
Cleared by software
D7 D6 D5 D4 D3 D2 D1
Receiving Data from Slave
RCEN cleared
automatically
Master configured as a receiver

by programming SSPCON2<3> (RCEN = 1)
A1 R/W
ACK from Slave
Master configured as a receiver

by programming SSPCON2<3> (RCEN = 1)
FIGURE 22-29:
SCL
SDA
SEN = 0
Write to SSPBUF occurs here,
start XMIT
Write to SSPCON2<0> (SEN = 1),

begin Start condition
Write to SSPCON2<4>
to start Acknowledge sequence
SDA = ACKDT (SSPCON2<5>) = 0
PIC16(L)F1454/5/9
I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
PIC16(L)F1454/5/9
22.6.8
ACKNOWLEDGE SEQUENCE
TIMING
22.6.9
A Stop bit is asserted on the SDA pin at the end of a

receive/transmit by setting the Stop Sequence Enable
bit, PEN bit of the SSPCON2 register. At the end of a
receive/transmit, the SCL line is held low after the
falling edge of the ninth clock. When the PEN bit is set,
the master will assert the SDA line low. When the SDA
line is sampled low, the Baud Rate Generator is
reloaded and counts down to 0. When the Baud Rate
Generator times out, the SCL pin will be brought high
and one TBRG (Baud Rate Generator rollover count)
later, the SDA pin will be deasserted. When the SDA
pin is sampled high while SCL is high, the P bit of the
SSPSTAT register is set. A TBRG later, the PEN bit is
cleared and the SSPIF bit is set (Figure 22-31).
An Acknowledge sequence is enabled by setting the

Acknowledge Sequence Enable bit, ACKEN bit of the
SSPCON2 register. When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate
Generator then counts for one rollover period (TBRG)
and the SCL pin is deasserted (pulled high). When the
SCL pin is sampled high (clock arbitration), the Baud
Rate Generator counts for TBRG. The SCL pin is then
pulled low. Following this, the ACKEN bit is automatically
cleared, the Baud Rate Generator is turned off and the
MSSP module then goes into Idle mode (Figure 22-30).
22.6.8.1
22.6.9.1
WCOL Status Flag
If the user writes the SSPBUF when a Stop sequence

is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write does
not occur).
WCOL Status Flag
If the user writes the SSPBUF when an Acknowledge

sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write does
not occur).
FIGURE 22-30:
STOP CONDITION TIMING
ACKNOWLEDGE SEQUENCE WAVEFORM

Acknowledge sequence starts here,
write to SSPCON2
ACKEN = 1, ACKDT = 0
ACKEN automatically cleared

TBRG
TBRG
SDA
ACK
D0
SCL
SSPIF
SSPIF set at
the end of receive
Cleared in
software
SSPIF set at the end
of Acknowledge sequence
Cleared in
software
Note: TBRG = one Baud Rate Generator period.
FIGURE 22-31:
STOP CONDITION RECEIVE OR TRANSMIT MODE

SCL = 1 for TBRG, followed by SDA = 1 for TBRG
after SDA sampled high. P bit (SSPSTAT<4>) is set.
Write to SSPCON2,
set PEN
PEN bit (SSPCON2<2>) is cleared by

hardware and the SSPIF bit is set
Falling edge of
9th clock
TBRG
SCL
SDA
ACK
P
TBRG
TBRG
TBRG
SCL brought high after TBRG

SDA asserted low before rising edge of clock
to setup Stop condition
Note: TBRG = one Baud Rate Generator period.
Preliminary
DS41639A-page 243
PIC16(L)F1454/5/9
22.6.10
SLEEP OPERATION
22.6.13
While in Sleep mode, the I C slave module can receive

addresses or data and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if the MSSP interrupt is enabled).
22.6.11
EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the

current transfer.
22.6.12
MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the

detection of the Start and Stop conditions allows the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the
MSSP module is disabled. Control of the I 2C bus may
be taken when the P bit of the SSPSTAT register is set,
or the bus is Idle, with both the S and P bits clear. When
the bus is busy, enabling the SSP interrupt will generate the interrupt when the Stop condition occurs.
In multi-master operation, the SDA line must be
monitored for arbitration to see if the signal level is the
expected output level. This check is performed by
hardware with the result placed in the BCLIF bit.
The states where arbitration can be lost are:
Address Transfer
Data Transfer
A Start Condition
A Repeated Start Condition
An Acknowledge Condition
MULTI -MASTER COMMUNICATION,

BUS COLLISION AND BUS
ARBITRATION
Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a 1 on SDA, by letting SDA float high and
another master asserts a 0. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a 1 and the data sampled on the SDA pin is 0,
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag, BCLIF and reset the
I2C port to its Idle state (Figure 22-32).
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted and the
SSPBUF can be written to. When the user services the
bus collision Interrupt Service Routine and if the I2C
bus is free, the user can resume communication by
asserting a Start condition.
If a Start, Repeated Start, Stop or Acknowledge condition was in progress when the bus collision occurred, the
condition is aborted, the SDA and SCL lines are deasserted and the respective control bits in the SSPCON2
register are cleared. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free,
the user can resume communication by asserting a Start
condition.
The master will continue to monitor the SDA and SCL
pins. If a Stop condition occurs, the SSPIF bit will be set.
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus
can be taken when the P bit is set in the SSPSTAT
register, or the bus is Idle and the S and P bits are
cleared.
FIGURE 22-32:
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE

Data changes
while SCL = 0
SDA line pulled low

by another source
SDA released
by master
Sample SDA. While SCL is high,

data does not match what is driven
by the master.
Bus collision has occurred.
SDA
SCL
Set bus collision

interrupt (BCLIF)
BCLIF
DS41639A-page 244
Preliminary
PIC16(L)F1454/5/9
22.6.13.1
Bus Collision During a Start

Condition
During a Start condition, a bus collision occurs if:

a)
b)
SDA or SCL are sampled low at the beginning of

the Start condition (Figure 22-33).
SCL is sampled low before SDA is asserted low
(Figure 22-34).
During a Start condition, both the SDA and the SCL

pins are monitored.
If the SDA pin is sampled low during this count, the

BRG is reset and the SDA line is asserted early
(Figure 22-35). If, however, a 1 is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The Baud Rate Generator is then reloaded and
counts down to zero; if the SCL pin is sampled as 0
during this time, a bus collision does not occur. At the
end of the BRG count, the SCL pin is asserted low.
Note:
If the SDA pin is already low, or the SCL pin is already

low, then all of the following occur:
the Start condition is aborted,
the BCLIF flag is set and
the MSSP module is reset to its Idle state
(Figure 22-33).
The Start condition begins with the SDA and SCL pins
deasserted. When the SDA pin is sampled high, the
Baud Rate Generator is loaded and counts down. If the
SCL pin is sampled low while SDA is high, a bus collision occurs because it is assumed that another master
is attempting to drive a data 1 during the Start
condition.
FIGURE 22-33:
The reason that bus collision is not a factor during a Start condition is that no two
bus masters can assert a Start condition
at the exact same time. Therefore, one
master will always assert SDA before the
other. This condition does not cause a bus
collision because the two masters must be
allowed to arbitrate the first address following the Start condition. If the address is
the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
BUS COLLISION DURING START CONDITION (SDA ONLY)

SDA goes low before the SEN bit is set.
Set BCLIF,
S bit and SSPIF set because
SDA = 0, SCL = 1.
SDA
SCL
Set SEN, enable Start
condition if SDA = 1, SCL = 1
SEN cleared automatically because of bus collision.

SSP module reset into Idle state.
SEN
BCLIF
SDA sampled low before

Start condition. Set BCLIF.
S bit and SSPIF set because
SDA = 0, SCL = 1.
SSPIF and BCLIF are
cleared by software
SSPIF
SSPIF and BCLIF are
cleared by software
Preliminary
DS41639A-page 245
PIC16(L)F1454/5/9
FIGURE 22-34:
BUS COLLISION DURING START CONDITION (SCL = 0)

SDA = 0, SCL = 1
TBRG
TBRG
SDA
sequence if SDA = 1, SCL = 1
SCL
SCL = 0 before SDA = 0,

bus collision occurs. Set BCLIF.
SEN
SCL = 0 before BRG time-out,
bus collision occurs. Set BCLIF.
BCLIF
Interrupt cleared
by software
S
SSPIF
FIGURE 22-35:
BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION

SDA = 0, SCL = 1
Set S
Less than TBRG
SDA
SCL
TBRG
SDA pulled low by other master.

Reset BRG and assert SDA.
S
SCL pulled low after BRG
time-out
SEN
BCLIF
Set SSPIF

sequence if SDA = 1, SCL = 1
SSPIF
SDA = 0, SCL = 1,
set SSPIF
DS41639A-page 246
Preliminary
Interrupts cleared
by software
PIC16(L)F1454/5/9
22.6.13.2
Bus Collision During a Repeated

Start Condition
If SDA is low, a bus collision has occurred (i.e., another

master is attempting to transmit a data 0, Figure 22-36).
If SDA is sampled high, the BRG is reloaded and begins
counting. If SDA goes from high-to-low before the BRG
times out, no bus collision occurs because no two
masters can assert SDA at exactly the same time.
During a Repeated Start condition, a bus collision

occurs if:
a)
b)
A low level is sampled on SDA when SCL goes

from low level to high level (Case 1).
SCL goes low before SDA is asserted low,
indicating that another master is attempting to
transmit a data 1 (Case 2).
If SCL goes from high-to-low before the BRG times out

and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data 1 during the Repeated Start condition,
see Figure 22-37.
When the user releases SDA and the pin is allowed to

float high, the BRG is loaded with SSPADD and counts
down to zero. The SCL pin is then deasserted and
when sampled high, the SDA pin is sampled.
FIGURE 22-36:
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is
complete.
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDA
SCL
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
RSEN
BCLIF
Cleared by software
S
SSPIF
FIGURE 22-37:
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)

TBRG
TBRG
SDA
SCL
BCLIF
SCL goes low before SDA,

set BCLIF. Release SDA and SCL.
Interrupt cleared
by software
RSEN
S
SSPIF
Preliminary
DS41639A-page 247
PIC16(L)F1454/5/9
22.6.13.3
Bus Collision During a Stop

Condition
The Stop condition begins with SDA asserted low.

When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with SSPADD and
counts down to zero. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data 0 (Figure 22-34). If the SCL pin is sampled
low before SDA is allowed to float high, a bus collision
occurs. This is another case of another master
attempting to drive a data 0 (Figure 22-34).
Bus collision occurs during a Stop condition if:

a)
b)
After the SDA pin has been deasserted and

allowed to float high, SDA is sampled low after
the BRG has timed out (Case 1).
After the SCL pin is deasserted, SCL is sampled
low before SDA goes high (Case 2).
FIGURE 22-38:
BUS COLLISION DURING A STOP CONDITION (CASE 1)

TBRG
TBRG
SDA sampled
low after TBRG,
set BCLIF
TBRG
SDA
SDA asserted low
SCL
PEN
BCLIF
P
SSPIF
FIGURE 22-39:
BUS COLLISION DURING A STOP CONDITION (CASE 2)

TBRG
TBRG
TBRG
SDA
SCL goes low before SDA goes high,
set BCLIF
Assert SDA
SCL
PEN
BCLIF
P
SSPIF
DS41639A-page 248
Preliminary
PIC16(L)F1454/5/9
TABLE 22-3:
Name
INTCON
SUMMARY OF REGISTERS ASSOCIATED WITH I2C OPERATION

Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values on
Page:
INTE
IOCIE
TMR0IF
INTF
IOCIF
96
Bit 7
Bit 6
Bit 5
Bit 4
GIE
PEIE
TMR0IE
(2)
PIE1
TMR1GIE
RCIE
TXIE
SSP1IE
TMR2IE
TMR1IE
97
PIE2
OSFIE
C2IE
C1IE
BCL1IE
USBIE
ACTIE
98
PIR1
TMR1GIF
ADIF(2)
RCIF
TXIF
SSP1IF
TMR2IF
TMR1IF
99
PIR2
OSFIF
C2IF
C1IF
BCL1IF
USBIF
ACTIF
100
TRISA5
TRISA4
(1)
(1)
(1)
132
TRISA
ADIE
SSP1ADD
SSP1BUF
SSP1CON1
ADD<7:0>
256
MSSP Receive Buffer/Transmit Register
207*
WCOL
SSPOV
SSPEN
CKP
SSP1CON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
254
SSP1CON3
ACKTIM
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
255
SSP1MSK
SSP1STAT
Legend:
*
Note 1:
2:
SSPM<3:0>
253
MSK<7:0>
SMP
CKE
D/A
256
S
R/W
UA
BF
251
= unimplemented location, read as 0. Shaded cells are not used by the MSSP module in I2C mode.
Preliminary
DS41639A-page 249
PIC16(L)F1454/5/9
22.7
BAUD RATE GENERATOR
The MSSP module has a Baud Rate Generator available for clock generation in both I2C and SPI Master
modes. The Baud Rate Generator (BRG) reload value
is placed in the SSPADD register (Register 22-6).
When a write occurs to SSPBUF, the Baud Rate Generator will automatically begin counting down.
Once the given operation is complete, the internal clock
will automatically stop counting and the clock pin will
remain in its last state.
clock line. The logic dictating when the reload signal is

asserted depends on the mode the MSSP is being
operated in.
Table 22-4 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
EQUATION 22-1:
FOSC
FCLOCK = ------------------------------------------------ SSPxADD + 1 4
An internal signal Reload in Figure 22-40 triggers the

value from SSPADD to be loaded into the BRG counter.
This occurs twice for each oscillation of the module
FIGURE 22-40:
BAUD RATE GENERATOR BLOCK DIAGRAM

SSPM<3:0>
SSPM<3:0>
Reload
SSPADD<7:0>
Reload
Control
SCL
SSPCLK
BRG Down Counter
FOSC/2
Note: Values of 0x00, 0x01 and 0x02 are not valid

for SSPADD when used as a Baud Rate
Generator for I2C. This is an implementation
limitation.
TABLE 22-4:
Note 1:
MSSP CLOCK RATE W/BRG
FOSC
FCY
BRG Value
FCLOCK
(2 Rollovers of BRG)
16 MHz
4 MHz
09h
400 kHz(1)
16 MHz
4 MHz
0Ch
308 kHz
16 MHz
4 MHz
27h
100 kHz
4 MHz
1 MHz
09h
100 kHz
The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
DS41639A-page 250
Preliminary
PIC16(L)F1454/5/9
22.8
Register Definitions: MSSP Control
REGISTER 22-1:
SSPSTAT: SSP STATUS REGISTER
R/W-0/0
R/W-0/0
R-0/0
R-0/0
R-0/0
R-0/0
R-0/0
R-0/0
SMP
CKE
D/A
R/W
UA
BF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
SMP: SPI Data Input Sample bit

SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
In I2 C Master or Slave mode:
1 = Slew rate control disabled for Standard-Speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for High-Speed mode (400 kHz)
bit 6
CKE: SPI Clock Edge Select bit (SPI mode only)

In SPI Master or Slave mode:
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state
In I2 C mode only:
1 = Enable input logic so that thresholds are compliant with SMbus specification
0 = Disable SMbus specific inputs
bit 5
bit 4
D/A: Data/Address bit (I2C mode only)

1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
P: Stop bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a Stop bit has been detected last (this bit is 0 on Reset)
0 = Stop bit was not detected last
bit 3
S: Start bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a Start bit has been detected last (this bit is 0 on Reset)
0 = Start bit was not detected last
bit 2
R/W: Read/Write bit information (I2C mode only)

This bit holds the R/W bit information following the last address match. This bit is only valid from the address match
to the next Start bit, Stop bit, or not ACK bit.
In I2 C Slave mode:
1 = Read
0 = Write
In I2 C Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress
OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode.
bit 1
UA: Update Address bit (10-bit I2C mode only)

1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
Preliminary
DS41639A-page 251
PIC16(L)F1454/5/9
REGISTER 22-1:
bit 0
SSPSTAT: SSP STATUS REGISTER (CONTINUED)
BF: Buffer Full Status bit

Receive (SPI and I2 C modes):
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I2 C mode only):
1 = Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full
0 = Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty
DS41639A-page 252
Preliminary
PIC16(L)F1454/5/9
REGISTER 22-2:
SSPCON1: SSP CONTROL REGISTER 1
R/C/HS-0/0
R/C/HS-0/0
R/W-0/0
R/W-0/0
WCOL
SSPOV
SSPEN
CKP
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
SSPM<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
HS = Bit is set by hardware
C = User cleared
bit 7
WCOL: Write Collision Detect bit

Master mode:
1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started
0 = No collision
Slave mode:
1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software)
0 = No collision
bit 6
SSPOV: Receive Overflow Indicator bit(1)

In SPI mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost.
Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPBUF, even if only transmitting data, to avoid
setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the
SSPBUF register (must be cleared in software).
0 = No overflow
2
In I C mode:
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a dont care in Transmit mode
(must be cleared in software).
0 = No overflow
bit 5
SSPEN: Synchronous Serial Port Enable bit

In both modes, when enabled, these pins must be properly configured as input or output
In SPI mode:
1 = Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins(2)
0 = Disables serial port and configures these pins as I/O port pins
In I2C mode:
1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins(3)
0 = Disables serial port and configures these pins as I/O port pins
bit 4
CKP: Clock Polarity Select bit

In SPI mode:
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I2C Slave mode:
SCL release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
In I2C Master mode:
Unused in this mode
bit 3-0
SSPM<3:0>: Synchronous Serial Port Mode Select bits

0000 = SPI Master mode, clock = FOSC/4
0011 = SPI Master mode, clock = TMR2 output/2
0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled
0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0110 = I2C Slave mode, 7-bit address
0111 = I2C Slave mode, 10-bit address
1000 = I2C Master mode, clock = FOSC / (4 * (SSPADD+1))(4)
1001 = Reserved
1010 = SPI Master mode, clock = FOSC/(4 * (SSPADD+1))(5)
1011 = I2C firmware controlled Master mode (Slave idle)
1100 = Reserved
1101 = Reserved
1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
Note
1:
2:
3:
4:
5:
In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register.
When enabled, these pins must be properly configured as input or output.
When enabled, the SDA and SCL pins must be configured as inputs.
SSPADD values of 0, 1 or 2 are not supported for I2C mode.
SSPADD value of 0 is not supported. Use SSPM = 0000 instead.
Preliminary
DS41639A-page 253
PIC16(L)F1454/5/9
REGISTER 22-3:
R/W-0/0
R-0/0
R/W-0/0
R/S/HS-0/0
R/S/HS-0/0
R/S/HS-0/0
R/S/HS-0/0
R/W/HS-0/0
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
HC = Cleared by hardware
S = User set
bit 7
GCEN: General Call Enable bit (in I2C Slave mode only)
1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPSR
0 = General call address disabled
bit 6
ACKSTAT: Acknowledge Status bit (in I2C mode only)

1 = Acknowledge was not received
0 = Acknowledge was received
bit 5
ACKDT: Acknowledge Data bit (in I2C mode only)

In Receive mode:
Value transmitted when the user initiates an Acknowledge sequence at the end of a receive
1 = Not Acknowledge
0 = Acknowledge
bit 4
ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only)
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence idle
bit 3
RCEN: Receive Enable bit (in I2C Master mode only)

1 = Enables Receive mode for I2C
0 = Receive idle
bit 2
PEN: Stop Condition Enable bit (in I2C Master mode only)
SCKMSSP Release Control:
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle
bit 1
RSEN: Repeated Start Condition Enable bit (in I2C Master mode only)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
bit 0
SEN: Start Condition Enable/Stretch Enable bit

In Master mode:
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
Note 1:
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be
set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).
DS41639A-page 254
Preliminary
PIC16(L)F1454/5/9
REGISTER 22-4:
R-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
ACKTIM
PCIE
SCIE
BOEN
SDAHT
SBCDE
AHEN
DHEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
ACKTIM: Acknowledge Time Status bit (I2C mode only)(3)

1 = Indicates the I2C bus is in an Acknowledge sequence, set on 8TH falling edge of SCL clock
0 = Not an Acknowledge sequence, cleared on 9TH rising edge of SCL clock
bit 6
PCIE: Stop Condition Interrupt Enable bit (I2C mode only)

1 = Enable interrupt on detection of Stop condition
0 = Stop detection interrupts are disabled(2)
bit 5
SCIE: Start Condition Interrupt Enable bit (I2C mode only)

1 = Enable interrupt on detection of Start or Restart conditions
0 = Start detection interrupts are disabled(2)
bit 4
BOEN: Buffer Overwrite Enable bit

In SPI Slave mode:(1)
1 = SSPBUF updates every time that a new data byte is shifted in ignoring the BF bit
0 = If new byte is received with BF bit of the SSPSTAT register already set, SSPOV bit of the
SSPCON1 register is set, and the buffer is not updated
In I2C Master mode and SPI Master mode:
In I2C Slave mode:
1 = SSPBUF is updated and ACK is generated for a received address/data byte, ignoring the state
of the SSPOV bit only if the BF bit = 0.
0 = SSPBUF is only updated when SSPOV is clear
bit 3
SDAHT: SDA Hold Time Selection bit (I2C mode only)

1 = Minimum of 300 ns hold time on SDA after the falling edge of SCL
0 = Minimum of 100 ns hold time on SDA after the falling edge of SCL
bit 2
SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)
If on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the
BCL1IF bit of the PIR2 register is set, and bus goes idle
1 = Enable slave bus collision interrupts
0 = Slave bus collision interrupts are disabled
bit 1
AHEN: Address Hold Enable bit (I2C Slave mode only)

1 = Following the 8th falling edge of SCL for a matching received address byte; CKP bit of the
SSPCON1 register will be cleared and the SCL will be held low.
0 = Address holding is disabled
bit 0
DHEN: Data Hold Enable bit (I2C Slave mode only)

1 = Following the 8th falling edge of SCL for a received data byte; slave hardware clears the CKP bit
of the SSPCON1 register and SCL is held low.
0 = Data holding is disabled
Note 1:
2:
3:
For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set
when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPBUF.
This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.
The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.
Preliminary
DS41639A-page 255
PIC16(L)F1454/5/9
REGISTER 22-5:
R/W-1/1
SSPMSK: SSP MASK REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
MSK<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-1
MSK<7:1>: Mask bits

1 = The received address bit n is compared to SSPADD<n> to detect I2C address match
0 = The received address bit n is not used to detect I2C address match
bit 0
MSK<0>: Mask bit for I2C Slave mode, 10-bit Address

I2C Slave mode, 10-bit address (SSPM<3:0> = 0111 or 1111):
1 = The received address bit 0 is compared to SSPADD<0> to detect I2C address match
0 = The received address bit 0 is not used to detect I2C address match
I2C Slave mode, 7-bit address, the bit is ignored
REGISTER 22-6:
R/W-0/0
SSPADD: MSSP ADDRESS AND BAUD RATE REGISTER (I2C MODE)
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
ADD<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
Master mode:
bit 7-0
ADD<7:0>: Baud Rate Clock Divider bits

SCL pin clock period = ((ADD<7:0> + 1) *4)/FOSC
10-Bit Slave mode Most Significant Address Byte:
bit 7-3
Not used: Unused for Most Significant Address Byte. Bit state of this register is a dont care. Bit pattern sent by master is fixed by I2C specification and must be equal to 11110. However, those bits are
compared by hardware and are not affected by the value in this register.
bit 2-1
ADD<2:1>: Two Most Significant bits of 10-bit address
bit 0
Not used: Unused in this mode. Bit state is a dont care.
10-Bit Slave mode Least Significant Address Byte:
bit 7-0
ADD<7:0>: Eight Least Significant bits of 10-bit address
7-Bit Slave mode:
bit 7-1
ADD<7:1>: 7-bit address
bit 0
Not used: Unused in this mode. Bit state is a dont care.
DS41639A-page 256
Preliminary
PIC16(L)F1454/5/9
23.0
ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
The EUSART module includes the following capabilities:
Full-duplex asynchronous transmit and receive

Two-character input buffer
One-character output buffer
Programmable 8-bit or 9-bit character length
Address detection in 9-bit mode
Input buffer overrun error detection
Received character framing error detection
Half-duplex synchronous master
Half-duplex synchronous slave
Programmable clock polarity in Synchronous
modes
Sleep operation
The Enhanced Universal Synchronous Asynchronous

Receiver Transmitter (EUSART) module is a serial I/O
communications peripheral. It contains all the clock
generators, shift registers and data buffers necessary
to perform an input or output serial data transfer
independent of device program execution. The
EUSART, also known as a Serial Communications
Interface (SCI), can be configured as a full-duplex
asynchronous system or half-duplex synchronous
system.
Full-Duplex
mode
is
useful
for
communications with peripheral systems, such as CRT
terminals and personal computers. Half-Duplex
Synchronous mode is intended for communications
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs or other microcontrollers.
These devices typically do not have internal clocks for
baud rate generation and require the external clock
signal provided by a master synchronous device.
FIGURE 23-1:
The EUSART module implements the following

additional features, making it ideally suited for use in
Local Interconnect Network (LIN) bus systems:
Automatic detection and calibration of the baud rate
Wake-up on Break reception
13-bit Break character transmit
Block diagrams of the EUSART transmitter and
receiver are shown in Figure 23-1 and Figure 23-2.
EUSART TRANSMIT BLOCK DIAGRAM

Data Bus
TXIE
Interrupt
TXIF
TXREG Register
8
MSb
TX/CK pin
LSb
(8)
Pin Buffer
and Control
TRMT
SPEN
Transmit Shift Register (TSR)
TXEN
Baud Rate Generator
FOSC
TX9
BRG16
+1
SPBRGH
SPBRGL
Multiplier
x4
x16 x64
SYNC
1 X 0 0
BRGH
X 1 1 0
BRG16
X 1 0 1
TX9D
Preliminary
DS41639A-page 257
PIC16(L)F1454/5/9
FIGURE 23-2:
EUSART RECEIVE BLOCK DIAGRAM

SPEN
CREN
RX/DT pin
Baud Rate Generator
Data
Recovery
FOSC
SPBRGH
SPBRGL
x4
x16 x64
SYNC
1 X 0 0
BRGH
X 1 1 0
BRG16
X 1 0 1
(8)
LSb
0 START
RX9
BRG16
Multiplier
Stop
RCIDL
RSR Register
MSb
Pin Buffer
and Control
+1
OERR
FERR
RX9D
RCREG Register
8
FIFO
Data Bus
RCIF
RCIE
Interrupt
The operation of the EUSART module is controlled

through three registers:
Transmit Status and Control (TXSTA)
Receive Status and Control (RCSTA)
Baud Rate Control (BAUDCON)
These registers are detailed in Register 23-1,
Register 23-2 and Register 23-3, respectively.
When the receiver or transmitter section is not enabled
then the corresponding RX or TX pin may be used for
general purpose input and output.
DS41639A-page 258
Preliminary
PIC16(L)F1454/5/9
23.1
EUSART Asynchronous Mode
23.1.1.2
The EUSART transmits and receives data using the

standard non-return-to-zero (NRZ) format. NRZ is
implemented with two levels: a VOH mark state which
represents a 1 data bit, and a VOL space state which
represents a 0 data bit. NRZ refers to the fact that
consecutively transmitted data bits of the same value
stay at the output level of that bit without returning to a
neutral level between each bit transmission. An NRZ
transmission port idles in the Mark state. Each character
transmission consists of one Start bit followed by eight
or nine data bits and is always terminated by one or
more Stop bits. The Start bit is always a space and the
Stop bits are always marks. The most common data
format is eight bits. Each transmitted bit persists for a
period of 1/(Baud Rate). An on-chip dedicated
8-bit/16-bit Baud Rate Generator is used to derive
standard baud rate frequencies from the system
oscillator. See Table 23-5 for examples of baud rate
configurations.
Transmitting Data
A transmission is initiated by writing a character to the

TXREG register. If this is the first character, or the
previous character has been completely flushed from
the TSR, the data in the TXREG is immediately
transferred to the TSR register. If the TSR still contains
all or part of a previous character, the new character
data is held in the TXREG until the Stop bit of the
previous character has been transmitted. The pending
character in the TXREG is then transferred to the TSR
in one TCY immediately following the Stop bit
transmission. The transmission of the Start bit, data bits
and Stop bit sequence commences immediately
following the transfer of the data to the TSR from the
TXREG.
23.1.1.3
Transmit Data Polarity
The EUSART transmits and receives the LSb first. The

EUSARTs transmitter and receiver are functionally
independent, but share the same data format and baud
rate. Parity is not supported by the hardware, but can
be implemented in software and stored as the ninth
data bit.
The polarity of the transmit data can be controlled with

the SCKP bit of the BAUDCON register. The default
state of this bit is 0 which selects high true transmit idle
and data bits. Setting the SCKP bit to 1 will invert the
transmit data resulting in low true Idle and data bits. The
SCKP bit controls transmit data polarity in
Asynchronous mode only. In Synchronous mode, the
SCKP bit has a different function. See Section 23.5.1.2
Clock Polarity.
23.1.1
23.1.1.4
EUSART ASYNCHRONOUS
TRANSMITTER
The EUSART transmitter block diagram is shown in

Figure 23-1. The heart of the transmitter is the serial
Transmit Shift Register (TSR), which is not directly
accessible by software. The TSR obtains its data from
the transmit buffer, which is the TXREG register.
23.1.1.1
Enabling the Transmitter
The EUSART transmitter is enabled for asynchronous

operations by configuring the following three control
bits:
TXEN = 1
SYNC = 0
SPEN = 1
All other EUSART control bits are assumed to be in
their default state.
Setting the TXEN bit of the TXSTA register enables the
transmitter circuitry of the EUSART. Clearing the SYNC
bit of the TXSTA register configures the EUSART for
asynchronous operation. Setting the SPEN bit of the
RCSTA register enables the EUSART and automatically
configures the TX/CK I/O pin as an output. If the TX/CK
pin is shared with an analog peripheral, the analog I/O
function must be disabled by clearing the corresponding
ANSEL bit.
Note:
Transmit Interrupt Flag
The TXIF interrupt flag bit of the PIR1 register is set

whenever the EUSART transmitter is enabled and no
character is being held for transmission in the TXREG.
In other words, the TXIF bit is only clear when the TSR
is busy with a character and a new character has been
queued for transmission in the TXREG. The TXIF flag bit
is not cleared immediately upon writing TXREG. TXIF
becomes valid in the second instruction cycle following
the write execution. Polling TXIF immediately following
the TXREG write will return invalid results. The TXIF bit
is read-only, it cannot be set or cleared by software.
The TXIF interrupt can be enabled by setting the TXIE
interrupt enable bit of the PIE1 register. However, the
TXIF flag bit will be set whenever the TXREG is empty,
regardless of the state of TXIE enable bit.
To use interrupts when transmitting data, set the TXIE
bit only when there is more data to send. Clear the
TXIE interrupt enable bit upon writing the last character
of the transmission to the TXREG.
The TXIF Transmitter Interrupt flag is set

when the TXEN enable bit is set.
Preliminary
DS41639A-page 259
PIC16(L)F1454/5/9
23.1.1.5
TSR Status
23.1.1.7
The TRMT bit of the TXSTA register indicates the

status of the TSR register. This is a read-only bit. The
TRMT bit is set when the TSR register is empty and is
cleared when a character is transferred to the TSR
register from the TXREG. The TRMT bit remains clear
until all bits have been shifted out of the TSR register.
No interrupt logic is tied to this bit, so the user has to
poll this bit to determine the TSR status.
Note:
23.1.1.6
1.
2.
3.
The TSR register is not mapped in data

memory, so it is not available to the user.
4.
5.
Transmitting 9-Bit Characters
The EUSART supports 9-bit character transmissions.

When the TX9 bit of the TXSTA register is set, the
EUSART will shift nine bits out for each character transmitted. The TX9D bit of the TXSTA register is the ninth,
and Most Significant, data bit. When transmitting 9-bit
data, the TX9D data bit must be written before writing
the eight Least Significant bits into the TXREG. All nine
bits of data will be transferred to the TSR shift register
immediately after the TXREG is written.
A special 9-bit Address mode is available for use with
multiple receivers. See Section 23.1.2.7 Address
Detection for more information on the address mode.
FIGURE 23-3:
Write to TXREG
BRG Output
(Shift Clock)
8.
Word 1
Start bit
bit 0
bit 1
bit 7/8
Stop bit
Word 1
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
FIGURE 23-4:
7.
Initialize the SPBRGH, SPBRGL register pair and

the BRGH and BRG16 bits to achieve the desired
baud rate (see Section 23.4 EUSART Baud
Rate Generator (BRG)).
Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
If 9-bit transmission is desired, set the TX9 control bit. A set ninth data bit will indicate that the
eight Least Significant data bits are an address
when the receiver is set for address detection.
Set SCKP bit if inverted transmit is desired.
Enable the transmission by setting the TXEN
control bit. This will cause the TXIF interrupt bit
to be set.
If interrupts are desired, set the TXIE interrupt
enable bit of the PIE1 register. An interrupt will
occur immediately provided that the GIE and
PEIE bits of the INTCON register are also set.
If 9-bit transmission is selected, the ninth bit
should be loaded into the TX9D data bit.
Load 8-bit data into the TXREG register. This
will start the transmission.
ASYNCHRONOUS TRANSMISSION
TX/CK
pin
TRMT bit
(Transmit Shift
Reg. Empty Flag)
6.
Asynchronous Transmission Set-up:
1 TCY
Word 1
Transmit Shift Reg.
ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Write to TXREG
BRG Output
(Shift Clock)
Word 1
TX/CK
pin
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Note:
Word 2
Start bit
bit 0
1 TCY
bit 1
Word 1
bit 7/8
Stop bit
Start bit
bit 0
Word 2
1 TCY
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
This timing diagram shows two consecutive transmissions.
DS41639A-page 260
Preliminary
PIC16(L)F1454/5/9
TABLE 23-1:
Name
BAUDCON
INTCON
SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
269
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
96
RCIE
TXIE
SSP1IE
TMR2IE
TMR1IE
97
TMR1GIE
PIE1
TMR1GIF
PIR1
RCSTA
SPEN
(2)
ADIE
ADIF
(2)
RX9
RCIF
TXIF
SSP1IF
TMR2IF
TMR1IF
99
SREN
CREN
ADDEN
FERR
OERR
RX9D
268*
SPBRGL
SPBRGH
(1)
(1)
TRISC6
TRISC5
TRISC
TRISC7
TXREG
EUSART Transmit Data Register
TXSTA
CSRC
TX9
TXEN
BRG<7:0>
270*
BRG<15:8>
270*
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
140
259
SYNC
SENDB
BRGH
TRMT
TX9D
267
Legend: = unimplemented location, read as 0. Shaded cells are not used for asynchronous transmission.
* Page provides register information.
Note 1: PIC16(L)F1459 only.
2: PIC16(L)F1455/9 only.
Preliminary
DS41639A-page 261
PIC16(L)F1454/5/9
23.1.2
EUSART ASYNCHRONOUS
RECEIVER
23.1.2.2
The Asynchronous mode is typically used in RS-232

systems. The receiver block diagram is shown in
Figure 23-2. The data is received on the RX/DT pin and
drives the data recovery block. The data recovery block
is actually a high-speed shifter operating at 16 times
the baud rate, whereas the serial Receive Shift
Register (RSR) operates at the bit rate. When all eight
or nine bits of the character have been shifted in, they
are immediately transferred to a two character
First-In-First-Out (FIFO) memory. The FIFO buffering
allows reception of two complete characters and the
start of a third character before software must start
servicing the EUSART receiver. The FIFO and RSR
registers are not directly accessible by software.
Access to the received data is via the RCREG register.
23.1.2.1
Enabling the Receiver
The EUSART receiver is enabled for asynchronous

operation by configuring the following three control bits:
CREN = 1
SYNC = 0
SPEN = 1
All other EUSART control bits are assumed to be in
their default state.
Setting the CREN bit of the RCSTA register enables the
receiver circuitry of the EUSART. Clearing the SYNC bit
of the TXSTA register configures the EUSART for
asynchronous operation. Setting the SPEN bit of the
RCSTA register enables the EUSART. The programmer
must set the corresponding TRIS bit to configure the
RX/DT I/O pin as an input.
Note:
If the RX/DT function is on an analog pin,

the corresponding ANSEL bit must be
cleared for the receiver to function.
Receiving Data
The receiver data recovery circuit initiates character

reception on the falling edge of the first bit. The first bit,
also known as the Start bit, is always a zero. The data
recovery circuit counts one-half bit time to the center of
the Start bit and verifies that the bit is still a zero. If it is
not a zero then the data recovery circuit aborts
character reception, without generating an error, and
resumes looking for the falling edge of the Start bit. If
the Start bit zero verification succeeds then the data
recovery circuit counts a full bit time to the center of the
next bit. The bit is then sampled by a majority detect
circuit and the resulting 0 or 1 is shifted into the RSR.
This repeats until all data bits have been sampled and
shifted into the RSR. One final bit time is measured and
the level sampled. This is the Stop bit, which is always
a 1. If the data recovery circuit samples a 0 in the
Stop bit position, then a framing error is set for this
character, otherwise, the framing error is cleared for
this character. See Section 23.1.2.4 Receive
Framing Error for more information on framing
errors.
Immediately after all data bits and the Stop bit have
been received, the character in the RSR is transferred
to the EUSART receive FIFO and the RCIF interrupt
flag bit of the PIR1 register is set. The top character in
the FIFO is transferred out of the FIFO by reading the
RCREG register.
Note:
23.1.2.3
If the receive FIFO is overrun, no additional

characters will be received until the overrun
condition is cleared. See Section 23.1.2.5
Receive Overrun Error for more
information on overrun errors.
Receive Interrupts
The RCIF interrupt flag bit of the PIR1 register is set

whenever the EUSART receiver is enabled and there is
an unread character in the receive FIFO. The RCIF
interrupt flag bit is read-only, it cannot be set or cleared
by software.
RCIF interrupts are enabled by setting all of the
following bits:
RCIE interrupt enable bit of the PIE1 register
PEIE peripheral interrupt enable bit of the
INTCON register
GIE Global Interrupt Enable bit of the INTCON
register
The RCIF interrupt flag bit will be set when there is an
unread character in the FIFO, regardless of the state of
interrupt enable bits.
DS41639A-page 262
Preliminary
PIC16(L)F1454/5/9
23.1.2.4
Receive Framing Error
23.1.2.7
Each character in the receive FIFO buffer has a

corresponding framing error Status bit. A framing error
indicates that a Stop bit was not seen at the expected
time. The framing error status is accessed via the
FERR bit of the RCSTA register. The FERR bit
represents the status of the top unread character in the
receive FIFO. Therefore, the FERR bit must be read
before reading the RCREG.
The FERR bit is read-only and only applies to the top
unread character in the receive FIFO. A framing error
(FERR = 1) does not preclude reception of additional
characters. It is not necessary to clear the FERR bit.
Reading the next character from the FIFO buffer will
advance the FIFO to the next character and the next
corresponding framing error.
The FERR bit can be forced clear by clearing the SPEN
bit of the RCSTA register which resets the EUSART.
Clearing the CREN bit of the RCSTA register does not
affect the FERR bit. A framing error by itself does not
generate an interrupt.
Note:
23.1.2.5
Address Detection
A special Address Detection mode is available for use

when multiple receivers share the same transmission
line, such as in RS-485 systems. Address detection is
enabled by setting the ADDEN bit of the RCSTA
register.
Address detection requires 9-bit character reception.
When address detection is enabled, only characters
with the ninth data bit set will be transferred to the
receive FIFO buffer, thereby setting the RCIF interrupt
bit. All other characters will be ignored.
Upon receiving an address character, user software
determines if the address matches its own. Upon
address match, user software must disable address
detection by clearing the ADDEN bit before the next
Stop bit occurs. When user software detects the end of
the message, determined by the message protocol
used, software places the receiver back into the
Address Detection mode by setting the ADDEN bit.
If all receive characters in the receive

FIFO have framing errors, repeated reads
of the RCREG will not clear the FERR bit.
Receive Overrun Error
The receive FIFO buffer can hold two characters. An

overrun error will be generated if a third character, in its
entirety, is received before the FIFO is accessed. When
this happens the OERR bit of the RCSTA register is set.
The characters already in the FIFO buffer can be read
but no additional characters will be received until the
error is cleared. The error must be cleared by either
clearing the CREN bit of the RCSTA register or by
resetting the EUSART by clearing the SPEN bit of the
RCSTA register.
23.1.2.6
Receiving 9-bit Characters
The EUSART supports 9-bit character reception. When

the RX9 bit of the RCSTA register is set the EUSART
will shift nine bits into the RSR for each character
received. The RX9D bit of the RCSTA register is the
ninth and Most Significant data bit of the top unread
character in the receive FIFO. When reading 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the eight Least Significant bits
from the RCREG.
Preliminary
DS41639A-page 263
PIC16(L)F1454/5/9
23.1.2.8
Asynchronous Reception Set-up:
23.1.2.9
1.
Initialize the SPBRGH, SPBRGL register pair

and the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 23.4 EUSART
Baud Rate Generator (BRG)).
2. Clear the ANSEL bit for the RX pin (if applicable).
3. Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
4. If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
5. If 9-bit reception is desired, set the RX9 bit.
6. Enable reception by setting the CREN bit.
7. The RCIF interrupt flag bit will be set when a
character is transferred from the RSR to the
receive buffer. An interrupt will be generated if
the RCIE interrupt enable bit was also set.
8. Read the RCSTA register to get the error flags
and, if 9-bit data reception is enabled, the ninth
data bit.
9. Get the received eight Least Significant data bits
from the receive buffer by reading the RCREG
register.
10. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
FIGURE 23-5:
Rcv Shift
Reg
Rcv Buffer Reg.
RCIDL
This mode would typically be used in RS-485 systems.

To set up an Asynchronous Reception with Address
Detect Enable:
1.

3. Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
INTCON register.
5. Enable 9-bit reception by setting the RX9 bit.
6. Enable address detection by setting the ADDEN
bit.
7. Enable reception by setting the CREN bit.
8. The RCIF interrupt flag bit will be set when a
character with the ninth bit set is transferred
from the RSR to the receive buffer. An interrupt
will be generated if the RCIE interrupt enable bit
was also set.
9. Read the RCSTA register to get the error flags.
The ninth data bit will always be set.
10. Get the received eight Least Significant data bits
from the receive buffer by reading the RCREG
register. Software determines if this is the
devices address.
11. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
12. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and generate interrupts.
ASYNCHRONOUS RECEPTION
Start
bit
bit 0
RX/DT pin
9-bit Address Detection Mode Set-up
bit 1
bit 7/8 Stop

bit
Start
bit
bit 0
Word 1
RCREG
bit 7/8 Stop

bit
Start
bit
bit 7/8 Stop

bit
Word 2
RCREG
Read Rcv
Buffer Reg.
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
DS41639A-page 264
Preliminary
PIC16(L)F1454/5/9
TABLE 23-2:
Name
BAUDCON
INTCON
SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
269
GIE
PEIE
TMR1GIE
PIE1
TMR1GIF
PIR1
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
96
(2)
RCIE
TXIE
SSP1IE
TMR2IE
TMR1IE
97
(2)
RCIF
TXIF
SSP1IF
TMR2IF
TMR1IF
ADIE
ADIF
RCREG
RCSTA
EUSART Receive Data Register

SPEN
RX9
SREN
SPBRGL
CREN
ADDEN
FERR
OERR
RX9D
BRG<7:0>
SPBRGH
TRISC
TRISC7
TXSTA
CSRC
268*
270*
BRG<15:8>
(1)
99
262*
270*
TRISC6(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
140
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
267
Legend: = unimplemented location, read as 0. Shaded cells are not used for asynchronous reception.
2: PIC16(L)F1455/9 only.
Preliminary
DS41639A-page 265
PIC16(L)F1454/5/9
23.2
Clock Accuracy with

Asynchronous Operation
The factory calibrates the internal oscillator block output (INTOSC). However, the INTOSC frequency may
drift as VDD or temperature changes, and this directly
affects the asynchronous baud rate. Two methods may
be used to adjust the baud rate clock, but both require
a reference clock source of some kind.
The first (preferred) method uses the OSCTUNE
register to adjust the INTOSC output. Adjusting the
value in the OSCTUNE register allows for fine resolution
changes to the system clock source. See Section 5.2.2
Internal Clock Sources for more information.
The other method adjusts the value in the Baud Rate
Generator. This can be done automatically with the
Auto-Baud Detect feature (see Section 23.4.1
Auto-Baud Detect). There may not be fine enough
resolution when adjusting the Baud Rate Generator to
compensate for a gradual change in the peripheral
clock frequency.
DS41639A-page 266
Preliminary
PIC16(L)F1454/5/9
23.3
Register Definitions: EUSART Control
REGISTER 23-1:
TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R-1/1
R/W-0/0
CSRC
TX9
TXEN(1)
SYNC
SENDB
BRGH
TRMT
TX9D
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
CSRC: Clock Source Select bit

Asynchronous mode:
Dont care
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6
TX9: 9-bit Transmit Enable bit

1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5
TXEN: Transmit Enable bit(1)

1 = Transmit enabled
0 = Transmit disabled
bit 4
SYNC: EUSART Mode Select bit

1 = Synchronous mode
0 = Asynchronous mode
bit 3
SENDB: Send Break Character bit

Asynchronous mode:
1 = Send Sync Break on next transmission (cleared by hardware upon completion)
0 = Sync Break transmission completed
Synchronous mode:
Dont care
bit 2
BRGH: High Baud Rate Select bit

Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode
bit 1
TRMT: Transmit Shift Register Status bit

1 = TSR empty
0 = TSR full
bit 0
TX9D: Ninth bit of Transmit Data

Can be address/data bit or a parity bit.
Note 1:
SREN/CREN overrides TXEN in Sync mode.
Preliminary
DS41639A-page 267
PIC16(L)F1454/5/9
RCSTA: RECEIVE STATUS AND CONTROL REGISTER(1)
REGISTER 23-2:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R-0/0
R-0/0
R-0/0
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
SPEN: Serial Port Enable bit

1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
0 = Serial port disabled (held in Reset)
bit 6
RX9: 9-bit Receive Enable bit

1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5
SREN: Single Receive Enable bit

Asynchronous mode:
Dont care
Synchronous mode Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode Slave
Dont care
bit 4
CREN: Continuous Receive Enable bit

Asynchronous mode:
1 = Enables receiver
0 = Disables receiver
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3
ADDEN: Address Detect Enable bit

Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 8-bit (RX9 = 0):
Dont care
bit 2
FERR: Framing Error bit

1 = Framing error (can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1
OERR: Overrun Error bit

1 = Overrun error (can be cleared by clearing bit CREN)
0 = No overrun error
bit 0
RX9D: Ninth bit of Received Data

This can be address/data bit or a parity bit and must be calculated by user firmware.
DS41639A-page 268
Preliminary
PIC16(L)F1454/5/9
REGISTER 23-3:
BAUDCON: BAUD RATE CONTROL REGISTER
R-0/0
R-1/1
U-0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
R/W-0/0
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
ABDOVF: Auto-Baud Detect Overflow bit

Asynchronous mode:
1 = Auto-baud timer overflowed
0 = Auto-baud timer did not overflow
Synchronous mode:
Dont care
bit 6
RCIDL: Receive Idle Flag bit

Asynchronous mode:
1 = Receiver is idle
0 = Start bit has been received and the receiver is receiving
Synchronous mode:
Dont care
bit 5
bit 4
SCKP: Synchronous Clock Polarity Select bit

Asynchronous mode:
1 = Transmit inverted data to the TX/CK pin
0 = Transmit non-inverted data to the TX/CK pin
Synchronous mode:
1 = Data is clocked on rising edge of the clock
0 = Data is clocked on falling edge of the clock
bit 3
BRG16: 16-bit Baud Rate Generator bit

1 = 16-bit Baud Rate Generator is used
0 = 8-bit Baud Rate Generator is used
bit 2
bit 1
WUE: Wake-up Enable bit

Asynchronous mode:
1 = Receiver is waiting for a falling edge. No character will be received, byte RCIF will be set. WUE
will automatically clear after RCIF is set.
0 = Receiver is operating normally
Synchronous mode:
Dont care
bit 0
ABDEN: Auto-Baud Detect Enable bit

Asynchronous mode:
1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete)
0 = Auto-Baud Detect mode is disabled
Synchronous mode:
Dont care
Preliminary
DS41639A-page 269
PIC16(L)F1454/5/9
23.4
EUSART Baud Rate Generator

(BRG)
EXAMPLE 23-1:
The Baud Rate Generator (BRG) is an 8-bit or 16-bit

timer that is dedicated to the support of both the
asynchronous and synchronous EUSART operation.
By default, the BRG operates in 8-bit mode. Setting the
BRG16 bit of the BAUDCON register selects 16-bit
mode.
For a device with FOSC of 16 MHz, desired baud rate

of 9600, Asynchronous mode, 8-bit BRG:
F OS C
Desired Baud Rate = -----------------------------------------------------------------------64 [SPBRGH:SPBRGL] + 1
Solving for SPBRGH:SPBRGL:

FOSC
--------------------------------------------Desired Baud Rate
X = --------------------------------------------- 1
64
The SPBRGH, SPBRGL register pair determines the

period of the free running baud rate timer. In
Asynchronous mode the multiplier of the baud rate
period is determined by both the BRGH bit of the TXSTA
register and the BRG16 bit of the BAUDCON register. In
Synchronous mode, the BRGH bit is ignored.
Table 23-3 contains the formulas for determining the
baud rate. Example 23-1 provides a sample calculation
for determining the baud rate and baud rate error.
CALCULATING BAUD
RATE ERROR
16000000
-----------------------9600
= ------------------------ 1
64
= 25.042 = 25
16000000
Calculated Baud Rate = --------------------------64 25 + 1
Typical baud rates and error values for various

Asynchronous modes have been computed for your
convenience and are shown in Table 23-3. It may be
advantageous to use the high baud rate (BRGH = 1),
or the 16-bit BRG (BRG16 = 1) to reduce the baud rate
error. The 16-bit BRG mode is used to achieve slow
baud rates for fast oscillator frequencies.
= 9615
Calc. Baud Rate Desired Baud Rate
Error = -------------------------------------------------------------------------------------------Desired Baud Rate
9615 9600
= ---------------------------------- = 0.16%
9600
Writing a new value to the SPBRGH, SPBRGL register

pair causes the BRG timer to be reset (or cleared). This
ensures that the BRG does not wait for a timer overflow
before outputting the new baud rate.
If the system clock is changed during an active receive
operation, a receive error or data loss may result. To
avoid this problem, check the status of the RCIDL bit to
make sure that the receive operation is idle before
changing the system clock.
DS41639A-page 270
Preliminary
PIC16(L)F1454/5/9
TABLE 23-3:
BAUD RATE FORMULAS
Configuration Bits
BRG/EUSART Mode
Baud Rate Formula
8-bit/Asynchronous
FOSC/[64 (n+1)]
8-bit/Asynchronous
16-bit/Asynchronous
16-bit/Asynchronous
8-bit/Synchronous
16-bit/Synchronous
SYNC
BRG16
BRGH
Legend:
Name
BAUDCON
SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR

Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
269
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
SPBRGL
BRG<7:0>
SPBRGH
BRG<15:8>
TXSTA
FOSC/[4 (n+1)]
x = Dont care, n = value of SPBRGH, SPBRGL register pair.
TABLE 23-4:
RCSTA
FOSC/[16 (n+1)]
CSRC
TX9
TXEN
SYNC
SENDB
268
270*
270*
BRGH
TRMT
TX9D
267
Legend: = unimplemented location, read as 0. Shaded cells are not used for the Baud Rate Generator.
Preliminary
DS41639A-page 271
PIC16(L)F1454/5/9
TABLE 23-5:
BAUD RATES FOR ASYNCHRONOUS MODES

SYNC = 0, BRGH = 0, BRG16 = 0
BAUD
RATE
FOSC = 20.000 MHz

Actual
Rate
%
Error
SPBRG
value
(decimal)
FOSC = 18.432 MHz

Actual
Rate
%
Error
SPBRG
value
(decimal)
FOSC = 16.000 MHz

Actual
Rate
%
Error
FOSC = 11.0592 MHz
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
1200
1221
1.73
255
1200
0.00
239
1202
0.16
207
1200
0.00
143
2400
2404
0.16
129
2400
0.00
119
2404
0.16
103
2400
0.00
71
9600
9470
-1.36
32
9600
0.00
29
9615
0.16
25
9600
0.00
17
10417
10417
0.00
29
10286
-1.26
27
10417
0.00
23
10165
-2.42
16
19.2k
19.53k
1.73
15
19.20k
0.00
14
19.23k
0.16
12
19.20k
0.00
57.6k
57.60k
0.00
57.60k
0.00
115.2k
SYNC = 0, BRGH = 0, BRG16 = 0

BAUD
RATE
FOSC = 8.000 MHz

Actual
Rate
%
Error
SPBRG
value
(decimal)
FOSC = 4.000 MHz

Actual
Rate
%
Error
SPBRG
value
(decimal)
FOSC = 3.6864 MHz

Actual
Rate
FOSC = 1.000 MHz
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
300
0.16
207
300
0.00
191
300
0.16
51
1200
1202
0.16
103
1202
0.16
51
1200
0.00
47
1202
0.16
12
2400
2404
0.16
51
2404
0.16
25
2400
0.00
23
9600
9615
0.16
12
9600
0.00
10417
10417
0.00
11
10417
0.00
19.2k
19.20k
0.00
57.6k
57.60k
0.00
115.2k
SYNC = 0, BRGH = 1, BRG16 = 0

BAUD
RATE
FOSC = 20.000 MHz

Actual
Rate
%
Error
SPBRG
value
(decimal)
FOSC = 18.432 MHz

Actual
Rate
%
Error
SPBRG
value
(decimal)
FOSC = 16.000 MHz

Actual
Rate
%
Error
FOSC = 11.0592 MHz
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
1200
2400
9600
9615
0.16
129
9600
0.00
119
9615
0.16
103
9600
0.00
71
10417
10417
0.00
119
10378
-0.37
110
10417
0.00
95
10473
0.53
65
19.2k
19.23k
0.16
64
19.20k
0.00
59
19.23k
0.16
51
19.20k
0.00
35
57.6k
56.82k
-1.36
21
57.60k
0.00
19
58.82k
2.12
16
57.60k
0.00
11
115.2k
113.64k
-1.36
10
115.2k
0.00
111.1k
-3.55
115.2k
0.00
DS41639A-page 272
Preliminary
PIC16(L)F1454/5/9
TABLE 23-5:
BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)

SYNC = 0, BRGH = 1, BRG16 = 0
BAUD
RATE
FOSC = 8.000 MHz

SPBRG
Actual
%
value
Rate
Error
(decimal)
FOSC = 4.000 MHz

SPBRG
Actual
%
value
Rate
Error
(decimal)
FOSC = 3.6864 MHz

SPBRG
Actual
%
value
Rate
Error
(decimal)
FOSC = 1.000 MHz

SPBRG
Actual
%
value
Rate
Error
(decimal)
300
1200
1202
0.16
207
1200
0.00
191
300
1202
0.16
0.16
207
51
2400
2404
0.16
207
2404
0.16
103
2400
0.00
95
2404
0.16
25
9600
9615
0.16
51
9615
0.16
25
9600
0.00
23
10417
10417
0.00
47
10417
0.00
23
10473
0.53
21
10417
0.00
19.2k
19231
0.16
25
19.23k
0.16
12
19.2k
0.00
11
57.6k
55556
-3.55
57.60k
0.00
115.2k
115.2k
0.00
SYNC = 0, BRGH = 0, BRG16 = 1

BAUD
RATE
FOSC = 20.000 MHz

Actual
Rate
FOSC = 18.432 MHz
%
Error
SPBRG
value
(decimal)
Actual
Rate
FOSC = 16.000 MHz
%
Error
SPBRG
value
(decimal)
Actual
Rate
FOSC = 11.0592 MHz
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
300.0
-0.01
4166
300.0
0.00
3839
300.03
0.01
3332
300.0
0.00
2303
1200
1200
-0.03
1041
1200
0.00
959
1200.5
0.04
832
1200
0.00
575
2400
2399
-0.03
520
2400
0.00
479
2398
-0.08
416
2400
0.00
287
9600
9615
0.16
129
9600
0.00
119
9615
0.16
103
9600
0.00
71
10417
10417
0.00
119
10378
-0.37
110
10417
0.00
95
10473
0.53
65
19.2k
19.23k
0.16
64
19.20k
0.00
59
19.23k
0.16
51
19.20k
0.00
35
57.6k
56.818
-1.36
21
57.60k
0.00
19
58.82k
2.12
16
57.60k
0.00
11
115.2k
113.636
-1.36
10
115.2k
0.00
111.11k
-3.55
115.2k
0.00
SYNC = 0, BRGH = 0, BRG16 = 1

BAUD
RATE
FOSC = 8.000 MHz

Actual
Rate
FOSC = 4.000 MHz
%
Error
SPBRG
value
(decimal)
Actual
Rate
FOSC = 3.6864 MHz
%
Error
SPBRG
value
(decimal)
Actual
Rate
FOSC = 1.000 MHz
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
299.9
-0.02
1666
300.1
0.04
832
300.0
0.00
767
300.5
0.16
207
1200
1199
-0.08
416
1202
0.16
207
1200
0.00
191
1202
0.16
51
2400
2404
0.16
207
2404
0.16
103
2400
0.00
95
2404
0.16
25
9600
9615
0.16
51
9615
0.16
25
9600
0.00
23
10417
10417
0.00
47
10417
0.00
23
10473
0.53
21
10417
0.00
19.2k
19.23k
0.16
25
19.23k
0.16
12
19.20k
0.00
11
57.6k
55556
-3.55
57.60k
0.00
115.2k
115.2k
0.00
Preliminary
DS41639A-page 273
PIC16(L)F1454/5/9
TABLE 23-5:
BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 20.000 MHz

SPBRG
Actual
%
value
Rate
Error
(decimal)
FOSC = 18.432 MHz

SPBRG
Actual
%
value
Rate
Error
(decimal)
FOSC = 16.000 MHz

SPBRG
Actual
%
value
Rate
Error
(decimal)
FOSC = 11.0592 MHz

SPBRG
Actual
%
value
Rate
Error
(decimal)
300
1200
300.0
1200
0.00
-0.01
16665
4166
300.0
1200
0.00
0.00
15359
3839
300.0
1200.1
0.00
0.01
13332
3332
300.0
1200
0.00
0.00
9215
2303
2400
2400
0.02
2082
2400
0.00
1919
2399.5
-0.02
1666
2400
0.00
1151
9600
9597
-0.03
520
9600
0.00
479
9592
-0.08
416
9600
0.00
287
10417
10417
0.00
479
10425
0.08
441
10417
0.00
383
10433
0.16
264
BAUD
RATE
19.2k
19.23k
0.16
259
19.20k
0.00
239
19.23k
0.16
207
19.20k
0.00
143
57.6k
57.47k
-0.22
86
57.60k
0.00
79
57.97k
0.64
68
57.60k
0.00
47
115.2k
116.3k
0.94
42
115.2k
0.00
39
114.29k
-0.79
34
115.2k
0.00
23
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

BAUD
RATE
FOSC = 8.000 MHz

Actual
Rate
FOSC = 4.000 MHz
%
Error
SPBRG
value
(decimal)
Actual
Rate
FOSC = 3.6864 MHz
%
Error
SPBRG
value
(decimal)
Actual
Rate
FOSC = 1.000 MHz
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
300.0
0.00
6666
300.0
0.01
3332
300.0
0.00
3071
300.1
0.04
832
1200
1200
-0.02
1666
1200
0.04
832
1200
0.00
767
1202
0.16
207
2400
2401
0.04
832
2398
0.08
416
2400
0.00
383
2404
0.16
103
9600
9615
0.16
207
9615
0.16
103
9600
0.00
95
9615
0.16
25
10417
10417
191
10417
0.00
95
10473
0.53
87
10417
0.00
23
19.2k
19.23k
0.16
103
19.23k
0.16
51
19.20k
0.00
47
19.23k
0.16
12
57.6k
57.14k
-0.79
34
58.82k
2.12
16
57.60k
0.00
15
115.2k
117.6k
2.12
16
111.1k
-3.55
115.2k
0.00
DS41639A-page 274
Preliminary
PIC16(L)F1454/5/9
23.4.1
AUTO-BAUD DETECT
The EUSART module supports automatic detection

and calibration of the baud rate.
In the Auto-Baud Detect (ABD) mode, the clock to the
BRG is reversed. Rather than the BRG clocking the
incoming RX signal, the RX signal is timing the BRG.
The Baud Rate Generator is used to time the period of
a received 55h (ASCII U) which is the Sync character
for the LIN bus. The unique feature of this character is
that it has five rising edges including the Stop bit edge.
Setting the ABDEN bit of the BAUDCON register starts
the auto-baud calibration sequence (Figure 23-6).
While the ABD sequence takes place, the EUSART
state machine is held in Idle. On the first rising edge of
the receive line, after the Start bit, the SPBRG begins
counting up using the BRG counter clock as shown in
Table 23-6. The fifth rising edge will occur on the RX pin
at the end of the eighth bit period. At that time, an
accumulated value totaling the proper BRG period is
left in the SPBRGH, SPBRGL register pair, the ABDEN
bit is automatically cleared and the RCIF interrupt flag
is set. The value in the RCREG needs to be read to
clear the RCIF interrupt. RCREG content should be
discarded. When calibrating for modes that do not use
the SPBRGH register the user can verify that the
SPBRGL register did not overflow by checking for 00h
in the SPBRGH register.
The BRG auto-baud clock is determined by the BRG16
and BRGH bits as shown in Table 23-6. During ABD,
both the SPBRGH and SPBRGL registers are used as
a 16-bit counter, independent of the BRG16 bit setting.
While calibrating the baud rate period, the SPBRGH
FIGURE 23-6:
Note 1: If the WUE bit is set with the ABDEN bit,

auto-baud detection will occur on the byte
following the Break character (see
Section 23.4.3 Auto-Wake-up on
Break).
2: It is up to the user to determine that the
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible.
3: During the auto-baud process, the
auto-baud counter starts counting at one.
Upon completion of the auto-baud
sequence, to achieve maximum accuracy,
subtract one from the SPBRGH:SPBRGL
register pair.
TABLE 23-6:
BRG COUNTER CLOCK RATES
BRG16
BRGH
BRG Base
Clock
BRG ABD
Clock
FOSC/64
FOSC/512
FOSC/16
FOSC/128
FOSC/16
FOSC/128
FOSC/4
FOSC/32
1
Note:
During the ABD sequence, SPBRGL and

SPBRGH registers are both used as a 16-bit
counter, independent of BRG16 setting.
AUTOMATIC BAUD RATE CALIBRATION

XXXXh
BRG Value
and SPBRGL registers are clocked at 1/8th the BRG

base clock rate. The resulting byte measurement is the
average bit time when clocked at full speed.
RX pin
0000h
001Ch
Start
Edge #1
bit 1
bit 0
Edge #2
bit 3
bit 2
Edge #3
bit 5
bit 4
Edge #4
bit 7
bit 6
Edge #5
Stop bit
BRG Clock
Auto Cleared
Set by User
ABDEN bit
RCIDL
RCIF bit
(Interrupt)
Read
RCREG
SPBRGL
XXh
1Ch
SPBRGH
XXh
00h
Note 1:
The ABD sequence requires the EUSART module to be configured in Asynchronous mode.
Preliminary
DS41639A-page 275
PIC16(L)F1454/5/9
23.4.2
AUTO-BAUD OVERFLOW
23.4.3.1
During the course of automatic baud detection, the

ABDOVF bit of the BAUDCON register will be set if the
baud rate counter overflows before the fifth rising edge
is detected on the RX pin. The ABDOVF bit indicates
that the counter has exceeded the maximum count that
can fit in the 16 bits of the SPBRGH:SPBRGL register
pair. After the ABDOVF bit has been set, the counter
continues to count until the fifth rising edge is detected
on the RX pin. Upon detecting the fifth RX edge, the
hardware will set the RCIF interrupt flag and clear the
ABDEN bit of the BAUDCON register. The RCIF flag
can be subsequently cleared by reading the RCREG
register. The ABDOVF flag of the BAUDCON register
can be cleared by software directly.
To terminate the auto-baud process before the RCIF
flag is set, clear the ABDEN bit then clear the ABDOVF
bit of the BAUDCON register. The ABDOVF bit will
remain set if the ABDEN bit is not cleared first.
23.4.3
AUTO-WAKE-UP ON BREAK
During Sleep mode, all clocks to the EUSART are

suspended. Because of this, the Baud Rate Generator
is inactive and a proper character reception cannot be
performed. The Auto-Wake-up feature allows the
controller to wake-up due to activity on the RX/DT line.
This feature is available only in Asynchronous mode.
The Auto-Wake-up feature is enabled by setting the
WUE bit of the BAUDCON register. Once set, the normal
receive sequence on RX/DT is disabled, and the
EUSART remains in an Idle state, monitoring for a
wake-up event independent of the CPU mode. A
wake-up event consists of a high-to-low transition on the
RX/DT line. (This coincides with the start of a Sync Break
or a wake-up signal character for the LIN protocol.)
The EUSART module generates an RCIF interrupt
coincident with the wake-up event. The interrupt is
generated synchronously to the Q clocks in normal CPU
operating modes (Figure 23-7), and asynchronously if
the device is in Sleep mode (Figure 23-8). The interrupt
condition is cleared by reading the RCREG register.
Special Considerations
Break Character
To avoid character errors or character fragments during
a wake-up event, the wake-up character must be all
zeros.
When the wake-up is enabled the function works
independent of the low time on the data stream. If the
WUE bit is set and a valid non-zero character is
received, the low time from the Start bit to the first rising
edge will be interpreted as the wake-up event. The
remaining bits in the character will be received as a
fragmented character and subsequent characters can
result in framing or overrun errors.
Therefore, the initial character in the transmission must
be all 0s. This must be ten or more bit times, 13-bit
times recommended for LIN bus, or any number of bit
times for standard RS-232 devices.
Oscillator Start-up Time
Oscillator start-up time must be considered, especially
in applications using oscillators with longer start-up
intervals (i.e., LP, XT or HS/PLL mode). The Sync
Break (or wake-up signal) character must be of
sufficient length, and be followed by a sufficient
interval, to allow enough time for the selected oscillator
to start and provide proper initialization of the EUSART.
WUE Bit
The wake-up event causes a receive interrupt by
setting the RCIF bit. The WUE bit is cleared in
hardware by a rising edge on RX/DT. The interrupt
condition is then cleared in software by reading the
RCREG register and discarding its contents.
To ensure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process
before setting the WUE bit. If a receive operation is not
occurring, the WUE bit may then be set just prior to
entering the Sleep mode.
The WUE bit is automatically cleared by the low-to-high

transition on the RX line at the end of the Break. This
signals to the user that the Break event is over. At this
point, the EUSART module is in Idle mode waiting to
receive the next character.
DS41639A-page 276
Preliminary
PIC16(L)F1454/5/9
FIGURE 23-7:
AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Auto Cleared
Bit set by user
WUE bit
RX/DT Line
RCIF
Note 1:
Cleared due to User Read of RCREG

The EUSART remains in Idle while the WUE bit is set.
FIGURE 23-8:
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4
OSC1
Auto Cleared
Bit Set by User

WUE bit
RX/DT Line
Note 1
RCIF
Sleep Command Executed
Note 1:
2:
Sleep Ends
Cleared due to User Read of RCREG
If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is
still active. This sequence should not depend on the presence of Q clocks.
The EUSART remains in Idle while the WUE bit is set.
Preliminary
DS41639A-page 277
PIC16(L)F1454/5/9
23.4.4
BREAK CHARACTER SEQUENCE
The EUSART module has the capability of sending the

special Break character sequences that are required by
the LIN bus standard. A Break character consists of a
Start bit, followed by 12 0 bits and a Stop bit.
To send a Break character, set the SENDB and TXEN
bits of the TXSTA register. The Break character transmission is then initiated by a write to the TXREG. The
value of data written to TXREG will be ignored and all
0s will be transmitted.
The SENDB bit is automatically reset by hardware after
the corresponding Stop bit is sent. This allows the user
to preload the transmit FIFO with the next transmit byte
following the Break character (typically, the Sync
character in the LIN specification).
The TRMT bit of the TXSTA register indicates when the
transmit operation is active or idle, just as it does during
normal transmission. See Figure 23-9 for the timing of
the Break character sequence.
23.4.4.1
Break and Sync Transmit Sequence
The following sequence will start a message frame

header made up of a Break, followed by an auto-baud
Sync byte. This sequence is typical of a LIN bus
master.
1.
2.
3.
4.
5.
23.4.5
RECEIVING A BREAK CHARACTER
The Enhanced EUSART module can receive a Break

character in two ways.
The first method to detect a Break character uses the
FERR bit of the RCSTA register and the Received data
as indicated by RCREG. The Baud Rate Generator is
assumed to have been initialized to the expected baud
rate.
A Break character has been received when;
RCIF bit is set
FERR bit is set
RCREG = 00h
The second method uses the Auto-Wake-up feature
described in Section 23.4.3 Auto-Wake-up on
Break. By enabling this feature, the EUSART will
sample the next two transitions on RX/DT, cause an
RCIF interrupt, and receive the next data byte followed
by another interrupt.
Note that following a Break character, the user will
typically want to enable the Auto-Baud Detect feature.
For both methods, the user can set the ABDEN bit of
the BAUDCON register before placing the EUSART in
Sleep mode.
Configure the EUSART for the desired mode.

Set the TXEN and SENDB bits to enable the
Break sequence.
Load the TXREG with a dummy character to
initiate transmission (the value is ignored).
Write 55h to TXREG to load the Sync character
into the transmit FIFO buffer.
After the Break has been sent, the SENDB bit is
reset by hardware and the Sync character is
then transmitted.
When the TXREG becomes empty, as indicated by the

TXIF, the next data byte can be written to TXREG.
FIGURE 23-9:
Write to TXREG
SEND BREAK CHARACTER SEQUENCE

Dummy Write
BRG Output
(Shift Clock)
TX (pin)
Start bit
bit 0
bit 1
bit 11
Stop bit
Break
TXIF bit
(Transmit
Interrupt Flag)
TRMT bit
(Transmit Shift
Empty Flag)
SENDB
(send Break
control bit)
DS41639A-page 278
SENDB Sampled Here
Preliminary
Auto Cleared
PIC16(L)F1454/5/9
23.5
EUSART Synchronous Mode
Synchronous serial communications are typically used

in systems with a single master and one or more
slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock
for all devices in the system. Slave devices can take
advantage of the master clock by eliminating the
internal clock generation circuitry.
There are two signal lines in Synchronous mode: a bidirectional data line and a clock line. Slaves use the
external clock supplied by the master to shift the serial
data into and out of their respective receive and transmit shift registers. Since the data line is bidirectional,
synchronous operation is half-duplex only. Half-duplex
refers to the fact that master and slave devices can
receive and transmit data but not both simultaneously.
The EUSART can operate as either a master or slave
device.
Start and Stop bits are not used in synchronous
transmissions.
23.5.1
SYNCHRONOUS MASTER MODE
Clearing the SCKP bit sets the Idle state as low. When
the SCKP bit is cleared, the data changes on the rising
edge of each clock.
23.5.1.3
Data is transferred out of the device on the RX/DT pin.

The RX/DT and TX/CK pin output drivers are
automatically enabled when the EUSART is configured
for synchronous master transmit operation.
A transmission is initiated by writing a character to the
TXREG register. If the TSR still contains all or part of a
previous character, the new character data is held in
the TXREG until the last bit of the previous character
has been transmitted. If this is the first character, or the
previous character has been completely flushed from
the TSR, the data in the TXREG is immediately transferred to the TSR. The transmission of the character
commences immediately following the transfer of the
data to the TSR from the TXREG.
Each data bit changes on the leading edge of the master clock and remains valid until the subsequent leading
clock edge.
Note:
The TSR register is not mapped in data

memory so it is not available to the user.
23.5.1.4
Synchronous Master Transmission

Set-up:
The following bits are used to configure the EUSART

for synchronous master operation:
SYNC = 1
CSRC = 1
SREN = 0 (for transmit); SREN = 1 (for receive)
CREN = 0 (for transmit); CREN = 1 (for receive)
SPEN = 1
1.
Setting the SYNC bit of the TXSTA register configures

the device for synchronous operation. Setting the CSRC
bit of the TXSTA register configures the device as a
master. Clearing the SREN and CREN bits of the RCSTA
register ensures that the device is in the Transmit mode;
otherwise, the device will be configured to receive.
Setting the SPEN bit of the RCSTA register enables the
EUSART.
23.5.1.1
23.5.1.2
2.
3.
4.
5.
6.
Master Clock
Synchronous data transfers use a separate clock line,

which is synchronous with the data. A device configured as a master transmits the clock on the TX/CK line.
The TX/CK pin output driver is automatically enabled
when the EUSART is configured for synchronous
transmit or receive operation. Serial data bits change
on the leading edge to ensure they are valid at the trailing edge of each clock. One clock cycle is generated
for each data bit. Only as many clock cycles are
generated as there are data bits.
Synchronous Master Transmission
7.
8.

Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
Disable Receive mode by clearing bits SREN
and CREN.
Enable Transmit mode by setting the TXEN bit.
If 9-bit transmission is desired, set the TX9 bit.
If interrupts are desired, set the TXIE bit of the
INTCON register.
If 9-bit transmission is selected, the ninth bit
should be loaded in the TX9D bit.
Start transmission by loading data to the TXREG
register.
Clock Polarity
A clock polarity option is provided for Microwire

compatibility. Clock polarity is selected with the SCKP
bit of the BAUDCON register. Setting the SCKP bit sets
the clock Idle state as high. When the SCKP bit is set,
the data changes on the falling edge of each clock.
Preliminary
DS41639A-page 279
PIC16(L)F1454/5/9
FIGURE 23-10:
SYNCHRONOUS TRANSMISSION
RX/DT
pin
bit 0
bit 1
Word 1
bit 2
bit 7
bit 0
bit 1
Word 2
bit 7
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
TXREG Reg
Write Word 1
Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
TXEN bit
1
Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words.
Note:
FIGURE 23-11:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)

RX/DT pin
bit 0
bit 2
bit 1
bit 6
bit 7
TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
TABLE 23-7:
SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER

TRANSMISSION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register on
Page
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
269
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
96
PIE1
TMR1GIE
ADIE(2)
RCIE
TXIE
SSP1IE
TMR2IE
TMR1IE
97
PIR1
TMR1GIF
ADIF(2)
RCIF
TXIF
SSP1IF
TMR2IF
TMR1IF
99
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
268
Name
BAUDCON
INTCON
RCSTA
SPBRGL
BRG<7:0>
SPBRGH
BRG<15:8>
TRISC7(1)
TRISC
TRISC6(1)
TRISC5
TXREG
TRISC4
TRISC3
270*
270*
TRISC2
TRISC1
TRISC0
BRGH
TRMT
TX9D
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
140
259*
267
Legend:
= unimplemented location, read as 0. Shaded cells are not used for synchronous master transmission.
2:
DS41639A-page 280
Preliminary
PIC16(L)F1454/5/9
23.5.1.5
Synchronous Master Reception
Data is received at the RX/DT pin. The RX/DT pin

output driver is automatically disabled when the
EUSART is configured for synchronous master receive
operation.
In Synchronous mode, reception is enabled by setting
either the Single Receive Enable bit (SREN of the
RCSTA register) or the Continuous Receive Enable bit
(CREN of the RCSTA register).
When SREN is set and CREN is clear, only as many
clock cycles are generated as there are data bits in a
single character. The SREN bit is automatically cleared
at the completion of one character. When CREN is set,
clocks are continuously generated until CREN is
cleared. If CREN is cleared in the middle of a character,
the CK clock stops immediately and the partial character is discarded. If SREN and CREN are both set, then
SREN is cleared at the completion of the first character
and CREN takes precedence.
To initiate reception, set either SREN or CREN. Data is
sampled at the RX/DT pin on the trailing edge of the
TX/CK clock pin and is shifted into the Receive Shift
Register (RSR). When a complete character is
received into the RSR, the RCIF bit is set and the character is automatically transferred to the two character
receive FIFO. The Least Significant eight bits of the top
character in the receive FIFO are available in RCREG.
The RCIF bit remains set as long as there are unread
characters in the receive FIFO.
Note:
23.5.1.6
If the RX/DT function is on an analog pin,

the corresponding ANSEL bit must be
cleared for the receiver to function.
Slave Clock
Synchronous data transfers use a separate clock line,

which is synchronous with the data. A device configured
as a slave receives the clock on the TX/CK line. The
TX/CK pin output driver is automatically disabled when
the device is configured for synchronous slave transmit
or receive operation. Serial data bits change on the
leading edge to ensure they are valid at the trailing edge
of each clock. One data bit is transferred for each clock
cycle. Only as many clock cycles should be received as
there are data bits.
Note:
23.5.1.7
If the device is configured as a slave and

the TX/CK function is on an analog pin, the
corresponding ANSEL bit must be
cleared.
buffer can be read; however, no additional characters

will be received until the error is cleared. The OERR bit
can only be cleared by clearing the overrun condition.
If the overrun error occurred when the SREN bit is set
and CREN is clear, then the error is cleared by reading
RCREG. If the overrun occurred when the CREN bit is
set, then the error condition is cleared by either clearing
the CREN bit of the RCSTA register, or by clearing the
SPEN bit which resets the EUSART.
23.5.1.8
Receiving 9-bit Characters
The EUSART supports 9-bit character reception. When

the RX9 bit of the RCSTA register is set, the EUSART
will shift 9 bits into the RSR for each character
received. The RX9D bit of the RCSTA register is the
ninth, and Most Significant, data bit of the top unread
character in the receive FIFO. When reading 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the eight Least Significant bits
from the RCREG.
23.5.1.9
Synchronous Master Reception

Set-up:
1.
Initialize the SPBRGH, SPBRGL register pair for

the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
3. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
4. Ensure bits CREN and SREN are clear.
INTCON register.
6. If 9-bit reception is desired, set bit RX9.
7. Start reception by setting the SREN bit or, for
continuous reception, set the CREN bit.
8. Interrupt flag bit RCIF will be set when reception
of a character is complete. An interrupt will be
generated if the enable bit RCIE was set.
9. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
10. Read the 8-bit received data by reading the
RCREG register.
11. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.
Receive Overrun Error
The receive FIFO buffer can hold two characters. An

overrun error will be generated if a third character, in its
entirety, is received before RCREG is read to access
the FIFO. When this happens, the OERR bit of the
RCSTA register is set. Previous data in the FIFO will
not be overwritten. The two characters in the FIFO
Preliminary
DS41639A-page 281
PIC16(L)F1454/5/9
FIGURE 23-12:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RX/DT
pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
bit SREN
SREN bit
CREN bit 0
RCIF bit
(Interrupt)
Read
RCREG
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
Note:
TABLE 23-8:
SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER

RECEPTION
Name
Bit 7
Bit 6
BAUDCON
ABDOVF
GIE
INTCON
PIE1
PIR1
Bit 1
Bit 0
Register
on Page
BRG16
WUE
ABDEN
269
IOCIE
TMR0IF
INTF
IOCIF
96
TXIE
SSP1IE
TMR2IE
TMR1IE
97
TXIF
SSP1IF
TMR2IF
TMR1IF
99
FERR
OERR
RX9D
Bit 4
Bit 3
RCIDL
SCKP
PEIE
TMR0IE
INTE
TMR1GIE
ADIE(2)
RCIE
TMR1GIF
ADIF(2)
RCIF
SPEN
RX9
SREN
RCREG
RCSTA
Bit 2
Bit 5
SPBRGL
SPBRGH
(1)
TRISC
TRISC7
TXSTA
CSRC
CREN
ADDEN
262*
268
BRG<7:0>
270*
BRG<15:8>
270*
TRISC6(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
140
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
267
Legend: = unimplemented location, read as 0. Shaded cells are not used for synchronous master reception.
2: PIC16(L)F1455/9 only.
DS41639A-page 282
Preliminary
PIC16(L)F1454/5/9
23.5.2
SYNCHRONOUS SLAVE MODE
The following bits are used to configure the EUSART

for synchronous slave operation:
SYNC = 1
CSRC = 0
SREN = 0 (for transmit); SREN = 1 (for receive)
CREN = 0 (for transmit); CREN = 1 (for receive)
SPEN = 1
1.
2.
3.
4.
Setting the SYNC bit of the TXSTA register configures the

device for synchronous operation. Clearing the CSRC bit
of the TXSTA register configures the device as a slave.
Clearing the SREN and CREN bits of the RCSTA register
ensures that the device is in the Transmit mode;
otherwise, the device will be configured to receive.
Setting the SPEN bit of the RCSTA register enables the
EUSART.
23.5.2.1
If two words are written to the TXREG and then the

SLEEP instruction is executed, the following will occur:
EUSART Synchronous Slave

Transmit
5.
23.5.2.2
1.
The operation of the Synchronous Master and Slave

Section 23.5.1.3
modes
are
identical
(see
Synchronous Master Transmission), except in the
case of the Sleep mode.
2.
3.
4.
5.
6.
7.
8.
TABLE 23-9:
Name
BAUDCON
The first character will immediately transfer to

the TSR register and transmit.
The second word will remain in the TXREG
register.
The TXIF bit will not be set.
After the first character has been shifted out of
TSR, the TXREG register will transfer the second
character to the TSR and the TXIF bit will now be
set.
If the PEIE and TXIE bits are set, the interrupt
will wake the device from Sleep and execute the
next instruction. If the GIE bit is also set, the
program will call the Interrupt Service Routine.
Synchronous Slave Transmission

Set-up:
Set the SYNC and SPEN bits and clear the

CSRC bit.
Clear the ANSEL bit for the CK pin (if applicable).
Clear the CREN and SREN bits.
PIE1 register, and the GIE and PEIE bits of the
INTCON register.
If 9-bit transmission is desired, set the TX9 bit.
Enable transmission by setting the TXEN bit.
If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
Start transmission by writing the Least
Significant 8 bits to the TXREG register.
SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE

TRANSMISSION
Bit 7
Bit 6
ABDOVF
Bit 2
Bit 1
Bit 0
Register
on Page
BRG16
WUE
ABDEN
269
IOCIE
TMR0IF
INTF
IOCIF
96
97
Bit 5
Bit 4
Bit 3
RCIDL
SCKP
INTE
GIE
PEIE
TMR0IE
PIE1
TMR1GIE
ADIE(2)
RCIE
TXIE
SSP1IE
TMR2IE
TMR1IE
PIR1
TMR1GIF
ADIF(2)
RCIF
TXIF
SSP1IF
TMR2IF
TMR1IF
99
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
268
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
140
INTCON
RCSTA
TRISC
TRISC7(1) TRISC6(1)
TXREG
TXSTA

CSRC
TX9
TXEN
SYNC
SENDB
BRGH
259*
TRMT
TX9D
267
Legend: = unimplemented location, read as 0. Shaded cells are not used for synchronous slave transmission.
2: PIC16(L)F1455/9 only.
Preliminary
DS41639A-page 283
PIC16(L)F1454/5/9
23.5.2.3
EUSART Synchronous Slave

Reception
23.5.2.4
The operation of the Synchronous Master and Slave

modes is identical (Section 23.5.1.5 Synchronous
Master Reception), with the following exceptions:
Sleep
CREN bit is always set, therefore the receiver is
never idle
SREN bit, which is a dont care in Slave mode
1.
2.
3.
A character may be received while in Sleep mode by

setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCREG register. If the RCIE enable bit is set, the
interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE bit is also
set, the program will branch to the interrupt vector.
4.
5.
6.
7.
8.
9.
Synchronous Slave Reception

Set-up:
Set the SYNC and SPEN bits and clear the

CSRC bit.
Clear the ANSEL bit for both the CK and DT pins
(if applicable).
If interrupts are desired, set the RCIE bit of the
INTCON register.
If 9-bit reception is desired, set the RX9 bit.
Set the CREN bit to enable reception.
The RCIF bit will be set when reception is
complete. An interrupt will be generated if the
RCIE bit was set.
If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCSTA
register.
Retrieve the 8 Least Significant bits from the
receive FIFO by reading the RCREG register.
If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.
TABLE 23-10: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE

RECEPTION
Name
BAUDCON
Bit 7
Bit 6
ABDOVF
Bit 2
Bit 1
Bit 0
Register
on Page
BRG16
WUE
ABDEN
269
IOCIE
TMR0IF
INTF
IOCIF
96
97
Bit 5
Bit 4
Bit 3
RCIDL
SCKP
INTE
GIE
PEIE
TMR0IE
PIE1
TMR1GIE
ADIE(2)
RCIE
TXIE
SSP1IE
TMR2IE
TMR1IE
PIR1
TMR1GIF
ADIF(2)
RCIF
TXIF
SSP1IF
TMR2IF
TMR1IF
INTCON
RCREG
99
262*
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
268
TRISC
TRISC7(1)
TRISC6(1)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
140
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
267
Legend: = unimplemented location, read as 0. Shaded cells are not used for synchronous slave reception.
2: PIC16(L)F1455/9 only.
DS41639A-page 284
Preliminary
PIC16(L)F1454/5/9
23.6
EUSART Operation During Sleep
The EUSART will remain active during Sleep only in the

Synchronous Slave mode. All other modes require the
system clock and therefore cannot generate the
necessary signals to run the Transmit or Receive Shift
registers during Sleep.
Synchronous Slave mode uses an externally generated
clock to run the Transmit and Receive Shift registers.
23.6.1
SYNCHRONOUS RECEIVE DURING

SLEEP
To receive during Sleep, all the following conditions

must be met before entering Sleep mode:
RCSTA and TXSTA Control registers must be
configured for Synchronous Slave Reception (see
Section 23.5.2.4 Synchronous Slave
Reception Set-up:).
If interrupts are desired, set the RCIE bit of the
INTCON register.
The RCIF interrupt flag must be cleared by reading RCREG to unload any pending characters in
the receive buffer.
Upon entering Sleep mode, the device will be ready to
accept data and clocks on the RX/DT and TX/CK pins,
respectively. When the data word has been completely
clocked in by the external device, the RCIF interrupt
flag bit of the PIR1 register will be set. Thereby, waking
the processor from Sleep.
Upon waking from Sleep, the instruction following the
SLEEP instruction will be executed. If the Global Interrupt Enable (GIE) bit of the INTCON register is also set,
then the Interrupt Service Routine at address 004h will
be called.
23.6.2
SYNCHRONOUS TRANSMIT
DURING SLEEP
To transmit during Sleep, all the following conditions

must be met before entering Sleep mode:
RCSTA and TXSTA Control registers must be
configured for synchronous slave transmission
(see Section 23.5.2.2 Synchronous Slave
Transmission Set-up:).
The TXIF interrupt flag must be cleared by writing
the output data to the TXREG, thereby filling the
TSR and transmit buffer.
PIE1 register and the PEIE bit of the INTCON
register.
Interrupt enable bits TXIE of the PIE1 register and
PEIE of the INTCON register must set.
Upon entering Sleep mode, the device will be ready to
accept clocks on the TX/CK pin and transmit data on
the RX/DT pin. When the data word in the TSR has
been completely clocked out by the external device, the
pending byte in the TXREG will transfer to the TSR and
the TXIF flag will be set, which wakes the processor
from Sleep. At this point, the TXREG is available to
accept another character for transmission, which will
clear the TXIF flag.
Upon waking from Sleep, the instruction following the
SLEEP instruction will be executed. If the Global
Interrupt Enable (GIE) bit is also set, then the Interrupt
Service Routine at address 0004h will be called.
23.6.3
ALTERNATE PIN LOCATIONS
This module incorporates I/O pins that can be moved to

other locations with the use of the alternate pin function
register, APFCON. To determine which pins can be
moved and what their default locations are upon a
Reset, see Section 12.1 Alternate Pin Function for
more information.
Preliminary
DS41639A-page 285
PIC16(L)F1454/5/9
NOTES:
DS41639A-page 286
Preliminary
PIC16(L)F1454/5/9
24.0
PULSE WIDTH MODULATION

(PWM) MODULE
For a step-by-step procedure on how to set up this

module for PWM operation, refer to Section 24.1.9
Setup for PWM Operation using PWMx Pins.
The PWM module generates a Pulse-Width Modulated

signal determined by the duty cycle, period, and
resolution that are configured by the following registers:
FIGURE 24-1:
PWM OUTPUT
Period
PR2
T2CON
PWMxDCH
PWMxDCL
PWMxCON
Pulse Width
TMR2 = 0
TMR2 = PR2
TMR2 =
PWMxDCH<7:0>:PWMxDCL<7:6>
Figure 24-1 shows a typical waveform of the PWM

signal. Figure 24-2 shows a simplified block diagram of
PWM operation.
FIGURE 24-2:
SIMPLIFIED PWM BLOCK DIAGRAM

Duty Cycle registers
PWMxDCL<7:6>
PWMxDCH
PWMxOUT
to other peripherals: CWG
Latched
(Not visible to user)
Output Enable (PWMxOE)

TRIS Control
Comparator
0
PWMx
TMR2 Module
TMR2
Output Polarity (PWMxPOL)
(1)
Comparator
PR2
Note 1:
Clear Timer,
PWMx pin and
latch Duty Cycle
8-bit timer is concatenated with the two Least Significant bits of 1/FOSC adjusted by
the Timer2 prescaler to create a 10-bit time base.
Preliminary
DS41639A-page 287
PIC16(L)F1454/5/9
24.1
PWMx Pin Configuration
All PWM outputs are multiplexed with the PORT data

latch. The user must configure the pins as outputs by
clearing the associated TRIS bits.
Note:
24.1.1
Clearing the PWMxOE bit will relinquish

control of the PWMx pin.
FUNDAMENTAL OPERATION
The PWM module produces a 10-bit resolution output.

Timer2 and PR2 set the period of the PWM. The
PWMxDCL and PWMxDCH registers configure the
duty cycle. The period is common to all PWM modules,
whereas the duty cycle is independently controlled.
Note:
The Timer2 postscaler is not used in the

determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
All PWM outputs associated with Timer2 are set when

TMR2 is cleared. Each PWMx is cleared when TMR2
is equal to the value specified in the corresponding
PWMxDCH (8 MSb) and PWMxDCL<7:6> (2 LSb) registers. When the value is greater than or equal to PR2,
the PWM output is never cleared (100% duty cycle).
Note:
24.1.2
When TMR2 is equal to PR2, the following three events

occur on the next increment cycle:
TMR2 is cleared
The PWM output is active. (Exception: When the
PWM duty cycle = 0%, the PWM output will
remain inactive.)
The PWMxDCH and PWMxDCL register values
are latched into the buffers.
Note:
24.1.4
Equation 24-2 is used to calculate the PWM pulse

width. Equation 24-3 is used to calculate the PWM duty
cycle ratio.
EQUATION 24-2:
T OS C (TMR2 Prescale Value)
Note: TOSC = 1/FOSC
EQUATION 24-3:
PWM OUTPUT POLARITY
PWM PERIOD
The PWM period is specified by the PR2 register of

Timer2. The PWM period can be calculated using the
formula of Equation 24-1.
PULSE WIDTH
Pulse Width = PWMxDCH:PWMxDCL<7:6>
The PWMxDCH and PWMxDCL registers

are double buffered. The buffers are
updated when Timer2 matches PR2. Care
should be taken to update both registers
before the timer match occurs.
EQUATION 24-1:
PWM DUTY CYCLE
The PWM duty cycle is specified by writing a 10-bit

value to the PWMxDCH and PWMxDCL register pair.
The PWMxDCH register contains the eight MSbs and
the PWMxDCL<7:6>, the two LSbs. The PWMxDCH
and PWMxDCL registers can be written to at any time.
DUTY CYCLE RATIO
PWMxDCH:PWMxDCL<7:6>
Duty Cycle Ratio = ----------------------------------------------------------------------------------4 PR2 + 1
The output polarity is inverted by setting the PWMxPOL

bit of the PWMxCON register.
24.1.3
The Timer2 postscaler has no effect on

the PWM operation.
The 8-bit timer TMR2 register is concatenated with the

two Least Significant bits of 1/FOSC, adjusted by the
Timer2 prescaler to create the 10-bit time base. The
system clock is used if the Timer2 prescaler is set to
1:1.
PWM PERIOD
PWM Period = PR2 + 1 4 T OSC

(TMR2 Prescale Value)
Note:
TOSC = 1/FOSC
DS41639A-page 288
Preliminary
PIC16(L)F1454/5/9
24.1.5
PWM RESOLUTION
The resolution determines the number of available duty

cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an
8-bit resolution will result in 256 discrete duty cycles.
The maximum PWM resolution is 10 bits when PR2 is
255. The resolution is a function of the PR2 register
value as shown by Equation 24-4.
EQUATION 24-4:
PWM RESOLUTION
log 4 PR2 + 1
Resolution = ------------------------------------------ bits
log 2
Note:
If the pulse width value is greater than the

period, the assigned PWM pin(s) will
remain unchanged.
TABLE 24-1:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
PWM Frequency
0.31 kHz
Timer Prescale (1, 4, 64)

PR2 Value
78.12 kHz
156.3 kHz
208.3 kHz
64
0xFF
0xFF
0x3F
0x1F
0x17
10
10
10
6.6
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)
PWM Frequency
0.31 kHz
Timer Prescale (1, 4, 64)

PR2 Value
4.90 kHz
19.61 kHz
76.92 kHz
153.85 kHz
200.0 kHz
64
0x65
0x65
0x65
0x19
0x0C
0x09
Maximum Resolution (bits)
24.1.6
19.53 kHz
0xFF
Maximum Resolution (bits)
TABLE 24-2:
4.88 kHz
OPERATION IN SLEEP MODE
In Sleep mode, the TMR2 register will not increment

and the state of the module will not change. If the
PWMx pin is driving a value, it will continue to drive that
value. When the device wakes up, TMR2 will continue
from its previous state.
24.1.7
CHANGES IN SYSTEM CLOCK

FREQUENCY
The PWM frequency is derived from the system clock

frequency (FOSC). Any changes in the system clock frequency will result in changes to the PWM frequency.
Refer to Section 6.0 Active Clock Tuning (ACT)
Module for additional details.
24.1.8
EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
PWM registers to their Reset states.
Preliminary
DS41639A-page 289
PIC16(L)F1454/5/9
24.1.9
SETUP FOR PWM OPERATION

USING PWMx PINS
The following steps should be taken when configuring

the module for PWM operation using the PWMx pins:
1.
2.
3.
4.
5.
6.
7.
8.
Disable the PWMx pin output driver(s) by setting

the associated TRIS bit(s).
Clear the PWMxCON register.
Load the PR2 register with the PWM period
value.
Clear the PWMxDCH register and bits <7:6> of
the PWMxDCL register.
Configure and start Timer2:
Clear the TMR2IF interrupt flag bit of the
PIR1 register. See note below.
Configure the T2CKPS bits of the T2CON
register with the Timer2 prescale value.
Enable Timer2 by setting the TMR2ON bit of
the T2CON register.
Enable PWM output pin and wait until Timer2
overflows; TMR2IF bit of the PIR1 register is set.
See note below.
Enable the PWMx pin output driver(s) by clearing the associated TRIS bit(s) and setting the
PWMxOE bit of the PWMxCON register.
Configure the PWM module by loading the
PWMxCON register with the appropriate values.
Note 1: In order to send a complete duty cycle
and period on the first PWM output, the
above steps must be followed in the order
given. If it is not critical to start with a
complete PWM signal, then replace Step
4 with Step 8.
2: For operation with other peripherals only,
disable PWMx pin outputs.
DS41639A-page 290
Preliminary
PIC16(L)F1454/5/9
24.2
Register Definitions: PWM Control
REGISTER 24-1:
PWMxCON: PWM CONTROL REGISTER
R/W-0/0
R/W-0/0
R-0/0
R/W-0/0
U-0
U-0
U-0
U-0
PWMxEN
PWMxOE
PWMxOUT
PWMxPOL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
PWMxEN: PWM Module Enable bit

1 = PWM module is enabled
0 = PWM module is disabled
bit 6
PWMxOE: PWM Module Output Enable bit

1 = Output to PWMx pin is enabled
0 = Output to PWMx pin is disabled
bit 5
PWMxOUT: PWM Module Output Value bit
bit 4
PWMxPOL: PWMx Output Polarity Select bit

1 = PWM output is active low
0 = PWM output is active high
bit 3-0
Preliminary
DS41639A-page 291
PIC16(L)F1454/5/9
REGISTER 24-2:
R/W-x/u
PWMxDCH: PWM DUTY CYCLE HIGH BITS
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
PWMxDCH<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
PWMxDCH<7:0>: PWM Duty Cycle Most Significant bits

These bits are the MSbs of the PWM duty cycle. The two LSbs are found in the PWMxDCL register.
REGISTER 24-3:
R/W-x/u
PWMxDCL: PWM DUTY CYCLE LOW BITS
R/W-x/u
PWMxDCL<7:6>
U-0
U-0
U-0
U-0
U-0
U-0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
PWMxDCL<7:6>: PWM Duty Cycle Least Significant bits

These bits are the LSbs of the PWM duty cycle. The MSbs are found in the PWMxDCH register.
bit 5-0
TABLE 24-3:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PWM

Bit 7
Bit 6
Bit 5
PWM1EN
PWM1OE
PWM1OUT
PR2
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Timer2 module Period Register
PWM1CON
PWM1DCH
PWM1DCL
PWM2CON
PWM1POL
199*
PWM1DCH<7:0>
PWM1DCL<7:6>
PWM2EN
PWM2OE
PWM2POL
PWM2DCH<7:0>
PWM2DCL
PWM2DCL<7:6>
T2CON
T2OUTPS<3:0>
TMR2
291
292
PWM2OUT
PWM2DCH
Register
on Page
292
292
292
TMR2ON
T2CKPS<1:0>
Timer2 module Register
292
201
199*
TRISA
TRISA5
TRISA4
(1)
(1)
(1)
132
TRISC
TRISC7(2)
TRISC6(2)
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
140
Legend:
Note
*
1:
2:
- = Unimplemented locations, read as 0, u = unchanged, x = unknown. Shaded cells are not used by the PWM.
PIC16(L)F1459 only.
DS41639A-page 292
Preliminary
PIC16(L)F1454/5/9
25.0
COMPLEMENTARY WAVEFORM
GENERATOR (CWG) MODULE
The Complementary Waveform Generator (CWG) produces a complementary waveform with dead-band
delay from a selection of input sources.
The CWG module has the following features:
Selectable dead-band clock source control

Selectable input sources
Output enable control
Output polarity control
Dead-band control with independent 6-bit rising
and falling edge dead-band counters
Auto-shutdown control with:
- Selectable shutdown sources
- Auto-restart enable
- Auto-shutdown pin override control
Preliminary
DS41639A-page 293
FIGURE 25-1:
SIMPLIFIED CWG BLOCK DIAGRAM
GxASDLA
GxCS
00
FOSC
10
11
cwg_clock
GxASDLA = 01
GxOEA
CWGxDBR
HFINTOSC
GxIS
Preliminary
async_C1OUT
async_C2OUT
PWM1OUT
PWM2OUT
EN
R
S
TRISx
GxPOLA
Input Source
CWGxDBF
6
EN
GxOEB
R
TRISx
0
GxPOLB
CWG1FLT (INT pin)

GxASDFLT
async_C2OUT
GxASDC2
DS41639A-page 294
GxASE Data Bit

WRITE
x = CWG module number
GxASE
Auto-Shutdown
Source
GxARSEN
set dominate
shutdown
10
11
GxASDLB
CWGxB
PIC16(L)F1454/5/9
GxASDLB = 01
00
async_C1OUT
GxASDC1
CWGxA
PIC16(L)F1454/5/9
FIGURE 25-2:
TYPICAL CWG OPERATION WITH PWM1 (NO AUTO-SHUTDOWN)
cwg_clock
PWM1
CWGxA
Rising Edge
Deadband
Rising Edge Deadband

Falling Edge Deadband
Rising Edge D
Falling Edge Deadband
CWGxB
Preliminary
DS41639A-page 295
PIC16(L)F1454/5/9
25.1
Fundamental Operation
25.4.2
The CWG generates a two output complementary

waveform from one of four selectable input sources.
The off-to-on transition of each output can be delayed
from the on-to-off transition of the other output thereby
creating an immediate time delay where neither output
is driven. This is referred to as dead time and is covered
in Section 25.5 Dead-Band Control. A typical
operating waveform, with dead band, generated from a
single input signal is shown in Figure 25-2.
It may be necessary to guard against the possibility of
circuit faults or a feedback event arriving too late or not
at all. In this case, the active drive must be terminated
before the Fault condition causes damage. This is
referred to as auto-shutdown and is covered in
Section 25.9 Auto-Shutdown Control.
POLARITY CONTROL
The polarity of each CWG output can be selected

independently. When the output polarity bit is set, the
corresponding output is active high. Clearing the output
polarity bit configures the corresponding output as
active low. However, polarity does not affect the
override levels. Output polarity is selected with the
GxPOLA and GxPOLB bits of the CWGxCON0 register.
25.5
Dead-Band Control
Dead-band control provides for non-overlapping output

signals to prevent shoot-through current in power
switches. The CWG contains two 6-bit dead-band
counters. One dead-band counter is used for the rising
edge of the input source control. The other is used for
the falling edge of the input source control.
The CWG module allows the following clock sources

to be selected:
Dead band is timed by counting CWG clock periods

from zero up to the value in the rising or falling deadband counter registers. See CWGxDBR and
CWGxDBF registers (Register 25-4 and Register 25-5,
respectively).
Fosc (system clock)

HFINTOSC (16 MHz only)
25.6
25.2
Clock Source
The clock sources are selected using the G1CS0 bit of

the CWGxCON0 register (Register 25-1).
25.3
Selectable Input Sources
The CWG can generate the complementary waveform

for the following input sources:
async_C1OUT
async_C2OUT
PWM1OUT
PWM2OUT
The input sources are selected using the GxIS<1:0>

bits in the CWGxCON1 register (Register 25-2).
25.4
Output Control
Immediately after the CWG module is enabled, the

complementary drive is configured with both CWGxA
and CWGxB drives cleared.
25.4.1
Rising Edge Dead Band
The rising edge dead-band delays the turn-on of the

CWGxA output from when the CWGxB output is turned
off. The rising edge dead-band time starts when the
rising edge of the input source signal goes true. When
this happens, the CWGxB output is immediately turned
off and the rising edge dead-band delay time starts.
When the rising edge dead-band delay time is reached,
the CWGxA output is turned on.
The CWGxDBR register sets the duration of the deadband interval on the rising edge of the input source
signal. This duration is from 0 to 64 counts of dead band.
Dead band is always counted off the edge on the input
source signal. A count of 0 (zero), indicates that no
dead band is present.
If the input source signal is not present long enough for
the count to complete, no output will be seen on the
respective output.
OUTPUT ENABLES
Each CWG output pin has individual output enable

control. Output enables are selected with the GxOEA
and GxOEB bits of the CWGxCON0 register. When an
output enable control is cleared, the module asserts no
control over the pin. When an output enable is set, the
override value or active PWM waveform is applied to
the pin per the port priority selection. The output pin
enables are dependent on the module enable bit,
GxEN. When GxEN is cleared, CWG output enables
and CWG drive levels have no effect.
DS41639A-page 296
Preliminary
PIC16(L)F1454/5/9
25.7
Falling Edge Dead Band
The falling edge dead band delays the turn-on of the

CWGxB output from when the CWGxA output is turned
off. The falling edge dead-band time starts when the
falling edge of the input source goes true. When this
happens, the CWGxA output is immediately turned off
and the falling edge dead-band delay time starts. When
the falling edge dead-band delay time is reached, the
CWGxB output is turned on.
The CWGxDBF register sets the duration of the deadband interval on the falling edge of the input source signal. This duration is from 0 to 64 counts of dead band.
Dead band is always counted off the edge on the input
source signal. A count of 0 (zero), indicates that no
dead band is present.
If the input source signal is not present long enough for
the count to complete, no output will be seen on the
respective output.
Refer to Figure 25-5 and Figure 25-6 for examples.
25.8
Dead-Band Uncertainty
When the rising and falling edges of the input source

trigger the dead-band counters, the input may be asynchronous. This will create some uncertainty in the deadband time delay. The maximum uncertainty is equal to
one CWG clock period. Refer to Equation 25-1 for more
detail.
Preliminary
DS41639A-page 297
FIGURE 25-3:
DEAD-BAND OPERATION, CWGxDBR = 01H, CWGxDBF = 02H
cwg_clock
Input Source
CWGxA
CWGxB
FIGURE 25-4:
DEAD-BAND OPERATION, CWGxDBR = 03H, CWGxDBF = 04H, SOURCE SHORTER THAN DEAD BAND
Preliminary
cwg_clock
Input Source
source shorter than dead band

CWGxB
DS41639A-page 298
PIC16(L)F1454/5/9
CWGxA
PIC16(L)F1454/5/9
EQUATION 25-1:
DEAD-BAND
UNCERTAINTY
1
TDEADBAND_UNCERTAINTY = ----------------------------Fcwg_clock
Example:
Fcwg_clock = 16 MHz
Therefore:
1
TDEADBAND_UNCERTAINTY = ----------------------------Fcwg_clock
1
= ------------------16 MHz
= 625ns
Preliminary
DS41639A-page 299
PIC16(L)F1454/5/9
25.9
Auto-Shutdown Control
25.10 Operation During Sleep
Auto-shutdown is a method to immediately override the

CWG output levels with specific overrides that allow for
the safe shutdown of the circuit. The shutdown state
can be either cleared automatically or held until cleared
by software.
25.9.1
SHUTDOWN
The shutdown state can be entered by either of the

following two methods:
Software generated
External Input
25.9.1.1
Software Generated Shutdown
Setting the GxASE bit of the CWGxCON2 register will

force the CWG into the shutdown state.
The CWG module operates independently from the

system clock and will continue to run during Sleep,
provided that the clock and input sources selected
remain active.
The HFINTOSC remains active during Sleep, provided
that the CWG module is enabled, the input source is
active, and the HFINTOSC is selected as the clock
source, regardless of the system clock source selected.
In other words, if the HFINTOSC is simultaneously
selected as the system clock and the CWG clock
source, when the CWG is enabled and the input source
is active, the CPU will go idle during Sleep, but the CWG
will continue to operate and the HFINTOSC will remain
active. This will have a direct effect on the Sleep mode
current.
When auto-restart is disabled, the shutdown state will

persist as long as the GxASE bit is set.
When auto-restart is enabled, the GxASE bit will clear
automatically and resume operation on the next rising
edge event. See Figure 25-6.
25.9.1.2
External Input Source
External shutdown inputs provide the fastest way to

safely suspend CWG operation in the event of a Fault
condition. When any of the selected shutdown inputs
go active, the CWG outputs will immediately go to the
selected override levels without a software delay. Any
combination of two input sources can be selected to
cause a shutdown condition. The sources are:
async_C1OUT
async_C2OUT
CWG1FLT
Shutdown inputs are selected using the GxASDS0 and
GxASDS1 bits of the CWGxCON2 register
(Register 25-3).
Note:
Shutdown inputs are level sensitive, not

edge sensitive. The shutdown state cannot be cleared, except by disabling
auto-shutdown, as long as the shutdown
input level persists.
DS41639A-page 300
Preliminary
PIC16(L)F1454/5/9
25.11 Configuring the CWG
25.11.1
The following steps illustrate how to properly configure

the CWG to ensure a synchronous start:
The levels driven to the output pins, while the shutdown

input is true, are controlled by the GxASDLA and
GxASDLB bits of the CWGxCON1 register
(Register 25-2). GxASDLA controls the CWG1A
override level and GxASDLB controls the CWG1B
override level. The control bit logic level corresponds to
the output logic drive level while in the shutdown state.
The polarity control does not apply to the override level.
1.
2.
3.
4.
5.
6.
7.
8.
9.
Ensure that the TRIS control bits corresponding

to CWGxA and CWGxB are set so that both are
configured as inputs.
Clear the GxEN bit, if not already cleared.
Set desired dead-band times with the CWGxDBR
and CWGxDBF registers.
Setup the following controls in the CWGxCON2
auto-shutdown register:
Select desired shutdown source.
Select both output overrides to the desired
levels (this is necessary even if not using
auto-shutdown because start-up will be from
a shutdown state).
Set the GxASE bit and clear the GxARSEN
bit.
Select the desired input source using the
CWGxCON1 register.
Configure the following controls in the
CWGxCON0 register:
Select desired clock source.
Select the desired output polarities.
Set the output enables for the outputs to be
used.
Set the GxEN bit.
Clear TRIS control bits corresponding to
CWGxA and CWGxB to be used to configure
those pins as outputs.
If auto-restart is to be used, set the GxARSEN
bit and the GxASE bit will be cleared automatically. Otherwise, clear the GxASE bit to start the
CWG.
25.11.2
PIN OVERRIDE LEVELS
AUTO-SHUTDOWN RESTART
After an auto-shutdown event has occurred, there are

two ways to have resume operation:
Software controlled
Auto-restart
The restart method is selected with the GxARSEN bit
of the CWGxCON2 register. Waveforms of software
controlled and automatic restarts are shown in
Figure 25-5 and Figure 25-6.
25.11.2.1
Software Controlled Restart
When the GxARSEN bit of the CWGxCON2 register is

cleared, the CWG must be restarted after an auto-shutdown event by software.
Clearing the shutdown state requires all selected shutdown inputs to be low; otherwise, the GxASE bit will
remain set. The overrides will remain in effect until the
first rising edge event after the GxASE bit is cleared.
The CWG will then resume operation.
25.11.2.2
Auto-Restart
When the GxARSEN bit of the CWGxCON2 register is

set, the CWG will restart from the auto-shutdown state
automatically.
The GxASE bit will clear automatically when all shutdown sources go low. The overrides will remain in
effect until the first rising edge event after the GxASE
bit is cleared. The CWG will then resume operation.
Preliminary
DS41639A-page 301
FIGURE 25-5:
SHUTDOWN FUNCTIONALITY, AUTO-RESTART DISABLED (GxARSEN = 0,GxASDLA = 01, GxASDLB = 01)

Shutdown Event Ceases
GxASE Cleared by Software
CWG Input
Source
Shutdown Source
GxASE
CWG1A
Tri-State (No Pulse)
CWG1B

No Shutdown
Preliminary
Output Resumes
Shutdown
FIGURE 25-6:
SHUTDOWN FUNCTIONALITY, AUTO-RESTART ENABLED (GxARSEN = 1,GxASDLA = 01, GxASDLB = 01)

Shutdown Event Ceases
GxASE auto-cleared by hardware
Shutdown Source
GxASE
DS41639A-page 302
CWG1A
CWG1B

No Shutdown
Shutdown
Output Resumes
PIC16(L)F1454/5/9
CWG Input
Source
PIC16(L)F1454/5/9
25.12 Register Definitions: CWG Control
REGISTER 25-1:
CWGxCON0: CWG CONTROL REGISTER 0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
U-0
R/W-0/0
GxEN
GxOEB
GxOEA
GxPOLB
GxPOLA
GxCS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
GxEN: CWGx Enable bit

1 = Module is enabled
0 = Module is disabled
bit 6
GxOEB: CWGxB Output Enable bit

1 = CWGxB is available on appropriate I/O pin
0 = CWGxB is not available on appropriate I/O pin
bit 5
GxOEA: CWGxA Output Enable bit

1 = CWGxA is available on appropriate I/O pin
0 = CWGxA is not available on appropriate I/O pin
bit 4
GxPOLB: CWGxB Output Polarity bit

1 = Output is inverted polarity
0 = Output is normal polarity
bit 3
GxPOLA: CWGxA Output Polarity bit

1 = Output is inverted polarity
0 = Output is normal polarity
bit 2-1
bit 0
GxCS0: CWGx Clock Source Select bit

1 = HFINTOSC
0 = FOSC
Preliminary
DS41639A-page 303
PIC16(L)F1454/5/9
REGISTER 25-2:
R/W-x/u
R/W-x/u
GxASDLB<1:0>
R/W-x/u
R/W-x/u
U-0
GxASDLA<1:0>
U-0
R/W-0/0
R/W-0/0
GxIS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
GxASDLB<1:0>: CWGx Shutdown State for CWGxB

When an auto-shutdown event is present (GxASE = 1):
11 = CWGxB pin is driven to 1, regardless of the setting of the GxPOLB bit
10 = CWGxB pin is driven to 0, regardless of the setting of the GxPOLB bit
01 = CWGxB pin is tri-stated
00 = CWGxB pin is driven to its inactive state after the selected dead-band interval. GxPOLB still will
control the polarity of the output
bit 5-4
GxASDLA<1:0>: CWGx Shutdown State for CWGxA

When an auto shutdown event is present (GxASE = 1):
11 = CWGxA pin is driven to 1, regardless of the setting of the GxPOLA bit
10 = CWGxA pin is driven to 0, regardless of the setting of the GxPOLA bit
01 = CWGxA pin is tri-stated
00 = CWGxA pin is driven to its inactive state after the selected dead-band interval. GxPOLA still will
control the polarity of the output
bit 3-2
bit 1-0
GxIS<2:0>: CWGx Input Source Select bits

11 = PWM2OUT
10 = PWM1OUT
01 = async_C1OUT
00 = async_C2OUT
DS41639A-page 304
Preliminary
PIC16(L)F1454/5/9
REGISTER 25-3:
R/W-0/0
R/W-0/0
GxASE
GxARSEN
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
GxASDC2
GxASDC1
GxASDFLT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
GxASE: Auto-Shutdown Event Status bit

1 = An auto-shutdown event has occurred
0 = No auto-shutdown event has occurred
bit 6
GxARSEN: Auto-Restart Enable bit

1 = Auto-restart is enabled
0 = Auto-restart is disabled
bit 5-4
bit 3
GxASDC2: CWG Auto-Shutdown on Comparator 2 Enable

1 = Shutdown when Comparator 2 output is high
0 = Comparator 2 output has no effect on shutdown
bit 2
GxASDC1: CWG Auto-Shutdown on Comparator 1 Enable

1 = Shutdown when Comparator 1 output is high
0 = Comparator 1 output has no effect on shutdown
bit 1
GxASDFLT: CWG Auto-Shutdown on FLT Enable bit

1 = Shutdown when CWG1FLT input is low
0 = CWG1FLT input has no effect on shutdown
bit 0
Preliminary
DS41639A-page 305
PIC16(L)F1454/5/9
REGISTER 25-4:
U-0
CWGxDBR: COMPLEMENTARY WAVEFORM GENERATOR (CWGx) RISING

DEAD-BAND COUNT REGISTER
U-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
CWGxDBR<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-0
CWGxDBR<5:0>: Complementary Waveform Generator (CWGx) Rising Counts bits

11 1111 = 63-64 counts of dead band

00 0000 = 0 counts of dead band
REGISTER 25-5:
CWGxDBF: COMPLEMENTARY WAVEFORM GENERATOR (CWGx) FALLING

DEAD-BAND COUNT REGISTER
U-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
CWGxDBF<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-0
CWGxDBF<5:0>: Complementary Waveform Generator (CWGx) Falling Counts bits


00 0000 = 0 counts of dead band. Dead-band generation is bypassed
DS41639A-page 306
Preliminary
PIC16(L)F1454/5/9
TABLE 25-1:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH CWG(2)

Bit 7
ANSELA
CWGxCON0
CWGxCON1
CWGxCON2
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Registe
r on
Page
ANSA4
133
GxEN
GxOEB
GxOEA
GxPOLB
GxPOLA
G1CS0
303
GxASDC2
GxASDC1
GxASDLB<1:0>
GxASE
GxARSEN
GxASDLA<1:0>
GxIS<1:0>
GxASDFLT
304
305
CWGxDBF<5:0>
306
CWGxDBR<5:0>
306
LATA
LATA5
LATA4
133
TRISA
TRISA5
TRISA4
(1)
(1)
(1)
132
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
140
CWGxDBF
CWGxDBR
TRISC
Legend:
Note 1:
2:
TRISC7(1) TRISC6(1)
x = unknown, u = unchanged, = unimplemented locations read as 0. Shaded cells are not used by CWG.
Preliminary
DS41639A-page 307
PIC16(L)F1454/5/9
NOTES:
DS41639A-page 308
Preliminary
PIC16(L)F1454/5/9
26.0
UNIVERSAL SERIAL BUS

(USB)
26.1
This device contains a full-speed and low-speed

compatible USB Serial Interface Engine (SIE) that
allows fast communication between any USB host and
the microcontroller. The SIE can be interfaced directly
to the USB by utilizing the internal transceiver. Some
special hardware features have been included to
improve performance. Dual access port memory in the
device's data memory space (USB RAM) has been
supplied to share direct memory access between the
microcontroller core and the SIE. Buffer descriptors are
also provided, allowing users to freely program
endpoint memory usage within the USB RAM space.
Figure 26-1 presents a general overview of the USB
peripheral and its features.
This section describes the details of the USB

peripheral. Because of the very specific nature of the
module, knowledge of USB is expected. Some highlevel USB information is provided in Section 26.1
Overview only for application design reference.
Designers are encouraged to refer to the official
specification published by the USB Implementers
Forum (USB-IF) for the latest information. USB
Specification Revision 2.0 is the most current
specification at the time of publication of this document.
FIGURE 26-1:
Overview
USB PERIPHERAL AND OPTIONS
USB PIC Microcontroller

3.3V LDO Regulator
(1)
VUSB3V3
(2)
Vcap
VDD
External 3.3V
Supply
P
Internal Pull-ups
FSEN
UPUEN
P
Transceiver
USB Clock from the

Oscillator Module
D+
FS
EN
USB
D-
USB Control and

Configuration
(3)
USB
SIE
512 byte
USB RAM
Note 1: Possible optional setup for LF parts only. F parts should use internal LDO to power VUSB3V3.
2: On F devices the regulator is powered by Vdd. On LF devices the regulator is internally bypassed to Vdd.
3: 496 bytes accessible in both linear and banked data space. 16 bytes accessible in access data space only.
Preliminary
DS41639A-page 309
PIC16(L)F1454/5/9
26.2
USB Status and Control
The operation of the USB module is configured and

managed through three control registers. In addition, a
total of 14 registers are used to manage the actual USB
transactions. The registers are:
USB Control register (UCON)

USB Configuration register (UCFG)
USB Transfer Status register (USTAT)
USB Device Address register (UADDR)
Frame Number registers (UFRMH:UFRML)
Endpoint Enable registers 0 through 7 (UEPn)
26.2.1
USB CONTROL (UCON) REGISTER
The USB Control register (Register 26-1) contains bits

needed to control the module behavior during
transfers. The register contains bits that control the
following:
Main USB Peripheral Enable

Ping-Pong Buffer Pointer Reset
Control of the Suspend mode
Packet Transfer Disable
The SE0 bit of the UCON register is used to indicate the

occurrence of a single-ended zero on the bus. When
the USB module is enabled, this bit should be
monitored to determine whether the differential data
lines have come out of a single-ended zero condition.
This helps to differentiate the initial power-up state from
the USB Reset signal.
The USBEN bit of the UCON register is used to enable
and disable the module. Setting this bit activates the
module and resets all of the PPBI bits in the Buffer
Descriptor Table to 0. If enabled, this bit will also
activate the USB internal pull-up resistors. Thus, this bit
can be used as a soft attach/detach to the USB. The
USB module needs to be supplied with an active clock
source before the USBEN bit can be set. Also, the USB
module needs to be fully preconfigured prior to
enabling the USB module.
Note:
If the PLL is being used, wait until the

PLLRDY bit is set in the OSCSTAT register
before attempting to set the USBEN bit.
The PPBRST bit of the UCON register controls the

Reset status when Double-Buffering mode (ping-pong
buffering) is used. When the PPBRST bit is set, all
Ping-Pong Buffer Pointers are set to the Even buffers.
The PPBRST bit must be cleared by firmware. This bit
is ignored in buffering modes not using ping-pong
buffering.
The PKTDIS bit of the UCON register is a flag indicating

that the SIE has disabled packet transmission and
reception. This bit is set by the SIE when a SETUP token
is received to allow setup processing. This bit cannot be
set by the microcontroller, only cleared. Clearing the bit
to 0 allows the SIE to continue transmission and/or
reception. Any pending events within the Buffer
Descriptor Table will still be available, indicated within
the USTAT register's FIFO buffer ENDP bits.
The RESUME bit of the UCON register configures the
peripheral to perform a remote wake-up by executing
Resume signaling. To generate a valid remote wake-up,
firmware must set the RESUME bit for 10 ms and then
automatically clear the bit. For more information on
resume signaling, see the USB 2.0 specification.
The SUSPND bit of the UCON register places the
module and supporting circuitry in a Low-Power mode.
The input clock to the SIE is also disabled. This bit must
be set by the firmware in response to an IDLEIF
interrupt. It should be reset by the microcontroller
firmware after an ACTVIF interrupt is observed. When
this bit is active, the device remains attached to the bus
but the transceiver outputs remain Idle. The voltage on
the VUSB3V3 pin may vary depending on the value of
this bit. Setting this bit before a IDLEIF request will
result in unpredictable bus behavior.
Note:
26.2.2
USB CONFIGURATION (UCFG)

REGISTER
The UCFG register (Register 26-2) is used in

configuring system level behavior of the USB module.
All internal and external hardware should be configured
prior to attempting communications. The UCFG
register is used for the following USB functions:
Bus Speed (Full/Low Speed)
On-Chip Pull-up Resistor Enable
Ping-Pong Buffer Usage
The UTEYE bit of the UCFG register enables the eye
pattern generation. This bit aids in module testing,
debugging and USB certification processes. Refer to
26.2.2.4 Eye Pattern Test Enable for more detail.
Note:
DS41639A-page 310
While in Suspend mode, a typical buspowered USB device is limited to the

suspend current discussed in the USB 2.0
specification Chapter 7.2.3. This is the
complete current, which may be drawn by
the microcontroller and its supporting
circuitry. Care should be taken to assure
minimum current draw when the device
enters Suspend mode.
Preliminary
The USB speed, transceiver and pull-up

should only be configured during the module setup phase. It is not recommended to
switch these settings while the module is
enabled.
PIC16(L)F1454/5/9
26.2.2.1
Internal Transceiver
26.2.2.3
Ping-Pong Buffer Configuration
The USB peripheral has a full-speed and low-speed

USB 2.0 capable transceiver internally built-in and
connected to the SIE. The internal transceiver is
enabled when the USBEN bit of the USBCON register
is set. Full-speed operation is selected by setting the
FSEN bit of the UCFG register.
The usage of ping-pong buffers is configured using the

PPB bits of the UCFG register. Refer to Section 26.4.4
Ping-Pong Buffering for a complete explanation of
the ping-pong buffers.
The on-chip USB pull-up resistors are controlled by the

UPUEN bit of the USFG register. The pull-up resistors
can only be active when the USBEN bit of the USBCON
register is set and the module is configured for use.
An automatic eye pattern test can be generated by setting

the UTEYE bit of the USFG register. The eye pattern
output is dependent upon the USB modules settings,
which must be configured prior to use. The module must
be enabled for eye pattern output to function.
The internal USB transceiver is powered from the

VUSB3V3 pin. In order to meet USB signaling level
specifications, VUSB3V3 must be supplied with a voltage
source between 3.0V and 3.6V. The best electrical
signal quality is obtained when a 3.3V supply is used
and locally bypassed with a high quality ceramic
capacitor. The capacitor should be placed as close as
possible to the VUSB3V3 and VSS pins.
26.2.2.4
Once UTEYE is set, the module emulates a switch from

a receive to transmit state and will start transmitting a
J-K-J-K bit sequence (K-J-K-J for full speed). The
sequence will be repeated indefinitely while the Eye
Pattern Test mode is enabled.
Note:
The VUSB3V3 voltage is supplied.
Note:
The D+ and D- signal lines can be routed directly to

their respective pins on the USB connector or cable (for
hard-wired applications). No additional resistors,
capacitors, or magnetic components are required as
the D+ and D- drivers have controlled slew rate and
output impedance intended to match with the
characteristic impedance of the USB cable. See the
USB specifications for the impedance matching
requirements.
26.2.2.2
Eye Pattern Test Enable
The UTEYE bit should never be set while

the module is connected to an actual USB
system.
This test mode is intended for board verification to aid

with USB certification tests. It is intended to show a
system developer the noise integrity of the USB signals
which can be affected by board traces, impedance
mismatches and proximity to other system components.
It does not properly test the transition from a receive to
a transmit state. Although the eye pattern is not meant
to replace the more complex USB certification test, it
should aid during first order system debugging.
Internal Pull-Up Resistors
The PIC devices have built-in pull-up resistors

designed to meet the requirements for low-speed and
full-speed USB. The UPUEN bit of the UCFG register
enables the internal pull-ups.
Note:
The official USB specifications require the

that USB devices must never source any
current onto the VBUS line of the USB
cable. Additionally, USB devices must
never source any current on the D+/Ddata lines when the VBUS is below the
required voltage. In order to meet this
requirement, applications which are not
purely bus powered should monitor the
VBUS line and avoid turning on the USB
module and D+/D- internal pull-up resistors until the VBUS meets requirements.
VBUS can be connected to and monitored
by any 5V tolerant I/O pin for this purpose.
Refer to USB Specification 2.0, 7.2.1 for
information.
Preliminary
DS41639A-page 311
PIC16(L)F1454/5/9
26.2.3
USB STATUS (USTAT) REGISTER
The USB Status register (Register 26-3) reports the

transaction status within the SIE. When the SIE issues
a USB transaction complete interrupt (TRNIF bit),
USTAT should be read to determine the status of the
transfer. USTAT contains the transfer endpoint number,
direction and Ping-Pong Buffer Pointer value (if used).
Note:
The data in the USB Status register is

valid two SIE clocks after the TRNIF bit is
asserted.
In low-speed operation with the system
clock operating at 48 MHz, a delay may
be required between receiving the transaction complete interrupt and processing
the data in the USTAT register.
The USTAT register is actually a read window into a

four-byte status FIFO, maintained by the SIE. It allows
the microcontroller to process one transfer while the
SIE processes additional endpoints (Figure 26-2).
When the SIE completes using a buffer for reading or
writing data, it updates the USTAT register. If another
USB transfer is performed before the TRNIF bit is
serviced, the SIE will store the status of the next
transaction into the status FIFO.
Clearing the TRNIF bit advances the FIFO. If the next
data in the FIFO holding register is valid, the SIE will
reassert the interrupt within 6 TCY of clearing the
TRNIF bit. If no additional data is present, the TRNIF bit
will remain clear; USTAT data will no longer be reliable.
Note:
If an endpoint request is received while

the USTAT FIFO is full, the SIE will
automatically issue a NAK back to the
host.
FIGURE 26-2:
USTAT FIFO
USTAT from SIE
26.2.4
Each bidirectional endpoint pair has its own

independent control register, UEPn (where 'n'
represents the endpoint number). Each register has an
identical complement of control bits (see Register 26-4).
The EPHSHK bit configures the USB handshaking for
the endpoint. Typically, this bit is always set except
when using isochronous endpoints.
The EPCONDIS bit configures the USB control
operations through the endpoint. Clearing this bit
enables SETUP transactions. The corresponding
EPINEN and EPOUTEN bits must be set to enable IN
and OUT transactions.
Note:
Data Bus
DS41639A-page 312
Clearing TRNIF
Advances FIFO
For Endpoint 0, the EPCONDIS bit should

always be cleared since the USB
specifications identify Endpoint 0 as the
default control endpoint.
The EPOUTEN bit configures USB OUT transactions

from the host. Setting this bit enables OUT
transactions. Similarly, the EPINEN bit is used to
configure the USB IN transactions from the host.
The EPSTALL bit indicates a STALL condition for the
endpoint. If a STALL is issued on a particular endpoint,
the EPSTALL bit for that endpoint pair will be set by the
SIE. This bit remains set until it is cleared through
firmware, or until the SIE is reset.
26.2.5
USB ADDRESS (UADDR) REGISTER
The USB Address register contains the unique USB

address that the peripheral will decode when active.
The UADDR register is reset to 00h when a USB Reset
is received, indicated by the USB Reset Interrupt bit
(URSTIF), or when a Reset is received from the microcontroller. The USB address must be written in
response to the USB SET_ADDRESS request.
26.2.6
4-Byte FIFO
for USTAT
USB ENDPOINT CONTROL (UEPN)

REGISTER
USB FRAME NUMBER REGISTERS

(UFRMH:UFRML)
The Frame Number registers contain the 11-bit frame

number. The low-order byte is contained in UFRML,
while the three high-order bits are contained in
UFRMH. The register pair is updated with the current
frame number whenever a SOF token is received. For
the microcontroller, these registers are read-only. The
Frame Number registers are primarily used for
isochronous transfers. The contents of the UFRMH and
UFRML registers are only valid when the 48 MHz SIE
clock is active (i.e., contents are inaccurate when
SUSPND bit of the UCON register is set).
Preliminary
PIC16(L)F1454/5/9
26.3
USB RAM
26.4
USB data moves between the microcontroller core and

the SIE through the dual-port USB RAM. This is a
special dual access memory that is mapped into a
normal data memory space (Figure 26-3).
The dual-port general purpose memory space is used
specifically for endpoint buffer control. Depending on
the type of buffering being used, all but 8 bytes of Bank
0 may also be available for use as USB buffer space.
Although USB RAM is available to the microcontroller as
data memory, the sections that are being accessed by
the SIE should not be accessed by the microcontroller.
A semaphore mechanism is used to determine the
access to a particular buffer at any given time. This is
discussed in Section 26.4.1.1 Buffer Ownership.
FIGURE 26-3:
IMPLEMENTATION OF
USB RAM IN DATA
MEMORY SPACE
2000h
512 Byte
CPU Dual-Port RAM
21FFh
2200h
512 Byte
CPU Single-Port RAM
23FFh
2400h
USB RAM Port Remap
(TSTDPEN = 1)
25FFh
2600h
Unimplemented
Read 0
29AFh
Buffer Descriptors and the Buffer

Descriptor Table
The dual-port general purpose memory space is used

specifically for endpoint buffer control in a structure
known as the Buffer Descriptor Table (BDT). This
provides a flexible method for users to construct and
control endpoint buffers of various lengths and
configuration.
The BDT is composed of Buffer Descriptors (BDs)
which are used to define and control the actual buffers
in the USB RAM space. Each BD, in turn, consists of
four registers:
BDnSTAT: BD Status register

BDnCNT: BD Byte Count register
BDnADRL: BD Address Low register
BDnADRH: BD Address High register
Note:
Wherever BDn is identified within this

document, the n represents one of the
possible BDs.
BDs always occur as a four-byte block in the sequence,

BDnSTAT:BDnCNT:BDnADRL:BDnADRH. The address
of BDnSTAT is accessible in linear data space at 2000h
+ (4n 1) with n being the buffer descriptor number.
Depending on the buffering configuration used
(Section 26.4.4 Ping-Pong Buffering), there are
multiple sets of buffer descriptors. The USB
specification mandates that every device must have
Endpoint 0 with both input and output for initial setup.
Although they can be thought of as Special Function
Registers, the Buffer Descriptor Status and Address
registers are not hardware mapped, as conventional
microcontroller SFRs are. When the endpoint
corresponding to a particular BD is not enabled, then its
registers are not used. Instead of appearing as
unimplemented addresses, however, they appear as
available RAM. Only when an endpoint is enabled by
setting the EPINEN bit of the UEPn register does the
memory at those addresses become functional as BD
registers. As with any address in the data memory
space, the BD registers have an indeterminate value on
any device Reset.
An example of a BD for a 64-byte buffer is shown in
Figure 26-4. A particular set of BD registers is only
valid if the corresponding endpoint has been enabled
using the EPINEN bit. All BD registers are available in
USB RAM. The BD for each endpoint should be set up
prior to enabling the endpoint.
Preliminary
DS41639A-page 313
PIC16(L)F1454/5/9
FIGURE 26-4:
2000h
2001h
2002h
2003h
EXAMPLE OF A BUFFER
DESCRIPTOR
BD0STAT
BD0CNT
BD0ADRL
BD0ADRH
(xxh)
(40h)
(80h)
(20h)
Size of Block
Starting
Address
The BDnSTAT byte of the BDT should always be the

last byte updated when preparing to arm an endpoint.
The SIE will clear the UOWN bit when a transaction
has completed.
2080h
Buffer
USB Data
20BFh
Note:
26.4.1
Memory regions not to scale.
BD STATUS AND CONFIGURATION
The USB Data memory ownership and the BDnSTAT

bits change functionality depending on the UOWN bit
level.
Unlike other control registers, the bit configuration for
the BDnSTAT register is context sensitive determined
by the UOWN bit. If the UOWN bit is clear, the
microcontroller has the ability to modify the BD and its
corresponding buffer. If the UOWN bit is set, the USB
SIE has the ability to modify the BD and its
corresponding buffer. The UOWN, BC9 and BC8 bit
definitions are contained within the BDnSTAT register,
regardless of the UOWN bit value.
26.4.1.1
Buffer Ownership
A simple semaphore mechanism is used to distinguish

if the CPU or USB module is allowed to update the BD
and associated buffers in memory, which is shared by
both.
The UOWN bit of the BDnSTAT register is used as a
semaphore to distinguish if the USB or CPU is allowed
to update the BD and associated buffers in memory.
Only the UOWN bit shares functionality between the
two configurations of the BDnSTAT register.
When the UOWN bit is clear, the BD entry and buffer
memory are owned by the microcontroller core. When
the UOWN bit is set, these are owned by the USB
peripheral. The BD and corresponding buffers should
only be modified by the owner. However, the
BDnSTAT register can be read by either the
microcontroller or the USB, even if they are not the
owner.
Because the buffer descriptor meanings are based
upon the source of the register update, the user must
configure the basic operation of the USB peripheral
through the BDnSTAT register prior to placing
ownership with the USB peripheral. While still owned
by the microcontroller, the byte count and buffer
location registers must also be set.
DS41639A-page 314
When the UOWN bit is set, giving ownership to the

USB peripheral, the SIE updates the BDs as
necessary, overwriting the original BD values. Thus,
values written by the user to BD are no longer
dependable. Instead, the BDnSTAT register is updated
automatically by the SIE with the token PID and
transfer count (BDnCNT).
Because no hardware mechanism exists to block

access to the memory, unexpected behavior can occur
if the microcontroller attempts to modify memory while
the SIE owns it. Also, reading the memory may
produce inaccurate data until the USB peripheral
returns ownership to the microcontroller.
26.4.1.2
BDnSTAT Register (CPU Mode)
When UOWN = 0, the microcontroller core owns the

BD and the other bits of the register become control
functions.
The Data Toggle Sync Enable (DTSEN) bit of the
BDnSTAT register controls data toggle parity checking
and, when set, enables data toggle synchronization by
the SIE. When enabled, the DTSEN checks the data
packet's parity against the value of the Data Toggle
Synchronization (DTS) bit. Packets incorrectly
synchronized are ignored and will not be written to the
USB RAM. The USB TRNIF bit will not be set.
However, the SIE will send an ACK token to the host to
acknowledge receipt. Refer to Table 26-1 for the effects
of the DTSEN bit on the SIE.
The Buffer Stall bit, BSTALL of the BDnSTAT register,
provides support for control transfers, usually one-time
stalls on Endpoint 0. It also provides support for the
SET_FEATURE/CLEAR_FEATURE
commands
specified in Chapter 9 of the USB specification.
Typically, these commands are executed by continuous
STALLs to any endpoint other than the default control
endpoint.
The BSTALL bit enables buffer stalls. Setting BSTALL
causes the SIE to return a STALL token to the host if a
received token would use the BD in that location. The
EPSTALL bit in the corresponding UEPn control
register is set and a STALL interrupt is generated when
a STALL is issued to the host. The UOWN bit remains
set and the BDs are not changed unless a SETUP
token is received. In this case, the STALL condition is
cleared and the ownership of the BD is returned to the
microcontroller core.
The BD bits of the BDnSTAT register store the two Most
Significant digits of the SIE byte count; the lower 8 digits
are stored in the corresponding BDnCNT register. See
Section 26.4.2 BD Byte Count for more information.
Preliminary
PIC16(L)F1454/5/9
TABLE 26-1:
OUT Packet
from Host
EFFECT OF DTSEN BIT ON ODD/EVEN (DATA0/DATA1) PACKET RECEPTION

BDnSTAT Settings
Device Response after Receiving Packet
DTSEN
DTS
Handshake
UOWN
TRNIF
BDnSTAT and USTAT Status
DATA0
ACK
Updated
DATA1
ACK
Not Updated
DATA0
ACK
Not Updated
DATA1
ACK
Updated
Either
ACK
Updated
Either, with error
NAK
Not Updated
Legend: x = dont care
26.4.1.3
BDnSTAT Register (SIE Mode)
When the BD and its buffer are owned by the SIE, most
of the bits in BDnSTAT take on a different meaning. The
configuration is shown in Register 26-6. Once the
UOWN bit is set, any data or control settings previously
written there by the user will be overwritten with data
from the SIE.
The BDnSTAT register is updated by the SIE with the
token Packet Identifier (PID), which is stored in the PID
bits of the BDnSTAT register. The transfer count in the
corresponding BDnCNT register is updated. Values
that overflow the 8-bit register carry over to the two
Most Significant digits of the count, BD bits of the
BDnSTAT register.
26.4.2
BD BYTE COUNT
The byte count represents the total number of bytes

that will be transmitted during an IN transfer. After an IN
transfer, the SIE will return the number of bytes sent to
the host.
For an OUT transfer, the byte count represents the
maximum number of bytes that can be received and
stored in USB RAM. After an OUT transfer, the SIE will
return the actual number of bytes received. If the
number of bytes received exceeds the corresponding
byte count, the data packet will be rejected and a NAK
handshake will be generated. When this happens, the
byte count will not be updated.
The 10-bit byte count is distributed over two registers.
The lower 8 bits of the count reside in the BDnCNT register. The upper two bits reside in the BC bits of the
BDnSTAT register. This represents a valid byte range
of 0 to 1023.
26.4.3
BD ADDRESS VALIDATION
The BD Address register pair contains the starting RAM

address location for the corresponding endpoint buffer.
No mechanism is available in hardware to validate the
BD address.
If the value of the BD address does not point to an
address in the USB RAM, or if it points to an address
within another endpoint's buffer, data is likely to be lost
or overwritten. Similarly, overlapping a receive buffer
(OUT endpoint) with a BD location in use can yield

unexpected results. When developing USB applications,
the user may want to consider the inclusion of softwarebased address validation in their code.
26.4.4
PING-PONG BUFFERING
An endpoint is defined to have a ping-pong buffer when

it has two sets of BD entries: one set for an Even
transfer and one set for an Odd transfer. This allows the
CPU to process one BD while the SIE is processing the
other BD. Double-buffering BDs in this way allows for
maximum throughput to/from the USB.
The USB module supports four modes of operation:
No ping-pong support
Ping-pong buffer support for OUT Endpoint 0 only
Ping-pong buffer support for all endpoints
Ping-pong buffer support for all other Endpoints
except Endpoint 0
The ping-pong buffer settings are configured using the

PPB bits in the UCFG register.
The USB module keeps track of the Ping-Pong Pointer
individually for each endpoint. All pointers are initially
reset to the Even BD when the module is enabled. After
the completion of a transaction (UOWN cleared by the
SIE), the pointer is toggled to the Odd BD. After the
completion of the next transaction, the pointer is
toggled back to the Even BD and so on.
The Even/Odd status of the last transaction is stored in
the PPBI bit of the USTAT register. The user can reset
all Ping-Pong Pointers to Even using the PPBRST bit.
Figure 26-5 shows the four different modes of operation and how USB RAM is filled with the BDs. BDs have
a fixed relationship to a particular endpoint depending
on the buffering configuration. The mapping of BDs to
endpoints is detailed in Table 26-2. This relationship
also means that gaps may occur in the BDT if endpoints are not enabled contiguously. This theoretically
means that the BDs for disabled endpoints could be
used as buffer space. In practice, users should avoid
using such spaces in the BDT unless a method of validating BD addresses is implemented.
Preliminary
DS41639A-page 315
PIC16(L)F1454/5/9
FIGURE 26-5:
BUFFER DESCRIPTOR TABLE MAPPING FOR BUFFERING MODES
PPB<1:0> = 00
No Ping-Pong
Buffers
2000h
PPB<1:0> = 01
Ping-Pong Buffer
on EP0 OUT
PPB<1:0> = 10
Ping-Pong
Buffers on all EPs
EP0 OUT 2000h

Descriptor
2000h
EP0 OUT
Even Descriptor
EP0 IN
Descriptor
EP0 OUT
Odd Descriptor
EP0 IN
Descriptor
EP0 OUT
Odd Descriptor
EP0 IN
Descriptor
EP1 OUT
Descriptor
EP0 IN
Even Descriptor
EP1 IN
Descriptor
EP1 OUT
Descriptor
EP1 OUT
Even Descriptor
EP0 IN
Odd Descriptor
EP1 IN
Descriptor
EP1 OUT
Odd Descriptor
EP1 OUT
Even Descriptor
EP1 IN
Even Descriptor
EP1 OUT
Odd Descriptor
EP1 IN
Odd Descriptor
Available
as
Data RAM
EP0 OUT
Descriptor
EP1 IN
Even Descriptor
EP7 IN
Descriptor
2043h
2000h
EP0 OUT
Even Descriptor
EP7 IN
Descriptor
203Fh
PPB<1:0> = 11
Ping-Pong Buffers on all
other EPs except EP0
EP1 IN
Odd Descriptor
EP7 IN
Odd Descriptor
2077h
Available
as
Data RAM
2200h
207Fh
2200h
Maximum Memory
Used: 64 bytes
Maximum BDs:
16 (BD0 to BD15)
EP7 IN
Odd Descriptor
Available
as
Data RAM
2200h
Maximum Memory
Used: 68 bytes
Maximum BDs:
17 (BD0 to BD15)
Available
as
Data RAM
2200h
Maximum Memory
Used: 128 bytes
Maximum BDs:
32 (BD0 to BD31)
Maximum Memory
Used: 120 bytes
Maximum BDs:
30 (BD0 to BD14
Note: Memory area not shown to scale.
TABLE 26-2:
ASSIGNMENT OF BUFFER DESCRIPTORS FOR THE DIFFERENT

BUFFERING MODES
BDs Assigned to Endpoint
Endpoint
Mode 0
(No Ping-Pong)
Mode 1
(Ping-Pong on EP0 OUT)
Mode 3
(Ping-Pong on all other EPs,
except EP0)
Mode 2
(Ping-Pong on all EPs)
Out
In
Out
In
Out
In
Out
In
0 (E), 1 (O)
0 (E), 1 (O)
2 (E), 3 (O)
4 (E), 5 (O)
6 (E), 7 (O)
2 (E), 3 (O)
4 (E), 5 (O)
8 (E), 9 (O)
10 (E), 11 (O)
12 (E), 13 (O)
14 (E), 15 (O)
10 (E), 11 (O) 12 (E), 13 (O)
6 (E), 7 (O)
8 (E), 9 (O)
10
16 (E), 17 (O)
18 (E), 19 (O)
14 (E), 15 (O) 16 (E), 17 (O)
10
11
11
12
20 (E), 21 (O)
22 (E), 23 (O)
18 (E), 19 (O) 20 (E), 21 (O)
12
13
13
14
24 (E), 25 (O)
26 (E), 27 (O)
22 (E), 23 (O) 24 (E), 25 (O)
14
15
15
16
28 (E), 29 (O)
30 (E), 31 (O) 26 (E), 27 (O) 28 (E), 29 (O)
Legend:
(E) = Even transaction buffer, (O) = Odd transaction buffer
DS41639A-page 316
Preliminary
PIC16(L)F1454/5/9
TABLE 26-3:
Name
SUMMARY OF USB BUFFER DESCRIPTOR TABLE REGISTERS

Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BDnSTAT(1)
UOWN
DTS(4)
PID3(2)
PID2(2)
PID1(2)
DTSEN(3)
PID0(2)
BSTALL(3)
BC9
BC8
BDnCNT(1)
Byte Count
BDnADRL(1)
Buffer Address Low
BDnADRH(1)
Buffer Address High
Note 1:
2:
3:
4:
For buffer descriptor registers, n may have a value of 0 to 31. For the sake of brevity, all 32 registers are
shown as one generic prototype. All registers have indeterminate Reset values (xxxx xxxx).
Bits <5:2> of the BDnSTAT register are used by the SIE to return PID<3:0> values once the register is
turned over to the SIE (UOWN bit is set). Once the registers have been under SIE control, the values
written for DTSEN and BSTALL are no longer valid.
Prior to turning the buffer descriptor over to the SIE (UOWN bit is cleared), bits 5 through 2 of the
BDnSTAT register are used to configure the DTSEN and BSTALL settings.
This bit is ignored unless DTSEN = 1.
Preliminary
DS41639A-page 317
PIC16(L)F1454/5/9
26.5
USB Interrupts
level and interrupts are enabled through the UIE

register, while flags are maintained through the UIF
register. USB error conditions are considered the
second level and interrupts are enabled through the
UEIE register, while flags are maintained through the
UEIF register. Any USB interrupt condition will trigger
the USB Error Interrupt Flag, the UERRIF bit of the UIF
register.
The USB module can generate multiple interrupt

conditions. To accommodate all of these interrupt
sources, the module is provided with its own interrupt
logic structure, similar to that of the microcontroller.
USB interrupts are enabled with one set of control
registers and trapped with a separate set of flag
registers. All sources are funneled into a single USB
interrupt request, USBIF bit of the PIR2 for use with the
microcontroller's interrupt logic.
Interrupts may be used to trap routine events in a USB

transaction. Figure 26-7 shows some common events
within a USB frame and their corresponding interrupts.
Figure 26-6 shows the interrupt logic for the USB

module, which is divided into two registers in the USB
module. USB status interrupts are considered the top
FIGURE 26-6:
USB INTERRUPT LOGIC FUNNEL

Second Level USB Interrupts
(USB Error Conditions)
Top Level USB Interrupts

(USB Status Interrupts)
UEIR (Flag) and UEIE (Enable) Registers
UIR (Flag) and UIE (Enable) Registers

SOFIF
SOFIE
BTSEF
BTSEE
TRNIF
TRNIE
BTOEF
BTOEE
USBIF
IDLEIF
IDLEIE
DFN8EF
DFN8EE
UERRIF
UERRIE
CRC16EF
CRC16EE
STALLIF
STALLIE
CRC5EF
CRC5EE
PIDEF
PIDEE
ACTVIF
ACTVIE
URSTIF
URSTIE
FIGURE 26-7:
EXAMPLE OF A USB TRANSACTION AND INTERRUPT EVENTS

From Host
From Host
To Host
SETUP Token
Data
ACK
To Host
From Host
Data
ACK
From Host
To Host
Empty Data
ACK
From Host
IN Token
USB Reset
URSTIF
From Host
Start-of-Frame (SOF)
SOFIF
OUT Token
Set TRNIF
Set TRNIF
Set TRNIF
Transaction
Transaction
Complete
RESET
SOF
SETUP
DATA
SOF
STATUS
Differential Data
Control Transfer(1)
1 ms Frame
Note
1:
The control transfer shown here is only an example showing events that can occur for every transaction. Typical control transfers
will spread across multiple frames.
DS41639A-page 318
Preliminary
PIC16(L)F1454/5/9
26.5.1
USB INTERRUPT STATUS (UIR)

REGISTER
26.5.2
The USB Interrupt Status register (Register 26-7) contains the flag bits for each of the USB Status interrupt
sources. Each of these sources has a corresponding
interrupt enable bit in the UIE register. All of the USB
status flags are ORed together to generate the USBIF
interrupt flag for the microcontroller's interrupt funnel.
Once an interrupt bit has been set by the SIE, it must
be cleared by software. The flag bits can also be set in
software which can aid in firmware debugging.
Note:
All status flags in the UIR register should

be resolved and cleared before the USBIF
bit is cleared.
26.5.1.1
Bus Activity Detect Interrupt Bit

(ACTVIF)
The ACTVIF bit cannot be cleared immediately after the

USB module wakes up from Suspend or while the USB
module is suspended. A few clock cycles are required to
synchronize the internal hardware state machine before
the ACTVIF bit can be cleared by firmware. Clearing the
ACTVIF bit in firmware before the internal hardware is
synchronized may not have an effect on the value of
ACTVIF. The USB module may not be immediately operational after clearing the SUSPND bit if using the 48 MHz
PLL source because the PLL will require time to lock.
The application code should clear the ACTVIF flag as
shown in Example 26-1.
Only one ACTVIF interrupt is generated when resuming from the USB bus Idle condition. If user firmware
clears the ACTVIF bit, even when there is continuous
bus traffic, the bit will not become set again until after a
IDLEIF condition occurs. Bus traffic must cease long
enough to generate another IDLEIF condition before
another ACTVIF interrupt can be generated.
EXAMPLE 26-1:
CLEARING ACTVIF BIT

(UIR<2>)
Assembly:
BCF
LOOP:
BTFSS
BRA
BCF
BRA
DONE:
UCON, SUSPND
UIR, ACTVIF
DONE
UIR, ACTVIF
LOOP
USB INTERRUPT ENABLE

REGISTER (UIE)
The USB Interrupt Enable register (Register 26-8) contains the enable bits for the USB Status interrupt
sources. Setting any of these bits will enable the
respective interrupt source in the UIR register.
The values in this register only affect the propagation of
an interrupt condition to the microcontroller's interrupt
logic. The flag bits are set by their interrupt conditions,
allowing them to be polled and serviced without actually generating an interrupt.
26.5.3
USB ERROR INTERRUPT STATUS

REGISTER (UEIR)
The USB Error Interrupt Status register (Register 26-9)

contains the flag bits for each of the error sources
within the USB peripheral. Each of these sources is
enabled by a corresponding bit in the UEIE register. All
of the USB error flags are ORed together to generate
the USB Error Interrupt Flag (UERRIF) at the top level
of the interrupt logic.
Each error bit is set as soon as the error condition is
detected. Thus, the interrupt will typically not correspond with the end of a token being processed.
Once an interrupt bit has been set by the SIE, it must
be cleared by software.
Note:
26.5.4
All status flags in the UEIR register should

be resolved and cleared before the
UERRIF bit is cleared.
USB INTERRUPT (UEIE) ENABLE

REGISTER
The USB Error Interrupt Enable register (Register 26-10)

contains the enable bits for each of the USB error interrupt sources. Setting any of these bits will enable the
respective error interrupt source in the UEIR register. If
enabled, the UERRIF bit of the UIR register will be set
when any USB error interrupt is set.
As with the UIE register, the enable bits only affect the
propagation of an interrupt condition to the
microcontroller's interrupt logic. The flag bits are set by
their interrupt conditions, allowing them to be polled
and serviced without actually generating an interrupt.
C:
UCONbits.SUSPND = 0;
while (UIRbits.ACTVIF) { UIRbits.ACTVIF = 0; }
Preliminary
DS41639A-page 319
PIC16(L)F1454/5/9
26.6
USB Power Modes
The USB peripheral often has different power

requirements and configurations depending on the
application.
The most common cases are presented here:
In order to meet compliance specifications, the USB

module (and the D+ or D- internal pull-ups) should not
be enabled until the host actively drives VBUS high.
The application should never source any current onto
the 5V VBUS pin of the USB cable.
FIGURE 26-9:
Bus Power Only

Self-Power Only
Dual Power with Self-Power Dominance
VSELF
Means of estimating the current consumption of the

USB transceiver are also provided.
26.6.1
VSS
In Bus Power Only mode, all power for the application

is drawn from the USB (Figure 26-8). This is effectively
the simplest power method for the device.
In order to meet the inrush current requirements of the
USB 2.0 specifications, the total effective capacitance
appearing across VBUS and ground must be no more
than 10 F. Circuitry is required to limit inrush current,
see section 7.2.4 of the USB specification for more
detail.
All USB devices must support a Low-Power Suspend
mode which meets the current limits from the 5V VBUS
line of the USB cable according to the USB 2.0 specification. For high-powered devices that are remote
wake-up capable, a higher limit is allocated. Refer to
USB Specification 2.0, 7.2.3 for information.
The host signals the USB device to enter the Suspend
mode by stopping all USB traffic to that device for more
than 3 ms. This condition will cause the IDLEIF bit in
the UIR register to become set.
During the USB Suspend mode, the D+ or D- pull-up
resistor must remain active, which will consume some
of the allowed suspend current budget.
VBUS
BUS POWER ONLY
26.6.3
DUAL POWER WITH SELF-POWER

DOMINANCE
In Dual Power with Self-Power Dominance mode, the

application uses internal power as the primary source,
but can switch power from the USB when no internal
power is available. Figure 26-10 shows a simple Dual
Power with Self-Power Dominance mode example,
which automatically switches between Self-Power Only
and USB Bus Power Only modes.
Dual power devices must also meet all of the special
requirements for inrush current and Suspend mode
current and must not enable the USB module (or the
D+/D- internal pull-ups) until VBUS is driven high. See
Section 26.6.1
Bus
Power
Only
and
Section 26.6.2 Self-Power Only for descriptions of
those requirements. Additionally, dual power devices
must never source current onto the 5V VBUS pin of the
USB cable.
FIGURE 26-10:
VDD
VBUS
~5V
VUSB3V3
DUAL POWER EXAMPLE
VDD
100 k
VSELF
~5V
VSS
26.6.2
VDD
VUSB3V3
BUS POWER ONLY
FIGURE 26-8:
SELF-POWER ONLY
VUSB3V3
VSS
SELF-POWER ONLY
In Self-Power Only mode, the USB application provides

its own power, with very little power being pulled from
the USB. Figure 26-9 shows an example.
DS41639A-page 320
Note:
Preliminary
Users should keep in mind the limits for

devices drawing power from the USB.
Refer to USB Specification 2.0, 7.2.3 for
more information.
PIC16(L)F1454/5/9
26.6.4
USB TRANSCEIVER CURRENT

CONSUMPTION
The USB transceiver consumes a variable amount of

current, depending on following factors:
Impedance of USB cable

Length of cable
VUSB3V3 supply voltage
Data patterns across cable
Note:
Longer cables have larger capacitance

and consume more total energy when
switching output states.
Data patterns consist of IN and OUT traffic. IN

traffic consumes more current and requires the
microcontroller to drive the USB cable, while OUT
traffic requires the host to drive the USB cable.
The data sent across the USB cable is NRZI encoded.
A 0 in the NRZI encoding scheme toggles the output
state of the transceiver (from J state to a K state, or
vice versa). A 1 in the NRZI does not change the
output state of the transceiver, with the exception of the
effects of bit-stuffing. Because IN traffic consists of
data bits of value 0, the transceiver must charge/
discharge the USB cable to change states resulting in
the most current consumption.
More details about NRZI encoding and bit-stuffing can be
found in the USB 2.0 specification's section 7.1, although
knowledge of such details is not required to make USB
applications using PIC microcontrollers. Among other
things, the SIE handles bit-stuffing/unstuffing, NRZI
encoding/decoding and CRC generation/checking in
hardware.
The total transceiver current consumption will be
application-specific. However, to help estimate how
much current actually may be required in full-speed
applications, Equation 26-1 can be used.
Example 26-2 shows how this equation can be used for
a theoretical application.
Preliminary
DS41639A-page 321
PIC16(L)F1454/5/9
EQUATION 26-1:
ESTIMATING USB TRANSCEIVER CURRENT CONSUMPTION

IXCVR =
Legend:
(60 mA VUSB3V3 PZERO PIN LCABLE)

+ IPULLUP
(3.3V 5m)
VUSB3V3:
Voltage on the VUSB3V3 pin in volts.

For F devices, VUSB3V3 = 3.3V supplied from the internal regulator, VDD 3.6V.
For LF devices, VUSB3V3 is supplied by VDD 3.0 VDD 3.6.
PZERO:
Percentage of the IN traffic bits sent by the PIC device that are a value of 0.
PIN:
Percentage of total bus bandwidth that is used for IN traffic.
LCABLE:
Length (in meters) of the USB cable. The USB 2.0 specification requires that full-speed applications
use cables no longer than 5m.
IPULLUP:
Current which the nominal, 1.5 k pull-up resistor (when enabled) must supply to the USB cable. On
the host or hub end of the USB cable, 15 k nominal resistors (14.25 k to 24.8 k) are present which
pull both the D+ and D- lines to ground. During bus Idle conditions (such as between packets or during
USB Suspend mode), this results in up to 218 A of quiescent current drawn at 3.3V.
IPULLUP is also dependant on bus traffic conditions and can be as high as 2.2 mA when the USB bandwidth
is fully utilized (either IN or OUT traffic) for data that drives the lines to the K state most of the time.
EXAMPLE 26-2:
CALCULATING USB TRANSCEIVER CURRENT
For this example, the following assumptions are made about the application:
3.3V will be applied to VUSB3V3 and VDD, with the core voltage regulator enabled.
This is a full-speed application that uses one interrupt IN endpoint that can send one packet of 64 bytes every
1 ms, with no restrictions on the values of the bytes being sent. The application may or may not have
additional traffic on OUT endpoints.
A regular USB B or mini-B connector will be used on the application circuit board.
In this case, PZERO = 100% = 1, because there should be no restriction on the value of the data moving through
the IN endpoint. All 64 kBps of data could potentially be bytes of value, 00h. Since 0 bits cause toggling of the
output state of the transceiver, they cause the USB transceiver to consume extra current charging/discharging the
cable. In this case, 100% of the data bits sent can be of value 0. This should be considered the max value, as
normal data will consist of a fair mix of ones and zeros.
This application uses 64 kBps for IN traffic out of the total bus bandwidth of 1.5 MBps (12 Mbps), therefore:
64 kBps
Pin =
= 4.3% = 0.043
1.5 MBps
Since a regular B or mini-B connector is used in this application, the end user may plug in any type of cable up
to the maximum allowed 5 m length. Therefore, we use the worst-case length:
LCABLE = 5 meters
Assume IPULLUP = 2.2 mA. The actual value of IPULLUP will likely be closer to 218 A, but allow for the worst-case.
USB bandwidth is shared between all the devices which are plugged into the root port (via hubs). If the application
is plugged into a USB 1.1 hub that has other devices plugged into it, your device may see host to device traffic on
the bus, even if it is not addressed to your device. Since any traffic, regardless of source, can increase the IPULLUP
current above the base 218 A, it is safest to allow for the worst-case of 2.2 mA.
Therefore:
IXCVR =
(60 mA 3.3V 1 0.043 5m)

+ 2.2 mA = 4.8 mA
(3.3V 5m)
The calculated value should be considered an approximation and additional guardband or application-specific product testing is recommended. The transceiver current is in addition to the rest of the current consumed by the
microcontroller.
DS41639A-page 322
Preliminary
PIC16(L)F1454/5/9
26.7
Oscillator
The USB module has specific clock requirements. For

full-speed operation, the clock source must be 48 MHz.
Even so, the microcontroller core and other peripherals
are not required to run at that clock speed. Available
clocking options are described in detail in Section 5.4
USB Operation.
26.8
Interrupt-On-Change for D+/DPins
The microcontroller has interrupt-on-change functionality on both D+ and D- data pins, which allows the
device to detect voltage level changes when first connected to a USB host/hub. This feature is not available
when the USB module is enabled.
The USB host/hub has 15K pull-down resistors on the
D+ and D- pins. When the microcontroller attaches to
the bus, the D+ and D- pins can detect voltage
changes. External resistors are needed for each pin to
maintain a high state on the pins when the
microcontroller is detached.
The USB module must be disabled (USBEN = 0) for the
interrupt-on-change to function. Enabling the USB
module (USBEN = 1) will automatically disable the
interrupt-on-change for D+ and D- pins. Refer to
Section 13.0 Interrupt-On-Change for more detail.
26.9
USB Firmware and Drivers
Microchip provides a number of application-specific

resources, such as USB firmware and driver support.
Refer to www.microchip.com for the latest firmware and
driver support.
Preliminary
DS41639A-page 323
PIC16(L)F1454/5/9
26.10 USB Operation Overview
26.10.2
This section presents some of the basic USB concepts

and useful information necessary to design a USB
device. Although a lot of information is provided in this
section, refer to the USB 2.0 specification for more
details, as needed.
Information communicated on the bus is grouped into

1 ms time slots, referred to as frames. Each frame can
contain many transactions to various devices and
endpoints. Figure 26-7 shows an example of a
transaction within a frame.
26.10.1
26.10.3
LAYERED FRAMEWORK
FRAMES
TRANSFERS
USB device functionality is structured into a layered

framework, graphically shown in Figure 26-11. Each level
is associated with a functional level within the device. The
highest layer, other than the device, is the configuration. A
device may have multiple configurations. For example, a
particular device may have multiple power requirements
based on Self-Power Only or Bus Power Only modes.
There are four transfer types defined in the USB

specification:
For each configuration, there may be multiple

interfaces. Each interface could support a particular
mode of that configuration.
Bulk: This type of transfer method allows for large

amounts of data to be transferred with ensured data
integrity; however, the delivery timeliness is not
ensured.
Isochronous: This type provides a transfer method for

large amounts of data (up to 1023 bytes) with timely
delivery ensured; however, the data integrity is not
ensured. This is good for streaming applications where
small data loss is not critical, such as audio.
Below the interface is the endpoint(s). Data is directly

moved at this level. Endpoint 0 is always a control
endpoint and, by default, when the device is on the bus,
Endpoint 0 must be available to configure the device.
Interrupt: This type of transfer provides for ensured

timely delivery for small blocks of data, plus data
integrity is ensured.
Control: This type provides device setup control.
While full-speed devices support all transfer types, lowspeed devices are limited to interrupt and control
transfers only.
FIGURE 26-11:
USB LAYERS
Device
To other Configurations (if any)
Configuration
To other Interfaces (if any)
Interface
Interface
Endpoint
DS41639A-page 324
Endpoint
Endpoint
Endpoint
Preliminary
Endpoint
Endpoint
PIC16(L)F1454/5/9
26.10.4
POWER
26.10.6
Power is available from the USB. The USB specification defines the bus power requirements. Devices may
either be self-powered or bus powered. Self-powered
devices draw power from an external source, while bus
powered devices use power supplied from the bus.
The USB specification limits the power taken from the
bus. Refer to USB Specification 2.0, 7.2.3 for power
limits information. Note that power above one unit load
is a request and the host or hub is not obligated to
provide the extra current. Thus, a device capable of
consuming more than one unit load must be able to
maintain a low-power configuration of a one unit load or
less, if necessary.
The USB specification also defines a Suspend mode.
In this situation, current must be limited. A device must
enter a Suspend state after 3 ms of inactivity (i.e., no
SOF tokens for 3 ms). A device entering Suspend
mode must drop current consumption within 10 ms
after Suspend. Likewise, when signaling a wake-up,
the device must signal a wake-up within 10 ms of
drawing current above the suspend limit. Refer to USB
Specification 2.0, 7.2.3 for current limit information.
26.10.5
ENUMERATION
When the device is initially attached to the bus, the host

enters an enumeration process in an attempt to identify
the device. Essentially, the host interrogates the device,
gathering information such as power consumption, data
rates and sizes, protocol and other descriptive
information; descriptors contain this information. A
typical enumeration process could be as follows:
1. USB Reset: Reset the device, which means the
device is not configured and does not have an address
(address 0).
2. Get Device Descriptor: The host requests a small
portion of the device descriptor.
3. USB Reset: Reset the device again.
4. Set Address: The host assigns an address to the
device.
5. Get Device Descriptor: The host retrieves the device
descriptor, gathering info such as manufacturer, type of
device, maximum control packet size.
6. Get configuration descriptors.
There are eight different standard descriptor types, of

which five are most important for this device.
26.10.6.1
26.10.6.2
Configuration Descriptors
The configuration descriptor provides information on the

power requirements of the device and how many different
interfaces are supported when in this configuration. There
may be more than one configuration for a device (i.e., lowpower and high-power configurations).
26.10.6.3
Interface Descriptors
The interface descriptor details the number of endpoints

used in this interface, as well as the class of the interface.
There may be more than one interface for a configuration.
26.10.6.4
Endpoint Descriptors
The interface descriptor details the number of endpoints

used in this interface, as well as the class of the interface.
There may be more than one interface for a configuration.
26.10.6.5
String Descriptors
Many of the previous descriptors reference one or more

string descriptors. String descriptors provide human
readable information about the layer (Section 26.10.1
Layered Framework) they describe. Often these
strings show up in the host to help the user identify the
device. String descriptors are generally optional to save
memory and are encoded in a unicode format.
26.10.7
BUS SPEED
Each USB device must indicate its bus presence and

speed to the host. This is accomplished through a pullup, which is connected to the bus at the time of the
attachment event. Depending on the speed of the
device, the pull-up connects either the D+ or D- line to
3.3V. For a low-speed device, the pull-up is connected
to the D- line. For a full-speed device, the pull-up is
connected to the D+ line.
8. Set a configuration.
The exact enumeration process depends on the host.
Device Descriptors
The device descriptor provides general information,

such as manufacturer, product number, serial number,
the class of the device and the number of configurations.
There is only one device descriptor.
26.10.8
7. Get any other descriptors.
DESCRIPTORS
CLASS SPECIFICATION AND

DRIVERS SPEED
USB specifications include class specifications, which

operating system vendors optionally support. Examples
of classes include Audio, Mass Storage, Communications
and Human Interface (HID). In most cases, a driver is
required at the host side to talk to the USB device. In
custom applications, a driver may need to be developed.
Fortunately, drivers are available for most common host
systems for the most common classes of devices. Thus,
these drivers can be reused.
Preliminary
DS41639A-page 325
PIC16(L)F1454/5/9
26.11 Register Definitions: USB
REGISTER 26-1:
U-0
UCON: USB CONTROL REGISTER

R/W-0
PPBRST
R-x
SE0
R/C-0
PKTDIS
R/W-0
(1)
USBEN
R/W-0
R/W-0
U-0
RESUME
SUSPND
bit 7
bit 0
Legend:
C = Clearable bit
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
PPBRST: Ping-Pong Buffers Reset bit

1 = Reset all Ping-Pong Buffer Pointers to the Even Buffer Descriptor (BD) banks
0 = Ping-Pong Buffer Pointers not being reset
bit 5
SE0: Live Single-Ended Zero Flag bit

1 = Single-ended zero active on the USB bus
0 = No single-ended zero detected
bit 4
PKTDIS: Packet Transfer Disable bit

1 = SIE token and packet processing disabled, automatically set when a SETUP token is received
0 = SIE token and packet processing enabled
bit 3
USBEN: USB Module Enable bit(1)

1 = USB module and supporting circuitry enabled (device attached)
0 = USB module and supporting circuitry disabled (device detached)
bit 2
RESUME: Resume Signaling Enable bit

1 = Resume signaling activated
0 = Resume signaling disabled
bit 1
SUSPND: Suspend USB bit

1 = USB module and supporting circuitry in Power Conserve mode, SIE clock inactive
0 = USB module and supporting circuitry in normal operation, SIE clock clocked at the configured rate
bit 0
Note 1:
This bit cannot be set if the USB module does not have an appropriate clock source.
DS41639A-page 326
Preliminary
PIC16(L)F1454/5/9
REGISTER 26-2:
R/W-0
UCFG: USB CONFIGURATION REGISTER

R/W-0
UTEYE
Reserved
U-0
R/W-0
UPUEN
(1)
R/W-0
Reserved
R/W-0
R/W-0
(1)
FSEN
R/W-0
PPB<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
UTEYE: USB Eye Pattern Test Enable bit

1 = Eye pattern test enabled
0 = Eye pattern test disabled
x = Bit is unknown
bit 5
Reserved: Read as 0. Maintain this bit clear
bit 4
UPUEN: USB On-Chip Pull-up Enable bit(1)

1 = On-chip pull-up enabled (pull-up on D+ with FSEN = 1 or D- with FSEN = 0)
0 = On-chip pull-up disabled
bit 3
Reserved: Read as 0. Maintain this bit clear
bit 2
FSEN: Full-Speed Enable bit(1)

1 = Full-speed device: controls transceiver edge rates; requires input clock at 48 MHz
0 = Low-speed device: controls transceiver edge rates; requires input clock at 6 MHz
bit 1-0
PPB<1:0>: Ping-Pong Buffers Configuration bits

11 = Even/Odd ping-pong buffers enabled for Endpoints 1 to 15
10 = Even/Odd ping-pong buffers enabled for all endpoints
01 = Even/Odd ping-pong buffer enabled for OUT Endpoint 0
00 = Even/Odd ping-pong buffers disabled
Note 1:
The UPUEN, and FSEN bits should never be changed while the USB module is enabled. These values
must be preconfigured prior to enabling the module.
Preliminary
DS41639A-page 327
PIC16(L)F1454/5/9
REGISTER 26-3:
U-0
USTAT: USB STATUS REGISTER

R-x
R-x
R-x
R-x
ENDP<3:0>
R-x
R-x
U-0
DIR
PPBI(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-3
ENDP<2:0>: Encoded Number of Last Endpoint Activity bits

(represents the number of the BDT updated by the last USB transfer)
1111 = Endpoint 15
1110 = Endpoint 14
0001 = Endpoint 1
0000 = Endpoint 0
bit 2
DIR: Last BD Direction Indicator bit

1 = The last transaction was an IN token
0 = The last transaction was an OUT or SETUP token
bit 1
PPBI: Ping-Pong BD Pointer Indicator bit(1)

1 = The last transaction was to the Odd BD bank
0 = The last transaction was to the Even BD bank
bit 0
Note 1:
x = Bit is unknown
This bit is only valid for endpoints with available Even and Odd BD registers.
DS41639A-page 328
Preliminary
PIC16(L)F1454/5/9
REGISTER 26-4:
UEPn: USB ENDPOINT n CONTROL REGISTER (UEP0 THROUGH UEP7)
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EPHSHK
EPCONDIS
EPOUTEN
EPINEN
EPSTALL(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7-5
bit 4
EPHSHK: Endpoint Handshake Enable bit

1 = Endpoint handshake enabled
0 = Endpoint handshake disabled (typically used for isochronous endpoints)
bit 3
EPCONDIS: Bidirectional Endpoint Control bit

If EPOUTEN = 1 and EPINEN = 1:
1 = Disable Endpoint n from control transfers; only IN and OUT transfers allowed
0 = Enable Endpoint n for control (SETUP) transfers; IN and OUT transfers also allowed
bit 2
EPOUTEN: Endpoint Output Enable bit

1 = Endpoint n output enabled
0 = Endpoint n output disabled
bit 1
EPINEN: Endpoint Input Enable bit

1 = Endpoint n input enabled
0 = Endpoint n input disabled
bit 0
EPSTALL: Endpoint STALL Enable bit(1)

1 = Endpoint n is stalled
0 = Endpoint n is not stalled
Note 1:
Valid only if Endpoint n is enabled; otherwise, the bit is ignored.
Preliminary
DS41639A-page 329
PIC16(L)F1454/5/9
REGISTER 26-5:
R/W-x
UOWN(1)
BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER (BD0STAT THROUGH

BD31STAT), CPU MODE (DATA IS WRITTEN TO THE SIDE)
R/W-x
U-0
U-0
(2)
(3)
(3)
DTS
R/W-x
R/W-x
R/W-x
R/W-x
DTSEN
BSTALL
BC9
BC8
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
UOWN: USB Own bit(1)

1 = Refer to Register 26-6.
0 = The microcontroller core owns the BD and its corresponding buffer
bit 6
DTS: Data Toggle Synchronization bit(2)

1 = Data 1 packet
0 = Data 0 packet
bit 5-4
bit 3
DTSEN: Data Toggle Synchronization Enable bit

1 = Data toggle synchronization is enabled; data packets with incorrect Sync value will be ignored
except for a SETUP transaction, which is accepted even if the data toggle bits do not match
0 = No data toggle synchronization is performed
bit 2
BSTALL: Buffer Stall Enable bit

1 = Buffer stall enabled; STALL handshake issued if a token is received that would use the BD in the
given location (UOWN bit remains set, BD value is unchanged)
0 = Buffer stall disabled
bit 1-0
BC<9:8>: Byte Count 9 and 8 bits

The byte count bits represent the number of bytes that will be transmitted for an IN token or received
during an OUT token. Together with BC<7:0>, the valid byte counts are 0-1023.
Note 1:
2:
3:
This bit must be initialized by the user to the desired value prior to enabling the USB module.
This bit is ignored unless DTSEN = 1.
If these bits are set, USB communication may not work. Hence, these bits should always be maintained as 0.
DS41639A-page 330
Preliminary
PIC16(L)F1454/5/9
REGISTER 26-6:
BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER (BD0STAT THROUGH

BD31STAT), SIE MODE (DATA RETURNED BY THE SIDE TO THE MCU)
R/W-x
U-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
UOWN
PID3
PID2
PID1
PID0
BC9
BC8
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
UOWN: USB Own bit

1 = The SIE owns the BD and its corresponding buffer
0 = Refer to Register 26-5.
bit 6
Reserved: Not written by the SIE
bit 5-2
PID<3:0>: Packet Identifier bits

The received token PID value of the last transfer (IN, OUT or SETUP transactions only).
bit 1-0
BC<9:8>: Byte Count 9 and 8 bits

These bits are updated by the SIE to reflect the actual number of bytes received on an OUT transfer
and the actual number of bytes transmitted on an IN transfer.
Preliminary
DS41639A-page 331
PIC16(L)F1454/5/9
REGISTER 26-7:
U-0
UIR: USB INTERRUPT STATUS REGISTER

R/W-0
SOFIF
R/W-0
STALLIF
R/W-0
IDLEIF
R/W-0
(1)
TRNIF
(2)
R/W-0
ACTVIF
(3)
R-0
UERRIF
R/W-0
(4)
URSTIF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
SOFIF: Start-of-Frame Token Interrupt bit

1 = A Start-of-Frame token received by the SIE
0 = No Start-of-Frame token received by the SIE
bit 5
STALLIF: A STALL Handshake Interrupt bit

1 = A STALL handshake was sent by the SIE
0 = A STALL handshake has not been sent
bit 4
IDLEIF: Idle Detect Interrupt bit(1)

1 = Idle condition detected (constant Idle state of 3 ms or more)
0 = No Idle condition detected
bit 3
TRNIF: Transaction Complete Interrupt bit(2)

1 = Processing of pending transaction is complete; read USTAT register for endpoint information
0 = Processing of pending transaction is not complete or no transaction is pending
bit 2
ACTVIF: Bus Activity Detect Interrupt bit(3)

1 = Activity on the D+/D- lines was detected
0 = No activity detected on the D+/D- lines
bit 1
UERRIF: USB Error Condition Interrupt bit(4)

1 = An unmasked error condition has occurred
0 = No unmasked error condition has occurred
bit 0
URSTIF: USB Reset Interrupt bit

1 = Valid USB Reset occurred; UADDR register is cleared
0 = No USB Reset has occurred
Note 1:
2:
3:
4:
Once an Idle state is detected, the user may want to place the USB module in Suspend mode.
Clearing this bit will cause the USTAT FIFO to advance (valid only for IN, OUT and SETUP tokens).
This bit is typically unmasked only following the detection of a UIDLE interrupt event.
Only error conditions enabled through the UEIE register will set this bit. This bit is a status bit only and
cannot be set or cleared by the user.
DS41639A-page 332
Preliminary
PIC16(L)F1454/5/9
REGISTER 26-8:
UIE: USB INTERRUPT ENABLE REGISTER
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SOFIE
STALLIE
IDLEIE
TRNIE
ACTVIE
UERRIE
URSTIE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
SOFIE: Start-of-Frame Token Interrupt Enable bit

1 = Start-of-Frame token interrupt enabled
0 = Start-of-Frame token interrupt disabled
bit 5
STALLIE: STALL Handshake Interrupt Enable bit

1 = STALL interrupt enabled
0 = STALL interrupt disabled
bit 4
IDLEIE: Idle Detect Interrupt Enable bit

1 = Idle detect interrupt enabled
0 = Idle detect interrupt disabled
bit 3
TRNIE: Transaction Complete Interrupt Enable bit

1 = Transaction interrupt enabled
0 = Transaction interrupt disabled
bit 2
ACTVIE: Bus Activity Detect Interrupt Enable bit

1 = Bus activity detect interrupt enabled
0 = Bus activity detect interrupt disabled
bit 1
UERRIE: USB Error Interrupt Enable bit

1 = USB error interrupt enabled
0 = USB error interrupt disabled
bit 0
URSTIE: USB Reset Interrupt Enable bit

1 = USB Reset interrupt enabled
0 = USB Reset interrupt disabled
Preliminary
x = Bit is unknown
DS41639A-page 333
PIC16(L)F1454/5/9
REGISTER 26-9:
UEIR: USB ERROR INTERRUPT STATUS REGISTER
R/C-0
U-0
U-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
BTSEF
BTOEF
DFN8EF
CRC16EF
CRC5EF
PIDEF
bit 7
bit 0
Legend:
R = Readable bit
C = Clearable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
BTSEF: Bit Stuff Error Flag bit

1 = A bit stuff error has been detected
0 = No bit stuff error
bit 6-5
bit 4
BTOEF: Bus Turnaround Time-out Error Flag bit

1 = Bus turnaround time-out has occurred (more than 16 bit times of Idle from previous EOP elapsed)
0 = No bus turnaround time-out
bit 3
DFN8EF: Data Field Size Error Flag bit

1 = The data field was not an integral number of bytes
0 = The data field was an integral number of bytes
bit 2
CRC16EF: CRC16 Failure Flag bit

1 = The CRC16 failed
0 = The CRC16 passed
bit 1
CRC5EF: CRC5 Host Error Flag bit

1 = The token packet was rejected due to a CRC5 error
0 = The token packet was accepted
bit 0
PIDEF: PID Check Failure Flag bit

1 = PID check failed
0 = PID check passed
DS41639A-page 334
Preliminary
PIC16(L)F1454/5/9
REGISTER 26-10: UEIE: USB ERROR INTERRUPT ENABLE REGISTER
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BTSEE
BTOEE
DFN8EE
CRC16EE
CRC5EE
PIDEE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
BTSEE: Bit Stuff Error Interrupt Enable bit

1 = Bit stuff error interrupt enabled
0 = Bit stuff error interrupt disabled
bit 6-5
bit 4
BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit

1 = Bus turnaround time-out error interrupt enabled
0 = Bus turnaround time-out error interrupt disabled
bit 3
DFN8EE: Data Field Size Error Interrupt Enable bit

1 = Data field size error interrupt enabled
0 = Data field size error interrupt disabled
bit 2
CRC16EE: CRC16 Failure Interrupt Enable bit

1 = CRC16 failure interrupt enabled
0 = CRC16 failure interrupt disabled
bit 1
CRC5EE: CRC5 Host Error Interrupt Enable bit

1 = CRC5 host error interrupt enabled
0 = CRC5 host error interrupt disabled
bit 0
PIDEE: PID Check Failure Interrupt Enable bit

1 = PID check failure interrupt enabled
0 = PID check failure interrupt disabled
Preliminary
x = Bit is unknown
DS41639A-page 335
PIC16(L)F1454/5/9
TABLE 26-4:
REGISTERS ASSOCIATED WITH USB MODULE OPERATION(1)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Details on
Page:
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
96
100
PIR2
OSFIF
C2IF
C1IF
BCL1IF
USBIF
ACTIF
PIE2
OSFIE
C2IE
C1IE
BCL1IE
USBIE
ACTIE
98
UCON
PPBRST
SE0
PKTDIS
USBEN
RESUME
SUSPND
326
UCFG
UTEYE
Reserved
UPUEN
Reserved
FSEN
DIR
PPBI
328
ADDR2
ADDR1
ADDR0
312
USTAT
UADDR
ADDR6
ADDR5
ADDR4
ADDR3
ENDP<3:0>
327
PPB<1:0>
UFRML
FRM7
FRM6
FRM5
FRM4
FRM3
FRM2
FRM1
FRM0
312*
UFRMH
FRM10
FRM9
FRM8
312*
UIR
SOFIF
STALLIF
IDLEIF
TRNIF
ACTVIF
UERRIF
URSTIF
332
UIE
SOFIE
STALLIE
IDLEIE
TRNIE
ACTVIE
UERRIE
URSTIE
333
UEIR
BTSEF
BTOEF
DFN8EF
CRC16EF
CRC5EF
PIDEF
334
UEIE
BTSEE
BTOEE
DFN8EE
CRC16EE
CRC5EE
PIDEE
335
UEP0
EPHSHK
EPCONDIS EPOUTEN
EPINEN
EPSTALL
329
UEP1
EPHSHK
EPCONDIS EPOUTEN
EPINEN
EPSTALL
329
UEP2
EPHSHK
EPCONDIS EPOUTEN
EPINEN
EPSTALL
329
UEP3
EPHSHK
EPCONDIS EPOUTEN
EPINEN
EPSTALL
329
UEP4
EPHSHK
EPCONDIS EPOUTEN
EPINEN
EPSTALL
329
UEP5
EPHSHK
EPCONDIS EPOUTEN
EPINEN
EPSTALL
329
UEP6
EPHSHK
EPCONDIS EPOUTEN
EPINEN
EPSTALL
329
UEP7
EPHSHK
EPCONDIS EPOUTEN
EPINEN
EPSTALL
329
Legend:
*
Note 1:
= unimplemented, read as 0. Shaded cells are not used by the USB module.
This table includes only those hardware mapped SFRs located in Bank 15 of the data memory space. The Buffer
Descriptor registers, which are mapped into Bank 4 and are not true SFRs, are listed separately in Table 26-3.
DS41639A-page 336
Preliminary
PIC16(L)F1454/5/9
27.0
IN-CIRCUIT SERIAL
PROGRAMMING (ICSP)
27.3
ICSP programming allows customers to manufacture

circuit boards with unprogrammed devices. Programming
can be done after the assembly process allowing the
device to be programmed with the most recent firmware
or a custom firmware. Five pins are needed for ICSP
programming:
ICSPCLK
ICSPDAT
MCLR/VPP
VDD
VSS
Connection to a target device is typically done through

an ICSP header. A commonly found connector on
development tools is the RJ-11 in the 6P6C (6-pin, 6
connector) configuration. See Figure 27-1.
FIGURE 27-1:
VDD
In Program/Verify mode the program memory, user IDs

and the Configuration Words are programmed through
serial communications. The ICSPDAT pin is a bidirectional I/O used for transferring the serial data and the
ICSPCLK pin is the clock input. For more information on
ICSP refer to the PIC16(L)F145X Memory Programming
Specification (DS41620).
27.1
The Low-Voltage Programming Entry mode allows the

PIC Flash MCUs to be programmed using VDD only,
without high voltage. When the LVP bit of Configuration
Words is set to 1, the low-voltage ICSP programming
entry is enabled. To disable the Low-Voltage ICSP
mode, the LVP bit must be programmed to 0.
ICSPDAT
NC
2 4 6
ICSPCLK
1 3 5
Target
VSS
PC Board
Bottom Side
Pin Description
1 = VPP/MCLR
High-Voltage Programming Entry

Mode
Low-Voltage Programming Entry

Mode
ICD RJ-11 STYLE

CONNECTOR INTERFACE
VPP/MCLR
2 = VDD Target
3 = VSS (ground)
4 = ICSPDAT
The device is placed into High-Voltage Programming

Entry mode by holding the ICSPCLK and ICSPDAT
pins low then raising the voltage on MCLR/VPP to VIHH.
27.2
Common Programming Interfaces
5 = ICSPCLK
6 = No Connect
Another connector often found in use with the PICkit

programmers is a standard 6-pin header with 0.1 inch
spacing. Refer to Figure 27-2.
Entry into the Low-Voltage Programming Entry mode

requires the following steps:
1.
2.
MCLR is brought to VIL.

A 32-bit key sequence is presented on
ICSPDAT, while clocking ICSPCLK.
Once the key sequence is complete, MCLR must be

held at VIL for as long as Program/Verify mode is to be
maintained.
If low-voltage programming is enabled (LVP = 1), the
MCLR Reset function is automatically enabled and
cannot be disabled. See Section 6.5 MCLR for more
information.
The LVP bit can only be reprogrammed to 0 by using
the High-Voltage Programming mode.
Preliminary
DS41639A-page 337
PIC16(L)F1454/5/9
FIGURE 27-2:
PICkit PROGRAMMER STYLE CONNECTOR INTERFACE

Pin 1 Indicator
Pin Description*
1 = VPP/MCLR
1
2
3
4
5
6
2 = VDD Target
3 = VSS (ground)
4 = ICSPDAT
5 = ICSPCLK
6 = No Connect
The 6-pin header (0.100" spacing) accepts 0.025" square pins.
For additional interface recommendations, refer to your

specific device programmer manual prior to PCB
design.
It is recommended that isolation devices be used to
separate the programming pins from other circuitry.
The type of isolation is highly dependent on the specific
application and may include devices such as resistors,
diodes, or even jumpers. See Figure 27-3 for more
information.
FIGURE 27-3:
TYPICAL CONNECTION FOR ICSP PROGRAMMING

External
Programming
Signals
Device to be
Programmed
VDD
VDD
VDD
VPP
MCLR/VPP
VSS
VSS
Data
ICSPDAT
Clock
ICSPCLK
To Normal Connections
* Isolation devices (as required).
DS41639A-page 338
Preliminary
PIC16(L)F1454/5/9
28.0
INSTRUCTION SET SUMMARY
28.1
Read-Modify-Write Operations
Byte Oriented
Bit Oriented
Literal and Control
Any instruction that specifies a file register as part of

the instruction performs a Read-Modify-Write (R-M-W)
operation. The register is read, the data is modified,
and the result is stored according to either the instruction, or the destination designator d. A read operation
is performed on a register even if the instruction writes
to that register.
The literal and control category contains the most varied instruction word format.
TABLE 28-1:
Each PIC16 instruction is a 14-bit word containing the

operation code (opcode) and all required operands.
The op codes are broken into three broad categories.
Table 28-3 lists the instructions recognized by the

MPASMTM assembler.
All instructions are executed within a single instruction
cycle, with the following exceptions, which may take
two or three cycles:
Subroutine takes two cycles (CALL, CALLW)
Returns from interrupts or subroutines take two
cycles (RETURN, RETLW, RETFIE)
Program branching takes two cycles (GOTO, BRA,
BRW, BTFSS, BTFSC, DECFSZ, INCSFZ)
One additional instruction cycle will be used when
any instruction references an indirect file register
and the file select register is pointing to program
memory.
One instruction cycle consists of 4 oscillator cycles; for
an oscillator frequency of 4 MHz, this gives a nominal
instruction execution rate of 1 MHz.
All instruction examples use the format 0xhh to
represent a hexadecimal number, where h signifies a
hexadecimal digit.
OPCODE FIELD
DESCRIPTIONS
Field
f
Description
Register file address (0x00 to 0x7F)
Working register (accumulator)
Bit address within an 8-bit file register
Literal field, constant data or label
Dont care location (= 0 or 1).

The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
Destination select; d = 0: store result in W,

d = 1: store result in file register f.
Default is d = 1.
FSR or INDF number. (0-1)
mm
Pre-post increment-decrement mode

selection
TABLE 28-2:
ABBREVIATION
DESCRIPTIONS
Field
PC
Program Counter
TO
Time-out bit
C
DC
Z
PD
Description
Preliminary
Carry bit
Digit carry bit
Zero bit
Power-down bit
DS41639A-page 339
PIC16(L)F1454/5/9
FIGURE 28-1:
GENERAL FORMAT FOR

INSTRUCTIONS
Byte-oriented file register operations

13
8 7 6
OPCODE
d
f (FILE #)
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations

13
10 9
7 6
OPCODE
b (BIT #)
f (FILE #)
b = 3-bit bit address

f = 7-bit file register address
Literal and control operations

General
13
OPCODE
0
k (literal)
k = 8-bit immediate value

CALL and GOTO instructions only
13
11 10
OPCODE
k (literal)

MOVLP instruction only
13
OPCODE
0
k (literal)

MOVLB instruction only
13
OPCODE
5 4
0
k (literal)

BRA instruction only
13
OPCODE
0
k (literal)

FSR Offset instructions
13
OPCODE
6
n
0
k (literal)
n = appropriate FSR
FSR Increment instructions
13
OPCODE
2 1
0
n m (mode)
n = appropriate FSR
m = 2-bit mode value
OPCODE only
13
0
OPCODE
DS41639A-page 340
Preliminary
PIC16(L)F1454/5/9
TABLE 28-3:
PIC16(L)F1454/5/9 ENHANCED INSTRUCTION SET
Mnemonic,
Operands
Description
Cycles
14-Bit Opcode
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF
ADDWFC
ANDWF
ASRF
LSLF
LSRF
CLRF
CLRW
COMF
DECF
INCF
IORWF
MOVF
MOVWF
RLF
RRF
SUBWF
SUBWFB
SWAPF
XORWF
f, d
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
Add W and f
Add with Carry W and f
AND W with f
Arithmetic Right Shift
Logical Left Shift
Logical Right Shift
Clear f
Clear W
Complement f
Decrement f
Increment f
Inclusive OR W with f
Move f
Move W to f
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Subtract with Borrow W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
00
11
00
11
11
11
00
00
00
00
00
00
00
00
00
00
00
11
00
00
0111
1101
0101
0111
0101
0110
0001
0001
1001
0011
1010
0100
1000
0000
1101
1100
0010
1011
1110
0110
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0000
dfff
dfff
dfff
dfff
dfff
1fff
dfff
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
00xx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
C, DC, Z
C, DC, Z
Z
C, Z
C, Z
C, Z
Z
Z
Z
Z
Z
Z
Z
C
C
C, DC, Z
C, DC, Z
Z
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
BYTE ORIENTED SKIP OPERATIONS

DECFSZ
INCFSZ
f, d
f, d
Decrement f, Skip if 0
Increment f, Skip if 0
BCF
BSF
f, b
f, b
Bit Clear f
Bit Set f
1(2)
1(2)
00
00
1, 2
1, 2
1011 dfff ffff

1111 dfff ffff
BIT-ORIENTED FILE REGISTER OPERATIONS

1
1
00bb bfff ffff

01bb bfff ffff
2
2
01
01
10bb bfff ffff

11bb bfff ffff
1, 2
1, 2
11
11
11
00
11
11
11
11
1110
1001
1000
0000
0001
0000
1100
1010
01
01
BIT-ORIENTED SKIP OPERATIONS

BTFSC
BTFSS
f, b
f, b
Bit Test f, Skip if Clear

Bit Test f, Skip if Set
ADDLW
ANDLW
IORLW
MOVLB
MOVLP
MOVLW
SUBLW
XORLW
k
k
k
k
k
k
k
k
Add literal and W

AND literal with W
Inclusive OR literal with W
Move literal to BSR
Move literal to PCLATH
Move literal to W
Subtract W from literal
Exclusive OR literal with W
1 (2)
1 (2)
LITERAL OPERATIONS
1
1
1
1
1
1
1
1
kkkk
kkkk
kkkk
001k
1kkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
C, DC, Z
Z
Z
C, DC, Z
Z
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one
additional instruction cycle.
Preliminary
DS41639A-page 341
PIC16(L)F1454/5/9
TABLE 28-3:
PIC16(L)F1454/5/9 ENHANCED INSTRUCTION SET (CONTINUED)
Mnemonic,
Operands
Description
Cycles
14-Bit Opcode
MSb
LSb
Status
Affected
Notes
CONTROL OPERATIONS
BRA
BRW
CALL
CALLW
GOTO
RETFIE
RETLW
RETURN
k
k
k
Relative Branch
Relative Branch with W
Call Subroutine
Call Subroutine with W
Go to address
Return from interrupt
Return with literal in W
Return from Subroutine
CLRWDT
NOP
OPTION
RESET
SLEEP
TRIS
Clear Watchdog Timer

No Operation
Load OPTION_REG register with W
Software device Reset
Go into Standby mode
Load TRIS register with W
ADDFSR
MOVIW
n, k
n mm
MOVWI
k[n]
n mm
Add Literal k to FSRn

Move Indirect FSRn to W with pre/post inc/dec
modifier, mm
Move INDFn to W, Indexed Indirect.
Move W to Indirect FSRn with pre/post inc/dec
modifier, mm
Move W to INDFn, Indexed Indirect.
2
2
2
2
2
2
2
2
11
00
10
00
10
00
11
00
001k
0000
0kkk
0000
1kkk
0000
0100
0000
kkkk
0000
kkkk
0000
kkkk
0000
kkkk
0000
kkkk
1011
kkkk
1010
kkkk
1001
kkkk
1000
00
00
00
00
00
00
0000
0000
0000
0000
0000
0000
0110
0000
0110
0000
0110
0110
0100 TO, PD
0000
0010
0001
0011 TO, PD
0fff
INHERENT OPERATIONS
1
1
1
1
1
1
C-COMPILER OPTIMIZED
1
1
11
00
1
1
11
00
0001 0nkk kkkk

0000 0001 0nmm Z
kkkk
1111 0nkk 1nmm Z
0000 0001 kkkk
2, 3
2
2, 3
2
11 1111 1nkk
k[n]
1
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
3: See Table in the MOVIW and MOVWI instruction descriptions.
DS41639A-page 342
Preliminary
PIC16(L)F1454/5/9
28.2
Instruction Descriptions
ADDFSR
Add Literal to FSRn
ANDLW
AND literal with W
Syntax:
[ label ] ADDFSR FSRn, k
Syntax:
[ label ] ANDLW
Operands:
-32 k 31
n [ 0, 1]
Operands:
0 k 255
Operation:
FSR(n) + k FSR(n)
Status Affected:
None
Description:
The signed 6-bit literal k is added to

the contents of the FSRnH:FSRnL
register pair.
Operation:
(W) .AND. (k) (W)
Status Affected:
Description:
The contents of W register are

ANDed with the eight-bit literal k.
The result is placed in the W register.
ANDWF
AND W with f
FSRn is limited to the range 0000h FFFFh. Moving beyond these bounds
will cause the FSR to wrap around.
ADDLW
Add literal and W
Syntax:
[ label ] ADDLW
Operands:
0 k 255
Operation:
(W) + k (W)
Status Affected:
C, DC, Z
Description:
The contents of the W register are

added to the eight-bit literal k and the
result is placed in the W register.
ADDWF
Add W and f
Syntax:
[ label ] ANDWF
Operands:
0 f 127
d 0,1
f,d
Operation:
(W) .AND. (f) (destination)
Status Affected:
Description:
AND the W register with register f. If

d is 0, the result is stored in the W
register. If d is 1, the result is stored
back in register f.
ASRF
Arithmetic Right Shift
Syntax:
[ label ] ADDWF
Syntax:
[ label ] ASRF
Operands:
0 f 127
d 0,1
Operands:
0 f 127
d [0,1]
Operation:
(W) + (f) (destination)
Operation:
(f<7>) dest<7>
(f<7:1>) dest<6:0>,
(f<0>) C,
f,d
Status Affected:
C, DC, Z
Description:
Add the contents of the W register

with register f. If d is 0, the result is
stored in the W register. If d is 1, the
result is stored back in register f.
ADDWFC
ADD W and CARRY bit to f
Syntax:
[ label ] ADDWFC
Operands:
0 f 127
d [0,1]
Status Affected:
C, Z
Description:
The contents of register f are shifted

one bit to the right through the Carry
flag. The MSb remains unchanged. If
d is 0, the result is placed in W. If d
is 1, the result is stored back in register f.
register f
f {,d}
Operation:
(W) + (f) + (C) dest
Status Affected:
C, DC, Z
Description:
Add W, the Carry flag and data memory location f. If d is 0, the result is
placed in W. If d is 1, the result is
placed in data memory location f.
f {,d}
Preliminary
DS41639A-page 343
PIC16(L)F1454/5/9
BCF
Bit Clear f
Syntax:
[ label ] BCF
BTFSC
f,b
Bit Test f, Skip if Clear
Syntax:
[ label ] BTFSC f,b

0 f 127
0b7
Operands:
0 f 127
0b7
Operands:
Operation:
0 (f<b>)
Operation:
skip if (f<b>) = 0
Status Affected:
None
Status Affected:
None
Description:
Bit b in register f is cleared.
Description:
If bit b in register f is 1, the next

instruction is executed.
If bit b, in register f, is 0, the next
instruction is discarded, and a NOP is
executed instead, making this a
2-cycle instruction.
BRA
Relative Branch
BTFSS
Bit Test f, Skip if Set
Syntax:
[ label ] BRA label

[ label ] BRA $+k
Syntax:
[ label ] BTFSS f,b
Operands:
Operands:
-256 label - PC + 1 255

-256 k 255
0 f 127
0b<7
Operation:
skip if (f<b>) = 1
Operation:
(PC) + 1 + k PC
Status Affected:
None
Status Affected:
None
Description:
Description:
Add the signed 9-bit literal k to the

PC. Since the PC will have incremented to fetch the next instruction,
the new address will be PC + 1 + k.
This instruction is a two-cycle instruction. This branch has a limited range.
If bit b in register f is 0, the next

instruction is executed.
If bit b is 1, then the next
instruction is discarded and a NOP is
executed instead, making this a
BRW
Relative Branch with W
Syntax:
[ label ] BRW
Operands:
None
Operation:
(PC) + (W) PC
Status Affected:
None
Description:
Add the contents of W (unsigned) to

the PC. Since the PC will have incremented to fetch the next instruction,
the new address will be PC + 1 + (W).
This instruction is a two-cycle instruction.
BSF
Bit Set f
Syntax:
[ label ] BSF
Operands:
0 f 127
0b7
Operation:
1 (f<b>)
Status Affected:
None
Description:
Bit b in register f is set.
DS41639A-page 344
f,b
Preliminary
PIC16(L)F1454/5/9
CALL
Call Subroutine
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CALL k
Syntax:
[ label ] CLRWDT
Operands:
0 k 2047
Operands:
None
Operation:
(PC)+ 1 TOS,
k PC<10:0>,
(PCLATH<4:3>) PC<12:11>
Operation:
Status Affected:
None
00h WDT
0 WDT prescaler,
1 TO
1 PD
Description:
Call Subroutine. First, return address

(PC + 1) is pushed onto the stack.
The eleven-bit immediate address is
loaded into PC bits <10:0>. The upper
bits of the PC are loaded from
PCLATH. CALL is a two-cycle instruction.
Status Affected:
TO, PD
Description:
CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler
of the WDT.
Status bits TO and PD are set.
CALLW
Subroutine Call With W
COMF
Complement f
Syntax:
[ label ] CALLW
Syntax:
[ label ] COMF
Operands:
None
Operands:
Operation:
(PC) +1 TOS,
(W) PC<7:0>,
(PCLATH<6:0>) PC<14:8>
0 f 127
d [0,1]
Operation:
(f) (destination)
Status Affected:
Description:
The contents of register f are complemented. If d is 0, the result is

stored in W. If d is 1, the result is
stored back in register f.
DECF
Decrement f
Syntax:
[ label ] DECF f,d
Status Affected:
None
Description:
Subroutine call with W. First, the

return address (PC + 1) is pushed
onto the return stack. Then, the contents of W is loaded into PC<7:0>,
and the contents of PCLATH into
PC<14:8>. CALLW is a two-cycle
instruction.
CLRF
Clear f
Syntax:
[ label ] CLRF
f,d
Operands:
0 f 127
Operands:
Operation:
00h (f)
1Z
0 f 127
d [0,1]
Operation:
(f) - 1 (destination)
Status Affected:
Status Affected:
Description:
The contents of register f are cleared

and the Z bit is set.
Description:
Decrement register f. If d is 0, the

result is stored in the W
back in register f.
CLRW
Clear W
Syntax:
[ label ] CLRW
Operands:
None
Operation:
00h (W)
1Z
Status Affected:
Description:
W register is cleared. Zero bit (Z) is

set.
Preliminary
DS41639A-page 345
PIC16(L)F1454/5/9
DECFSZ
Decrement f, Skip if 0
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ] DECFSZ f,d
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f) - 1 (destination);
skip if result = 0
Operation:
(f) + 1 (destination),
skip if result = 0
Status Affected:
None
Status Affected:
None
Description:
The contents of register f are decremented. If d is 0, the result is placed

in the W register. If d is 1, the result
is placed back in register f.
If the result is 1, the next instruction is
executed. If the result is 0, then a
NOP is executed instead, making it a
Description:
The contents of register f are incremented. If d is 0, the result is placed

If the result is 1, the next instruction is
executed. If the result is 0, a NOP is
executed instead, making it a 2-cycle
instruction.
GOTO
Unconditional Branch
IORLW
Inclusive OR literal with W
Syntax:
[ label ]
Syntax:
[ label ]
GOTO k
INCFSZ f,d
IORLW k
Operands:
0 k 2047
Operands:
0 k 255
Operation:
k PC<10:0>
PCLATH<4:3> PC<12:11>
Operation:
(W) .OR. k (W)
Status Affected:
Status Affected:
None
Description:
Description:
GOTO is an unconditional branch. The

eleven-bit immediate value is loaded
into PC bits <10:0>. The upper bits of
PC are loaded from PCLATH<4:3>.
GOTO is a two-cycle instruction.

ORed with the eight-bit literal k. The
result is placed in the W register.
INCF
Increment f
IORWF
Inclusive OR W with f
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operation:
(f) + 1 (destination)
Operation:
(W) .OR. (f) (destination)
Status Affected:
Status Affected:
Description:
The contents of register f are incremented. If d is 0, the result is placed

Description:
Inclusive OR the W register with register f. If d is 0, the result is placed in

the W register. If d is 1, the result is
placed back in register f.
DS41639A-page 346
INCF f,d
Preliminary
IORWF
f,d
PIC16(L)F1454/5/9
LSLF
Logical Left Shift
MOVF
f {,d}
Move f
Syntax:
[ label ] LSLF
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f<7>) C
(f<6:0>) dest<7:1>
0 dest<0>
Operation:
(f) (dest)
Status Affected:
C, Z
Description:

one bit to the left through the Carry flag.
A 0 is shifted into the LSb. If d is 0,
the result is placed in W. If d is 1, the
result is stored back in register f.
C
register f
Status Affected:
Description:
The contents of register f is moved to

a destination dependent upon the
status of d. If d = 0,
destination is W register. If d = 1, the
destination is file register f itself. d = 1
is useful to test a file register since
status flag Z is affected.
Words:
Cycles:
Example:
Logical Right Shift
Syntax:
[ label ] LSRF
Operands:
0 f 127
d [0,1]
Operation:
0 dest<7>
(f<7:1>) dest<6:0>,
(f<0>) C,
Status Affected:
C, Z
Description:

flag. A 0 is shifted into the MSb. If d is
0, the result is placed in W. If d is 1,
the result is stored back in register f.
f {,d}
register f
MOVF
FSR, 0
After Instruction
W = value in FSR register
Z = 1
LSRF
MOVF f,d
Preliminary
DS41639A-page 347
PIC16(L)F1454/5/9
MOVIW
Move INDFn to W
Syntax:
[ label ] MOVIW ++FSRn

[ label ] MOVIW --FSRn
[ label ] MOVIW FSRn++
[ label ] MOVIW FSRn-[ label ] MOVIW k[FSRn]
MOVLP
Operands:
n [0,1]
mm [00,01, 10, 11]
-32 k 31
Operation:
INDFn W
Effective address is determined by
FSR + 1 (preincrement)
FSR - 1 (predecrement)
FSR + k (relative offset)
After the Move, the FSR value will be
either:
FSR + 1 (all increments)
FSR - 1 (all decrements)
Unchanged
Status Affected:
Syntax:
[ label ] MOVLP k
Operands:
0 k 127
Operation:
k PCLATH
Status Affected:
None
Description:
The seven-bit literal k is loaded into the

PCLATH register.
MOVLW
Move literal to W
Syntax:
[ label ]
0 k 255
Operation:
k (W)
Status Affected:
None
Description:
The eight-bit literal k is loaded into W

register. The dont cares will assemble as 0s.
Words:
1
1
Mode
Syntax
mm
Cycles:
Preincrement
++FSRn
00
Example:
--FSRn
01
Postincrement
FSRn++
10
Postdecrement
FSRn--
11
Description:
Note: The INDFn registers are not

physical registers. Any instruction that
accesses an INDFn register actually
accesses the register at the address
specified by the FSRn.
Syntax:
[ label ] MOVLB k
Operands:
0 k 15
Operation:
k BSR
Status Affected:
None
Description:
The five-bit literal k is loaded into the

Bank Select Register (BSR).
DS41639A-page 348
0x5A
MOVWF
Move W to f
Syntax:
[ label ]
MOVWF
Operands:
0 f 127
Operation:
(W) (f)
0x5A
Status Affected:
None
Description:
Move data from W register to register

f.
Words:
Cycles:
Example:
FSRn is limited to the range 0000h FFFFh. Incrementing/decrementing it

beyond these bounds will cause it to
wrap-around.
Move literal to BSR
MOVLW
After Instruction
W =
This instruction is used to move data

between W and one of the indirect
registers (INDFn). Before/after this
move, the pointer (FSRn) is updated by
pre/post incrementing/decrementing it.
MOVLB
MOVLW k
Operands:
Predecrement
Move literal to PCLATH
Preliminary
MOVWF
OPTION_REG
Before Instruction
OPTION_REG =
W
=
After Instruction
OPTION_REG =
W
=
0xFF
0x4F
0x4F
0x4F
PIC16(L)F1454/5/9
MOVWI
Move W to INDFn
Syntax:
[ label ] MOVWI ++FSRn

[ label ] MOVWI --FSRn
[ label ] MOVWI FSRn++
[ label ] MOVWI FSRn-[ label ] MOVWI k[FSRn]
Operands:
Operation:
Status Affected:
n [0,1]
mm [00,01, 10, 11]
-32 k 31
W INDFn
Effective address is determined by
FSR + 1 (preincrement)
FSR - 1 (predecrement)
FSR + k (relative offset)
After the Move, the FSR value will be
either:
FSR + 1 (all increments)
FSR - 1 (all decrements)
Unchanged
None
Mode
Syntax
mm
Preincrement
++FSRn
00
Predecrement
--FSRn
01
Postincrement
FSRn++
10
Postdecrement
FSRn--
11
Description:
This instruction is used to move data

between W and one of the indirect
registers (INDFn). Before/after this
move, the pointer (FSRn) is updated by
pre/post incrementing/decrementing it.
Note: The INDFn registers are not

physical registers. Any instruction that
accesses an INDFn register actually
accesses the register at the address
specified by the FSRn.
NOP
No Operation
Syntax:
[ label ]
Operands:
None
Operation:
No operation
Status Affected:
None
Description:
No operation.
Words:
Cycles:
Example:
NOP
NOP
OPTION
Load OPTION_REG Register

with W
Syntax:
[ label ] OPTION
Operands:
None
Operation:
(W) OPTION_REG
Status Affected:
None
Description:
Move data from W register to

OPTION_REG register.
RESET
Software Reset
Syntax:
[ label ] RESET
Operands:
None
Operation:
Execute a device Reset. Resets the

nRI flag of the PCON register.
Status Affected:
None
Description:
This instruction provides a way to

execute a hardware Reset by software.
FSRn is limited to the range 0000h FFFFh. Incrementing/decrementing it

beyond these bounds will cause it to
wrap-around.
The increment/decrement operation on
FSRn WILL NOT affect any Status bits.
Preliminary
DS41639A-page 349
PIC16(L)F1454/5/9
RETFIE
Return from Interrupt
RETURN
Return from Subroutine
Syntax:
[ label ]
Syntax:
[ label ]
None
RETFIE
RETURN
Operands:
None
Operands:
Operation:
TOS PC,
1 GIE
Operation:
TOS PC
Status Affected:
None
Status Affected:
None
Description:
Description:
Return from Interrupt. Stack is POPed

and Top-of-Stack (TOS) is loaded in
the PC. Interrupts are enabled by
setting Global Interrupt Enable bit,
GIE (INTCON<7>). This is a two-cycle
instruction.
Return from subroutine. The stack is

POPed and the top of the stack (TOS)
is loaded into the program counter.
This is a two-cycle instruction.
Words:
Cycles:
Example:
RETFIE
After Interrupt
PC =
GIE =
TOS
1
RETLW
Return with literal in W
Syntax:
[ label ]
Operands:
0 k 255
Operation:
k (W);
TOS PC
Status Affected:
None
Description:
The W register is loaded with the eight

bit literal k. The program counter is
loaded from the top of the stack (the
return address). This is a two-cycle
instruction.
Words:
Cycles:
Example:
TABLE
RETLW k
Rotate Left f through Carry
Syntax:
[ label ]
Operands:
0 f 127
d [ 0, 1]
Operation:
See description below
Status Affected:
Description:
The contents of register f are rotated

one bit to the left through the Carry
flag. If d is 0, the result is placed in
RLF
C
CALL TABLE;W contains table
;offset value
;W now has table value
ADDWF PC ;W = offset
RETLW k1 ;Begin table
RETLW k2 ;
RETLW kn ; End of table
Before Instruction
W =
After Instruction
W =
DS41639A-page 350
RLF
Words:
Cycles:
Example:
RLF
f,d
Register f
REG1,0
Before Instruction
REG1
C
After Instruction
REG1
W
C
=
=
1110 0110
0
=
=
=
1110 0110
1100 1100
1
0x07
value of k8
Preliminary
PIC16(L)F1454/5/9
SUBLW
Subtract W from literal
Syntax:
[ label ]
RRF
Rotate Right f through Carry
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 k 255
Operation:
k - (W) W)
Operation:
See description below
Status Affected:
C, DC, Z
Status Affected:
Description:
Description:
The contents of register f are rotated

flag. If d is 0, the result is placed in
placed back in register f.
The W register is subtracted (2s complement method) from the eight-bit

literal k. The result is placed in the W
register.
RRF f,d
Register f
SUBLW k
C=0
Wk
C=1
Wk
DC = 0
W<3:0> k<3:0>
DC = 1
W<3:0> k<3:0>
SLEEP
Enter Sleep mode
SUBWF
Subtract W from f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
SLEEP
Operands:
None
Operation:
00h WDT,
0 WDT prescaler,
1 TO,
0 PD
Status Affected:
TO, PD
Description:
The power-down Status bit, PD is

cleared. Time-out Status bit, TO is
set. Watchdog Timer and its
prescaler are cleared.
The processor is put into Sleep mode
with the oscillator stopped.
SUBWF f,d
Operation:
(f) - (W) destination)
Status Affected:
C, DC, Z
Description:
Subtract (2s complement method) W

register from register f. If d is 0, the
result is stored in the W
back in register f.
C=0
Wf
C=1
Wf
DC = 0
W<3:0> f<3:0>
DC = 1
W<3:0> f<3:0>
SUBWFB
Subtract W from f with Borrow
Syntax:
SUBWFB
Operands:
0 f 127
d [0,1]
Operation:
(f) (W) (B) dest
f {,d}
Status Affected:
C, DC, Z
Description:
Subtract W and the BORROW flag

(CARRY) from register f (2s complement method). If d is 0, the result is
stored in W. If d is 1, the result is
Preliminary
DS41639A-page 351
PIC16(L)F1454/5/9
SWAPF
Swap Nibbles in f
XORLW
Exclusive OR literal with W
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operation:
SWAPF f,d
(f<3:0>) (destination<7:4>),
(f<7:4>) (destination<3:0>)
XORLW k
Operands:
0 k 255
Operation:
(W) .XOR. k W)
Status Affected:
Description:

XORed with the eight-bit
literal k. The result is placed in the
W register.
Status Affected:
None
Description:
The upper and lower nibbles of register f are exchanged. If d is 0, the

result is placed in the W register. If d
is 1, the result is placed in register f.
TRIS
Load TRIS Register with W
XORWF
Exclusive OR W with f
Syntax:
[ label ] TRIS f
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
5f7
Operation:
(W) TRIS register f
Status Affected:
None
Description:
DS41639A-page 352
Move data from W register to TRIS

register.
When f = 5, TRISA is loaded.
When f = 6, TRISB is loaded.
When f = 7, TRISC is loaded.
XORWF
f,d
Operation:
(W) .XOR. (f) destination)
Status Affected:
Description:
Exclusive OR the contents of the W

register with register f. If d is 0, the
result is stored in the W register. If d
is 1, the result is stored back in register f.
Preliminary
PIC16(L)F1454/5/9
29.0
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings()

Ambient temperature under bias....................................................................................................... -40C to +125C
Storage temperature ........................................................................................................................ -65C to +150C
Voltage on VDD with respect to VSS, PIC16LF1454/5/9 ..................................................................... -0.3V to +6.5V
Voltage on VDD with respect to VSS, PIC16LF1454/5/9 ..................................................................... -0.3V to +4.0V
Voltage on MCLR with respect to Vss ................................................................................................. -0.3V to +9.0V
Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V)
Total power dissipation(1) ............................................................................................................................... 800 mW
Maximum current out of VSS pin, -40C TA +85C for industrial............................................................... 396 mA
Maximum current out of VSS pin, -40C TA +125C for extended ............................................................ 114 mA
Maximum current into VDD pin, -40C TA +85C for industrial.................................................................. 292 mA
Maximum current into VDD pin, -40C TA +125C for extended ............................................................... 107 mA
Clamp current, IK (VPIN < 0 or VPIN > VDD) 20 mA
Maximum output current sunk by any I/O pin.................................................................................................... 25 mA
Maximum output current sourced by any I/O pin .............................................................................................. 25 mA
Note 1:
Power dissipation is calculated as follows: PDIS = VDD x {IDD IOH} + {(VDD VOH) x IOH} + (VOl x
IOL).
NOTICE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.
Preliminary
DS41639A-page 353
PIC16(L)F1454/5/9
PIC16F1454/5/9 VOLTAGE FREQUENCY GRAPH, -40C TA +125C
FIGURE 29-1:
VDD (V)
5.5
2.7
2.3
10
20
40
48
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 29-1 for each Oscillator modes supported frequencies.
PIC16LF1454/5/9 VOLTAGE FREQUENCY GRAPH, -40C TA +125C
VDD (V)
FIGURE 29-2:
3.6
2.7
1.8
0
10
20
40
48
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 29-1 for each Oscillator modes supported frequencies.
DS41639A-page 354
Preliminary
PIC16(L)F1454/5/9
29.1
DC Characteristics: PIC16(L)F1454/5/9-I/E (Industrial, Extended)
PIC16LF1454/5/9
Standard Operating Conditions (unless otherwise stated)

Operating temperature
-40C TA +85C for industrial
-40C TA +125C for extended
PIC16F1454/5/9

Param.
No.
D001
Sym.
VDD
Characteristic
VDR
VPOR*
VPORR*
Units
PIC16LF1454/5/9
1.8
2.5
3.6
3.6
V
V
FOSC 20 MHz
FOSC 48 MHz
PIC16F1454/5/9
2.3
2.5
5.5
5.5
V
V
FOSC 20 MHz
FOSC 48 MHz
PIC16LF1454/5/9
1.5
Device in Sleep mode
PIC16F1454/5/9
1.7
Device in Sleep mode
PIC16LF1454/5/9
1.6
PIC16F1454/5/9
1.7
V
V
Power-on Reset Rearm Voltage

PIC16LF1454/5/9
0.8
PIC16F1454/5/9
1.65
Fixed Voltage Reference Voltage for

ADC, Initial Accuracy
1
1
1
1
1
1
D003C* TCVFVR
Temperature Coefficient, Fixed

Voltage Reference
-130
ppm/C
D003D* VFVR/
VIN
Line Regulation, Fixed Voltage

Reference
0.270
%/V
D004*
VDD Rise Rate to ensure internal

Power-on Reset signal
0.05
V/ms
D002B
D003
VADFVR
SVDD
Conditions
Power-on Reset Release Voltage
D002A
D002B
Max.
RAM Data Retention Voltage(1)
D002*
D002A
Typ
Supply Voltage (VDDMIN, VDDMAX)
D001
D002*
Min.
1.024V, VDD 2.5V, 85C (NOTE 2)

1.024V, VDD 2.5V, 125C (NOTE 2)
2.048V, VDD 2.5V, 85C
2.048V, VDD 2.5V, 125C
4.096V, VDD 4.75V, 85C
4.096V, VDD 4.75V, 125C
See Section 6.1 Power-On Reset

(POR) for details.
Note
These parameters are characterized but not tested.

Data in Typ column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
2: For proper operation, the minimum value of the ADC positive voltage reference must be 1.8V or greater. When selecting
the FVR or the VREF+ pin as the source of the ADC positive voltage reference, be aware that the voltage must be 1.8V or
greater.
Preliminary
DS41639A-page 355
PIC16(L)F1454/5/9
FIGURE 29-3:
POR AND POR REARM WITH SLOW RISING VDD
VDD
VPOR
VPORR
VSS
NPOR
POR REARM
VSS
TVLOW(2)
Note 1:
2:
3:
DS41639A-page 356
TPOR(3)
When NPOR is low, the device is held in Reset.

TPOR 1 s typical.
TVLOW 2.7 s typical.
Preliminary
PIC16(L)F1454/5/9
29.2
DC Characteristics: PIC16(L)F1454/5/9-I/E (Industrial, Extended)
PIC16LF1454/5/9

PIC16F1454/5/9

Param
No.
Device
Characteristics
Conditions
Min.
Typ
Max.
Units
1.8
3.0
16
2.3
16
3.0
19
5.0
40
1.8
80
3.0
110
2.3
130
3.0
160
5.0
120
1.8
220
3.0
230
2.3
300
3.0
350
5.0
30
1.8
50
3.0
75
2.3
100
3.0
VDD
Note
Supply Current (IDD)(1, 2)

D010
D010
D011
D011
D012
D012
D013
D013
D014
D014
D015
D015
115
5.0
100
1.8
180
3.0
225
2.3
300
3.0
350
5.0
2.3
1.8
4.0
3.0
23
2.3
46
3.0
145
5.0
FOSC = 32 kHz LP Oscillator mode

FOSC = 32 kHz LP Oscillator mode
FOSC = 1 MHz XT Oscillator mode


FOSC = 1 MHz
EC Oscillator mode, Medium-power mode
FOSC = 1 MHz
EC Oscillator mode
Medium-power mode
FOSC = 4 MHz
EC Oscillator mode,
Medium-power mode
FOSC = 4 MHz
EC Oscillator mode
Medium-power mode
FOSC = 31 kHz
LFINTOSC mode
FOSC = 31 kHz
LFINTOSC mode

tested.
Note 1: The test conditions for all IDD measurements in active operation mode are: CLKIN = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended
by the formula IR = VDD/2REXT (mA) with REXT in k.
Preliminary
DS41639A-page 357
PIC16(L)F1454/5/9
29.2
DC Characteristics: PIC16(L)F1454/5/9-I/E (Industrial, Extended) (Continued)
PIC16LF1454/5/9

PIC16F1454/5/9

Param
No.
Device
Characteristics
Conditions
Min.
Typ
Max.
Units
220
1.8
280
3.0
340
2.3
410
3.0
535
5.0
380
1.8
560
3.0
720
2.3
920
3.0
1017
5.0
520
1.8
810
3.0
1000
2.3
1300
3.0
1600
5.0
D019A
750
3.0
FOSC = 20 MHz
ECH mode
D019A
1400
3.0
1600
5.0
FOSC = 20 MHz
ECH mode
D019B
1.8
FOSC = 32 kHz ECL mode
3.0
11
2.3
15
3.0
18
5.0
15
1.8
20
3.0
35
2.3
45
3.0
D016
D016
D017*
D017*
D018
D018
D019B
D019C
D019C
D020
D020
VDD
55
5.0
150
1.8
280
3.0
230
2.3
310
3.0
370
5.0
Note
FOSC = 500 kHz HFINTOSC mode
FOSC = 500 kHz HFINTOSC mode
FOSC = 8 MHz
HFINTOSC mode
FOSC = 8 MHz
HFINTOSC mode
FOSC = 16 MHz
HFINTOSC mode
FOSC = 16 MHz
HFINTOSC mode

FOSC = 4 MHz EXTRC mode (Note 3)

FOSC = 4 MHz EXTRC mode (Note 3)

tested.
consumption.
DS41639A-page 358
Preliminary
PIC16(L)F1454/5/9
29.2
DC Characteristics: PIC16(L)F1454/5/9-I/E (Industrial, Extended) (Continued)
PIC16LF1454/5/9

PIC16F1454/5/9

Param
No.
Device
Characteristics
Min.
Typ
Max.
Units
Conditions
VDD
Note
D021
1000
3.0
FOSC = 20 MHz HS Oscillator mode
D021
1350
3.0
FOSC = 20 MHz HS Oscillator mode
1700
5.0

tested.
consumption.
Preliminary
DS41639A-page 359
PIC16(L)F1454/5/9
29.3
DC Characteristics: PIC16(L)F1454/5/9-I/E (Power-Down)
PIC16LF1454/5/9

PIC16F1454/5/9

Param
No.
Device Characteristics
Power-down Current
D022
D022
D022A
D023
D023
D023A
D023A
Min.
Typ
Max.
+85C
Max.
+125C
Units
0.025
0.035
0.20
0.25
Conditions
VDD
Note
1.8
3.0
Base Current: WDT, BOR, FVR,

and SOSC disabled, all Peripherals inactive
2.3
3.0
0.30
5.0
10
2.3
11
3.0
12
5.0
0.29
1.8
0.39
3.0
10.5
2.3
11.3
3.0
12.5
5.0
14
1.8
23
3.0
23
2.3
30
3.0
5.0
(IPD)(2)
WDT, BOR, FVR, and SOSC disabled, all Peripherals inactive

(VREGPM = 1; Low-Power mode)
Base Current: WDT, BOR, FVR
and SOSC disabled, all peripheral
inactive (VREGPM = 0; Normal
Power mode)
LPWDT Current (Note 1)
LPWDT Current (Note 1)
FVR current (Note 1)

FVR current (Note 1)
34
D024
3.0
BOR Current (Note 1)
D024
15
3.0
BOR Current (Note 1)
17
5.0
D24A
0.1
3.0
LPBOR Current (Note 1)
D24A
11
3.0
LPBOR Current (Note 1)
12
5.0
Note 1:
2:
3:

Data in Typ column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are
not tested.
The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is
enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max
values should be used when calculating total current consumption.
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
A/D oscillator source is FRC.
DS41639A-page 360
Preliminary
PIC16(L)F1454/5/9
29.3
DC Characteristics: PIC16(L)F1454/5/9-I/E (Power-Down) (Continued)
PIC16LF1454/5/9

PIC16F1454/5/9

Param
No.
Device Characteristics
D025
D025
D026
D026
D026A*
D026A*
D027
D027
Note 1:
2:
3:
Conditions
Min.
Typ
Max.
+85C
Max.
+125C
Units
0.6
1.8
1.8
3.0
11
2.3
13
3.0
19
5.0
.025
1.8
.035
3.0
10
2.3
11
3.0
VDD
12
5.0
250
1.8
250
3.0
280
2.3
280
3.0
280
5.0
1.8
3.0
17
2.3
18
3.0
19
5.0
Note
SOSC Current (Note 1)
SOSC Current (Note 1)
A/D Current (Note 1, Note 3), no

conversion in progress
A/D Current (Note 1, Note 3), no
A/D Current (Note 1, Note 3),

A/D Current (Note 1, Note 3),
Comparator, Low-Power mode

(Note 1)
Comparator, Low-Power mode
(Note 1)

not tested.
The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is
enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max
values should be used when calculating total current consumption.
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
A/D oscillator source is FRC.
Preliminary
DS41639A-page 361
PIC16(L)F1454/5/9
29.4
DC Characteristics: PIC16(L)F1454/5/9-I/E
DC CHARACTERISTICS
Param
No.
Sym.
VIL
Characteristic

Operating temperature -40C TA +85C for industrial
Min.
Typ
Max.
Units
Conditions
Input Low Voltage

I/O PORT:
D030
0.8
4.5V VDD 5.5V
0.15 VDD
1.8V VDD 4.5V
with Schmitt Trigger buffer
0.2 VDD
2.0V VDD 5.5V
with SMBus
0.8
3.0 VDD
0.2 VDD
2.0
4.5V VDD 5.5V
0.25 VDD +
0.8
1.8V VDD 4.5V
with TTL buffer
D030A
D031
D032
MCLR
VIH
Input High Voltage

I/O ports:
D040
with TTL buffer
D040A
D041
with Schmitt Trigger buffer

with SMBus
D042
MCLR
IIL
0.8 VDD
2.0V VDD 5.5V
2.1
VDD
3.0 VDD
0.8 VDD
V
nA
Input Leakage Current(1)
D060
I/O ports
125
1000
nA
VSS VPIN VDD, Pin at highimpedance at 85C

125C
D061
MCLR(2)
50
200
nA
VSS VPIN VDD at 85C
25
25
100
140
200
300
VDD = 3.3V, VPIN = VSS

VDD = 5.0V, VPIN = VSS
0.6
IOL = 8mA, VDD = 5V

IOL = 6mA, VDD = 3.3V
IOL = 1.8mA, VDD = 1.8V
VDD - 0.7
IOH = 3.5mA, VDD = 5V

IOH = 3mA, VDD = 3.3V
IOH = 1mA, VDD = 1.8V
50
pF
IPUR
Weak Pull-up Current
D070*
VOL
D080
Output Low Voltage(3)

I/O ports
VOH
D090
Output High Voltage(3)

I/O ports
Capacitive Loading Specs on Output Pins

D101A* CIO
All I/O pins

not tested.
Note 1: Negative current is defined as current sourced by the pin.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Including OSC2 in CLKOUT mode.
DS41639A-page 362
Preliminary
PIC16(L)F1454/5/9
29.5
Memory Programming Requirements

Operating temperature -40C TA +125C
DC CHARACTERISTICS
Param
No.
Sym.
Characteristic
Min.
Typ
Max.
Units
Conditions
Program Memory
Programming Specifications
D110
VIHH
Voltage on MCLR/VPP pin
8.0
9.0
D111
IDDP
Supply Current during

Programming
10
mA
D112
VBE
VDD for Bulk Erase
2.7
VDDMAX
D113
VPEW
VDD for Write or Row Erase
VDDMIN
VDDMAX
D114
IPPPGM Current on MCLR/VPP during

Erase/Write
1.0
mA
D115
IDDPGM Current on VDD during Erase/

Write
5.0
mA
D121
EP
Cell Endurance
10K
E/W
(Note 2)
Program Flash Memory

-40C to +85C (Note 1)
D122
VPRW
VDD for Read/Write
VDDMIN
VDDMAX
D123
TIW
Self-timed Write Cycle Time
2.5
ms
D124
TRETD
Characteristic Retention
40
Year
Provided no other
specifications are violated
D125
EHEFC
High-Endurance Flash Cell
100K
E/W
0C to +60C lower byte,

last 128 addresses
Data in Typ column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Self-write and Block Erase.
2: Required only if single-supply programming is disabled.
Preliminary
DS41639A-page 363
PIC16(L)F1454/5/9
29.6
USB Module Specifications
Operating Conditions-40C TA +85C (unless otherwise state)

Param
No.
Sym
Characteristic
Min
Typ
Max
Units
Conditions
D313
VUSB
USB Voltage
3.0
3.6
Voltage on VUSB3V3 pin must be

in this range for proper USB
operation
D314
IIL
Input Leakage on pin
VSS VPIN VDD pin athigh

impedance
D315
VILUSB Input Low Voltage for USB

Buffer
0.8
For VUSB3V3 range
D316
VIHUSB Input High Voltage for USB

Buffer
2.0
For VUSB3V3 range
D318
VDIFS
Differential Input Sensitivity
0.2
The difference between D+ and

D- must exceed this value while
VCM is met
D319
VCM
Differential Common Mode

Range
0.8
2.5
D320
ZOUT
Driver Output Impedance(1)
28
44
D321
VOL
Voltage Output Low
0.0
0.3
1.5 kload connected to 3.6V
D322
VOH
Voltage Output High
2.8
3.6
1.5 kload connected to ground
Note 1: The D+ and D- signal lines have been built-in impedance matching resistors. No external resistors,
capacitors or magnetic components are necessary on the D+/D- signal paths between the
PIC16(L)F1454/5/9 family device and USB cable.
DS41639A-page 364
Preliminary
PIC16(L)F1454/5/9
29.7
Thermal Considerations

Operating temperature -40C TA +125C
Param
No.
TH01
TH02
Sym.
Characteristic
Typ.
Units
JA
Thermal Resistance Junction to Ambient
70
C/W
14-Pin PDIP package
95.3
C/W
14-Pin SOIC package
100
C/W
14-Pin TSSOP package
45.7
C/W
16-Pin QFN 4x4mm package
62.2
C/W
20-pin PDIP package
77.7
C/W
20-pin SOIC package
87.3
C/W
20-pin SSOP package
43.0
C/W
20-pin QFN 4x4mm package
32
C/W
14-Pin PDIP package
31
C/W
14-Pin SOIC package
24.4
C/W
14-Pin TSSOP package
6.3
C/W
16-Pin QFN 4x4mm package
27.5
C/W
20-pin PDIP package
23.1
C/W
20-pin SOIC package
31.1
C/W
20-pin SSOP package
5.3
C/W
20-pin QFN 4x4mm package
150
PD = PINTERNAL + PI/O
PINTERNAL = IDD x VDD(1)
JC
TH03
TJMAX
TH04
PD
TH05
Thermal Resistance Junction to Case
Maximum Junction Temperature

Power Dissipation
PINTERNAL Internal Power Dissipation
Conditions
TH06
PI/O
I/O Power Dissipation
PI/O = (IOL * VOL) + (IOH * (VDD - VOH))
TH07
PDER
Derated Power
PDER = PDMAX (TJ - TA)/JA(2)
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature
3: TJ = Junction Temperature
Preliminary
DS41639A-page 365
PIC16(L)F1454/5/9
29.8
Timing Parameter Symbology
The timing parameter symbols have been created with

one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
ck
CLKOUT
cs
CS
di
SDIx
do
SDO
dt
Data in
io
I/O PORT
mc
MCLR
Uppercase letters and their meanings:
S
F
Fall
H
High
I
Invalid (High-impedance)
L
Low
FIGURE 29-4:
Time
osc
rd
rw
sc
ss
t0
t1
wr
CLKIN
RD
RD or WR
SCKx
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
High-impedance
LOAD CONDITIONS
Load Condition
Pin
CL
VSS
Legend: CL = 50 pF for all pins
DS41639A-page 366
Preliminary
PIC16(L)F1454/5/9
29.9
AC Characteristics: PIC16(L)F1454/5/9-I/E
FIGURE 29-5:
CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
CLKIN
OS12
OS02
OS11
OS03
CLKOUT
(CLKOUT Mode)
Note
See Table 29-3 for timing information.
1:
TABLE 29-1:
CLOCK OSCILLATOR TIMING REQUIREMENTS

-40C TA +125C
Param
No.
OS01
Sym.
FOSC
Characteristic
External CLKIN Frequency(1)
Min.
Typ
Max.
Units
Conditions
DC
0.5
MHz
EC Oscillator mode (low)
DC
MHz
EC Oscillator mode (medium)
DC
20
MHz
EC Oscillator mode (high)
OS02
TOSC
External CLKIN Period(1)
31.25
ns
EC mode
OS03
TCY
Instruction Cycle Time(1)
125
DC
ns
TCY = FOSC/4

tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at min values with an external clock applied to CLKIN pin. When an external
clock input is used, the max cycle time limit is DC (no clock) for all devices.
TABLE 29-2:
OSCILLATOR PARAMETERS

Operating Temperature
-40C TA +125C
Param
No.
OS08
Sym.
HFOSC
OS08A HFTOL
Characteristic
Min.
Typ
Max.
Units
Internal Calibrated HFINTOSC Frequency(1)
16.0
MHz
Frequency Tolerance
+25C, 16 MHz
0C TA +85C, 16 MHz
OS09
LFOSC
Internal LFINTOSC Frequency
31
kHz
OS10*
TIOSC ST
HFINTOSC
Wake-up from Sleep Start-up Time
OS11*
TUNELOCK HFINTOSC
Self-tune Lock Time
<5
mS
Conditions
0C TA +85C
-40C TA +125C
NOTE 2

not tested.
Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
2: Time for reference clock stable and in range to HFINTOSC tuned within range specified by OS08A (with Self-Tune).
Preliminary
DS41639A-page 367
PIC16(L)F1454/5/9
FIGURE 29-6:
CLKOUT AND I/O TIMING
Cycle
Write
Fetch
Read
Execute
Q4
Q1
Q2
Q3
FOSC
OS12
OS11
OS20
OS21
CLKOUT
OS19
OS18
OS16
OS13
OS17
I/O pin
(Input)
OS14
OS15
I/O pin
(Output)
New Value
Old Value
OS18, OS19
TABLE 29-3:
CLKOUT AND I/O TIMING PARAMETERS

Operating Temperature -40C TA +125C
Param
No.
OS11
Sym.
TosH2ckL
Characteristic
Min.
Typ
Max.
Units
Conditions
FOSC to CLKOUT (1)
70
ns
VDD = 3.3-5.0V
(1)
72
ns
VDD = 3.3-5.0V
20
ns
TOSC + 200 ns
50
50
70*
ns
ns
ns
20
ns
25
25
15
40
28
15
32
72
55
30
ns
OS12
TosH2ckH FOSC to CLKOUT
OS13
TckL2ioV
CLKOUT to Port out valid(1)
OS14
OS15
OS16
TioV2ckH
TosH2ioV
TosH2ioI
OS17
TioV2osH
OS18* TioR
Port input valid before CLKOUT(1)

Fosc (Q1 cycle) to Port out valid
Fosc (Q2 cycle) to Port input invalid
(I/O in hold time)
Port input valid to Fosc(Q2 cycle)
(I/O in setup time)
Port output rise time(2)
OS19* TioF
Port output fall time(2)
OS20* Tinp
OS21* Tioc
INT pin input high or low time

Interrupt-on-change new input level
time
* These parameters are characterized but not tested.
Data in Typ column is at 3.0V, 25C unless otherwise stated.
Note 1: Measurements are taken in EC mode where CLKOUT output is 4 x TOSC.
DS41639A-page 368
Preliminary
ns
VDD = 3.3-5.0V
VDD = 3.3-5.0V
VDD = 2.0V
VDD = 5.0V
VDD = 2.0V
VDD = 5.0V
ns
ns
PIC16(L)F1454/5/9
FIGURE 29-7:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
Internal Reset(1)
Watchdog Timer
Reset(1)
31
34
34
I/O pins
Note 1: Asserted low.
FIGURE 29-8:
BROWN-OUT RESET TIMING AND CHARACTERISTICS
VDD
VBOR and VHYST
VBOR
(Device in Brown-out Reset)
(Device not in Brown-out Reset)
37
Reset
33(1)
(due to BOR)
Note 1: 64 ms delay only if PWRTE bit in the Configuration Words is programmed to 0.

2 ms delay if PWRTE = 0 and VREGEN = 1.
Preliminary
DS41639A-page 369
PIC16(L)F1454/5/9
TABLE 29-4:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER

AND BROWN-OUT RESET PARAMETERS

Param
No.
Sym.
Characteristic
Min.
Typ
Max.
Units
Conditions
2
5
s
s
VDD = 3.3-5V, -40C to +85C

VDD = 3.3-5V
10
16
27
ms
VDD = 3.3V-5V,
1:16 Prescaler used
30
TMCL
31
TWDTLP Low-Power Watchdog Timer

Time-out Period
33*
TPWRT
Power-up Timer Period, PWRTE = 0
40
65
140
ms
34*
TIOZ
I/O high-impedance from MCLR Low

or Watchdog Timer Reset
2.0
35
VBOR
Brown-out Reset Voltage(2)
2.55
1.80
2.70
1.90
2.85
2.11
V
V
36*
VHYST
Brown-out Reset Hysteresis
25
50
mV
-40C to +85C
37*
TBORDC Brown-out Reset DC Response

Time
VDD VBOR
1.8
2.1
2.5
LPBOR = 1
38*
VLPOR
MCLR Pulse Width (low)
Low-Power Brown-out
BORV = 0
BORV = 1

Note 1: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as
2: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as
FIGURE 29-9:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
40
41
42
T1CKI
45
46
47
49
TMR0 or
TMR1
DS41639A-page 370
Preliminary
PIC16(L)F1454/5/9
TABLE 29-5:
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Param
No.
40*
Sym.
TT0H
Characteristic
T0CKI High Pulse Width
Min.
No Prescaler
TT0L
T0CKI Low Pulse Width
No Prescaler
TT0P
T0CKI Period
45*
TT1H
T1CKI High Synchronous, No Prescaler

Time
Synchronous,
with Prescaler
ns
ns
0.5 TCY + 20
ns
10
ns
Greater of:
20 or TCY + 40
N
ns
0.5 TCY + 20
ns
15
ns
Asynchronous
46*
TT1L
T1CKI Low
Time
Units
10
With Prescaler
42*
Max.
0.5 TCY + 20
With Prescaler
41*
Typ
30
ns
Synchronous, No Prescaler
0.5 TCY + 20
ns
Synchronous, with Prescaler
15
ns
Asynchronous
30
ns
Greater of:
30 or TCY + 40
N
ns
47*
TT1P
49*
TCKEZTMR1 Delay from External Clock Edge to Timer

Increment
T1CKI Input Synchronous

Period
Asynchronous
60
ns
2 TOSC
7 TOSC
Conditions
N = prescale value
(2, 4, ..., 256)
N = prescale value
(1, 2, 4, 8)
Timers in Sync
mode

tested.
Note 1: For proper operation, the minimum value of the ADC positive voltage reference must be 1.8V or greater.
TABLE 29-6:
PIC16(L)F1454/5/9 A/D CONVERTER (ADC) CHARACTERISTICS:

Operating temperature Tested at 25C
Param
Sym.
No.
Characteristic
Min.
Typ
Max.
Units
Conditions
AD01
NR
Resolution
10
AD02
EIL
Integral Error
1.7
AD03
EDL
Differential Error
AD04
EOFF Offset Error
2.5
LSb VREF = 3.0V
AD05
EGN
2.0
LSb VREF = 3.0V
AD06
VREF Reference Voltage(3)
1.8
VDD
AD07
VAIN
Full-Scale Range
VSS
VREF
AD08
ZAIN
Recommended Impedance of
Analog Voltage Source
10
Note 1:
2:
3:
4:
Gain Error
bit
LSb VREF = 3.0V
LSb No missing codes
VREF = 3.0V
VREF = (VREF+ minus VREF-)

Can go higher if external 0.01F capacitor is
present on input pin.

tested.
Total Absolute Error includes integral, differential, offset and gain errors.
The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
ADC VREF is from external VREF+ pin, VDD pin, whichever is selected as reference input.
When ADC is off, it will not consume any current other than leakage current. The power-down current specification
includes any such leakage from the ADC module.
Preliminary
DS41639A-page 371
PIC16(L)F1454/5/9
TABLE 29-7:
PIC16(L)F1454/5/9 A/D CONVERSION REQUIREMENTS

-40C TA +125C
Param
No.
Sym.
Characteristic
AD130* TAD
AD131
TCNV
AD132* TACQ
Min.
Typ
Max.
Units
Conditions
A/D Clock Period
1.0
9.0
TOSC-based
A/D Internal FRC Oscillator

Period
1.0
1.6
6.0
ADCS<1:0> = 11 (ADFRC mode)
Conversion Time (not including

Acquisition Time)(1)
11
TAD
Set GO/DONE bit to conversion

complete
Acquisition Time
5.0

tested.
Note 1: The ADRES register may be read on the following TCY cycle.
FIGURE 29-10:
PIC16(L)F1454/5/9 A/D CONVERSION TIMING (NORMAL MODE)
BSF ADCON0, GO
AD134
1 TCY
(TOSC/2(1))
AD131
Q4
AD130
A/D CLK
9
A/D Data
OLD_DATA
ADRES
0
NEW_DATA
1 TCY
ADIF
GO
Sample
DONE
AD132
Sampling Stopped
Note 1: If the A/D clock source is selected as FRC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
DS41639A-page 372
Preliminary
PIC16(L)F1454/5/9
FIGURE 29-11:
PIC16(L)F1454/5/9 A/D CONVERSION TIMING (SLEEP MODE)
BSF ADCON0, GO
AD134
(TOSC/2 + TCY(1))
1 TCY
AD131
Q4
AD130
A/D CLK
9
A/D Data
OLD_DATA
ADRES
0
NEW_DATA
ADIF
1 TCY
GO
DONE
Sample
AD132
Sampling Stopped
Note 1: If the A/D clock source is selected as FRC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
Preliminary
DS41639A-page 373
PIC16(L)F1454/5/9
TABLE 29-8:
COMPARATOR SPECIFICATIONS
Operating Conditions: 1.8V < VDD < 5.5V, -40C < TA < +125C (unless otherwise stated).
Param
No.
Sym.
Characteristics
CM01
VIOFF
Input Offset Voltage
CM02
VICM
Min.
Typ.
Max.
Units
Comments
7.5
60
mV
High Power mode

VICM = VDD/2
Input Common Mode Voltage
VDD
CM04A
Response Time Rising Edge
400
800
ns
High-Power mode
(Note 1)
CM04B
Response Time Falling Edge
200
400
ns
High-Power mode
(Note 1)
Response Time Rising Edge
1200
ns
Low-Power mode
(Note 1)
Response Time Falling Edge
550
ns
Low-Power mode
(Note 1)
Comparator Mode Change to

Output Valid*
10
65
mV
CM04C
TRESP
CM04D
CM05
TMC2OV
CM06
CHYSTER Comparator Hysteresis
*
Note 1:
2:
Note 2

Response time measured with one comparator input at VDD/2, while the other input transitions
from VSS to VDD.
Comparator Hysteresis is available when the CxHYS bit of the CMxCON0 register is enabled.
TABLE 29-9:
DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS
Operating Conditions: 1.8V < VDD < 5.5V, -40C < TA < +125C (unless otherwise stated).
Param
No.
Sym.
Characteristics
Min.
Typ.
Max.
Units
DAC01*
CLSB
Step Size
VDD/32
DAC02*
CACC
Absolute Accuracy
1/2
LSb
DAC03*
CR
Unit Resistor Value (R)
5K
DAC04*
CST
Settling Time(1)
10
*
Note 1:
Comments

Settling time measured while DACR<4:0> transitions from 0000 to 1111.
DS41639A-page 374
Preliminary
PIC16(L)F1454/5/9
FIGURE 29-12:
USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
CK
US121
US121
DT
US122
US120
Note:
Refer to Figure 29-4 for load conditions.
TABLE 29-10: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS

-40C TA +125C
Param.
No.
Symbol
Characteristic
Min.
Max.
Units
US120 TCKH2DTV SYNC XMIT (Master and Slave)

Clock high to data-out valid
3.0-5.5V
80
ns
1.8-5.5V
100
ns
US121 TCKRF
Clock out rise time and fall time

(Master mode)
3.0-5.5V
45
ns
1.8-5.5V
50
ns
Data-out rise time and fall time
3.0-5.5V
45
ns
1.8-5.5V
50
ns
US122 TDTRF
FIGURE 29-13:
Conditions
USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING

CK
US125
DT
US126
Note: Refer to Figure 29-4 for load conditions.
TABLE 29-11: USART SYNCHRONOUS RECEIVE REQUIREMENTS

-40C TA +125C
Param.
No.
Symbol
Characteristic
US125 TDTV2CKL SYNC RCV (Master and Slave)

Data-hold before CK (DT hold time)
US126 TCKL2DTL
Data-hold after CK (DT hold time)
Preliminary
Min.
Max.
Units
10
ns
15
ns
Conditions
DS41639A-page 375
PIC16(L)F1454/5/9
FIGURE 29-14:
SPI MASTER MODE TIMING (CKE = 0, SMP = 0)
SS
SP70
SCK
(CKP = 0)
SP71
SP72
SP78
SP79
SP79
SP78
SCK
(CKP = 1)
SP80
bit 6 - - - - - -1
MSb
SDO
LSb
SP75, SP76
SDI
MSb In
bit 6 - - - -1
LSb In
SP74
SP73
FIGURE 29-15:
SPI MASTER MODE TIMING (CKE = 1, SMP = 1)
SS
SP81
SCK
(CKP = 0)
SP71
SP72
SP79
SP73
SCK
(CKP = 1)
SP80
SDO
MSb
SP78
bit 6 - - - - - -1
LSb
SP75, SP76
SDI
MSb In
bit 6 - - - -1
LSb In
SP74
DS41639A-page 376
Preliminary
PIC16(L)F1454/5/9
FIGURE 29-16:
SPI SLAVE MODE TIMING (CKE = 0)
SS
SP70
SCK
(CKP = 0)
SP83
SP71
SP72
SP78
SP79
SP79
SP78
SCK
(CKP = 1)
SP80
MSb
SDO
LSb
bit 6 - - - - - -1
SP77
SP75, SP76
SDI
MSb In
bit 6 - - - -1
LSb In
SP74
SP73
FIGURE 29-17:
SS
SPI SLAVE MODE TIMING (CKE = 1)

SP82
SP70
SP83
SCK
(CKP = 0)
SP71
SP72
SCK
(CKP = 1)
SP80
MSb
SDO
bit 6 - - - - - -1
LSb
SP77
SP75, SP76
SDI
MSb In
bit 6 - - - -1
LSb In
SP74
Preliminary
DS41639A-page 377
PIC16(L)F1454/5/9
TABLE 29-12: SPI MODE REQUIREMENTS
Param
No.
Symbol
Characteristic
SP70* TSSL2SCH, SS to SCK or SCK input

TSSL2SCL
Min.
Typ
Max. Units Conditions
TCY
ns
SP71* TSCH
SCK input high time (Slave mode)
TCY + 20
ns
SP72* TSCL
SCK input low time (Slave mode)
TCY + 20
ns
100
ns
100
ns
3.0-5.5V
10
25
ns
1.8-5.5V
25
50
ns
10
25
ns
SP73* TDIV2SCH, Setup time of SDI data input to SCK edge

TDIV2SCL
SP74* TSCH2DIL,
TSCL2DIL
Hold time of SDI data input to SCK edge
SP75* TDOR
SDO data output rise time
SP76* TDOF
SDO data output fall time
SP77* TSSH2DOZ
SS to SDO output high-impedance
10
50
ns
SP78* TSCR
SCK output rise time

(Master mode)
3.0-5.5V
10
25
ns
1.8-5.5V
25
50
ns
SP79* TSCF
SCK output fall time (Master mode)
10
25
ns
3.0-5.5V
50
ns
1.8-5.5V
145
ns
Tcy
ns
50
ns
1.5TCY + 40
ns
SP80* TSCH2DOV, SDO data output valid after

TSCL2DOV SCK edge
SP81* TDOV2SCH, SDO data output setup to SCK edge

TDOV2SCL
SP82* TSSL2DOV
SDO data output valid after SS edge
SP83* TSCH2SSH, SS after SCK edge

TSCL2SSH
* These parameters are characterized but not tested.

DS41639A-page 378
Preliminary
PIC16(L)F1454/5/9
FIGURE 29-18:
I2C BUS START/STOP BITS TIMING
SCL
SP93
SP91
SP90
SP92
SDA
Stop
Condition
Start
Condition
TABLE 29-13: I2C BUS START/STOP BITS REQUIREMENTS

Param
No.
Symbol
SP90*
TSU:STA
SP91*
THD:STA
SP92*
TSU:STO
SP93
Characteristic
Typ
Max. Units
Start condition
100 kHz mode
4700
Setup time
400 kHz mode
600
Start condition
100 kHz mode
4000
Hold time
400 kHz mode
600
Stop condition
100 kHz mode
4700
Setup time
400 kHz mode
600
100 kHz mode
4000
400 kHz mode
600
THD:STO Stop condition

Hold time
*
Min.
Conditions
ns
Only relevant for Repeated

Start condition
ns
After this period, the first

clock pulse is generated
ns
ns
FIGURE 29-19:
I2C BUS DATA TIMING

SP103
SCL
SP100
SP90
SP102
SP101
SP106
SP107
SP91
SDA
In
SP92
SP110
SP109
SP109
SDA
Out
Preliminary
DS41639A-page 379
PIC16(L)F1454/5/9
TABLE 29-14: I2C BUS DATA REQUIREMENTS
Param.
No.
Symbol
SP100* THIGH
Characteristic
Clock high time
Min.
Max.
Units
100 kHz mode
4.0
Device must operate at a

minimum of 1.5 MHz
400 kHz mode
0.6

minimum of 10 MHz
1.5TCY
100 kHz mode
4.7

minimum of 1.5 MHz
400 kHz mode
1.3

minimum of 10 MHz
SSP module
SP101* TLOW
Clock low time
1.5TCY
SDA and SCL rise

time
100 kHz mode
1000
ns
400 kHz mode
20 + 0.1CB
300
ns
SDA and SCL fall

time
100 kHz mode
250
ns
400 kHz mode
20 + 0.1CB
250
ns
SSP module
SP102* TR
SP103* TF
SP106* THD:DAT
SP107* TSU:DAT
SP109* TAA
SP110*
SP111
*
Note 1:
2:
TBUF
CB
Data input hold time 100 kHz mode
ns
400 kHz mode
0.9
Data input setup

time
Output valid from
clock
Bus free time
Conditions
100 kHz mode
250
ns
400 kHz mode
100
ns
100 kHz mode
3500
ns
400 kHz mode
ns
100 kHz mode
4.7
400 kHz mode
1.3
400
pF
Bus capacitive loading
CB is specified to be from
10-400 pF
CB is specified to be from
10-400 pF
(Note 2)
(Note 1)
Time the bus must be free

before a new transmission
can start

As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but
the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does
not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal,
it must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to
the Standard mode I2C bus specification), before the SCL line is released.
DS41639A-page 380
Preliminary
PIC16(L)F1454/5/9
NOTES:
Preliminary
DS41639A-page 381
PIC16(L)F1454/5/9
DS41639A-page 382
Preliminary
PIC16(L)F1454/5/9
30.0
DC AND AC
CHARACTERISTICS GRAPHS
AND CHARTS
Graphs and charts are not available at this time.
Preliminary
DS41639A-page 383
PIC16(L)F1454/5/9
NOTES:
DS41639A-page 384
Preliminary
PIC16(L)F1454/5/9
31.0
DEVELOPMENT SUPPORT
31.1
The PIC microcontrollers and dsPIC digital signal

controllers are supported with a full range of software
and hardware development tools:
Integrated Development Environment
- MPLAB IDE Software
Compilers/Assemblers/Linkers
- MPLAB C Compiler for Various Device
Families
- HI-TECH C for Various Device Families
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
Simulators
- MPLAB SIM Software Simulator
Emulators
- MPLAB REAL ICE In-Circuit Emulator
In-Circuit Debuggers
- MPLAB ICD 3
- PICkit 3 Debug Express
Device Programmers
- PICkit 2 Programmer
- MPLAB PM3 Device Programmer
Low-Cost Demonstration/Development Boards,
Evaluation Kits, and Starter Kits
MPLAB Integrated Development

Environment Software
The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16/32-bit
microcontroller market. The MPLAB IDE is a Windows
operating system-based application that contains:
A single graphical interface to all debugging tools
- Simulator
- Programmer (sold separately)
- In-Circuit Emulator (sold separately)
- In-Circuit Debugger (sold separately)
A full-featured editor with color-coded context
A multiple project manager
Customizable data windows with direct edit of
contents
High-level source code debugging
Mouse over variable inspection
Drag and drop variables from source to watch
windows
Extensive on-line help
Integration of select third party tools, such as
IAR C Compilers
The MPLAB IDE allows you to:
Edit your source files (either C or assembly)
One-touch compile or assemble, and download to
emulator and simulator tools (automatically
updates all project information)
Debug using:
- Source files (C or assembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
Preliminary
DS41639A-page 385
PIC16(L)F1454/5/9
31.2
MPLAB C Compilers for Various

Device Families
The MPLAB C Compiler code development systems

are complete ANSI C compilers for Microchips PIC18,
PIC24 and PIC32 families of microcontrollers and the
dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration
capabilities, superior code optimization and ease of
use.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
31.3
HI-TECH C for Various Device

Families
For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE
debugger.
The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple
platforms.
MPASM Assembler
The MPASM Assembler is a full-featured, universal

macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
MPLINK Object Linker/

MPLIB Object Librarian
The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
The HI-TECH C Compiler code development systems

are complete ANSI C compilers for Microchips PIC
family of microcontrollers and the dsPIC family of digital
signal controllers. These compilers provide powerful
integration capabilities, omniscient code generation
and ease of use.
31.4
31.5
Efficient linking of single libraries instead of many

smaller files
Enhanced code maintainability by grouping
related modules together
Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
31.6
MPLAB Assembler, Linker and

Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine

code from symbolic assembly language for PIC24,
PIC32 and dsPIC devices. MPLAB C Compiler uses
the assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
Support for the entire device instruction set

Support for fixed-point and floating-point data
Command line interface
Rich directive set
Flexible macro language
MPLAB IDE compatibility
Integration into MPLAB IDE projects

User-defined macros to streamline
assembly code
Conditional assembly for multi-purpose
source files
Directives that allow complete control over the
assembly process
DS41639A-page 386
Preliminary
PIC16(L)F1454/5/9
31.7
MPLAB SIM Software Simulator
31.9
The MPLAB SIM Software Simulator allows code

development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C Compilers,
and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and
debug code outside of the hardware laboratory environment, making it an excellent, economical software
development tool.
31.8
MPLAB REAL ICE In-Circuit

Emulator System
MPLAB REAL ICE In-Circuit Emulator System is

Microchips next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC Flash MCUs and dsPIC Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The emulator is connected to the design engineers PC
using a high-speed USB 2.0 interface and is connected
to the target with either a connector compatible with incircuit debugger systems (RJ11) or with the new highspeed, noise tolerant, Low-Voltage Differential Signal
(LVDS) interconnection (CAT5).
The emulator is field upgradable through future firmware
downloads in MPLAB IDE. In upcoming releases of
MPLAB IDE, new devices will be supported, and new
features will be added. MPLAB REAL ICE offers
significant advantages over competitive emulators
including low-cost, full-speed emulation, run-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
MPLAB ICD 3 In-Circuit Debugger

System
MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost effective high-speed hardware
debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU)
devices. It debugs and programs PIC Flash microcontrollers and dsPIC DSCs with the powerful, yet easyto-use graphical user interface of MPLAB Integrated
Development Environment (IDE).
The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a high-speed
USB 2.0 interface and is connected to the target with a
connector compatible with the MPLAB ICD 2 or MPLAB
REAL ICE systems (RJ-11). MPLAB ICD 3 supports all
MPLAB ICD 2 headers.
31.10 PICkit 3 In-Circuit Debugger/

Programmer and
PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and programming of PIC and dsPIC Flash microcontrollers at a
most affordable price point using the powerful graphical
user interface of the MPLAB Integrated Development
Environment (IDE). The MPLAB PICkit 3 is connected
to the design engineer's PC using a full speed USB
interface and can be connected to the target via an
Microchip debug (RJ-11) connector (compatible with
MPLAB ICD 3 and MPLAB REAL ICE). The connector
uses two device I/O pins and the reset line to implement in-circuit debugging and In-Circuit Serial Programming.
The PICkit 3 Debug Express include the PICkit 3, demo
board and microcontroller, hookup cables and CDROM
with users guide, lessons, tutorial, compiler and
MPLAB IDE software.
Preliminary
DS41639A-page 387
PIC16(L)F1454/5/9
31.11 PICkit 2 Development
Programmer/Debugger and
PICkit 2 Debug Express
31.13 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
The PICkit 2 Development Programmer/Debugger is

a low-cost development tool with an easy to use interface for programming and debugging Microchips Flash
families of microcontrollers. The full featured
Windows programming interface supports baseline
(PIC10F,
PIC12F5xx,
PIC16F5xx),
midrange
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,
dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit
microcontrollers, and many Microchip Serial EEPROM
products. With Microchips powerful MPLAB Integrated
Development Environment (IDE) the PICkit 2
enables in-circuit debugging on most PIC microcontrollers. In-Circuit-Debugging runs, halts and single
steps the program while the PIC microcontroller is
embedded in the application. When halted at a breakpoint, the file registers can be examined and modified.
A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The PICkit 2 Debug Express include the PICkit 2, demo

board and microcontroller, hookup cables and CDROM
with users guide, lessons, tutorial, compiler and
MPLAB IDE software.
31.12 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modular, detachable socket assembly to support various
package types. The ICSP cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an MMC card for file
storage and data applications.
DS41639A-page 388
The boards support a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM and dsPICDEM demonstration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
for analog filter design, KEELOQ security ICs, CAN,
IrDA, PowerSmart battery management, SEEVAL
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
Preliminary
PIC16(L)F1454/5/9
32.0
PACKAGING INFORMATION
32.1
Package Marking Information
14-Lead PDIP (300 mil)
Example
PIC16F1454
-E/P e3
1220123
14-Lead SOIC (3.90 mm)
Example
PIC16F1455
-E/SL e3
1220123
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week 01)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
Standard PICmicro device marking consists of Microchip part number, year code, week code and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
Preliminary
DS41639A-page 389
PIC16(L)F1454/5/9
14-Lead TSSOP (4.4 mm)
Example
XXXXXXXX
YYWW
NNN
F1454EST
1220
123
16-Lead QFN (4x4x0.9 mm)
Example
PIN 1
PIN 1
20-Lead PDIP (300 mil)
Example
PIC16F1459
-E/P e3
1220123
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
DS41639A-page 390
PIC16
F1455
E/ML e3
220123
Preliminary
PIC16(L)F1454/5/9
20-Lead SOIC (7.50 mm)
Example
PIC16F1459
-E/SO e3
1220123
20-Lead SSOP (5.30 mm)
Example
PIC16F1459
-E/SS e3
1220123
Example
20-Lead QFN (4x4x0.9 mm)
PIN 1
PIN 1
Preliminary
PIC16
F1459
E/ML e3
220123
DS41639A-page 391
PIC16(L)F1454/5/9
32.2
Package Details
The following sections give the technical details of the packages.

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DS41639A-page 392
Preliminary
PIC16(L)F1454/5/9
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Preliminary
DS41639A-page 393
PIC16(L)F1454/5/9
Note:
DS41639A-page 394
Preliminary
PIC16(L)F1454/5/9
Note:
Preliminary
DS41639A-page 395
PIC16(L)F1454/5/9
Note:
DS41639A-page 396
Preliminary
PIC16(L)F1454/5/9
Note:
Preliminary
DS41639A-page 397
PIC16(L)F1454/5/9
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Preliminary
PIC16(L)F1454/5/9
Note:
Preliminary
DS41639A-page 399
PIC16(L)F1454/5/9
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Preliminary
PIC16(L)F1454/5/9
Note:
Preliminary
DS41639A-page 401
PIC16(L)F1454/5/9
Note:
DS41639A-page 402
Preliminary
PIC16(L)F1454/5/9
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DS41639A-page 403
PIC16(L)F1454/5/9
Note:
DS41639A-page 404
Preliminary
PIC16(L)F1454/5/9
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DS41639A-page 405
PIC16(L)F1454/5/9

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DS41639A-page 406
Preliminary
PIC16(L)F1454/5/9
APPENDIX A:
DATA SHEET
REVISION HISTORY
Revision A (06/2012)
Initial release.
Preliminary
DS41639A-page 407
PIC16(L)F1454/5/9
NOTES:
DS41639A-page 408
Preliminary
PIC16(L)F1454/5/9
INDEX
A
A/D
Specifications.................................................... 371, 372
Absolute Maximum Ratings .............................................. 353
AC Characteristics
Industrial and Extended ............................................ 367
Load Conditions ........................................................ 366
ACKSTAT ......................................................................... 238
ACKSTAT Status Flag ...................................................... 238
ADC .................................................................................. 153
Acquisition Requirements ......................................... 165
Associated registers.................................................. 167
Block Diagram........................................................... 154
Calculating Acquisition Time..................................... 165
Channel Selection..................................................... 155
Configuration............................................................. 155
Configuring Interrupt ................................................. 159
Conversion Clock...................................................... 155
Conversion Procedure .............................................. 159
Internal Sampling Switch (RSS) Impedance.............. 165
Interrupts................................................................... 157
Operation .................................................................. 158
Operation During Sleep ............................................ 158
Port Configuration ..................................................... 155
Reference Voltage (VREF)......................................... 155
Source Impedance.................................................... 165
Starting an A/D Conversion ...................................... 157
ADCON0 Register....................................................... 38, 160
ADCON1 Register....................................................... 38, 161
ADCON2 Register............................................................. 162
ADDFSR ........................................................................... 343
ADDWFC .......................................................................... 343
ADRESH Register............................................................... 38
ADRESH Register (ADFM = 0) ......................................... 163
ADRESH Register (ADFM = 1) ......................................... 164
ADRESL Register (ADFM = 0).......................................... 163
ADRESL Register (ADFM = 1).......................................... 164
Alternate Pin Function....................................................... 130
Analog-to-Digital Converter. See ADC
ANSELA Register ............................................................. 133
ANSELB Register ............................................................. 137
ANSELC Register ............................................................. 141
APFCON Register............................................................. 130
Assembler
MPASM Assembler................................................... 386
Automatic Context Saving................................................... 95
B
Bank 10 ............................................................................... 41
Bank 11 ............................................................................... 41
Bank 12 ............................................................................... 41
Bank 13 ............................................................................... 41
Bank 14-28.......................................................................... 41
Bank 2 ................................................................................. 39
Bank 3 ................................................................................. 39
Bank 30 ............................................................................... 42
Bank 31 ............................................................................... 43
Bank 4 ................................................................................. 40
Bank 5 ................................................................................. 40
Bank 6 ................................................................................. 40
Bank 7 ................................................................................. 40
Bank 8 ................................................................................. 40
Bank 9 ................................................................................. 40
BAUDCON Register ......................................................... 269

BF ............................................................................. 238, 240
BF Status Flag .......................................................... 238, 240
Block Diagrams
ADC .......................................................................... 154
ADC Transfer Function............................................. 166
Analog Input Model........................................... 166, 178
Clock Source .............................................................. 58
Comparator............................................................... 174
Crystal Operation.................................................. 60, 61
Digital-to-Analog Converter (DAC) ........................... 170
EUSART Receive ..................................................... 258
EUSART Transmit .................................................... 257
External RC Mode ...................................................... 62
Fail-Safe Clock Monitor (FSCM)................................. 71
Generic I/O Port........................................................ 129
Interrupt Logic............................................................. 91
On-Chip Reset Circuit................................................. 79
PIC16(L)F1454/5/9 ..................................................... 14
PIC16C74 ................................................................. 5, 6
PIC16C74A............................................................... 5, 6
PWM......................................................................... 287
Resonator Operation .................................................. 60
Self Tuning ................................................................. 73
Timer0 ...................................................................... 183
Timer1 ...................................................................... 187
Timer1 Gate.............................................. 192, 193, 194
Timer2 ...................................................................... 199
USB Interrupt Logic .................................................. 318
USB Peripheral and Options .................................... 309
Voltage Reference.................................................... 149
Voltage Reference Output Buffer Example .............. 170
BORCON Register.............................................................. 81
BRA .................................................................................. 344
Break Character (12-bit) Transmit and Receive ............... 278
Brown-out Reset (BOR)...................................................... 81
Specifications ........................................................... 370
Timing and Characteristics ....................................... 369
C
C Compilers
MPLAB C18.............................................................. 386
CALL................................................................................. 345
CALLW ............................................................................. 345
CLKRCON Register............................................................ 88
Clock Accuracy with Asynchronous Operation ................. 266
Clock Sources
External Modes........................................................... 59
EC ...................................................................... 59
HS ...................................................................... 59
LP ....................................................................... 59
OST .................................................................... 60
RC ...................................................................... 62
XT ....................................................................... 59
Internal Modes............................................................ 62
HFINTOSC ......................................................... 62
Internal Oscillator Clock Switch Timing .............. 64
LFINTOSC.......................................................... 63
Clock Switching ............................................................ 66, 67
CMOUT Register .............................................................. 180
CMxCON0 Register .......................................................... 179
CMxCON1 Register .......................................................... 180
Preliminary
DS41639A-page 409
PIC16(L)F1454/5/9
Code Examples
A/D Conversion ......................................................... 159
Initializing PORTA............................................. 129, 131
Writing to Flash Program Memory ............................ 121
Comparator
Associated Registers ................................................ 181
Operation .................................................................. 173
Comparator Module .......................................................... 173
Cx Output State Versus Input Conditions ................. 175
Comparator Specifications ................................................ 374
Comparators
C2OUT as T1 Gate ................................................... 189
Complementary Waveform Generator (CWG) .......... 293, 294
CONFIG1 Register.............................................................. 52
CONFIG2 Register.............................................................. 54
Core Function Register ....................................................... 37
CPU Clock Divider .............................................................. 66
Customer Change Notification Service ............................. 415
Customer Notification Service........................................... 415
Customer Support ............................................................. 415
CWG
Auto-shutdown Control ............................................. 300
Clock Source............................................................. 296
Output Control........................................................... 296
Selectable Input Sources .......................................... 296
CWGxCON0 Register ....................................................... 303
CWGxDBF Register .......................................................... 306
CWGxDBR Register.......................................................... 306
D
DACCON0 (Digital-to-Analog Converter
Control 0) Register .................................................... 172
DACCON1 (Digital-to-Analog Converter
Control 1) Register .................................................... 172
Data Memory....................................................................... 26
DC and AC Characteristics ............................................... 383
DC Characteristics
Extended and Industrial ............................................ 362
Industrial and Extended ............................................ 355
Development Support ....................................................... 385
Device Configuration........................................................... 51
Code Protection .......................................................... 55
Configuration Word ..................................................... 51
Device ID and Revision ID .......................................... 56
User ID ........................................................................ 55
Device ID Register .............................................................. 56
Device Overview ......................................................... 13, 107
Digital-to-Analog Converter (DAC).................................... 169
Effects of a Reset...................................................... 170
Specifications ............................................................ 374
E
Effects of Reset
PWM mode ............................................................... 289
Electrical Specifications .................................................... 353
Enhanced Mid-Range CPU................................................. 21
Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART)............................... 257
Equations
Estimating USB Transceiver Current
Consumption..................................................... 322
Errata .................................................................................. 11
DS41639A-page 410
EUSART ........................................................................... 257

Associated Registers
Baud Rate Generator ....................................... 271
Asynchronous Mode ................................................. 259
12-bit Break Transmit and Receive .................. 278
Receive .................................................... 265
Transmit.................................................... 261
Auto-Wake-up on Break ................................... 276
Baud Rate Generator (BRG) ............................ 270
Clock Accuracy................................................. 266
Receiver ........................................................... 262
Setting up 9-bit Mode with Address Detect ...... 264
Transmitter ....................................................... 259
Baud Rate Generator (BRG)
Auto Baud Rate Detect..................................... 275
Baud Rate Error, Calculating............................ 270
Baud Rates, Asynchronous Modes .................. 272
Formulas........................................................... 271
High Baud Rate Select (BRGH Bit) .................. 270
Synchronous Master Mode............................... 279, 283
Receive .................................................... 282
Transmit.................................................... 280
Reception ......................................................... 281
Transmission .................................................... 279
Synchronous Slave Mode
Receive .................................................... 284
Transmit.................................................... 283
Reception ......................................................... 284
Transmission .................................................... 283
Extended Instruction Set
ADDFSR ................................................................... 343
F
Fail-Safe Clock Monitor ...................................................... 71
Fail-Safe Condition Clearing....................................... 71
Fail-Safe Detection ..................................................... 71
Fail-Safe Operation..................................................... 71
Reset or Wake-up from Sleep .................................... 71
Firmware Instructions ....................................................... 339
Fixed Voltage Reference (FVR)........................................ 149
Flash Program Memory .................................................... 112
Configuration Word w/ Flash
Program Memory.............................................. 128
Erasing ..................................................................... 116
Modifying .................................................................. 122
Write Verify ............................................................... 124
Writing ...................................................................... 118
FSR Register ...................................................................... 37
FVRCON (Fixed Voltage Reference Control) Register..... 150
I
I2C Mode (MSSP)
Acknowledge Sequence Timing ............................... 242
Bus Collision
During a Repeated Start Condition................... 246
During a Stop Condition ................................... 247
Effects of a Reset ..................................................... 243
I2C Clock Rate w/BRG.............................................. 249
Master Mode
Operation.......................................................... 234
Reception ......................................................... 240
Preliminary
PIC16(L)F1454/5/9
Start Condition Timing .............................. 236, 237
Transmission .................................................... 238
Multi-Master Communication, Bus Collision
and Arbitration .................................................. 243
Multi-Master Mode .................................................... 243
Read/Write Bit Information (R/W Bit) ........................ 219
Slave Mode
Transmission .................................................... 224
Sleep Operation ........................................................ 243
Stop Condition Timing............................................... 242
INDF Register ..................................................................... 37
Indirect Addressing ............................................................. 47
Instruction Format ............................................................. 340
Instruction Set ................................................................... 339
ADDLW ..................................................................... 343
ADDWF..................................................................... 343
ADDWFC .................................................................. 343
ANDLW ..................................................................... 343
ANDWF..................................................................... 343
BRA........................................................................... 344
CALL ......................................................................... 345
CALLW...................................................................... 345
LSLF ......................................................................... 347
LSRF......................................................................... 347
MOVF........................................................................ 347
MOVIW ..................................................................... 348
MOVLB ..................................................................... 348
MOVWI ..................................................................... 349
OPTION .................................................................... 349
RESET ...................................................................... 349
SUBWFB................................................................... 351
TRIS.......................................................................... 352
BCF........................................................................... 344
BSF ........................................................................... 344
BTFSC ...................................................................... 344
BTFSS ...................................................................... 344
CALL ......................................................................... 345
CLRF......................................................................... 345
CLRW ....................................................................... 345
CLRWDT................................................................... 345
COMF ....................................................................... 345
DECF ........................................................................ 345
DECFSZ.................................................................... 346
GOTO ....................................................................... 346
INCF.......................................................................... 346
INCFSZ ..................................................................... 346
IORLW ...................................................................... 346
IORWF ...................................................................... 346
MOVLW .................................................................... 348
MOVWF .................................................................... 348
NOP .......................................................................... 349
RETFIE ..................................................................... 350
RETLW ..................................................................... 350
RETURN ................................................................... 350
RLF ........................................................................... 350
RRF........................................................................... 351
SLEEP ...................................................................... 351
SUBLW ..................................................................... 351
SUBWF ..................................................................... 351
SWAPF ..................................................................... 352
XORLW..................................................................... 352
XORWF..................................................................... 352
INTCON Register ................................................................ 96
Internal Oscillator Block

INTOSC
Specifications ................................................... 367
Internal Sampling Switch (RSS) Impedance ..................... 165
Internet Address ............................................................... 415
Interrupt-On-Change......................................................... 143
Associated Registers................................................ 148
Interrupts ............................................................................ 91
ADC .......................................................................... 159
Associated registers w/ Interrupts ............................ 101
Configuration Word w/ Clock Sources........................ 78
Configuration Word w/ Reference Clock Sources ...... 89
TMR1........................................................................ 191
INTOSC Specifications ..................................................... 367
IOCAF Register ................................................................ 146
IOCAN Register ................................................................ 145
IOCAP Register ................................................................ 145
IOCBF Register ................................................................ 147
IOCBN Register ................................................................ 147
IOCBP Register ................................................................ 146
L
LATA Register .......................................................... 133, 141
LATB Register .................................................................. 137
Load Conditions................................................................ 366
LSLF ................................................................................. 347
LSRF ................................................................................ 347
M
Master Synchronous Serial Port. See MSSP
MCLR ................................................................................. 82
Internal........................................................................ 82
Memory Organization ......................................................... 23
Data ............................................................................ 26
Program...................................................................... 23
Microchip Internet Web Site.............................................. 415
MOVIW ............................................................................. 348
MOVLB ............................................................................. 348
MOVWI ............................................................................. 349
MPLAB ASM30 Assembler, Linker, Librarian ................... 386
MPLAB Integrated Development
Environment Software .............................................. 385
MPLAB PM3 Device Programmer .................................... 388
MPLAB REAL ICE In-Circuit Emulator System ................ 387
MPLINK Object Linker/MPLIB Object Librarian ................ 386
MSSP ............................................................................... 203
SPI Mode.................................................................. 206
SSPBUF Register..................................................... 209
SSPSR Register ....................................................... 209
MSSPx
I2C Mode .................................................................. 214
I2C Mode Operation.................................................. 216
O
OPCODE Field Descriptions............................................. 339
OPTION ............................................................................ 349
OPTION_REG Register.................................................... 185
OSCCON Register.............................................................. 75
Oscillator
Associated Registers.................................................. 78
Associated registers ................................................. 307
Oscillator Module ........................................................ 57, 309
ECH ............................................................................ 57
ECL............................................................................. 57
ECM............................................................................ 57
HS............................................................................... 57
Preliminary
DS41639A-page 411
PIC16(L)F1454/5/9
INTOSC ...................................................................... 57
LP................................................................................ 57
RC ............................................................................... 57
XT ............................................................................... 57
Oscillator Parameters........................................................ 367
Oscillator Specifications .................................................... 367
Oscillator Start-up Timer (OST)
Specifications ............................................................ 370
Oscillator Switching
Fail-Safe Clock Monitor............................................... 71
Two-Speed Clock Start-up .......................................... 69
OSCSTAT Register............................................................. 76
OSCTUNE Register ............................................................ 77
P
Packaging ......................................................................... 389
Marking ..................................................................... 389
PDIP Details.............................................................. 392
PCL and PCLATH ............................................................... 21
PCL Register....................................................................... 37
PCLATH Register................................................................ 37
PCON Register ............................................................. 38, 85
PIE1 Register ................................................................ 38, 97
PIE2 Register ................................................................ 38, 98
Pinout Descriptions
PIC16(L)F1454 ........................................................... 15
PIC16(L)F1455 ........................................................... 17
PIC16(L)F1459 ........................................................... 19
PIR1 Register................................................................ 38, 99
PIR2 Register.............................................................. 38, 100
PMADR Registers ............................................................. 112
PMADRH Registers .......................................................... 112
PMADRL Register............................................................. 126
PMADRL Registers ........................................................... 112
PMCON1 Register .................................................... 112, 127
PMCON2 Register .................................................... 112, 128
PMDATH Register............................................................. 125
PMDATL Register ............................................................. 125
PMDRH Register............................................................... 126
PORTA.............................................................................. 131
LATA Register............................................................. 39
PORTA Register ......................................................... 38
Specifications ............................................................ 368
PORTA Register ............................................................... 132
PORTB.............................................................................. 135
LATB Register............................................................. 39
PORTB Register ......................................................... 38
PORTB Register ............................................................... 136
PORTC
LATC Register ............................................................ 39
Pin Descriptions and Diagrams................................. 139
PORTC Register ......................................................... 38
PORTC Register ............................................................... 140
Power-Down Mode (Sleep) ............................................... 103
Power-on Reset .................................................................. 80
Power-up Time-out Sequence ............................................ 82
Power-up Timer (PWRT)..................................................... 80
Specifications ............................................................ 370
PR2 Register....................................................................... 38
Program Memory ................................................................ 23
Map and Stack (PIC16(L)F1509 ................................. 24
Programming, Device Instructions .................................... 339
DS41639A-page 412
Pulse Width Modulation (PWM)........................................ 287

Associated registers w/ PWM ................................... 292
PWM Mode
Duty Cycle ........................................................ 288
Effects of Reset ................................................ 289
Example PWM Frequencies and
Resolutions, 20 MHZ ................................ 289
Example PWM Frequencies and
Resolutions, 8 MHz .................................. 289
Operation in Sleep Mode.................................. 289
Setup for Operation using PWMx pins ............. 290
System Clock Frequency Changes .................. 289
PWM Period.............................................................. 288
Setup for PWM Operation using PWMx Pins ........... 290
PWMxCON Register ......................................................... 291
PWMxDCH Register ......................................................... 292
PWMxDCL Register.......................................................... 292
R
RCREG............................................................................. 264
RCREG Register ................................................................ 39
RCSTA Register ......................................................... 39, 268
Reader Response............................................................. 416
Read-Modify-Write Operations ......................................... 339
Reference Clock ................................................................. 87
Associated Registers .................................................. 89
Registers
ADCON0 (ADC Control 0) ........................................ 160
ADRESH (ADC Result High) with ADFM = 0) .......... 163
ADRESH (ADC Result High) with ADFM = 1) .......... 164
ADRESL (ADC Result Low) with ADFM = 0)............ 163
ADRESL (ADC Result Low) with ADFM = 1)............ 164
ANSELA (PORTA Analog Select)............................. 133
ANSELB (PORTB Analog Select)............................. 137
ANSELC (PORTC Analog Select) ............................ 141
APFCON (Alternate Pin Function Control) ............... 130
BAUDCON (Baud Rate Control)............................... 269
BDnSTAT (Buffer Descriptor n Status,
CPU Mode)............................................... 314, 330
BDnSTAT (Buffer Descriptor n Status,
SIE Mode)................................................. 315, 331
BORCON Brown-out Reset Control) .......................... 81
CLKRCON (Reference Clock Control)........................ 88
CMOUT (Comparator Output) .................................. 180
CMxCON0 (Cx Control) ............................................ 179
CMxCON1 (Cx Control 1) ......................................... 180
Configuration Word 1.................................................. 52
Configuration Word 2.................................................. 54
Core Function, Summary............................................ 37
CWGxCON0 (CWG Control 0) ................................. 303
CWGxDBF (CWGx Dead Band Falling Count)......... 306
CWGxDBR (CWGx Dead Band Rising Count) ......... 306
DACCON0 ................................................................ 172
DACCON1 ................................................................ 172
Device ID .................................................................... 56
FVRCON................................................................... 150
INTCON (Interrupt Control)......................................... 96
IOCAF (Interrupt-on-Change PORTA Flag).............. 146
IOCAN (Interrupt-on-Change PORTA
Negative Edge)................................................. 145
IOCAP (Interrupt-on-Change PORTA
Positive Edge) .................................................. 145
Preliminary
PIC16(L)F1454/5/9
IOCBF (Interrupt-on-Change PORTB Flag).............. 147
IOCBN (Interrupt-on-Change PORTB
Negative Edge) ................................................. 147
IOCBP (Interrupt-on-Change PORTB
Positive Edge)................................................... 146
LATA (Data Latch PORTA)....................................... 133
LATB (Data Latch PORTB)....................................... 137
LATC (Data Latch PORTC) ...................................... 141
OPTION_REG (OPTION) ......................................... 185
OSCCON (Oscillator Control) ..................................... 75
OSCSTAT (Oscillator Status) ..................................... 76
OSCTUNE (Oscillator Tuning) .................................... 77
PCON (Power Control Register) ................................. 85
PCON (Power Control) ............................................... 85
PIE1 (Peripheral Interrupt Enable 1)........................... 97
PIE2 (Peripheral Interrupt Enable 2)........................... 98
PIR1 (Peripheral Interrupt Register 1) ........................ 99
PIR2 (Peripheral Interrupt Request 2) ...................... 100
PMADRL (Program Memory Address)...................... 126
PMCON1 (Program Memory Control 1).................... 127
PMCON2 (Program Memory Control 2).................... 128
PMDATH (Program Memory Data) ........................... 125
PMDATL (Program Memory Data)............................ 125
PMDRH (Program Memory Address) ....................... 126
PORTA...................................................................... 132
PORTB...................................................................... 136
PORTC ..................................................................... 140
PWMxCON (PWM Control)....................................... 291
PWMxDCH (PWM Control)....................................... 292
PWMxDCL (PWM Control) ....................................... 292
RCREG ..................................................................... 275
RCSTA (Receive Status and Control)....................... 268
SPBRGH................................................................... 270
SPBRGL ................................................................... 270
Special Function, Summary ........................................ 38
SSPADD (MSSP Address and Baud Rate,
I2C Mode) ......................................................... 255
SSPCON1 (MSSP Control 1).................................... 252
SSPCON2 (SSP Control 2)....................................... 253
SSPCON3 (SSP Control 3)....................................... 254
SSPMSK (SSP Mask)............................................... 255
SSPSTAT (SSP Status)............................................ 250
STATUS...................................................................... 27
T1CON (Timer1 Control)........................................... 195
T1GCON (Timer1 Gate Control) ............................... 196
T2CON...................................................................... 201
TRISA (Tri-State PORTA)......................................... 132
TRISB (Tri-State PORTB)......................................... 136
TRISC (Tri-State PORTC) ........................................ 140
TXSTA (Transmit Status and Control) ...................... 267
UCFG (USB Configuration)............................... 310, 327
UCON (USB Control) ........................................ 310, 326
UEIE (USB Error Interrupt Enable) ........................... 335
UEIE (USB Interrupt Enable) .................................... 319
UEIR (USB Error Interrupt Status) .................... 319, 334
UEPN (USB Endpoint Control) ................................. 312
UEPn (USB Endpoint n Control) ............................... 329
UIE (USB Interrupt Enable)............................... 319, 333
UIR (USB Interrupt Status) ............................... 319, 332
USTAT (USB Status) ........................................ 312, 328
VREGCON (Voltage Regulator Control) ................... 106
WDTCON (Watchdog Timer Control) ....................... 110
WPUA (Weak Pull-up PORTA) ................................. 134
WPUB (Weak Pull-up PORTB) ................................. 138
RESET .............................................................................. 349
Reset .................................................................................. 79
Reset Instruction................................................................. 82
Resets ................................................................................ 79
Associated Registers.................................................. 86
Revision History................................................................ 407
S
Software Simulator (MPLAB SIM) .................................... 387
SPBRG Register................................................................. 39
SPBRGH Register ............................................................ 270
SPBRGL Register............................................................. 270
Special Function Registers (SFRs)..................................... 38
SPI Mode (MSSP)
SPI Clock.................................................................. 209
SPI Mode (MSSPx)
SSPADD Register............................................................. 255
SSPCON1 Register .......................................................... 252
SSPCON2 Register .......................................................... 253
SSPCON3 Register .......................................................... 254
SSPMSK Register ............................................................ 255
SSPOV ............................................................................. 240
SSPOV Status Flag .......................................................... 240
SSPSTAT Register ........................................................... 250
R/W Bit ..................................................................... 219
ST
Block Diagram ............................................................ 73
Stack................................................................................... 45
Accessing ................................................................... 45
Reset .......................................................................... 47
Stack Overflow/Underflow .................................................. 82
STATUS Register ............................................................... 27
SUBWFB .......................................................................... 351
T
T1CON Register ......................................................... 38, 195
T1GCON Register ............................................................ 196
T2CON (Timer2) Register................................................. 201
T2CON Register ................................................................. 38
Temperature Indicator Module.......................................... 151
Thermal Considerations.................................................... 365
Timer0 .............................................................................. 183
Operation.................................................................. 183
Specifications ........................................................... 371
Timer1 .............................................................................. 187
Asynchronous Counter Mode ................................... 189
Reading and Writing ......................................... 189
Clock Source Selection ............................................ 188
Interrupt .................................................................... 191
Operation.................................................................. 188
Operation During Sleep ............................................ 191
Oscillator................................................................... 189
Prescaler .................................................................. 189
Specifications ........................................................... 371
Timer1 Gate
Selecting Source .............................................. 189
TMR1H Register....................................................... 187
TMR1L Register ....................................................... 187
Timer2 .............................................................................. 199
Preliminary
DS41639A-page 413
PIC16(L)F1454/5/9
Timers
Timer1
T1CON.............................................................. 195
T1GCON ........................................................... 196
Timer2
T2CON.............................................................. 201
Timing Diagrams
A/D Conversion ......................................................... 372
A/D Conversion (Sleep Mode) .................................. 373
Acknowledge Sequence ........................................... 242
Asynchronous Reception .......................................... 264
Asynchronous Transmission ..................................... 260
Asynchronous Transmission (Back to Back) ............ 260
Auto Wake-up Bit (WUE) During
Normal Operation.............................................. 277
Auto Wake-up Bit (WUE) During Sleep .................... 277
Automatic Baud Rate Calibration .............................. 275
Baud Rate Generator with Clock Arbitration ............. 235
BRG Reset Due to SDA Arbitration
During Start Condition....................................... 245
Brown-out Reset (BOR) ............................................ 369
Brown-out Reset Situations ........................................ 81
Start Condition (Case 1) ................................... 246
Start Condition (Case 2) ................................... 246
Bus Collision During a Start Condition (SCL = 0) ..... 245
Bus Collision During a Stop Condition (Case 1) ....... 247
Bus Collision During a Stop Condition (Case 2) ....... 247
Bus Collision During Start Condition (SDA only) ...... 244
Bus Collision for Transmit and Acknowledge............ 243
CLKOUT and I/O....................................................... 368
Clock Synchronization .............................................. 232
Clock Timing ............................................................. 367
Comparator Output ................................................... 173
Fail-Safe Clock Monitor (FSCM) ................................. 72
First Start Bit Timing ................................................. 236
I2C Bus Data ............................................................. 379
I2C Bus Start/Stop Bits.............................................. 379
I2C Master Mode (7 or 10-Bit Transmission) ............ 239
I2C Master Mode (7-Bit Reception) ........................... 241
I2C Stop Condition Receive or Transmit Mode ......... 242
INT Pin Interrupt.......................................................... 94
Internal Oscillator Switch Timing................................. 65
Repeat Start Condition.............................................. 237
Reset Start-up Sequence............................................ 83
Reset, WDT, OST and Power-up Timer ................... 369
Send Break Character Sequence ............................. 278
SPI Master Mode (CKE = 1, SMP = 1) ..................... 376
SPI Mode (Master Mode) .......................................... 209
SPI Slave Mode (CKE = 0) ....................................... 377
SPI Slave Mode (CKE = 1) ....................................... 377
Synchronous Reception (Master Mode, SREN) ....... 282
Synchronous Transmission....................................... 280
Synchronous Transmission (Through TXEN) ........... 280
Timer0 and Timer1 External Clock ........................... 370
Timer1 Incrementing Edge........................................ 191
Two Speed Start-up .................................................... 70
USART Synchronous Receive (Master/Slave) ......... 375
USART Synchronous Transmission (Master/Slave) . 375
Wake-up from Interrupt ............................................. 104
Timing Parameter Symbology........................................... 366
Timing Requirements
I2C Bus Data ............................................................. 380
I2C Bus Start/Stop Bits ............................................. 379
DS41639A-page 414
SPI Mode .................................................................. 378

TMR0 Register.................................................................... 38
TMR1H Register ................................................................. 38
TMR1L Register.................................................................. 38
TMR2 Register.................................................................... 38
TRIS.................................................................................. 352
TRISA Register........................................................... 38, 132
TRISB Register........................................................... 38, 136
TRISC ............................................................................... 139
TRISC Register........................................................... 38, 140
Two-Speed Clock Start-up Mode........................................ 69
TXREG ............................................................................. 259
TXREG Register ................................................................. 39
TXSTA Register.......................................................... 39, 267
BRGH Bit .................................................................. 270
U
Universal Serial Bus
BD Address Validation.............................................. 315
BD Byte Count .......................................................... 315
Buffer Descriptor Table (BDT) .................................. 313
Buffer Descriptors
Assignment in Different Buffering Modes ......... 316
Example............................................................ 314
Memory Map..................................................... 316
Register Summary............................................ 317
Buffer Descriptors (BDn)........................................... 313
Interrupt-on-change .................................................. 323
Interrupts .................................................................. 318
and USB Transactions...................................... 318
Oscillator................................................................... 323
Ping-Pong Buffering ................................................. 315
Power Modes............................................................ 320
RAM.......................................................................... 313
Memory Map..................................................... 313
Status and Control .................................................... 310
Universal Serial Bus (USB)............................................... 309
USART
Synchronous Master Mode
Requirements, Synchronous Receive .............. 375
Requirements, Synchronous Transmission...... 375
Timing Diagram, Synchronous Receive ........... 375
Timing Diagram, Synchronous Transmission... 375
USB .................................................................................. 309
USB Operation.................................................................... 66
V
VREF. SEE ADC Reference Voltage
VREGCON Register ......................................................... 106
W
Wake-up on Break ............................................................ 276
Wake-up Using Interrupts ................................................. 104
Watchdog Timer (WDT)...................................................... 82
Modes ....................................................................... 108
Specifications ........................................................... 370
WCOL ....................................................... 235, 238, 240, 242
WCOL Status Flag.................................... 235, 238, 240, 242
WDTCON Register ........................................................... 110
WPUA Register................................................................. 134
WPUB Register................................................................. 138
Write Protection .................................................................. 55
WWW Address ................................................................. 415
WWW, On-Line Support ..................................................... 11
Preliminary
PIC16(L)F1454/5/9
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance

through several channels:
Product Support Data sheets and errata,

application notes and sample programs, design
resources, users guides and hardware support
documents, latest software releases and archived
software
General Technical Support Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
Business of Microchip Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
CUSTOMER CHANGE NOTIFICATION

SERVICE
Microchips customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under Support, click on
Customer Change Notification and follow the
registration instructions.
Preliminary
DS41639A-page 415
PIC16(L)F1454/5/9
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
(480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
TO:
Technical Publications Manager
RE:
Reader Response
Total Pages Sent ________
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Device: PIC16(L)F1454/5/9
Literature Number: DS41639A
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS41639A-page 416
Preliminary
PIC16(L)F1454/5/9
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
[X](1)
PART NO.
Device
Tape and Reel Temperature

Option
Range
/XX
XXX
Package
Pattern
Examples:
a)
b)
Device:
PIC16F1454, PIC16LF1454,
PIC16F1455, PIC16LF1455,
PIC16F1459, PIC16LF1459
c)
Tape and Reel

Option:
Blank
T
= Standard packaging (tube or tray)

= Tape and Reel(1)
Temperature
Range:
I
E
= -40C to +85C
= -40C to +125C
Package:(2)
ML
P
SS
ST
SO
SL
Pattern:
QTP, SQTP, Code or Special Requirements

(blank otherwise)
=
=
=
=
=
=
(Industrial)
(Extended)
QFN 4x4
Plastic DIP
SSOP
TSSOP
SOIC 20-Lead
SOIC 14-Lead
PIC16F1454T - E/SL
Tape and Reel,
Industrial temperature,
SOIC package
PIC16F1459 - I/P
Industrial temperature
PDIP package
PIC16F1459 - E/ML
Extended temperature,
QFN package
Note
Preliminary
1:
2:
Tape and Reel identifier only appears in

the catalog part number description. This
identifier is used for ordering purposes and
is not printed on the device package.
Check with your Microchip Sales Office
for package availability with the Tape and
Reel option.
Small form-factor packaging options may
be available. Please check
www.microchip.com/packaging for small
form-factor package availability, or contact
your local sales office.
DS41639A-page 417
Worldwide Sales and Service

AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office

Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Japan - Osaka
Tel: 81-66-152-7160
Fax: 81-66-152-9310
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
China - Hangzhou
Tel: 86-571-2819-3187
Fax: 86-571-2819-3189
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hong Kong SAR

Tel: 852-2401-1200
Fax: 852-2401-3431
Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu

Tel: 886-3-5778-366
Fax: 886-3-5770-955
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-330-9305
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
DS41639A-page 418
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
11/29/11
Preliminary

41639A

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PIC16(L)F1454/5/9

2012 Microchip Technology Inc.

Information contained in this publication regarding device

QUALITY MANAGEMENT SYSTEM

Microchip received ISO/TS-16949:2009 certification for its worldwide

2012 Microchip Technology Inc.

Extreme Low-Power Management

C Compiler Optimized Architecture

Flexible Oscillator Structure:

Special Microcontroller Features:

Universal Serial Bus (USB) Features:

2012 Microchip Technology Inc.

Sleep mode: 25 nA @ 1.8V, typical

16 MHz Internal Oscillator Block:

Analog features are not available on

Not available on PIC16(L)F1454 devices.

For other small form-factor package availability and marking

PIC16(L)F1454 (1) 8192 1024 11

10-bit ADC (ch)

Data Sheet Index

PIC16(L)F145X Family Types

2012 Microchip Technology Inc.

14-PIN PDIP, SOIC, TSSOP DIAGRAM FOR PIC16(L)F1454/1455

PDIP, SOIC, TSSOP

Note 1: LVP support for PIC18(L)F1XK50 legacy designs.

16-PIN QFN DIAGRAM FOR PIC16(L)F1454/1455

Note 1: LVP support for PIC18(L)F1XK50 legacy designs.

2012 Microchip Technology Inc.

20-PIN PDIP, SOIC, SSOP DIAGRAM FOR PIC16(L)F1459

PDIP, SOIC, SSOP

Note 1: LVP support for PIC18(L)F1XK50 legacy designs.

20-PIN QFN DIAGRAM FOR PIC16(L)F1459

Note 1: LVP support for PIC18(L)F1XK50 legacy designs.

2012 Microchip Technology Inc.

14-PIN ALLOCATION TABLE (PIC16(L)F1454)

2012 Microchip Technology Inc.

14-PIN ALLOCATION TABLE (PIC16(L)F1455)

2012 Microchip Technology Inc.

20-PIN ALLOCATION TABLE (PIC16(L)F1459)

2012 Microchip Technology Inc.

Device Overview ........................................................................................................................................................................ 13

2012 Microchip Technology Inc.

Most Current Data Sheet

Customer Notification System

2012 Microchip Technology Inc.

2012 Microchip Technology Inc.

The PIC16(L)F1454/5/9 are described within this data

Analog-to-Digital Converter (ADC)

Complementary Wave Generator (CWG)

DEVICE PERIPHERAL SUMMARY

Fixed Voltage Reference (FVR)

Enhanced Universal Synchronous/Asynchronous Receiver/Transmitter

Universal Serial Bus (USB)

Master Synchronous Serial Ports

2012 Microchip Technology Inc.

PIC16(L)F1454/5/9 BLOCK DIAGRAM

2012 Microchip Technology Inc.

PIC16(L)F1454 PINOUT DESCRIPTION

CMOS General purpose I/O.

USB differential plus line.