Design and Analysis of A Dual Chamber Cardiac Pacemaker Using VHDL in Biomedical Application
Design and Analysis of A Dual Chamber Cardiac Pacemaker Using VHDL in Biomedical Application
Design and Analysis of A Dual Chamber Cardiac Pacemaker Using VHDL in Biomedical Application
Volume: 2 Issue: 7
ISSN: 2321-8169
2007 2009
_______________________________________________________________________________________________
Amandeep Kaur
Abstract This research paper aims at a dual-chamber pacemaker design which is being simulated using VLSI architecture in Xilinx and is
being modified by changing clock cycle to provide better results as compared to other pacemaker. It follows a state machine approach to achieve
the desired purpose. The heart of the system is the pacing pulse generator, which forms the major part of the project. It is being designed using
VHDL and implemented in hardware using FPGA. The code has been modified and optimized for different modes of stimulation. Reasonable
components in the construction of the detection circuit and other peripherals had been used for simulation. It had been assured that memory and
data compression techniques monitoring devices remotely had been used for improvements in the overall performance.
__________________________________________________*****_________________________________________________
I.
INTRODUCTION (HEADING 1)
_______________________________________________________________________________________
ISSN: 2321-8169
2007 2009
_______________________________________________________________________________________________
the dual chamber pacemaker, after the pacing of atrium, the
state of the pacemaker changes to the Reset Timer condition
of the ventricle. In the case of single-chamber pacemaker, it
changes the Reset Timer state of the atrium.
Accomplishment of this task continues in a cyclic manner time
and again [6].
The following is the state diagram.
_______________________________________________________________________________________
ISSN: 2321-8169
2007 2009
_______________________________________________________________________________________________
The basic output is dependent upon the sensing circuit and its
design concept. Therefore, lesser importance has been given to
that parts which are associated with the normal activities of the
pacemaker.
The simulation in figure 1 shows the following behavior of the
timer. It starts to count from 0 to the timeout value. If the start
is held high, it just repeats but if the start is not held high; it
resets and stops at zero.
REFERENCES
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Figure 2: Complete schematic diagram of the circuit
The timeout value of the circuit is changed from 255 to the
value which is less than the current count then the timer times
out immediately.
The following simulation result shows that the tests conducted
for the pacemaker controller component are in the normal
condition at present. In the case of systems which are driven
by the timers, testing the controller independently is an
excellent way to increase the speed of the system.
[8]
[9]
[10]
2009
IJRITCC | July 2014, Available @ http://www.ijritcc.org
_______________________________________________________________________________________