Serial Peripheral Interface

Serial peripheral interphase:-
 SPI can also achieve significantly higher data rates than I2C.
 SPI really gains efficiency in applications that take advantage of its duplex capability,
such as the communication between a "codec" (coder-decoder) and a digital signal
processor, which consists of simultaneously sending samples in and out.
 SPI devices communicate using a master-slave relationship.
 Due to its lack of built-in device addressing, SPI requires more effort and more hardware
resources i.e. the lack of device addressing means less overhead.
 SPI is a serial bus standard established by Motorola and supported in silicon products
from various manufacturers.
 SPI interfaces are available on popular communication processors such as the MPC8260
and microcontrollers such as the M68HC11. It is a synchronous serial data link that
operates in full duplex (signals carrying data go in both directions simultaneously).
 Devices communicate using a master/slave relationship, in which the master initiates

the data frame. When the master generates a clock and selects a slave device, data may
be transferred in either or both directions simultaneously. In fact, as far as SPI is
concerned, data are always transferred in both directions. It is up to the master and
slave devices to know whether a received byte is meaningful or not. So a device must
discard the received byte in a "transmit only" frame or generate a dummy byte for a
"receive only" frame.
 SPI specifies four signals: clock (SCLK); master data output, slave data input (MOSI);
master data input, slave data output (MISO); and slave select (ÇSS). Figure 1 shows
these signals in a single-slave configuration. SCLK is generated by the master and input
to all slaves. MOSI carries data from master to slave. MISO carries data from slave back
to master. A slave device is selected when the master asserts its ÇSS signal.
 If multiple slave devices exist, the master generates a separate slave select signal for
each slave. These relationships are illustrated in Figure 2.
 The master generates slave select signals using general-purpose discrete input/output
pins or other logic.
 A pair of parameters called clock polarity (CPOL) and clock phase (CPHA) determine the
edges of the clock signal on which the data are driven and sampled. Each of the two
parameters has two possible states, which allows for four possible combinations, all of
which are incompatible with one another. So a master/slave pair must use the same
parameter pair values to communicate. If multiple slaves are used that are fixed in
different configurations, the master will have to reconfigure itself each time it needs to
communicate with a different slave.
 SPI does not have an acknowledgement mechanism to confirm receipt of data. In fact,
without a communication protocol, the SPI master has no knowledge of whether a slave
even exists. SPI also offers no flow control. If you need hardware flow control, you might
need to do something outside of SPI.
Serial Peripheral Interface Bus
 The Serial Peripheral Interface Bus or SPI is a synchronous serial data link standard
named by Motorola that operates in full duplex mode. Devices communicate in
master/slave mode where the master device initiates the data frame. Multiple slave
devices are allowed with individual slave select (chip select) lines. Sometimes SPI is
called a "four wire" serial bus, contrasting with three, two, and one wire serial buses.
 The SPI bus specifies four logic signals.

SCLK — Serial Clock (output from master)
MOSI/SIMO — Master Output, Slave Input (output from master)
MISO/SOMI — Master Input, Slave Output (output from slave)
SS — Slave Select (active low; output from master)
 The SPI bus can operate with a single master device and with one or more slave devices.
 If a single slave device is used, the SS pin may be fixed to logic low if the slave permits it.
Some slaves require the falling edge (high->low transition) of the slave select to initiate
an action. With multiple slave devices, an independent SS signal is required from the
master for each slave device.
 Most slave devices have tri-state outputs so their MISO signal becomes high impedance
("disconnected") when the device is not selected. Devices without tristate outputs can't
share SPI bus segments with other devices; only one such slave could talk to the master,
and only its chip select could be activated.

 To begin a communication, the master first configures the clock, using a frequency less
than or equal to the maximum frequency the slave device supports. Such frequencies
are commonly in the range of 1-70 MHz.
 The master then pulls the slave select low for the desired chip. If a waiting period is
required (such as for analog-to-digital conversion) then the master must wait for at least
that period of time before starting to issue clock cycles.
 During each SPI clock cycle, a full duplex data transmission occurs:
 the master sends a bit on the MOSI line; the slave reads it from that same line
 the slave sends a bit on the MISO line; the master reads it from that same line
 The master must select only one slave at a time.

Advantages
 Full duplex communication

 Uses only four pins on IC packages, and wires in board layouts or connectors, much less
than parallel interfaces.
 Extremely simple hardware interfacing.
 At most one "unique" bus signal per device (chip select); all others are shared.
Disadvantages
 No hardware flow control (but master can delay the next clock edge to slow the transfer
rate).
 No hardware slave acknowledgment (the master could be "talking" to nothing and not
know it).
 No error-checking protocol is defined.
 Only handles short distances compared to RS-232, RS-485, or CAN-bus
Serial Peripheral Interface, SPI

 The SPI is a synchronous serial interface in which data in an 8-bit byte can be shifted in
and/or out one bit at a time. It can be used to communicate with a serial peripheral
device or with another microcontroller with an SPI interface. The SPI system in the
68HC12 contains the four signals as shown in Fig. 1.
Operation of the SPI
 In the master SPI, the bits are sent out of the MOSI pin and received in the MISO pin.
The bits to be shifted out are stored in the SPI data register, SP0DR, and are sent out
most significant bit (bit 7) first. When bit 7 of the master is shifted out through MOSI
pin, a bit from bit 7 of the slave is being shifted into bit 0 of the master via the MISO pin.
After 8 clock pulses or shifts, this bit will eventually end up in bit 7 of the master.
 In the 68HC12 the least significant bit can be sent out first by setting the LSBF bit to 1 in
the SPI Control Register. The clock, which controls how fast the bits are shifted out and
into SP0DR, is the signal SCLK at PS6. The frequency of this clock can be controlled by
the SPI baud rate register, SP0BR. The SS pin must be low to select a slave. This signal
can come from any pin on the master, including its SS pin when it is configured as an
output.
 Spi microchip ppt

Serial Peripheral Interface

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What are the main components of an SPI system?

How does data transfer work in SPI communication?

Serial peripheral interphase:-

 SPI devices communicate using a master-slave relationship.

 Devices communicate using a master/slave relationship, in which the master initiates

 The SPI bus specifies four logic signals.

 The master must select only one slave at a time.

 Full duplex communication

Serial Peripheral Interface, SPI

 Spi microchip ppt

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