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As the circulating tank current flows through C1, C2, C3 in series, the equivalent
capacitance is
1
C1C2C3
C=
=
1 + 1 + 1
C1C2 + C2C3 + C3C1
C
C
C
1

1 1
1
1
f =
LC1 + LC 2 + LC3
2
In a clapp oscillator C3 is much smaller than C1 and C2. As a result, the equivalent
capacitance C is approximately equal to C3, and frequency of oscillation is given as
1
f =
2 LC3
Advantages:
In a clap - oscillator, the transistor and stray capacitances have no effect on capacitor C3,
so the oscillation frequency is more stable and accurate.

Q.24

Explain how opamp can be used as a

(i) Differentiator
(iii) Inverting amplifier

Ans:
(i)

(ii) Integrator
(iv) Summer

Differentiator:

Let i be the rate of change of charge i.e. dq/dt

Now charge, q = CVc
dq d
dV
i=
= CVc = C c
dt dt
dt
dV
Vout = iR = C. c R
dt
dV
Vout = CR c
dt

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(ii)

i (t ) =

Integrator:

V (t )
R

1
i (t ).dt
c
1 V (t )
Vout (t ) =
.dt
c R
1
Vout (t ) =
V (t ).dt + A
Rc
(iii) Inverting Amplifier:
Vout (t ) =

Iin

Vin V2 V2 Vout
=
R1
Rf

V2 = 0
Vin
V
= out
R1
Rf
R
Vout
= f
R1
Vin
(iv)
Summer
shows the summer circuit
Af =

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Since Ri and Av of the opamp are ideally infinity, IB = zeroAmps and V1=V2=0V
because of virtual ground.
Therefore, Va/Ra + Vb/Rb + Vc/Rc = - (Vo/RF)
Vo = - [(RF/Ra) Va + (RF/Rb)Vb + (RF/Rc)Vc]
If
Ra = R b= Rc = R then Vo = (-RF/R) [Va+Vb+Vc]
(v)
i.e., output voltage is equal to the negative sum of all the input times the gain of the circuit
RF/R.

Q.25

Explain the operation of a foldback current-limiting circuit connected to a series voltage

regulator, by drawing a neat circuit diagram.
(8)

Ans:
In a simple current limiting circuit, a large amount of power dissipation in series pass
transistor Q1 while the regulator remains short-circuited. The fold-back current limiting
circuit is the solution to this problem.
In this circuit base of transistor Q3 is based by a voltage divider network consisting of
resistor R6 and R7.
R7
VB3 =
(I L R5 + Vout ) = K (I L R5 + Vout )
--------(1)
R6 + R7
R7
Where K =
R6 + R7
Vout + VBE3 = VB3

VBE3 = VB3 Vout = K (I L R5 + Vout ) Vout

VBE3 = KI L R5 + ( K 1)Vout

---------(2)

Now if load resistance decreases, may be due to any reason, load current IL will increase
causing voltage drop ILR5 to increase. This causes VB3 to increase and therefore VBE3 to
increase. This makes transistor Q3 ON in a stronger way. The increased collector current
I C3 of transistor Q3 flows through the resistor R3 thereby decreasing the base voltage of
transistor Q1. This results in reduction of the conduction level of transistor Q1. Thus further
increase in load current is prevented.
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Q.26

BASIC ELECTRONICS
Prepare the truth-table for the function
(a, b, c) = abc + abc + a bc
Minimize the function using K-map. Draw the logic diagram using gates of your choice to
realize the minimized function.
(8)

Ans:
The function is f(a, b, c) = abc + abc + abc

f(a, b, c) = ac + ab

Logic realization:-

Q.27

Define mobility in a semiconductor. Does it also depend on doping levels?

(3)

Ans:
In the presence of electric field in a semiconductor, the electrons move with an
average velocity called drift velocity. Mobility is the ratio of drift velocity and
electric field.
The drift velocity is given by vd=E where
E=Electric field
=constant called mobility of the charge carrier.
Yes, the mobility depends on the doping levels.
Q.28

What is the quantity of mobility for electrons and for holes in a silicon semiconductor?

(2)

Ans:
The typical value of mobility of electrons in a silicon semiconductor is 0.13m2/V-s and that of
holes is 0.046m2/V-s.
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Q.29

BASIC ELECTRONICS
A semiconductor has donor and acceptor concentrations of ND and NA, respectively. What
relationship must be used to determine the electron n and hole
p concentrations in terms of intrinsic concentration ni?
(2)

Ans:

Q.30

We know that np = ni 2
For n type semiconductors: n ND
p = (ni) 2 / ND
For p type semiconductors: p NA
n = (ni) 2 / NA

What do you understand by cut-in voltage of a diode?

(4)

Ans:
The cut in voltage is the voltage across the diode below which current is very small(less than
1% of rated current) in the forward biased condition only.

Fig. 3(i)
The above figure shows the V-I characteristics of diode in the forward biased region. The
current is negligibly small for V smaller than about 0.5V. This value is usually referred to as
cut in voltage.
Q.31

Sketch the volt-ampere characteristics of zener diode. Indicate the knee on the curve and
explain its significance. What happens when the current in zener decreases below the knee
current?
(10)

Ans:
In the normal applications of zener diode, cathode is made positive with respect to the
anode. From the characteristics shown in fig 3 (ii), we see that for currents greater than the
knee current ( Izk ), the V-I characteristic is almost a straight line. The zener voltage Vz is
specified at nominal current Izt. As the current through the zener deviates from Izt, voltage
across changes only slightly.
The current change I is related to zener voltage change V by
V = rzI where rz = inverse of the slope of V-I curve at point Q.

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Fig. 3(ii)
Resistance rz is called dynamic resistance or incremental resistance of the zener diode at
operating point Q. Lower the value of rz, more constant is the zener voltage as the current
varies. From the V- I characteristics, it can be seen that rz remains low and almost constant
over a wide range of current. When the magnitude of I decreases below Izk, the zener ceases
to operate as a voltage regulator. Because small variations in current gives rise to large voltage
variations.

Q.32

(6)

Classify the amplifiers based on frequency response.

Ans:

(i) Wide band

(ii) Direct coupled

(iii) Tuned amplifier

(i) Wide band amplifier: The gain remains constant over wide frequency range, but falls off
at low and high frequencies as shown in the above Fig (i) .These are also called R-C
coupled or capacitively coupled amplifiers.
(ii) Direct coupled amplifier: It is also called as dc amplifier. The amplifier maintains its gain
at low frequencies as well as for dc signal as shown in Fig (ii).
(iii)Tuned amplifier: The gain peaks around certain frequency say 0 and falls off drastically
on both sides of this frequency. This is shown in Fig (iii).

Q.33 The low frequency response of an amplifier is characterized by the transfer

Function FL(s) = s(s+10) / [(s+100) (s+25)]. Represent its 3dB frequency
graphically.
Ans:
FL(s) = ((s+z1) (s+z2).) / ((s+p1) (s+p2).)
p1 and p2.. represent poles.
z1 and z2.. represent zeros.
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In many cases zeros have lower frequency much smaller than L. Also one of the poles will
have much higher frequency than all the other poles.
Therefore FL(s) s / (s+p1), where p1 = the largest value pole.
In this case, low frequency response of amplifier is dominated by the pole at
s = -p1 and lower 3dB frequency is approximately = p1
i.e.,L p1

This is called as dominant pole approximation. This approximation can be made if highest
frequency pole is separated from the nearest pole or zero by at least 2 octaves (i.e., factor of
4). If dominant low frequency pole does not exist, then

L = ( p1+p2-2z1-z2)
If FL(s) = (s (s+10)) / ((s+100) (s+25))

p1=100rad/sec is 2 octaves higher than 2nd pole and a decade higher than 0.
Hence, L= p1 = 100 rad/sec

Or L = p21 + 2p 2 2p1

)1/ 2

L = p21 + 2p 2 2 p1

Q.34

(100 2 + 25 2 2 10 2 = 102 rad/sec

Draw the characteristics of an n channel JFET. Enunciate the linear relationship that
represents the ip- Vs characteristics near the origin.

(8)

Ans:
The figure below shows a family of ID v/s VDS characteristics of an n channel JFET for various
values of VGS. For small values of VDS (below pinch-off), the depletion region of the gate
would not be affected much by the flow of drain current ID from one end of the gate to the
other end of the gate. This is true for a given value of VGS. As such, a linear relationship exists
between ID and VDS and the JFET behaves like a voltage-controlled resistor.
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Q.35

BASIC ELECTRONICS

Why are the characteristics of an n channel JFET, called static?

(2)

Ans:
The characteristics shown in answer to Q 34 are valid for dc conditions. Hence
they are called static characteristics.
Q.36

Write the equation, which represents the boundary between the triode region
region?

and pinch off

(4)

Ans:
The JFET operates in the triode region for
Vds > Vgs - Vp
Where Vds = drain to source voltage
Vgs = gate to source voltage
Vp = pinch off voltage
Q.37

Give the simplified circuit symbol for the depletion type n-channel MOSFET.

(2)

Ans:

Q.38

With the help of iD-VDS characteristic curve for small values of VDS explain the
physical operation of depletion type MOSFET (assume IDSS=16mA, VP=-4V
for the device)
(12)

Ans:
The depletion type n-channel MOSFET has originally n-type channel region. If a voltage VDS
is applied between drain and source, a current iD flows even for VGS=0. Applying positive
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VGS enhances the conductivity of the channel by attracting more electrons into it
(Enhancement mode). Applying negative VGS causes electrons to be repelled from the channel
resulting in lower conductivity and therefore is called depletion mode operation.
The depletion MOSFET can be operated in 3 distinct regions: Cut off, triode and saturation
region. FET used as an amplifier should be operated in saturation region. For operation as a
switch, cut off and triode regions are used.

For a depletion type n channel MOSFET, threshold voltage Vt is negative. The MOSFET will
operate in triode region as long as drain voltage does not exceed the gate voltage by more than
| Vt |. For it to operate in saturation, the drain voltage must be greater than the gate voltage by
at least | Vt | volts. The device is cut off when |VGS| < | Vt |. In saturation region the MOSFET
provides a drain current whose value is independent of drain voltage VDS and is determined by
gate voltage only. When VGS=0, application of positive VDS produces an appreciable drain
current IDSS. As VGS decreases towards threshold, the drain current decreases. At fixed VGS,
increasing values of VDS cause the drain current to saturate as the channel becomes pinched
off.

Q.39

What is Hall effect in a semiconductor? How the Hall Effect can be used to determine some of
the properties of a semiconductor?
(7)

Ans:
If a specimen of semiconductor carrying a current(I) is placed in a transverse magnetic field
(B) then an electric field is induced in a direction perpendicular to both I and B. This
phenomenon is known as Hall Effect.
Hall effect is used to measure carrier concentration and mobility. Consider an N type
semiconductor carrying current (I) placed in a transverse magnetic field (B) in the direction as
shown in the Fig.
Due to forces exerted on the electron by electric and magnetic field, a Hall voltage (VH) is
induced as shown. In order to obtain equilibrium state,
F (electric) + F (magnetic) =0
n.q.E + B.J= 0
i.e E = - BJ/n.q
where J = current density
n = electron concentration
q = electronic charge
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Fig.
The Hall co-efficient RH is given by RH = 1/n.q
E = + B.J. RH
But E = VH / d
where VH = Hall voltage
d = distance between front and back surface
Also J = I/A = I/d.t
where t = thickness of the semiconductor.
VH /d = B (I / d t)* (1 / n q)
VH = BI / n.q.t or n = BI / q tVH
n = density of electrons.
Conductivity of an extrinsic semiconductor is given by
= n.q.n
Where n = electron mobility &
Or = p.q.p
p = Hole mobility
Therefore n = /nq =RH
Q.40

Draw the circuits of the various transistor configurations. Why common emitter
configuration is mostly used? Give its typical uses.

Ans:
A transistor can be connected in a circuit in the following three configurations.
1. Common base configuration

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2. Common emitter configuration

3. Common collector configuration

The reasons for wide use of CE configuration are

High current gain: In CE configuration IC is output current and IB is the input current.
Collector current is given by IC = IB. As the value of is very large output current IC is
much more than the input current IB. The value of is ordinarily high and ranges from 10 to
500.
(ii) High voltage and power gain: Due to high current gain the CE configuration has the
highest voltage and power gain of the three transistor configurations.
(iii) Moderate output to input impedance ratio: In the CE configuration the ratio of output
impedance to input impedance is small. Therefore this configuration is ideal for coupling
between various transistor stages. CE configuration is used for small signal and power
amplifier applications.
(i)

Q.41

What is transistor biasing? What are the basic conditions which are to be necessarily
fulfilled for achieving faithful amplification of input signal in transistor amplifiers? (7)

Ans:
Fixing the d.c values of current and voltages of transistor under quiescent or no signal
condition is biasing. The quiescent point should lie in the central area of an active, linear
region of the transistor.
The basic purpose of transistor biasing is to keep the base emitter junction properly forward
biased and collector base junction properly reverse biased.
The basic conditions required for achieving faithful amplification of input signal in transistor
amplifiers are:
1) Proper zero signal collector current: The value of zero signal current should be at least
equal to the maximum collector current when the signal is present.
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2) Proper minimum base emitter voltage: To achieve faithful amplification the base emitter
voltage (VBE) should not fall below 0.5V for germanium and 0.7V for silicon transistors at any
instant.

Q.42

What are the advantages of the FET over a conventional bipolar junction transistor? Define
pinch off voltage, transconductance, amplification factor and drain resistance of a FET.
Explain with the help of circuit diagram how an FET is used as a voltage amplifier and as
voltage dependent resistor (VDR).
(14)

Ans:
FET is a majority carrier device. FET is a voltage controlled current source. An important
advantage of the FET is that it is simpler to fabricate and occupies less space on a chip than
does a BJT. FET has a negative temperature co-efficient at high current levels, which
prevents FET from thermal break down. FET has high switching speed and cut off frequency.
Pinch off Voltage:
It is the voltage at which the drain current reaches the maximum value and beyond which
drain current becomes constant.
Transconductance (gm):
It is the ratio of small change in drain current (ID) to the corresponding change in gate to
source voltage (VGS) for a constant drain to source voltage VDS. i.e.,
gm = ID / VGS VDS constant.
Amplification factor ():
It is the ratio of small change in drain to source voltage (VDS) to the corresponding change in
gate to source voltage (VGS) for a small constant drain current ID. i.e.,
= VDS / VGS at constant ID.
Drain resistance:
This may be DC or AC. DC or static drain resistance is the ratio of VDS to ID.
i.e RDS = VDS / ID
A.C or dynamic drain resistance is the resistance between the drain and source when FET is
operating in pinch off or saturation region.
rd = VDS /ID
FET as an amplifier is shown in Fig.9 i.

Fig:9 (i)
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An enhancement n-channel MOSFET is biased with a battery VGS. A time varying signal vgs
which is to be amplified is superimposed on gate to source dc bias VGS. Thus the total
instantaneous gate voltage is
vGS = VGS + vgs
The operating point can be got by intersection of load line and ID versus VDS curve
corresponding to instantaneous values of vGS.
When a sinusoidal signal vGS is applied the instantaneous operating point will move along the
load line in correspondence with total instantaneous voltage vGS. The output signal is an
amplified replica of the input signal. Linear amplification can be obtained by properly
choosing the dc bias point Q and by keeping the input signal amplified.
FET as voltage dependent resistor:

FIG: 9 (ii)
Figure 9 (ii) shows the output characteristics of an FET. It shows the variations of ID with VDS
for constant VGS.
If we consider the slope of the curve for low values of VDS, we see that the slope varies with
variations in VGS. As the slope is related to the resistance, we can say that the resistance would
be different for different values of VGS.
Hence for a given VDS = V1, the resistance depends on gate voltage and thus it is seen that FET
acts as voltage dependent resistor.
Q.43

What is a tuned amplifier? What is the fundamental difference between audio

amplifiers and tuned amplifiers? How is bandwidth related to resonant frequency (fr)
and the quality factor (Q).

(7)

Ans:
Tuned amplifiers are the ones, which amplify a specific frequency or a narrow band of
frequencies. Audio amplifiers provide the constant gain over a wide band of frequencies.
Tuned amplifiers are designed to have specific, usually narrow bandwidth. This is shown in
Fig. 10 (a). BWA is the bandwidth of response of a typical audio amplifier, while BWT is the
bandwidth of tuned amplifier and fr is called the center frequency of tuned amplifier.

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Fig. 10(a)
The quality factor Q of a tuned amplifier is equal to the ratio of center frequency (fr) to
bandwidth (BWT) i.e
Q = fr/BWT
Q is determined by the circuit component values. For a parallel resonance circuit is given by
fr = 1/ (2LC) and Q = X L / R where XL is the reactance of the inductor having resistance R.

Q.44

Discuss the terminal properties of an ideal operational amplifier.

(7)

Ans:
The Fig. 11(a) shows the schematic of an ideal op-amp. The following are the important
properties of an ideal op-amp.
i) The input impedance of an ideal op-amp is infinite. Hence it draws no current at both the
input terminals.
ii)The gain of an ideal op-amp is infinite ( ), hence the differential input Vd =V1-V2 is zero
for the finite output voltage V0.

Fig. 11(a)
iii) The output voltage V0 is independent of the current drawn from the output terminal. Thus
its output impedance is zero.
This results in the following Characteristic of an ideal op-amp.
a) Infinite Voltage gain: It is denoted as AOL. It is the differential open loop gain.
b) Infinite input impedance: It is denoted as Rin and ensures that no current flows into an
ideal op-amp.
c) Zero output impedance: It is denoted as Ro and ensures that the output voltage of the opamp remains the same, irrespective of the load.
d) Zero offset voltage: This ensures zero output for zero input signal voltage in an ideal opamp.
e) Infinite bandwidth: This ensures that the gain of the op-amp will be constant over the
frequency range from d.c to infinite.
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f)

Infinite CMRR: This ensures zero common mode gain for an ideal op-amp. Due to this
common mode noise output voltage is zero.
g) Infinite slew rate: This ensures that the changes in the o/p voltage occur simultaneously
with the changes in the input voltage.

Q.45

What is an ideal diode? Sketch the characteristics of an ideal diode.

(7)

Ans:
An ideal diode may be defined as a two terminal device which
a. Conducts with Rf = 0, when forward biased
b. Rr = , when reverse biased
In other words, an ideal diode acts as a short circuit in the forward direction and as an open
circuit in the reverse direction. An ideal diode behaves like a switch which is closed in the
forward direction and open in the reverse direction.
VI characteristics of an ideal diode:
The VI characteristics of an ideal diode are shown in Fig. 12a. The part of the characteristics
in forward biased condition coincides with the iD axis, and the part for reverse condition
coincides with the VD axis as shown by the dark lines.

Fig.12a
Q.46

Describe the construction and operation of JFET. How does it differ from a MOSFET? Draw
the equivalent circuit of a JFET and explain how do we bias for operation as an amplifier.
(7)
Ans:
The basic structure of an n-channel JFET is as shown in Fig.14a(i). The drain and source
terminals are made by ohmic contacts at the ends of n-type semiconductor bar. Gate is formed
by electrically connecting two shallow p+ regions. The n-type region between two p+ gates is
called the channel through which majority carriers flow between the source and the drain.
Operation:
Gate regions and channel constitute pn junction. In normal operating mode, this pn junction is
maintained in reverse biased state. Gate to source voltage is negative and drain to source
voltage is positive. This reverse biases the junction, and hence the depletion region exists. The
depletion region contains immobile charges.

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Fig.14a(i)
Also, depletion region extends more into region of lower doping. Since gate region is heavily
doped than the channel region, depletion region penetrates more deeply into the channel. The
conductivity of this region is nominally zero because of unavailability of charge carriers.
Therefore, as reverse bias increases, the effective width of the channel decreases. At specific
value of gate to source voltage (VGS) the channel width becomes zero because all the free
charges have been removed from the channel. This voltage is called pinch off voltage (Vp).
Therefore, for a fixed drain to source voltage, the drain current will be a function of reverse
bias voltage across the gate junction.
In a MOSFET metal gate electrode is separated by an oxide layer from the semiconductor
channel.
FET as an amplifier: Fig.14a(ii) shows a Common Source (CS) configuration. The signal to be
amplified is V1. VGG provides the necessary reverse bias between gate and source of JFET.
This is the biasing arrangement for the operation of JFET as an amplifier.

Fig.14a(ii)
Low frequency small signal equivalent circuit of JFET

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Fig.14a(iii)
Q.47 Draw the circuit diagram of a collector tuned amplifier and derive the expression
for the voltage gain at the tuned frequency.
Ans:
The collector tuned circuit is shown in Fig.16a (i)

Fig.16a(i)

Fig.16a(ii)

Fig.16a(iii)

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The equivalent circuit of the amplifier is shown in Fig.16a(ii),
Rt = Ro || Rp || Ri
where R0 = output resistance of current generator gmVbe and is equal to (1/hoe)
Ri = input resistance of next stage
Rp = equivalent internal resistance of L calculated when series L circuit is
represented by its equivalent parallel circuit.
Voltage Gain AV= Vo/Vi
From Fig.16a(iii) output voltage can be given as
Vo = -gmVbeZ
where Z = impedance of C, L and Rt in parallel or,
Z = Rt/(1+2jQeff)
Qeff = Rt/rL
and r = resonant frequency
and = fractional variation in resonant frequency = (-r) / r
At resonant frequency = r and = 0.
Z (at resonance) = Rt
Fig.16a(iii)shows the final equivalent circuit of Fig.16a(ii).
Hence Vo = -gmVbeRt at resonance
Also Vbe = Vi(rbe/(rbb+rbe)) ( from Fig.16a(ii) neglecting Cs)
Vo = -gmVi( rbeZ / (rbb+rbe))
AV = Vo/Vi = -gmVi(rbeZ/(rbb+rbe))
= -gm(rbe/(rbb+rbe)) x (Rt/(1+2jQeff))
At resonance, voltage gain is
AV = -gm(rbe/(rbb+rbe)) x Rt

Q.48

Explain the reasons for potential instability in tuned amplifiers.

(7)

Ans:
A tuned amplifier is required to be highly selective. Instability is because of
positive feedback in tuned amplifiers.
Q.49

What are intrinsic and extrinsic semiconductors? Comment on the conductivity of extrinsic
semiconductor.
(4)

Ans:
A pure semiconductor which is not doped is said to be intrinsic semiconductor. They have
very low conductivity. When pure semiconductors are mixed (doped) using trivalent or
pentavalent elements, we get extrinsic ones, which are p type in the former case and n type in
the latter.
The crystalline nature of the original semiconductor is unaltered by doping as the doping
element atoms replace the original semiconductor atoms without disturbing the crystal
structure as such. This happens by participation of electrons of doping element with those of
semiconductor in forming bonds. However, either an extra electron as in the case of
pentavalent dopant or a free hole as in the case of trivalent dopant greatly enhances the
conductivity.
Q.50 Explain the classification of power amplifiers according to operational modes.

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Ans:
Classification according to operation mode:
The duration of device conduction with respect to input signal cycle period determines the
class of operation.
Class A: Device current flows for the full period of input (Q point in the active region of the
device).
Class B: Device conducts only during one half cycle of input. (Q point just at the cut off
region of the device)
Class AB: Device conducts for greater than half cycle but less than full cycle of input.
Class C: Device conducts for less than half cycle of input. (Q point beyond cut off).
These different operations are achieved by appropriate biasing of the device by setting up the
desired quiescent current and voltage (or Q-point). Fig. 20 b. illustrates the conditions for
class A and class B.

Fig. 20 b
Q.51 Draw a block diagram of a single loop feedback amplifier, and explain the function of each
block. What are the characteristics of an amplifier that are modified by negative feedback? For
the four topologies of negative feedback, indicate whether the input impedance and out
impedance increase or decrease as a result of feedback.
(9)

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Ans:
The block diagram of a single loop feedback amplifier is as shown in Fig. 21a
Signal source: The signal source is either a voltage source or a current source providing input
Xs.
Comparator or mixer: This block combines the source signal with the feedback signal.
Depending upon the nature of signal and feedback this may be series or shunt mixing.
Basic amplifier: The ratio of output signal to the input signal of a basic amplifier is
represented by A and depends on the type of amplifier.
Sampling network: It is used to sample the output signal of the basic amplifier. When voltage
has to be sampled, feedback network is connected in parallel to the output terminals and in
series when current is to be sampled.

Fig. 21a
Feedback network: This is a passive two port network providing a known fraction of the
input to the mixer at input.
The characteristics of an amplifier that are modified by negative feedback are:
1. Sensitivity of transfer characteristics.
2. Non linear distortion.
3. Noise.
4. Frequency distortion.
5. Bandwidth.
6. Input and output impedances of the amplifier.
Table below shows how the input impedance and output impedance in the four topologies of
negative feedback are affected.

I/P impedance
O/P impedance

Voltage
Series
Increases
Decreases

Current
Series
Increases
Increases

Q.52 Write short notes on any two.

i) Nyquist criterion.
ii) BIFET and BIMOS circuits.
iii) Schmitt trigger.
iv) The digital comparator.

Current
Shunt
Decreases
Increases

Voltage
Shunt
Decreases
Decreases

(2x7)

Ans:
i) Nyquist criterion:
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Fig.22 (i)-Stable system

Fig.22(ii) unstable system

The diagrams above shows Nyquist plot for 2 types of systems (stable and unstable).
Solid line is for positive frequencies. The Nyquist plot intersects the negative real axis at a
frequency 180. If intersection occurs to the left of point (-1, 0), then the magnitude of loop
gain at this frequency is greater than unity and amplifier will be unstable. If intersection occurs
to the right of point (-1, 0) the amplifier will be stable. In other words, if Nyquist plot encircles
the point (-1, 0) then amplifier will be unstable.
Nyquist plot is used to determine whether there are any poles on the right half of s-plane for a
feedback amplifier.
Nyquist criterion states that the number of clockwise encirclements of the point 1+j0 is equal
to the difference between the number of poles and zeros of F(s)=1+T(s) in the right half of s
plane. (T(s) is the return ratio).
Closed loop gain of feedback amplifier = AF(s) = AOL(s) / F(s)
AOL(s) = loop gain of the amplifier without feedback.
Therefore for a stable feedback amplifier, the Nyquist plot of function AF(s) should not
encircle the point 1+j0. The clockwise encirclements of 1+j0 are determined by drawing a
radius vector from 1+j0 to Nyquist diagram and tracing the locus of points from - < < .
In Fig.22 (i) there is no encirclement, therefore AF(s) has no right half poles and hence the
amplifier is stable.
In Fig.22 (ii)there are two encirclements, therefore AF(s) has two right half poles and hence
the amplifier is unstable.
ii) BIFET and BIMOS circuits:
Ion implantation permits the fabrication of JFETs / MOSFETs and BJTs on the same chip. The
ICs fabricated by this process are called as BIFET/BIMOS. (BIFET=BJT+FET,
BIMOS=BJT+MOSFET). All BIFET (BIMOS) op-amps use FET input stages. The remaining
stages use BJTs. FET input stages have the following advantages over BJT input stages:
1) Higher differential mode input resistance.
2) Lower input current and hence decreased input offset currents and higher slew rates.
The input resistances of FET differential stages are 4 times higher in magnitude than that of
BJTs. Input bias current of JFET is the reverse saturation current IGSS of reverse biased gate to
channel junction. The gate current of FET is usually much smaller than the base current of
BJT for similar values of drain/collector currents. Since the input current IG is very small, the
offset current due to device mismatch is also much smaller than that with BJT circuits. For a
given drain current ID, value of gm in FET is smaller than the gm of BJT biased at IC= ID.
Therefore, the reduction of gm results in increased slew rate. This lower value usually results
in lower differential mode gain in FET stage compared to that with BJT circuits. To overcome
this limitation, BIFET and BIMOS Op-amps employ three-stage architecture.

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iii) Schmitt trigger:
It is also called as regenerative comparator. It converts any given waveform into a rectangular
output. The Schmitt trigger circuit is shown in Fig 7 (iii a). Input is applied to inverting
terminal (2) and feedback voltage to non-inverting terminal (1).
Assuming that the output resistance of the comparator is negligible compared with R1+R2, we
get V1 = [R2 / (R1+R2)] Vo.
Let vo = Vz+VD
Vz = drop across reverse biased zener.
VD = drop across forward biased zener.
And if v2<v1 so that vo= +Vo

Fig 22 (iiia) Schmitt Trigger

The voltage at non-inverting terminal is given by
VA+ R2 (V0-VA) = V1 (v2<V1)
R1+R2
If v2 is now increased, then vo remains constant and vo = + V0 constant until v2=V1, when v2
exceeds V1, v0 changes.
At this threshold voltage, the output regeneratively switches to -V0 and remains at this value
as long as V2>V1. This is shown in Fig 22 (iiib).

Fig 22 (iii c): Hysteresis curve

Fig 22 (iii b)
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The voltage at non-inverting terminal for V2>V1 is given by
V1 = VA- R2 (Vo+VA) = V2 (V2<V1)
R1+R2
Note that and difference between these 2 values is called as hysteresis VH.
VH=V1-V2
If we now decrease V2, output remains at Vo until V2 = V2. At this voltage a
regenerative transition takes place as indicated in fig 22(iii c) and output returns to +Vo almost
instantaneously.
This circuit can be used as a squaring circuit. The output is asymmetric square wave,
the amplitude of which is independent of peak-to-peak value of input signal. The input and
output waveforms are as shown in the following figure below.

Fig 22 (iiid)
(a)

Alternative Solutions I
Schmitt trigger:
Consider the circuit shown in figure 22 (i). This circuit converts an irregular shaped
waveform to a square wave or pulse. The circuit is known as the Schmitt trigger or squaring
circuit.

The input voltage Vin triggers the output Vo every time it exceeds certain voltage level
called the upper threshold voltage Vut or becomes smaller than the lower threshold voltage Vlt
as in Fig below. These threshold voltages are maintained in the circuit by using the voltage
divider R1, R2 where the voltage across R1 is fed back to the (+) input. The voltage across R1 is
dependent upon the value and polarity of Vo. When Vo = +Vsat voltage across R1 is called
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upper threshold voltage Vut, Where Vut = (R1/(R1 + R2)) *Vsat . When V0 = -Vsat voltage across
R1 is referred to as the lower threshold voltage Vlt and is given by
Vlt = (R1/ (R1 + R2))* (-Vsat).
If Vut & Vlt are larger than the input noise voltages, +ve feedback will eliminate the false
output transitions & due to regenerative action Vo switches faster between +Vsat and
Vsat. ROM R1 R2 is used to minimize the offset problems.

A comparator with a positive feedback exhibits hysteresis. When input of the

comparator exceeds Vut, its output switches from +Vsat to Vsat & reverts to its original state.
Hysteresis voltage Vhy = Vut Vlt.
(b) Alternative Solution II
Schmitt trigger is used to change a slowly varying input voltage into an output waveform of an
abrupt discontinuous change that occurs at a precise value of the input voltage. It is used as a
squaring circuit.
Schmitt trigger is also called as regenerative comparator. Input is applied to inverting terminal
and feedback voltage to non-inverting terminal .The Schmitt trigger circuit is as shown in the
Fig.(i). It consists of two similar transistors Q1 and Q2 coupled through RE and resistors R1, R3,
R4 from a voltage divider across VCC to VBB which places a small positive voltage on the
base of Q2.
Circuit operation:
When positive half cycles of input A.C voltage is applied to the input and suppose this
positive voltage is sufficient to overcome the reverse bias on the base of Q1, The sequence of
events that follows is as follows.
1. Q1 comes out of cut off and starts to conduct.
2. Its collector voltage drops. (swings negative).
3. This negative swinging is coupled to the base of Q2 via R3 reducing its forward
bias and hence its IE .
4 With reduced IE voltage drop across RE is reduced.
5. Consequently, the reverse bias of Q1 is further lowered and it conducts more
heavily.
6. As a result, collector voltage of Q1 falls further there by driving Q2 still closer to cut off.
This process ends up with
1. Q1 conducting at saturation with its collector voltage almost zero.
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2.

Q2 becoming cut off with its collector voltage nearly VCC.

Fig.(i)-Schmitt Trigger
This circuit can be used as a squaring circuit. The output is asymmetric square wave, the
amplitude of which is independent of peak-to-peak value of input signal. The input and output
waveforms are as shown in the Fig.(ii).

Fig.(ii)
Hysteresis:

Fig.(iii)
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The transfer characteristics i.e., Vin v/s Vo is shown in Fig.(iii).
Due to the positive feedback the comparator is said to exhibit hysteresis. The portion without
arrows may be traversed in either direction, but other segments can be obtained only if V2 is
increased or decreased in given direction.
Because of hysteresis, circuit triggers at a higher voltage for increasing than for decreasing
signals.
iv) The digital comparator:
A comparator is used to detect whether a binary number is greater than, equal to or less than
another binary number. Consider two single bit numbers A and B,

One bit comparator

Where C=1 for A>B
E=1 for A=B
D=1 for A<B
a) Let A=B
EX - NOR gate is an equality detector. The output E of EX-NOR is given by

b) Condition A>B is given by C=AB=1 because if A>B then A=1 and B=0 therefore C=1
here
if A=B or A<B (A=0, B=1) then C=0.
c) Condition A<B is determined from D=AB=1
Consider a 4-bit comparator. (A & B are 4 bit numbers).
a) For A = B, A3 = B3, A2 = B2, A1 = B1, A0 = B0
Therefore E=E3E2E1E0
If A = B then E = 1
If A B then E = 0
b) For A>B: A3 >B3 (MSB)
Or A3=B3 and A2>B2
Or A3=B3 and A2=B2 and A1>B1
Or A3=B3 and A2=B2 and A1=B1 and A0>B0
This is given by
C = B3A3 +B2E3A2 +B1 E3E2A1 +B0 E3E2E1A0
If A>B then C = 1
d) For A<B: in the above equation interchange A and B, to get the output D.
Digital comparators are useful in comparing binary words and the result of comparison is used
to initiate various actions in a digital system.

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Q.53

BASIC ELECTRONICS
With the help of a circuit diagram, explain the working of a half wave rectifier
with capacitor filter.
Ans:

(8)

Fig 23 (i)
The circuit of a half wave rectifier is shown in the Fig 23 (i). For a sinusoidal input, the
capacitor charges to the peak (Vp) of input. Then the diode cuts off and the capacitor
discharges through the load resistor R. As the capacitor is discharging, the voltage at the
cathode of the diode decreases. At some instant of time input voltage exceeds the capacitor
voltage and the diode turns on. The capacitor now starts charging and the process repeats, and
is shown in the figure 8 (ii b).To keep the output voltage from decreasing too much, during
capacitor discharge, value of C is selected so that the time constant RC is much greater than
the discharge interval.

Q.54 Draw the load voltage waveform for a half wave and full wave rectifier with a
capacitor filter (no explanation required).
(6)
Ans:

Fig 23 (ii a): for Half wave rectifier

Fig 23 (ii b): for Full wave rectifier

Q.55

Explain the terms fan in and fan out in logic gates.

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Ans:
Fan in: Fan in of a gate is the number of inputs it can accept without affecting the input
characteristics of the gate. If fan in is exceeded, a logic gate will produce either an undefined
or incorrect output state. Also, the input signals may be deteriorated because of excessive
loading.
Fan out: A logic gate may be capable of providing input to several similar gates. Fan out is
the number of similar circuits a gate can drive without any effect on its output characteristics.

Q.56

Using 4 variable K map, find all the prime implicants of the following switching
function.
f(w,x,y,z)=(0,1,2,5,7,8,9,10,13,15)
And from the set of prime implicants thus obtained, find out minimal sum of
product expression of the function.
(10)

Ans:

The K map is shown above for the given function. The prime implicants are
(i) xz
(ii)xy
(iii)xz
The minimum SOP representation is:
f (w,x,y,z) = xz +xy+xz

Q.57

(4)

What is the function of A/D converter?

Ans:
Data obtained from the physical system will be analog in nature. For processing
these signals several methods are employed and all these systems require the inputs in the
digital form. So if the analog signals are to be processed and analyzed, they should be
converted into digital form. Therefore A/D converters are used to convert the signals in analog
form into digital form.
Q.58

Explain 3 bit parallel comparator ADC with the help of a diagram and give its truth
table.
(10)

Ans:
Parallel comparator ADC is the fastest type. In this method, analog voltage Va is
applied to all the comparators. The reference voltage to first comparator is (7/8) V, to second
comparator is (6/8) V and so on. The reference voltage to last comparator is V/8. Above
diagram shows a 3 bit ADC. It requires 7 comparators.
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Working: When input voltage is below the reference voltage of the comparator, the output of
the comparator is low (logic 0). When input voltage is above the reference voltage, the output
of that comparator is high (logic 1).

For example:if input voltage Va is between (2/8) V and (3/8) V then W1=1, W2=1 and all
other W values are 0. For this, the digital output of the encoder should be 2 (Y2=0, Y1=1,
Y0=0) which is interpreted as an analog voltage between (2/8) V and (3/8) V.
When Va < (1/8) V, then W1 to W7 are all 0 and output is zero. (Y2=Y1=Y0=0).

The truth table is as follows:

INPUTS
W7 W6 W5 W4 W3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
1
1
1
0
1
1
1
1
1
1
1
1
1
Q.59

W2
0
0
1
1
1
1
1
1

W1
0
1
1
1
1
1
1
1

Y2
0
0
0
0
1
1
1
1

OUTPUTS
Y1
Y0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1

What is an oscillator? How does it differ from an amplifier? What are the essential parts of an
oscillator circuit?
(7)

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Ans:
The oscillator is a circuit which generates signals of constant amplitude and frequency. The
circuits which generate sine waves using resonance phenomena are known as linear
oscillators. The circuits which generate square, pulse or rectangular waveforms are called as
nonlinear oscillators.

Fig 27a: Basic structure of a sinusoidal oscillator

Amplifier is a device which produces an enlarged version of the output signals same as that of
input. Amplifier is an energy conversion device, which gets energy from the dc source and
converts into an a.c source. Conversion is controlled by the input signal. Oscillator produces
an output signal without any input signal of any frequency. It produces output signal, as long
as the dc power is supplied.
An amplifier usually employs negative feedback whereas the oscillator will have positive
feedback.
The essential parts of an oscillator circuit are
i) Transistor amplifier
ii) Frequency selective network: The Frequency selective network is connected in positive
feedback loop. A part of the output signal is fed to the amplifier in phase to aid the
oscillations, as shown in Fig 27a, where Xs= 0 for an oscillator.

Q 60

Draw the circuit diagram of Colpitts oscillator and explain its working.

(7)

Ans:
The circuit diagram of a Colpitts oscillator is as shown Fig 27b.It uses two capacitors C1 and
C2 placed across a common inductor L and the center of the two capacitors is tapped. This
forms the frequency selective feedback network. The transistor circuit is the amplifier.
Operation:
When the circuit is turned on, the capacitors C1 and C2 are charged. The capacitors discharge
through L, which sets up oscillations of frequency
fo = 1 / 2LC
Where C = C1 C2 / (C1 + C2). The output voltage of the amplifier appears across C1 and
feedback voltage is across C2. The voltage across C2 is 180o out of phase with the voltage
across C1. The voltage across C2 is fedback to the transistor providing a positive feedback.

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Fig 27b
A phase shift of 180o is produced by the transistor and a further phase shift of 1800 is
produced by C1-C2 voltage divider. Therefore, the feedback is properly used to produce
continuous undamped oscillation.

Q.61

What is an integrator? Derive the formula for its output voltage. Explain its working with neat
and clean waveform i) In case of square wave input ii) In case of sine wave input. (8)

Ans:
A circuit in which the output voltage is directly proportional to the integral of the input
voltage is called an integrator. Integrators can be passive integrator or active integrator. Fig
28a(i) shows an active integrator using op-amp.

Fig 28a(i)
Expression for output voltage:
Since node B is grounded, node A is also at ground potential. Hence VA=VB=0. As the input
current of op- amp is zero, the current through CF is the current through R1. From input side
I = Vin/R1
From output side
I = CF d(VA-VO)/dt = - CF(dVO/dt )
Therefore
Vin/R1 = - CF (dVO/dt )
Integrating
t
(Vin/R1) dt = - CF dVo / dt = - CF VO
0
t
Vo = -(1/R1 CF) Vin dt
0

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Working of an integrator for square wave input:
Let the input waveform be a square wave as shown in Fig 28a(ii). It can be observed that the
square wave is made up of steps i.e., step of A between time period of 0 to T/2 while a step
of -A between T/2 and T.
Mathematically it can be expressed as
Vin (t) = A, 0<t<T/2
= -A, T/2<t<T
The output for step input is a straight line with a slope of A. So in the period 0 to T/2,
the slope is A. From T/2 to T slope becomes (-A) i.e. +A.
Therefore output VO (t) = -At 0<t<T/2
= +At T/2<t<T.

Fig 28a(ii)

Fig 28a(iii)
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Working of an integrator for sine wave input signal:
Let the input waveform is purely sinusoidal with a frequency of rad/sec.
i.e., Vin (t) = Vm Sin t, where Vm is the amplitude of sine wave and T is the period of the
waveform. To find the output waveform, let R1C1 = 1 and VO (0) = 0V.
VO (t) = - Vin dt = - Vm sin t dt
= - Vm [1/ (-cos t)] = -Vm / (-cos t)
Thus the output of an integrator is a cosine waveform for a sine wave input. The waveforms
are as shown in Fig 28a(iii).

Q.62

Derive the formula for summing amplifier and on averaging amplifier in non
Inverting configuration.

(6)

Ans:
A summer that gives non inverted sum of the input signals is called as non- inverting summing
amplifier. The circuit is shown in Fig 28b(i).

Fig 28b(i)

Q.63

Let the voltage at node B be VB. Node A is at the same potential.

Therefore VA = VB
From input side I1 = (V1 VB)/R1 and I2 = (V2 VB)/R2
As input current of op-amp is zero, I1 + I2 = 0
Therefore (V1 VB)/R1 + (V2 VB)/R2 = 0
V1/R1 + V2/R2 = VB (1/ R1 + 1/ R2)
This gives, VB = (R2V1 + R1V2)/ (R1 + R2)
At node A, I = VA/R = VB/R and I = (VO VA) / R3 = (VO VB) /R3
Therefore, VB/R = (VO VB) /R3
i.e., VO/R3 = VB (1/R3 + 1/R)
Therefore, VO = VB [(R + R3) / R]
i.e., VO = ([R2V1 + R1V2] / [R1 + R2])* ([R + R3] / R)
Therefore VO = R2(R + R3) V1 / R (R1 + R2) + R1(R + R3) V2 / R (R1 + R2)
If R1 = R2 = R = R3 we get VO = V1 + V2
If in the summer circuit the value of resistance are selected as R1 = R2 = R and
R3 = R / 2. Then
VO = [(R/2) V1/R + (R/2) V2/R]
= [(V1 + V2)/2]
Thus the magnitude of the output voltage is the average of the input voltages. In that case the
input becomes a averaging amplifier.
_
_
For the logic expression Z = AB + AB
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(2)
(1)
(4)

i) Obtain the truth table.

ii) Name the operation performed
iii) Realize this operation using *AND, OR, NOT gates * only NAND gates

Ans:
(i) Truth Table
_ _ _
_
_
_
A B A B AB AB
AB + AB = Z
0 0 1 1
0
0
0
0 1 1 0
0
1
1
1 0 0 1
1
0
1
1 1 0 0
0
0
0
(ii) The operation performed is Exclusive OR operation.
(iii)Circuit realization using AND, OR, NOT gates.

(iv)Circuit realization using NAND gates only.

Q.64

State and prove De Morgans theorem using truth table.

(7)

Ans:
The De Morgans theorem can be stated as follows
Theorem 1: The complement of a product of variables is equal to the sum of the complements
of the individual variables. Symbolically,
(A.B.C.D.) = A + B + C + D +
Theorem 2: The complement of the sum of variables is equal to the product of individual
complements of variables. Symbolically,
___________
_ _ _
(A + B + C +..) = A. B. C . . . .
The theorems can be verified by using truth table.
The truth table shown in table 1 for two variables A and B gives justification for theorem 1,
and table 2 for theorem 2.
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____ _ _ _ _
B A+B A+B A B A.B
0
0
1
1 1
1
1
1
0
1 0
0
0
1
0
0 1
0
1
1
0
0 0
0
Table 1
___ _ _ _ _
A B AB AB A B A + B
0 0 0
1
1 1
1
0 1 0
1
1 0
1
1 0 0
1
0 1
1
1 1 1
0
0 0
0
Table 2
A
0
0
1
1

Q.65

What is a JK flip flop? How does it differ from the SR flip flop in construction and operation?
(7)
Ans:
A JK flip flop is a refinement of the RS flips flop, in that the indeterminate state of the RS
type is well defined in the JK type. When input to RS flip flop are R=S=1, both outputs of flipflop are at logic 0. When J = K =1 JK is flip flop, it complements the outputs. That is if
Q =1, it switches to Q =0 and vice versa. Fig 30 (a) shows the logic diagrams of SR flip flop
and JK flip flop. In the logic circuit of JK flip-flop output Q is ANDed with K and CP inputs
so that the flip-flop is cleared during a clock pulse only if Q was previously 1. Q is ANDed
with J and CP inputs so that the flip-flop is set with a clock pulse only if Q was previously 1.

RS flip flop

Fig 30 (a)

JK flip flop

Thus JK flip-flop behaves like an RS flip flop, except when both J & K are equal to 1. When
both J & K are 1, the clock pulse is transmitted through one AND gate only, the one whose
input is connected to the output which is presently equal to 1. Thus if Q = 1, the output of the
upper AND gate becomes 1 upon application of a clock pulse and the flip-flop is cleared. If
Q = 1, the output of the lower AND gate becomes a 1 d the flip flop is set. In either case the
output state of the flip-flop is complemented.

Q.66

What is a sequential logic circuit? How does it differ from the combinational type?

(4)

Ans:
A sequential circuit is one whose output depends on the present inputs as well as on the past
outputs In a combinational circuit, output at any instant of time depends only on the present
inputs. Such systems are called memory less systems.
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A block diagram of a sequential circuit is shown in Fig 30 (B). A combinational circuit and
storage elements are interconnected to form the sequential circuit. Storage elements store
binary information.

Fig 30 (B)
The sequential circuits receive binary information from its environment via inputs. These
inputs together with the present state of the storage elements, determine the output. They also
determine the values used to specify the next state of the storage elements.

Q.67

Show how a full adder may be implemented by using two half adders.

(3)

Ans:

Fig 30 (c )
Q.68

Write short notes on

(i) Voltage Regulator
(ii) Multivibrator
(iii) Shift Register

(2x7)

Ans:
(i) Voltage Regulator:
Voltage regulation may be defined as the ability of the power supply or source to maintain a
constant output voltage in spite of a.c voltage fluctuations and changes in the load resistance.
Mathematically, it is given by the relation,
( (Vmax Vmin) /Vmax )x 100
Vmax = maximum d.c. output voltage.
Vmin = minimum d.c. output voltage.
In general, the voltage regulation may also be expressed as
((VNL VFL) /VFL) x 100
VFL = full load voltage of the supply.
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VNL = no load or open circuit voltage of the supply.
It is a known fact, that all the electronic devices and circuits require a constant d.c voltage for
their operation, and a fluctuating d.c voltage result in erratic operation of the electronic
devices. The d.c voltage can be supplied from dry cells or batteries. But these are expensive
compared to the conventional regulated d.c power supplies. The regulated d.c power supply is
made by converting the domestic a.c supply to d.c supply. The essential elements, which
constitute a regulated d.c power supply, are given below:
1)Rectifier ,
2)Filter, and
3)Voltage regulator.
The rectifier is the front or the first element of a regulated d.c power supply, the filter is the
second or the intermediate element and the voltage regulator is the last element.
Working: As an example let us consider a combination of full wave rectifier and a filter
circuit connected to an a.c. input voltage source. When the a.c input voltage, of the rectifier
input, changes above or below its normal value, it will cause a change in d.c voltage produced
at the filter output. A similar change in d.c voltage may also occur, when the load resistance
connected at the filter output changes above or below its normal value. It means that the d.c.
output voltage fluctuates whenever the a.c input voltage or the load resistance varies above or
below the normal values.
Although there are many types of voltage regulators, yet the following ones are some of the
important types of voltage regulators,
1. zener diode shunt regulator.
2. Transistor shunt regulator.
3. Transistor series regulator.
4. Controlled transistor series regulator.
5. Monolithic regulator.
(ii) Multivibrator: An electronic circuit that generates square wave is known as a
multivibrator. A multivibrator is a switching circuit which depends, for operation, on
positive feedback. It is basically a two stage amplifier with output of one given as the
input to the other as shown in Fig: 31(iii).
.

Fig: 31(iii)
The circuit operates in two stages controlled by the circuit conditions. Each amplifier stage
supplies feedback to the other in such a manner that will drive the transistor of one stage to
saturation and the other to cut off. After a certain time, controlled by circuit conditions, the
action is reversed i.e., saturation stage is driven to cut off and cut off stage is driven to
saturation. The output may be taken across any of the stages and may be rectangular or square
wave depending upon the circuit conditions.
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Types of multivibrators:
Multivibrators are classified into three categories.
a) Astable multivibrator or free running multivibrator
b) Monostable multivibrator or one-shot multivibrator
c) Bi-stable multivibrator or flip-flop multivibrator
a) Astable multivibrator or free running multivibrator alternates automatically between the
two states and remains in each state for a time dependent upon the circuit constants. Thus, it is
just an oscillator since it requires no external pulse for its operation. Because it continuously
produces the square-wave output, it is often referred to as a free running multivibrator.
b) Monostable multivibrator or one-shot multivibrator has one stable state and one quasistable state. The application of input pulse triggers the circuit into its quasi-stable state, in
which it remains for a period determined by circuit constants. After that period of time the
circuit returns to its initial state, the process is repeated upon application of each trigger pulse.
c) Bi-stable multivibrator or flip-flop multivibrator has two stable states. It requires the
application of an external triggering pulse to change the operation from one state to the other.
Thus one pulse is used to generate half-cycle of square wave and another pulse is to generate
the next half-cycle of square wave. It is also known as flip-flop multivibrator because of its
two possible states it can assume.
d) Shift registers: A register capable of shifting its stored bits laterally in one or both
directions is called a shift register. The logical configuration of a shift register consists of a
chain of flip flops in cascade with the out put of one flip flop connected to the input of the next
flip flop. All the flip flops receive a common clock pulse, which activates the shift from each
stage to the next.
The simplest possible one is that which uses only D flip flops as shown in figure 18.
The output of a given flip flop is connected to the D input of the flip flop at its right. Clock is
common to all flip flops. Serial input SI is the input to the leftmost flip flop during the shift.
The serial output SI is taken from the output of the right most flip flop.

Fig 18 A 4 bit shift register

Shift registers can be used for converting serial data to parallel data and vice versa. If we have
access to all the flip flop outputs of a shift register, then information entered serially by
shifting can be taken out in parallel from the outputs of the flip flops or vice versa.

Q.69 Discuss the basic concept behind the operation of a Wien-bridge oscillator with the help of
suitable circuitry and derive expression for relevant oscillation frequency.
(7)
Ans:
Wein-bridege oscillator is used in audio frequency range. It uses two transistors, each
producing a phase shift of 1800 and thus producing a total phase shift of 3600 or 00.
The Fig. 32a. shows the circuit diagram of an Wien-bridge oscillator. It is a two stage
amplifier with an RC bridge circuit. RC bridge circuit is a lead lag network. The phase shift
107

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across the network lags with increasing frequency and leads with decreasing frequency. By
adding a feedback network, the oscillator becomes sensitive to a signal of only one particular
frequency. This frequency is that at which Wien bridge is balanced and for which phase shift
is 00.

Fig. 32a.
The bridge is balanced only when
R4 (R2 / (1+jC2R2)) = R3 (R1 j / C1)
R2 R4 = R3 (1 + jC2R2) (R1 j / C1)
or
R2R4 R3R1 (C2 / C1) R2R3 + (jR3 / C1) j C2R2R1R3=0
Separating real and imaginary parts, we have
R2R4 R3R1 (C2 / C1) R2R3=0
or
(C2 / C1) = (R4/ R3) (R1 / R2)
and (R3 / C1) C2R2R1R3=0
2= (1 / C2C1R2R1) or =(1 / C2C1R2R1)
fo= 1/ (2 (R1R2C1C2))
If R1 = R2 = R and C1 = C2 = C then
fo = 1/(2 x R x C)
and
R4=2R3
Q.70 What are the main considerations which are to be kept in view while selecting an oscillator for
(7)
a particular application?
Ans:
The main considerations which are kept in view while selecting an oscillator for a particular
application are
1.Frequency range:
The oscillator selected for a particular application should be capable of supplying an output
signal whose upper and lower frequency limits exceeds those required by the application. The
frequency of operation of the oscillator has been selected, it should not drift from the related
frequency.
2.Accuracy and dial resolution:
The accuracy of an oscillator specifies how closely the output frequency corresponds to the
frequency indicated on the dial of the output frequency value the dial setting can be read.
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3.Amplitude and frequency stability:
The amplitude stability is a measure of an oscillators ability of maintaining a constant voltage
amplitude with variations in the output signal frequency. Frequency stability determines how
closely the oscillator maintains a constant frequency over a given time period.
4.Waveform distortion:
This quantity is the measure of how closely the output waveform of the oscillator resembles a
pure sinusoidal signal. The distortion should be kept minimum.
5.Output impedance:
This is the impedance value of load which must be connected to it for maximum power
transfer. The output impedance of the oscillator be equal to the characteristic impedance of the
system to which it is to be connected.

Q.71

In a circuit shown in figure below, calculate and sketch the waveforms of current i over one
period of input voltage. Assume the diodes to be ideal.
(14)

Ans:
Between the duration 0 and /2 both diodes are ON.
Between the duration /2 and diode D2 is ON.
Between the duration and 3 /2 both diodes are OFF.
Between the duration 3 /2 and 2 diode D1 is ON.
i = 1/2 (sin t + cos t)
for 0 t /2
i = 1/2 (sin t)
for /2 t
i=0
for t 3 /2
i = 1/2 (cos t)
for 3 /2 t 2

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BASIC ELECTRONICS
State the principle of operation of a bistable multivibrator with the help of a circuit diagram.
(7)
Ans:
Bistable multivibrator (BVM)
It has two absolutely stable states. It can stay in one of its two states indefinitely, and changes
to other state only when it receives a trigger pulse from outside.
Since one trigger pulse causes the multivibrator to flip from one state to another and the next
pulse causes it to flip back to its original state, the multivibrator is also known as flip-flop
circuit.

Fig.34a
Circuit operation:
In the circuit shown in Fig.34a, when Q1 is conducting, then the fact that point A is at nearly
0V makes the base of Q2 negative (by the potential divider R2-R4) and holds Q2 OFF.
Similarly, when Q2 is OFF, the potential divider from VCC to VBB (RL2, R1, and R3) is
designed to keep the base of Q1, at about 0.7V, ensuring that Q1 conducts. Now suppose a
positive pulse is applied to R, it will cause Q2 to conduct. As collector of Q2 falls to 0, it cuts
Q1 OFF and bistable multivibrator switches to its other state.
Q.73

What is flip-flop? Explain the principle of operation of S-R flip-flop with truth table.
(7)
Ans:
For a sequential system, we must know what has happened in the past. Therefore we must
have storage device to retain this information until we are ready to use it. The basic unit of this
storage is flip-flop. It is a device with two stages i.e., the output is either 0 (logic 0) or +5V
dc (logic 1).
A flip-flop maintains its output state until directed by an input signal to change its state. This
means that it can store 1-bit information.
S-R flip-flop:
It uses a pair of cross coupled transistors as shown in Fig. 36a. When, transistor T1 is in
saturation then its collector voltage is the base drive for transistor T2, i.e., no base drive for
T2. Hence T2 is cutoff and its collector voltage is approximately + VCC (logic 1). This drives
the base of T1 and thus T1 operates in saturation region.
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R
0
0
1
1

S
0
1
0
1

Q
No change
1
0
Invalid

Fig. 36a
In effect T2 is OFF and T1 is ON making Q=1(+VCC). Similarly if T2 is in saturation T1 is
OFF resulting Q=0. By introducing one input at the base of each transistor we can control the
state of operation of the transistor.

Q.74

Explain with a neat diagram the working of a BCD counter

(7)

Ans:
BCD decade counter goes through a straight binary sequence from 0000 to 1001 state. Then
recycles back to 0000 state. The circuit of a BCD counter is given in fig.
States of BCD decade counter:
FlipFlop-A toggles on each clock pulse so that logic equation for its J and K inputs is
JA = KA = 1

Fig. A BCD counter

This is implemented by connecting these inputs to a constant high level.
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FlipFlop-B changes state on next clock pulse each time QA = 1 and QD = 1 so that
__
JB = KB = QAQD.
__
This is implemented by ANDing QA and QD and connecting the gate output to JK inputs of
FlipFlop -B.
Clock
0
1
2
3
4
5
6
7
8
9

QA
0
0
0
0
0
0
0
0
1
1

QB
0
0
0
0
1
1
1
1
0
0

QC
0
0
1
1
0
0
1
1
0
0

QD
0
1
0
1
0
1
0
1
0
1

FlipFlop-C changes on next clock pulse each time both QA = 1 and QB = 1

JC = KC =QAQB
This is implemented by ANDing QA and QB and connecting gate output to JK inputs of
FlipFlop F-C.
FlipFlop -D changes on next clock pulse each time QA = 1 and QB = 1, QC = 1 or when
QA = 1 and QD =1
JD = KD =QAQBQC+QAQD

Q.75 Draw the block schematic of a typical operational amplifier and briefly explain the function of
each block. Also give the equivalent circuit of the opamp.
(9)
Ans:
The block diagram of a typical opamp

Equivalent circuit of the opamp

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The first stage is double-ended high-gain differential amplifier. In this stage high-gain is
desirable so that there would be a negligible effect on the output of any shortcoming in the
following stages. Also this stage determines the input resistance of the op-amp.
The second stage is usually another differential amplifier, which is driven by the output of
first stage. In most amplifiers the intermediate stage is dual input, unbalanced output
differential amplifier in order to increase the gain. In this amplifier output is measured at the
collector of only one of the two transistors with respect to ground. In the quiescent
condition some dc- voltage exists at the output terminal and there is no other collector
voltage at output to balance or nullify this output dc voltage.
The third stage, known as level shifting stage, is usually an Emitter-follower circuit in order
to shift dc-level at the output of the intermediate stage downward to zero volts with respect
to ground. Here error signals is developed in the intermediate stage due to direct coupling
and gets amplified in the succeeding stages. This increase in dc-level tends to shift the
operating point of the succeeding stages which also limits the output voltage swing or may
distort the output signal.
The final stage is usually a push-pull complementary amplifier. This stage increases the
output voltage swing and current supplying capability of the amplifier. A well designed
output stage also provides low output resistance.

Q.76 Draw the circuit of a monostable multivibrator using op-amp. Describe its operation and
derive an expression for its pulse period.
(10)
Ans:
Monostable multivibrator circuit using op-amp can be drawn as in the Fig. 38a(i). The circuit
remains in its stable state until a triggering signal causes a transition to the quasi stable state.

Fig. 38a(i)
At stable state Vo = + Vz and C is clamped at Vc = Vd = 0.7V.
By trigger of suitable duration and amplitude, output will switch to Vo = -VD. The capacitor
will charge through Rf towards +Vz as D1 becomes reverse biased.
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Fig. 38a(ii)
When Vc < - Vz, the comparator again swings back to +Vz and capacitor C will charge
towards +Vz until Vo = VD where C will be clamped again at VD

Derivation:
Charging from VD to Vz: Vc = -Vz + (VD + Vz) e-t/
Where = Rf C.
At t = T, Vc = -Vz. Hence Vz = -Vz + (VD + Vz) e-T/
Solving for T, we get T = RfC ln [(VD+Vz)/ (Vz- Vz)] = RfC ln [(1 + VD/ Vz)/ 1-]
Q.77

Show how the monostable multivibrator circuit you have drawn can be converted to astable
type by simple changes in the monostable circuit.
(4)

Ans:
Removing triggering circuit, D2 and D1 from the circuit shown in Q.76, we can convert
monostable multivibrator to astable multivibrator as shown in Fig. 38b.

Fig. 38b.

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Q.78 Sketch the circuit of a bridge rectifier and describe its operation. Derive expressions for
rectification efficiency and ripple factor of the circuit. If a capacitor is added to the circuit,
show the output voltage waveform of the rectifier.
(8)
Ans:
The bridge rectifier circuit is as shown in Fig. 39a(i).

Fig. 39a(i)

Operation: During positive half cycle of the input voltage point A becomes positive. Diodes
D1 and D2 will be forward biased and D3 and D4 reverse biased. D1 and D2 conduct in series
with the load and the current flows in the direction as shown in figure1 by solid arrows.
In the next half cycle, when the polarity of the ac voltage reverses, B becomes positive D3
and D4 are forward biased, while D1 and D2 are reverse biased. D3 and D4 conduct in series
with the load and the current flows as shown by dotted arrows.
During both the half cycles of input signal, the current through RL is in same direction and is
as shown in Fig. 39a(ii).

Fig. 39a(ii)
Expression for efficiency and ripple factor:
iL = Im sin t 0 t
iL = -Im sin t t 2

Idc = (1/) Im sin t d(t)

0

Idc = 2Im / and Edc = 2Em /

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In bridge rectifier, in each half cycle two diodes conduct simultaneously. Hence maximum
value of load current is
Im = Em / (Rs+2Rf+RL), where Rs = transformer secondary winding resistance.
PDC = IDC2RL = (2Im/) 2 RL
PAC = Irms2 (2Rf+Rs+RL) = (Im/2)2 (2Rf+Rs+RL)
[(4Im2/2) RL]
Therefore, rectification = PDC/PAC =
efficiency
Im2/2 (2Rf+Rs+RL)

8RL
(since 2Rf+Rs<< RL)
2

RL

= 8/2 = 81.05%
Ripple factor = (Irms/IDC) 2 1
= [(Im/2)/ (2Im/)] 2 1 = (2/8) 1 = 0.48.
The Fig. 39a(iii) shows how a capacitor filter is connected to the rectifier output and the
output voltage waveform of the rectifier across the load, with capacitor filter.

Fig. 39a(iii)

Fig. 39a(iv)
The dotted line in Fig. 39a(iv) shows the rectifier output without filter and solid line
shows the output across the capacitor filter.
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Q.79 Describe using a neat circuit diagram, the operation of a transistor series voltage regulator.
(6)
Ans:
Fig. 39b shows the circuit of a transistor series voltage regulator.

Fig. 39b
In the above circuit, transistor behaves as an emitter follower. i.e it behaves as a variable
resistor whose value is determined by the base current. The load voltage VL is equal to the
difference of zener voltage (Vz) and the base to emitter voltage VBE.
i.e VL = Vz VBE or VBE = Vz VL
Any increase in VL decreases VBE as Vz is fixed. Therefore the forward bias of the transistor is
reduced, which reduces the level of conductance. Due to this VCE of transistor increases which
in turn slightly decreases the input current to compensate for the increase in the value of load
resistance, so load voltage may remain at a constant value.

Q.80

Prepare the truth table for the output F of the logic circuit shown in figure below.
Write also the canonical SOP expression for F.

Ans:
The truth table for the above expression is as shown below.
A
0
0
0
0
1
1
1
1

B
0
0
1
1
0
0
1
1

C
0
1
0
1
0
1
0
1

AB
0
0
0
0
0
0
1
1

_
AC
0
1
0
1
0
0
0
0

_
AB+AC
0
1
0
1
0
0
1
1

117

BC
0
0
0
1
0
0
0
1

_
(AB+AC)BC
0
0
0
1
0
0
0
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BASIC ELECTRONICS
The canonical SOP expression for F is found from 1s in the 4th and 8th rows.
_
i.e. F (A,B,C) = ABC + ABC

Q.81 Write the logic diagram and truth table of clocked S-R flip flop and explain its operation. What
are the drawbacks of S-R flip flop?
(6)
Ans:
Fig. 41a(i) shows clocked RS flip flop. It consists of a basic NOR gate and two AND gates.
The outputs of the two AND gates remain at 0, regardless of the R and S inputs as long as
Cp=0.When the clock pulse goes to 1, information from the R and S inputs are allowed to
reach the basic flip flop.

Fig.41a(i)
Fig. 41a(ii) shows truth table for clocked RS flip flop. The waveforms in Fig. 41a(iii) illustrate
the operation of clocked RS flip flop.

Fig. 41a(ii)
Drawbacks of SR flip-flop:
i) A 11 input (R =S =1) is not allowed as it will make both Q and Q = 1 while the clock
pulse is 1. The state of output will be unpredictable when Cp goes to 0.
ii) While clock pulse is 1, change in inputs changes the output.
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Fig. 41a(iii)
Q.82

Construct a 4-bit binary ripple counter using suitable flip-flop and describe its working?
(6)
Ans:
Fig. 41b shows the circuits of a 4-bit ripple counter consisting of edge-triggered flip-flop (JK).

Fig. 41b
In this ripple or asynchronous counter, the clocking for all flip-flops except the one at the LSB
is obtained by the transition of the flip-flop at the previous stage. By keeping J=K= 1 all flip
flops are ready to change state at the arrival of clock pulse which is effective only when a
transition from 1 to 0 takes place. Flip-flops as shown are sensitive to negative edge of clock
signal. The output of one stage acts as a clock to the next stage. For each negative transition of
a clock, Q0 changes its state. Q1 changes its state for every 1 to 0 transition of Q0. Q2 changes
its state for every 1 to 0 transition of Q1. Similarly Q3 changes its state for every 1 to 0
transition of Q2. The truth table is as follows:
Clk
Q3
Q2
Q1
Q0
0

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Clk

Q3

Q2

Q1

Q0

10

11

12

13

14

15

Q.83 What is doping of a semiconductor? Explain how p- and n-type semiconductors are formed.
Also write their energy band diagrams, clearly showing the different energy levels.
(8)
Ans: pp 102 - 104
Q.84 What is Early effect? Explain how it affects the characteristics of BJT in CB configuration.
(8)
Ans: p. 238 - 39
Q.85 Draw a neat circuit of a differential amplifier and explain its operation.

(8)

Ans: p. 450 52
Q.86

Explain the effect of temperature on a JFET.

(8)

Ans: p. 276.
Q.87

Describe how oscillations are developed in a tank circuit.

Ans: p. 655
Q.88

Define the following terms as applied to characterisation of opamps.

(i) CMRR
(ii) slew rate

Ans: p. 800, p. 826

Q.89

Draw a neat diagram to show the functional blocks of a complete regulated power supply.
Explain the role of each block.
(9)

Ans: p. 908 09.

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BASIC ELECTRONICS

Draw the circuit of 4-bit ring counter using suitable flip-flop. Explain its operation using
timing diagrams and truth table.
(8)

Ans: p. 1021
Q.91

Show how a T-flop-flop can be constructed using J-K flip-flop. Write the truth table of T flipflop.
(2)

Ans: p. 1016
Q.92

Distinguish between avalanche and zener breakdown in p-n junction diode.

(7)

Ans:
Both avalanche breakdown and zener breakdown occur under reverse biased condition of
p-n junction and the common cause is the electric field accelerating a carrier which collides
with an ion and breaks the covalent bond releasing one or more extra carriers. In the case of
avalanche breakdown, the carriers are thermally generated ones accelerating under
externally applied large electric field in reverse bias and the process is cumulative giving
rise to more and more pairs of carriers by multiple collision of ions. The result is
destructive.
On the other hand, in a zener diode, the breaking of ionic bond and generation of extra
carriers is by the intense electric field across a very narrow depletion region at the junction,
due mainly to rather heavy doping of both p and n regions of the diode. The resulting
process gives rise to large reverse current and is reversible. This phenomenon is called
Zener breakdown.
Q.93 Draw the circuit of Darlington amplifier and analyse it to obtain expressions for its current
(10)
gain and input impedance. Also mention its merits and application.
Ans: The circuit for Darlington amplifier is shown below

The equivalent circuit for small signal is as shown below

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Considering Q 2 , Zin 2 = hfe 2 R E

(1)
Current Gain: A i 2 = I0e2 / I 2 = I e 2 / I b 2 ~ hfe 2 ..(2)
For transistor Q1, 1/hoel is comparable with becomes the load impedance for Q1.
Hence without neglecting 1/hoel,
the current gain for Q1 is
h fe1
h fe1
I
A i1 = 2 =
=
(3)
I1 1 + h Oe1Zin 2 1 + h Oe1 (h fe 2 R E )
If h fe1 = h fe 2 and h oe1 = h oe 2 = h oe , equation (3) can be written as
h fe
Ai1 =
and Ai2 = h fe
1 + hoe (h fe RE )
The overall gain of the amplifier is A i = A i1Ai 2

h fe 2
i.e., A i =
1 + h oe h fe R E
For h oe h fe R E 0.1 , a good approximation would be ignored w.r.t Zin2,
Input impedance

1
1
= h fe1 h fe 2 R E ||

Zin1 = h fe1 Zin 2 ||

h oe1
h oe1

h fe1h fe 2 R E
=
h Oe1h fe 2 R E + 1
If h fe1 = h fe 2 = h fe and h oe1 = h oe 2 = h oe then

.(4)
..(5)

h fe 2 R E
Zin1 =
h Oe h fe R E
if h oe h fe R E 0.1 , then Zin1 h fe 2 R E = 2 R E
The advantage of darlington amplifier is its very high current gain and very high Zin. It is used
to isolate high impedance source from low impedance load.

Q.94 Draw the circuit of common source amplifier using JFET and show its equivalent circuit.
Analyse the equivalent circuit to find an expression for voltage gain and output resistance.
(6)
Ans:
The circuit of n-channel, JFET common source amplifier is shown below in fig(1) and its ac
equivalent circuit is shown in fig(2).

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Fig(2) shows current source equivalent circuit where gm Vi represents controlled source
and rd represents the incremental drain resistance. The output impedance Zout of the
amplifier is given by the parallel combination of rd RD
R D rd
i.e. ZO = R D || rd =
R D + rd
The voltage gain is found as follows:
Vo = g m Vi (rd || R D || R L )
V
The voltage gain, A v = o = g m (rd || R D || R L )
Vi
Z R
Or A v = g m o L .
Zo + R L

Q.95 For an amplifier having open loop gain A, find an expression for gain with negative feedback
of feedback ratio . Show how stabilization of gain of an amplifier is achieved with negative
feedback.
(6)
Ans:
An amplifier block without any feedback is shown in fig(1). If to this amplifier
negative(voltage) feedback is provided, the situation is shown in fig(2).

Fig(1)
Fig(2)
In the basic amplifier, the gain is A i.e. A = Vo / V i which is now called the open loop gain.
In fig(2), it is shown that a fraction of the output voltage (i.e. Vo ) is added negatively (i.e.
123

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BASIC ELECTRONICS
negative feedback) to the signal input Vi so that the actual input to the basic amplifier is
Vi Vf = Vi Vo . Thus by the basic amplifier characteristic
A(Vi Vo ) = Vo ,i.e.
i.e. AVi = Vo (1+A) or
where Af is the gain with negative feedback
Basic amplifier gain
i.e. A f =
1 + (Basic amplifier gain )
Gain stability with negative feedback consider the expression for Af
A
i.e. A f =
(1)
1 + A
Differentiating this expression w.r.t. A
dA f (1 + A) A
1
=
=
dA
(1 + A) 2
(1 + A) 2
dA
dA f =
Now divide this expression by (1)
(1 + A) 2
A
Then A f =
1 + A
This shows that though the per unit change in the gain of the basic amplifier is

dA
, the
A

1
times the same.
1 + A
Generally (1 + A) >> 1 Hence considerable improvement in gain stability is effected by
negative feedback.
change in the gain of the overall amplifier with negative feedback is

Q.96 Show an FET source follower circuit. What type of negative feedback takes place in the
circuit? Analyse the circuit to derive an expression for voltage gain with feedback.
(6)
Ans:
An FET source follower circuit is shown below. Its equivalent circuit for analysis is also
shown.

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The sampled signal is the voltage across R which is fully fed back. Hence this is a case of
voltage series feedback.
To identify the basic amplifier without feedback, let Vo = 0. Then Vi appears across G and
S. The output circuit is found by setting Ii = 0. Then R is present only in the output circuit.
Thus the basic amplifier is shown in fig (2).
The equivalent circuit, by replacing the FET by its low frequency model, is shown in fig(3).
V
It is seen that Vf and Vo are equal. Hence = f = 1
Vo
The gain of the basic amplifier is (as Vi = VGS )

Vo
g m rd Vi
R
=
=
.(1)
Vi (rd + R )Vi rd + R
where = g m rd
using the general relation in a ve f.b. amplifier
A
i.e. A f =
the gain with f.b. in the source follower is
1 + A
Af =

i.e. A f =
rd + (1+ ) R

.(2) the expression for gain of the source follower.

Q.97 Explain the principle underlying the working of R-C oscillators. Mention the applications of
R-C oscillators.
(7)
Ans:
The general requirement for producing oscillations in an amplifier is to provide positive
feedback so that feedback voltage is in phase with the input to the amplifier. This means
there should be 2 shift in phase from input through the output and back at input. As an
inverting amplifier provides (1800) phase shift, it can be used along with a phase shifting
network that provides further (1800) shift at the desired frequencies as shown in the block
schematic below.
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Typically, for phase shift, RC networks may be used as shown in figure. The Rs and Cs
must be so chosen as to produce 1800 shift at the frequency of oscillation required.
It is also necessary that the output impedance of the phase shift network must be much
smaller than the input impedance of the amplifier. All these, essentially mean that
Barkhausen criterion of unity loop gain i.e. A = 1, is network, which also means that
there should be positive feedback to the basic amplifier.
Application: RC oscillators are commonly used as audio oscillators.

Q.98 Draw the circuit of sample and hold using op-amp and explain its operation.

(9)

Ans:
A sample and hold circuit is essentially a switch in series with a capacitor, as in fig(1)

fig(1)

S/H Control voltage

Fig(2)

The voltage across the capacitor C tracks the input signal Vi during the time TON, when a
logic control closes the switch S. The capacitor holds the instantaneous value developed on
C at the end of Ton, when the control opens S. The switch may be a relay, a diode bridge
gate, a BJT or a MOSFET controlled by a gating signal.
A S/H circuit using op amp and an n-channel enhancement MOSFET is shown in fig(2).
The analog signal Vi to be sampled is to be applied at the drain terminal of the E-MOSFET
and a pulse train is applied at the gate, the MOSFET connects the drain to the source so that
Vin is applied across the capacitor during the time the pulse is present. The action of the
switch and the capacitor are illustrated in the timing diagram in fig(3).

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fig(3)
During the time the MOSFET is ON, the Vi appears across the capacitor and so at the
output of the non-inverting amplifier as Vo. When MOSFET is off during TOFF, the input is
isolated from C and thee op-amp circuit. During this time, the voltage on C will be held
constant at a value of Vi, which prevailed at the end of TON. The TON is often called the
sample period and the TOFF the hold period. To obtain an output that closely
approximates the input, the frequency of the control voltage at the gate should be as large as
possible. To retain the sampled voltage without loss, the capacitor should be of very good
quality with the least charge leakage.

Q.99 Write a neat circuit diagram of saw-tooth wave generator using op-amps and describe its
operation. Derive an expression for the frequency of the wave.
(10)
Ans:
The circuit of triangular wave generator using two op amps is shown in the figure below

R4

The operation of the circuit is explained with reference to the wave diagram shown below.

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The Zener diodes will clamp the voltage Vi at either + Vz or Vz depending on the polarity
of the saturation voltage at the output of the comparator.
To begin with say V1 = + Vz at t = to
The integrator causes charging of capacitor C and Vo(t) will be a ramp with negative slope.
V
The current into C is I = z and Vo(t) is given by
R3
1 t
1
V (t ) = V (t ) I dt = V (t ) (t t )
(1)
o
o o C
o o C
o
t
o
Now the voltage Vz(t) is found by using superposition
R V (t )
R 4 Vz
Vz ( t ) =
+ 1 o
R1 + R 4 R1 + R 4
When Vz(t) reaches zero at t = t1, the comparator output changes to V1 = -Vz. Using
equation(2) to find Vo(t1),
R V (t)
R 4 Vz
Vz (t1 ) = 0 =
+ 1 0
R 1 + R 4 R1 + R 4
R
.(3)
i.e. Vz (t1 ) = - 4 Vz
R1
The direction of current into the integrator will reverse from t1 until t2 and is given by
Vz
I=
= I
R3
During t2 > t > t1 the Vo(t) will be a positive going ramp. At t2 the output is
R
Vo (t 2 ) = 4 Vz
..(4)
R1
as this value is limited by +Vz
At t2, the comparator switches its output again and the cycle repeats.
Derivation of expression for the frequency:
As seen by the analysis above and as shown in the wave diagram,
R
V(t o ) = Vo (t 2 ) = 4 Vz
R1
R
and at t = t 0 + t1 , V0 (t 0 + t1 ) = 4 Vz as at equation (3)
R1
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Now using equation(1), V0 (t 0 + t 1 ) - V0 ( t 0 ) =
Hence

I
t1
C

by equation I =

Vz
R3

Assuming matched zener diodes i.e. Vz1 = Vz 2 = Vz

We get equal magnitudes of +ve and ve ramps
4R 4 R 3C
Hence the period T = 2t1 =
R1
The frequency of triangular waveform is therefore, f =

R1
4R 4 R 3C

Q.100 Explain how an astable multivibrator can be implemented using 555 timer IC.

(6)

Ans:
The connections to be made to the 555 timer IC chip and the relevant internal details are
shown in the figure(1) below.

fig(1)

fig(2)
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At the non-inverting inputs of comparators, the potential division of Vcc across the Rs
causes V1 = 2 3 Vcc and V2 = 13 Vcc . The Vcc also charges C through RA and RB.
Assume that at t = 0, Vc = V2, which causes comp 1 output to be high and Q output of the
latch is in reset condition, which in turn makes V0 ~ 0 volts, as shown in fig 2. At the same
time, as Q = 1 , the transistor Q1 is on causing gradual discharge of C through RB. At t =
T1, let the value of Vc which is also threshold voltage of the timer, be V1. This will cause
the output of comparator 2 to be high and thus setting the latch. The transistor Q1 is now cut
off Q = 0 . This leads to charging of C again and gradual rise in V0 as shown in figure 2. At
t = T2 , Vc = V2 again which causes repetition of cycle of events described above. The
duration of T1 and T2 are given by T1 = R BCIn 2 and T2 T1 = (R A + R B )In 2 .
1
.
The frequency of oscillation is f =
T2

Q.101 Why filters are used along with rectifiers in the construction of a power supply? List the filter
(10)
types used in power supplies. Explain their effect on rectifier output waveforms.
Ans:
Necessity of filters for rectifiers:
The output from any basic rectifiers is not a pure d.c. There would be considerable a.c.
component in their output, called ripple, in addition to the desired d.c. component. Most
sophisticated electronic systems need pure d.c. supply to drive, or power them. To construct
a good power supply which gives pure d.c. output, we need to remove or filter out the a.c.
component from the output of rectifiers. The output from basic rectifiers which contain a.c.
component or ripple, is fed to filter circuits so that the output from the filter is pure d.c.
This situation is illustrated in the figure below.

fig(1)
Following are the commonly used filter types are:
(i) Capacitor filter (ii) Series inductor filter (iii) Choke input filter (iv) -filter (v) RC filter.
Their effect on rectifier output waveforms are explained below.
(i) Capacitor filter:
It is connected in shunt or parallel with the load as shown in the fig (1)

fig(2)

fig(3)
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This is the simplest and the least expensive filter. A large value capacitor offers high
impedance to d.c. Fig(3) shows how the capacitor helps in maintaining the load voltage as
constant as possible. In the case of a full-wave rectifier without filter, the load voltage
would also be the rectified waveform shown by the dotted line. But with C filter, the
voltage across the load has much less ripple as shown by the full line trace.
(ii) Series Inductor filter:
Property of an inductor is to oppose any change in the current through it. An inductor can
be connected to act as a filter between the load and a basic rectifier as shown in fig(4).

fig(4)

fig(5)

The inductor or choke stores energy in its magnetic field when the current is above an
average value. The stored energy is released when the load current falls below the average
value. The effect of the inductor filter is illustrated in fig 5 above.
(iii) Choke Input filter (LSection filter):
As explained above in connection with inductor filter and capacitor filter, while capacitor
acts to keep the voltage across itself constant and inductor acts to keep the current through
it constant, the advantages of the properties of both an inductor and a capacitor are
combined into an L-Section filter shown in fig 6.

fig(6)

fig(7)

The effect of the L-Section filter is illustrated in fig 7. This provides d.c. output more ripple
free than either C-filter alone or choke filter alone.
(iv) -filter: The circuit of -filter is shown in fig 8.

fig(8)

fig(9)

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Because of the additional capacitor at the input of the filter, the d.c. output is of a higher
value and more ripple-free than is possible by any of the filters discussed earlier. The effect
of the filter on a full-wave rectifier output is illustrated in fig 9.
(v) RC-Filter: The RC filter circuit is shown in fig 10.

fig(10)

fig(11)

The disadvantages of the -filter are its bulk, weight and higher cost. In place of L, if
resistor R is used, the effect is almost similar to that obtained from -filter. However, the R
being dissipative of energy, the overall efficiency of the power supply will be less than
possible with -section filter. Also the ripple factor in this case would be poorer than in a
-section filter where an inductor is used.

Q.102

Delineate the concept of duality in Boolean algebra.

(3)

Ans:
It is the property of Boolean algebra that for a given Boolean expression there always exists
a dual. Stated succinctly
Functions
Expressions

Two Boolean
will be called duals if they differ only by the simultaneous
tables

maps

interchange of AND for OR and 0 for 1

All postulates, theorems and axioms of Boolean algebra are to be stated in pairs, one
statement being the dual of the other statement.
e.g.: The expression x + xy = x which is law of absorption has a dual x(x + y) = x.
Dual logic tables:
Table for OR

Table for AND

If the I are replaced by 0

we get the table for AND as
shown on right side
Dual K maps

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Dual K maps
Consider a function f = AC + BC + BD. The K-map for this function is

fig (1)

fig (2)

If a dual map is drawn by replacing 1 by 0 and 0 by 1 as shown in, and if we simplify

the function represented by the map, we get the expression
f d = (A + C)( B + C)(B + D)
= CD + CB + ABD
which is the dual function f = AC + BC + BD

Q.103 For the function, F(A,B,C) = (1,5,7), write the canonical POS and SOP expressions.

(2)

Ans:
Canonical SOP form is directly obtained for
F ( A, B, C ) = (1,5,7) as ( M 1 + M 5 + M 7 )
i.e. F(A, B, C) = A BC + ABC + ABC --------- canonical SOP expression.
POS expression is obtained as product of maxterms
i.e. F(A,B,C) = (0,2,3,4,6)
i.e. F(A, B, C) = (A + B + C)(A + B + C)(A + B + C )( A + B + C)( A + B + C)
which is canonical POS expression.

Q.104 Write the logic diagram of a clocked R-S flip-flop using only NAND gates. Explain its
operation with reference to truth table.
(6)
Ans:
The logic diagram of a clocked S-R flip-flop based on NAND gates only is shown in the
figure below

Clocked S-R flip-flop

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The gates 1 and 2 form the latch and the fates 3 and 4 are control or steering fates. When
the clock is low of CK = 0, the outputs of both the gates are 1 irrespective of the values of
S and R. The outputs Q and Q remain as they were, i.e. the flip-flop does not change state
during CK = 0. Now let the CK = 1. We examine the operation for the four different
combinations of S and R. For S = 0, R = 0, the outputs of 3 and 4 are 1. If Q were to be 0
(and Q = 1) there will not be change in the value of Q or the state of the flip-flop. This is
indicated in the truth-table, at the first row.
For S = 1, R = 1, the inputs to 1 and 2 will be A1 = B1 =0, and A2 = B2 = 1. For these inputs
the Q is 1. That is, even if Q were to be 0 before clock is active, it will be forced to be 1.
This action is called setting the flip-flop and is indicated at the second row of the truthtable.
Next for S = 0, R = 1, the condition is seen to be the opposite of the one that prevailed when
S = 1; R = 0.
Thus Q will be forced to be at logical zero and Q = 1. This is indicated at the third row of
the truth-table.
For S = 1, R = 1, the outputs from both 3 and 4 are zero and therefore the outputs of the
both the gates 1 and 2 are 1. This condition is logically inconsistent. Hence the state of the
flip-flop is unidentified or indeterminate. Therefore, S = R = 1 input combination is
forbidden, which is indicated in the fourth row of the truth-table.

Q.105 Write the truth table for full adder and show its implementation using gates.

(5)

Ans:
The requirement of a full adder is indicated in the block shown below.
Truth-table

A full adder is required to perform addition of added and augend bits at the same digit
position of two binary numbers, taking into account any carry resulting from the lower digit
position. Thus considering all the possible combinations for the augend( A n ), addend ( Bn )
and carry( C n 1 ) inputs, the truth-table is drawn to obtain the required sum and carry
outputs, as shown above.
From the truth-table, the Boolean expressions for Sn and Cn are given by
Sn = AnBnCn-1 + AnBnCn+1+ AnBnCn-1 + AnBnCn-1
This cannot be simplified any further.
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For finding simplified expression for Cn, a k-map is drawn as below

k-map for Cn
from the map
Cn = AnBn + AnCn-1 + BnCn-1
The implementations of Sn and Cn are shown by the AND OR logic below

Q.106

In an astable multivibrator, the base registers are of 12.5 K ohm and the capacitors are of
0.01 ohm. Determine the PRR (pulse repetition rate).

Ans: 5772 pulses per second.

Q.107

A single-phase full-wave rectifier uses two diodes, the internal resistance of each being
20. The transformer rms secondary voltage from centre tap to each end of secondary is
50V and load resistance is 980. Find
(8)
(i) the mean load current.
(ii) rms load current and output efficiency.

Ans: (i) 45 mA
Q.108

(ii) 50 mA

(iii) 79.58 %

Simplify the following expression using Boolean algebra technique

Z = AB + A(B + C) + B(B + C)
(8)

Ans: B + AC
Z = AB + A(B + C) + B(B + C)
= AB + AB + AC + BB + BC
= AB + AC + B(1+C)
( A + A = A and B + B = B )
= AB + AC + B(1+C)
= AB + AC + B
( 1+A = 1 AND B +1 = B)
= B + AB + AC
= B(1+A) + AC
( 1 + A = 1 and B + 1 = B)
= B + AC

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