Chess Panel Project
Chess Panel Project
Chess Panel Project
Presented to.
Chess panel
Project Overview ::
Chess Game is one of the most intelligent games over the world , we
decide to develop this game using Altera DE0 kit and VHDL
programming language ..
Basic operation ; depending on the motion in two axes X and Y , using
2D array with 2 stepper motors ,, and by detecting piece before moving
it using a magnetic field between chess piece and a permanent magnet
,, and Displaying operation on 7-segment display with inputs of Places
of chess piece wanted to move and the place wanted to move to ..
there is a LED of error detection upon the fault movement of chess
piece ..
Our project consists of two main parts (( Mechanical and Electrical
Parts ))
Due to the Electrical Part as a software and hardware ::
We Use VHDL applicable on Cyclon III FPGA Altera ..
it consists of main blocks :1- Input & Display .
2- FSM .
3- Motors ( Stepper & Servo ) .
Its Component :The input of chess panel consists of three push buttons ,, up , down &
set taken from the kit ( note : they are active low ) . which represent the
input block ,, its component are :1- Two DemuX.
2- Counter mod 5 .
3- Four counter mod 8 .
1- DeMuX :The First DeMux use up switch as input ,, two selector from counter 5
mod. & four output which control the horizontal motion ( X-axis ) .
The second DeMux use down switch as input ,, two selector from
counter 5 mod. & four output which control the vertical motion ( Y-axis )
2- Counter 5 mod :The input is "set" push button ,, its output is from 000 to 100 and it is
used as the selector of the two DeMux .
:= "000";
END if ;
s_m <= cnt ;
END process ;
END behaviour ;
3- counter 8 mod :The input is depend on the first demultiplexer when we press the push
button up or depend on the second demultiplexer when we press the
switch down .
Its output when we press up is from 000 to 111 & Its output when we
press down is from 111 to 000 ,, it goes to the seven segment & the
detection block . when it appear on the seven segment it will be as from
A to H on the horizontal axis (X-axis) or appear as from 1 to 8 on the
vertical axis (Y-axis) .
The Technique :The technique which happen when the player want to play is :- initially the counter 5 mod is at state 000 , so the first counter 8 mod
will be operated , its input are ( sso1 and sso5 ) depend on up or down .
- when the player finish putting the input of place on the X-axis ,, he
must press the set switch so it will count and it will be at state 001 .
- so the second counter 8 mod will operate ,, its input are ( sso2 and
sso6) depend on up or down .
- after inputting the second value and pressing set switch so we have
entered the place of chess piece which the player want to move .
- by repeating the previous steps we can obtain the destination the
player want , so after entering the place and destination the first turn
will be finished and the another player will do the same previous steps .
Seven-Segment Display
Role description:
- The two 7-segments display are used to show each play of the two
players.
- They receive the place where the player want to move its piece, then
decode the binary numbers inputs into letters and decimal numbers,
and display the new place.
- The horizontal squares are numbered from 1 to 8
- The eight vertical squares are from A to H.
- So the code of the input with the display after connection between
them is :-
library IEEE ;
use IEEE.std_logic_1164.all ;
entity top_level1 is
port (
clkt : std_logic ;
upt,downt,sett : IN std_logic ;
a1,b1,c1,d1,e1,f1,g1 ,a2,b2,c2,d2,e2,f2,g2 ,
a3,b3,c3,d3,e3,f3,g3 ,a4,b4,c4,d4,e4,f4,g4
std_logic );
end top_level1 ;
:OUT
component seven_segment_horz is
port( no_input
: in std_logic_vector(2 downto 0);
a,b,c,d,e,f,g : out std_logic
);
end component;
BEGIN
selector : cnt_st5 port map (sett ,s_mo);
dem1 : DeMux4 port map (s_mo ,upt, sso1,sso2,sso3,sso4) ;
dem2 : DeMux4 port map (s_mo ,downt, sso5,sso6,sso7,sso8)
;
count1 : mod_8 port map ( clkt,sso1,sso5,Qy1);
count2 : mod_8 port map ( clkt,sso2,sso6,Qx1);
count3 : mod_8 port map ( clkt,sso3,sso7,Qy2);
count4 : mod_8 port map ( clkt,sso4,sso8,Qx2);
sv_sgv1 : seven_segment_vert port map ( Qy1
,a1,b1,c1,d1,e1,f1,g1);
sv_sgvh1 : seven_segment_horz port map ( Qx1
,a2,b2,c2,d2,e2,f2,g2);
sv_sgv2 : seven_segment_vert port map (
Qy2,a3,b3,c3,d3,e3,f3,g3);
sv_sgh2 : seven_segment_horz port map ( Qx2
,a4,b4,c4,d4,e4,f4,g4);
end ckt ;
1-initial state :- in this state we initialize the place that we start from as
the motor is at the 000 on x-axis & 000 on y-axis ( the old_X & old_y
values ) . after the player enter the place of the piece that he/she want
to move so he/she will have pressed two set counts ,, so to move from
this state to the next state (Rcvp) set_count must equal 010 .
2- Rcvp :- in this state new_x & new_y will save the values the player
have entered .. after saving these values so we could move to the next
state ( cx1) .
3- c1x :- in this state the motor move a constant motion in order to
move from the place which the motor stopped in ,, to go to the place of
the chess piece which he want to go ,, the motor x move the distance of
half square (n) in which n=3.2 cm ,, in this state motor y must equal 0 .
then to move to the next state ( c1y ) the done of motor x must equal 1
as this means that the motor have finished its motion .
4- c1y :- in this state the motor move a constant motion in order to
continue moving from the place which the motor stopped in ,, to go to
the place of the chess piece which he want to go ,, the motor y move
the distance of half square (n) in which n=3.2 cm ,, in this state motor x
must equal 0 . then to move to the next state ( mvx ) the done of motor
y must equal 1 as this means that the motor have finished its motion .
5- mvx :- in this state the motor will move the number of steps which
are the difference between new_x and old _x ,, this operation will be
end fsm ;
architecture mealy of fsm is
component clk_fsm IS
PORT (clk
:IN std_LOGIC;
lowspeedclock
:OUT std_LOGIC);
END component;
component subt IS
port ( P1,P2 : IN std_logic_vector (2 downto 0);
-- clk : IN std_LOGIC ;
Qout : OUT std_logic_vector(2 downto 0) ;
Dirc : OUT std_LOGIC );
End component ;
signal clk_sig : std_LOGIC ;
signal DirX,DirY : std_logic ;
signal n_stpx,n_stpy : std_logic_vector(2 downto 0) ; ---- modification try (stable)
--signal nu_stpx,nu_stpy : unsigned(2 downto 0) ;
signal old1,old2: std_logic_vector (2 downto 0):="000" ;
signal NEW1 ,NEW2 : std_logic_vector (2 downto 0);
signal stp_xx,stp_yy : Integer range 0 to 7 ; --- modified try
type state_type is
(INIT , RCVP,RCVD , C1X ,C1Y , MVX ,MVY ,C2X,C2Y , RGST );
signal current_state : state_type := INIT ;
signal next_state : state_type ;
begin
stp_xx<= to_integer(unsigned(n_stpx)); --- modification try conversion
stp_yy<= to_integer(unsigned(n_stpy)); ---mod........
--nu_stpx<= unsigned(n_stpx);
--stp_xx<= to_integer (nu_stpx);
--nu_stpy<= unsigned(n_stpy);
--stp_yy<= to_integer (nu_stpy);
subx : subt port map (NEW1,old1,n_stpx,DirX);
suby : subt port map (NEW2,old2,n_stpy,DirY);
dly : clk_fsm port map (clk,clk_sig) ;
st : process (current_state, next_state ,set_count , New1, New2 , donex,
doney )
begin
case current_state is
when INIT =>
enx<='0' ; eny <= '0' ;
if set_count = "010" then next_state <= RCVP ;
else
next_state <= INIT ;
end if ;
when RCVP =>
enx<='0' ; eny <= '0' ;
New1<= Q0 ;
New2<= Q1 ;
-- srvv <= '0' ;
if (NEW1 = Q0 and NEW2 = Q1 ) then
next_state <= C1X ;
else
next_state <= RCVP ;
end if ;
when C1X =>
dircx<='1' ;
enx<='1' ; eny <= '0' ;
x_stps<= k ;
IF Donex='1' then
next_state <= C1y ;
else next_state <= C1x;
end if ;
when C1y =>
dircy<='1' ;
eny<='1' ; enx<='0' ;
y_stps <= k ;
if doney='1' then
next_state <= Mvx ;
else next_state <= C1y ;
end if ;
when Mvx =>
dircx <= DirX ; -- out <= signal
x_stps<=stp_xx*2* k ; --modified
enx<='1' ;
eny<='0' ;
if donex = '1' then
next_state <= Mvy;
else next_state <= Mvx ;
end if ;
when Mvy =>
dircy<= DirY ;
y_stps<=stp_yy*2*k ;
eny<='1' ;
enx<='0' ;
if doney = '1' then
next_state <= C2x ;
else next_state <= Mvy;
end if ;
when C2x =>
dircx<='0' ;
enx<= '1' ;
x_stps<= k ; --- modified
eny<='0' ;
if donex = '1' then
next_state <= C2y ;
else next_state <= C2x;
end if ;
when C2y =>
dircy<='0' ;
eny<='1' ;
y_stps<= k ; --- modified
enx<='0' ;
if doney ='1' then
next_state <= RgsT ;
else next_state <= C2y ;
end if ;
when RgsT =>
old1<= new1;
old2<=new2;
if set_count = "100" then
next_state <= RcvD ;
elsif set_count = "010" then
next_state <= RcvP ;
elsif
New1 /= Old1 and New2 /= Old2 then
next_state <= RgsT;
end if ;
when RCVD =>
New1<=Q2;
New2<=Q3;
-- srvv <= '1' ;
if (new1=Q1 and new2=Q2) then
next_state <= C1x ;
else next_state <= RCVD;
end if ;
end case ;
end process ;
output : process (clk_sig)
Begin
if (clk_sig='1' and clk_sig'event) then
current_state <= next_state ;
end if ;
end process ;
END mealy;
In this code ,, "ck" is the clock input of the counter , " maincount " is
a signal of type integer that represents the output of the counter and
the input for the decoder , "qm" represents the out of the counter
and the states that moves the coil by using "direction" input to the
counter we can control the stepper to move forward or backward for
the stepper in y-axis , right or left for the x-axis stepper ,, the
following diagram shows the codes blocks ,,
but how to make the motor rotates only number of times that is
required to move the piece to a determined state ? how to recieve
the input from the player that determine the place of the pieces and
their destination and translate it into a desired number of states
that's only cause the motor to go to the right place each time ?
Main Code of Stepper control :we shall use the block shown to illustrate how the work of the stepper
is controlled ,,
--component trafficclock IS
--PORT (clk
:IN std_logic ;
--lowspeedclock
:OUT std_logic ) ;
---END component ;
begin
---pp: trafficclock port map (clck,cckk) ;
process (clck , count,Enab)
Begin
If (Enab='1') then
if (clck'Event and clck='1' and Flag ='1') then
qstate <= count-1 ;
Flag
<= '0' ;
mclk
<= '1' ;
end if
;
if ( (clck'Event and clck='1') and (Flag ='0' and
qstate /= 0)) then
qstate <= qstate 1
END if ;
if ( (clck'Event and clck='1') and (Flag ='0' and
qstate = 0)) then
mclk
<= '0'
;
END if ;
mainclock <= mclk and clck
ENd if
;
END process ;
END ckt ;
thus we now have an clock that has number of pulses equal to numer of
desired states by applying this clock to the counter in the first component
shown above we thus have the desired rotations of the motor in the
required direction ..
ENTITY steper_control IS
PORT ( clok:IN std_LOGIC;
En : in std_LOGIC;
do : out std_LOGIC;
dir :in std_LOGIC;
counter : in integer range 0 to 15;
qout :OUT std_logic_vector (3 DOWNTO 0
(
;
END steper_control;
ARCHITECTURE vhdl OF steper_control IS
component pwm is
port ( Enab : in std_LOGIC;
clck : in STD_LOGIC;
count : in integer range 0 to 15;
mainclock : out STD_LOGIC;
done : out std_LOGIC;)
END component;
component steep IS
PORT ( ck :IN std_logic;
Enable : in std_logic;
qm :OUT std_logic_vector (3 DOWNTO 0);
direction :in std_logic ;)
END component;
SIGNAL mainclck:
std_LOGIC ;
BEGIN
Stepper External Circuit :The output current of DE0 board is too small to operate the stepper motor
,, and in case of connecting the DE0 board directly to the stepper , there is
a possibility of damaging the board due to too much high current ,, so the
circuit below is used to raise the output current and protecting the DE0
board ..
The operation of the circuit is that when the FPGA signal is high no current
passes through the optocoupler and to the base of Q1 so Q1 is off and no
signal is applied to the motor ,, In case of low FPGA signal , current passes
through the optocoupler to the transistor Q1 so Q1 is on and Q1 collector
current operates the stepper ,, the insulation of DE0 board from the stepper
and external circuit is achieved by using the optocoupler and thus we reached
our goal.