CHAPTER-1

INTRODUCTION

1.1 Introduction

Section below focuses on what is expected to be done during the

project period. It will also outline the general background, activities done
and project goals. Furthermore, in order to give a more deeply concern, it
will list out the key reasons for launch and what are the primary
concerns that cause this project compulsory to be launched.

1.2

Project Background

Introduction of title with reference to electrical industry:

The Inverter is an electrical device which converts direct current (DC) to
alternate current (AC). The inverter is used for emergency backup power
for various applications
Now a days many industrial applications have begun to require high
power. Some appliances in the industries however require medium or low
power for their operation. Using a high power source for all industrial
loads may prove beneficial to some motors requiring high power, while it
may damage the other loads. Some medium voltage motor drives and
utility applications require medium voltage. The multi level inverter has
been introduced since 1975 as alternative in high power and medium
voltage situations. The Multi level inverter is like an inverter and it is used
for industrial applications as alternative in high power and medium
voltage situations.
The need of multilevel converter is to give a high output power from
medium voltage source. Sources like batteries, super capacitors, solar
panel are medium voltage sources. The multi level inverter consists of
several switches. In the multi level inverter the arrangement switches
angles are very important.
Nowadays, the demands for the electronic products are getting higher due
to the rapid advances in technology. The usage of electronic appliances
now is a part of our lives, where it covers 80% of the performance in our
daily activities. For example, we require a computer to find the latest
information on recent developments, mobile phones are used to
communicate, machines and motors AC/DC are used by both small and
large-scale industries to lift or move objects. Most of the electronic

equipment is called distortion current also known as non-linear load.

This non-linear load might be a single phase or three phase load. For
example for the variable speed drives, the current production is called
Harmonic distortion.

Harmonic distortion will produce a high frequency where it will increase

the current and damage the electrical equipment. To reduce this
harmonic distortion sinusoidal pulse width modulation technique is
applied in this project. The project aims to compare the total harmonic
distortion of various multilevel inverters.
1.3

Problem Statement

As stated above, the largest problem in power quality is harmonic

distortion. Harmonic distortion is divided in to two of the harmonic
which are voltage and current harmonics. Harmonic currents produced
by the harmonics contained in the supply voltage depending on the
types of loads such as resistive load, capacitive load and inductive load.
These harmonics can be generated from the source side or load side.
Harmonic at the load side is due to the nonlinear operation of electronic
devices they include. This can cause magnetic core transformer and
motor overheat thus, reduce the eficiency and life time of the
equipment.
Induction motor drives are widely used in high performance drive
system. It is due to the good power factor, high efciency, extremely
rugged and do not require starting motor. This function is to allow the
adjustment of speed motor by using the frequency and amplitude of the
stator voltage. However, the ratio of stator voltage to frequency should be
kept constant.
In order to make the motor operates smoothly, there are several
modulation technique that are used to cater the output variable that
have maximum basic component with minimum harmonic and less
switching losses. In this project, Sinusoidal PWM is used as a
modulation technique. Actually, this technique was originally developed
as a PWM for single
phase inverter. It is a more sophisticated
technique for generating sine wave that provides a higher voltage to the
motor with lower total harmonic distortion.

1.4

Project Objective
Analysis of a Cascaded H-Bridge multilevel inverter employing sinusoidal pulse
width modulation for providing the gate pulses for various levels of switches of
the multilevel inverter. The various sinusoidal pulse width modulation techniques
employed are

Phase Disposition modulation (PDM), Phase Opposition Disposition modulation

(PODM), Alternate Phase Opposition Disposition (APODM).

The several objectives accomplished in this project are

1) Analysis of the concepts of inverter and sinusoidal pulse width modulation.
2) Building a firing sequence generator to employ all the three techniques.
3) Design of the suitable model for the analysis.

1.5

Project Scope
There are several types modulating technique that controls the
amount of time and the sequence that uses to switch on and off. The
most modulating techniques used are the carrier-based technique. For
example the sinusoidal pulse width modulation (SPWM), the spacevector (SV) technique, and the selective-harmonic-elimination (SHE)
technique. The scope of this project is focused on the implementation of
SPWM for phase voltage source inverter using the software
MATLAB/SIMULINK this includes:
1)
Focus on development of MATLAB/SIMULINK model of level
shifting SPWM step by step.

2)

Compares the output waveforms of 5-level, 7-leveland15-level

inverters and also observes the THD of both inverters.

3)
Simulation model of SPWM using cascaded h-bridge multilevel
inverter using MATLAB/SIMULINK

1.6 Conclusion
In this chapter we have discussed about the project statement,
project scope and project objectives.

4) CHAPTER-2
5) LITERATURE REVIEW
6) A LITERATURES SURVEY REGARDING WITH MULTILEVEL
INVERTER TOPOLOGIES AND CONTROL TECHNIQUE

7)
8) 2.1 Introduction
9)
In this chapter we are going to discuss the literature review of
all topologies to convert dc to ac and also the diferent control
techniques.
10)
2.2 Diode clamped inverter:
11)
Zhiguo Pan, et al., presented in this literature a new voltage
balancing control for the diode clamped multilevel rectifier/inverter
system. A complete analysis of the voltage balance theory for a five-level
back to- back system is given. The proposed control strategy regulates
the dc bus voltage, balances the capacitors, and decrseases the harmonic
components of the voltage and current. Grain P. Adam, et al, introduced
a new operational mode for diode-clamped multilevel inverters termed
quasi two-level operation is proposed. Such operation aims to avoid the
imbalance problem of the dc-link capacitors for multilevel inverters with
more than three levels and reduces the dc-link capacitance without
introducing any significant voltage ripple at the dc-link nodes. Baoming
Ge, et al, suggested an efective control technique for medium-voltage
high-power induction motor fed by cascaded neutral-point clamped
inverter. Jefrey Ewanchuk, et al, addressed a five/nine-level twelveswitch inverter is described for three-phase high-speed electric machines
having a low per-unit leakage reactance. Operational and design details
are described for the NPC-CI inverter using a three-limb inductor core,
including practical considerations for the inverter construction and
operation, 480 V/208 V inductor mass comparison between six- and
twelve-switch topologies, natural voltage balancing of the split capacitor
5

dc link, and voltage stresses of the freewheel diodes. Arash A. Boora, et

al, used a new single-inductor multi-output dc/dc converter is proposed
that can control the dc-link voltages of a single-phase diode-clamped
inverter asymmetrically to achieve voltage quality enhancement. The
circuit of the presented converter is explained and the main equations
are developed. C. Attaianese, et al, proposed a comparative analysis
between the classical structure of Neutral Point Clamped (NPC) converter
and the emerging Active NPC converter. Numerical analyses of losses
distribution among power devices for some known carrier based PWM
techniques are reported. Jain, et al, presented in this literature

DC bus

short circuit protection is usually done, using the sensed voltage across
collector and emitter (i.e., VCE sensing), of all the devices in a leg. This
feature is accommodated with the conventional gate drive circuits used in
the two level converters.The literature explains the detailed circuit
behavior and reasons, which result in the occurrence of such false VCE
fault signals also illustrates that such a phenomenon shows dependence
on the power factor of the supplied three-phase load. It is shown that the
problem can be avoided by blocking out the VCE sense fault signals of
the inner devices of the leg. Jun Li, et al, introduced a new nine-level
active neutral-point-clamped (9L ANPC) converter is proposed for the grid
connection of large wind turbines (WTs) to improve the waveform quality
of the converter output voltage and current. The topology, operating
principles, control schemes, and main features, as well as semiconductor
device selection of the proposed converter are presented in detail. Robert
Stala, et al, focused on investigations of dc-link voltages balance with the
use of a passive RLC circuit in a single-phase diode-clamped inverter
composed of two three

level legs. This

literature

also

presents

mathematical analysis of the PWM modulation method and the inverter

operation, and an analytical description of the natural balancing process
6

with contribution of the load current and the balancing circuit current.
Jin Li, et al, suggested three level active neutral-point-clamped zerocurrent transition (3L-ANPC ZCT) converter for the sustainable energy
power conversion systems. The operation principle and comparison with
the 3LDNPC ZCT are analyzed in detail. Marcelo C. Cavalcanti, et al,
addressed new modulation techniques for three-phase transformer less
neutral point clamped inverters to eliminate leakage currents in
photovoltaic systems without requiring any modification on the multilevel
inverter or any additional hardware. Jin Li, et al., used comparison
between three level diode neutral point-clamped zero-current transition
(DNPC-3L ZCT) inverter and three-level active neutral-point clamped
zero-current-transition (ANPC-3L ZCT) inverter. The two multilevel soft
switching topologies are compared with respect to switching energy,
volume, as well as parasitic inductance influence.
12)
13)
14)
15)
16)
2.3 Cascaded multilevel inverter:
17)

Zhongyuan Cheng, et al, suggested a novel switching sequence design

for the space-vector modulation of high power multilevel converters. Pablo

Lezana, et al, addressed the use of a single-phase reduced cell suitable for
cascaded multilevel converters. The results presented confirm that this
medium voltage inverter efectively eliminates low frequency input current
harmonics at the primary side of the transformer and operates without
problems in regenerative mode. H. K. Al-Hadidi, et al, investigated a new
configuration for a cascade (H-bridge) converter-based dynamic voltage
regulator in which the basic cascade converter is supplemented with a
shunt thyristor-switched inductor. Yidan Li, et a, presented in this literature
a novel dc voltage detection technique, referred to as single multiple voltage
7

(SMV) detector, is developed to obtain dc capacitor voltages in the cascaded

H-bridge (CHB) multilevel inverter- based static synchronous compensator
(STATCOM). Zhong Du, et al, used a cascaded H-bridge multilevel inverter
that can be implemented using only a single dc power source and
capacitors. This literature mainly discusses control of seven-level HCMLI
with fundamental frequency switching control and how its modulation index
range can be extended using triplen harmonic compensation. Zhong Du, et
al, focused on a cascaded H-bridge multilevel boost inverter for electric
vehicle (EV) and hybrid EV (HEV) applications implemented without the use
of inductors. Currently available power inverter systems for HEVs use a dc
dc boost converter to boost the battery voltage for a traditional three phase
inverter. Yu Liu, et al, suggested a new feedback control strategy for
balancing individual dc capacitor voltages in a three-phase cascade
multilevel inverter-based static synchronous compensator. Elena Villanueva,
et al, addressed a single-phase cascaded H-bridge converter for a gridconnected photovoltaic (PV) application. The adopted control scheme permits
the independent control of each dc-link voltage, enabling, in this way, the
tracking of the maximum power point for each string of PV panels. Farid
Khoucha, et al, investigated a hybrid cascaded H-bridge multilevel motor
drive direct torque control (DTC) scheme for electric vehicles (EVs) or hybrid
EVs. The control method is based on DTC operating principles. Rajesh
Gupta, et al, presented in this literature a generalized multiband hysteresis
modulation and its characterization have been proposed for the slidingmode control of cascaded H-bridge multilevel-inverter (CHBMLI)controlled
systems. A frequency-domain method is proposed for the determination of
net hysteresis bandwidth for a given desired maximum switching frequency
of the inverter. Domingo A. RuizCaballero, et al, used novel symmetric
hybrid multilevel topologies are introduced for both single- and three-phase
medium-voltage high power systems. Gierri Waltrich, et al, focused
8

modular three-phase medium-voltage high power systems. Gierri Waltrich,

et al, focused a modular three-phase multilevel inverter specially suited for
electrical drive applications is proposed. The topology is based on power
cells connected in cascade using two inverter legs in series. K. Sivakumar, et
al, suggested a new five-level inverter topology for open-end winding
induction motor (IM) drive is proposed. Farid Khoucha, et al, addressed a
comparison study for a cascaded H-bridge multilevel direct torque control
(DTC) induction motor drive. In this case, symmetrical and asymmetrical
arrangements of five-level and seven-level H-bridge inverters are compared
in order to find an optimum arrangement with lower switching losses and
optimized output voltage quality. Jianjiang Shi, et al, presented in this
literature the solid-state transformer (SST) is one of the key elements in
power electronic-based micro grid systems. This literature presents a novel
single-phase dq vector based common-duty-ratio control method for the
multilevel rectifier, and a voltage feed forward and feedback based controller
for the modular DAB converter. Makoto Hagiwara, et al, introduced the
modular multilevel cascade converter based on double-star chopper-cells,
which is intended for grid connection to medium-voltage power systems
without using line-frequency transformers. This proposes an arm-balancing
control to achieve voltage balancing under all the operating conditions.
Hossein Sepahvand, et al, suggested the impacts of the connected load to
the cascaded H-bridge converter as well as the switching angles on the
voltage regulation of the capacitors are studied. This literature proves that
voltage regulation is only attainable in a much limited operating conditions
that it was originally reported. Javad Ebrahimi, et al, used a new topology of
a cascaded multilevel converter is proposed. The proposed topology is based
on a cascaded connection of single-phase sub multi level converter units
and full-bridge converters. Then, the structure of the proposed topology is
optimized.
9

18)
19)

2.4

Flying capacitor multilevel inverter:

20)

Byeong-Mun Song, et al, presented in this literature a new soft-

switching flying capacitor multilevel inverter that can be generalized and be

extended from three levels to any number of levels. Miguel F. Escalante, et
al, addressed the requirements imposed by a direct torque control (DTC)
strategy on multilevel inverters are analyzed. A control strategy is proposed
in order to fulfill those requirements. Keith A. Corzine, et , suggested an
approach of balancing capacitors, thus expanding the application fields of
FBCS inverters to the family of the flying capacitor multilevel inverters
under the condition of choosing a suitable modulation index. Xiaomin Kou,
et al, used a unique design for flying capacitor type multilevel Xiaomin Kou,
et al, used a unique design for flying capacitor type multilevel inverters with
fault-tolerant features. The most attractive point of the proposed design is
that it can undertake the single-switch fault per phase without sacrificing
power converting quality. The capacitor balancing approach under

fault-

conditions are also given. Anshuman Shukla, et al, investigated a method for
controlling the FCMLI is proposed which ensures that the flying capacitor
voltages remain nearly constant using the preferential charging and
discharging

of

these

capacitors.

static

synchronous

compensator

(STATCOM) and a static synchronous series compensator (SSSC) based on

five-level flying capacitor inverters are proposed. Dae-Wook Kang, et al,
presented in this literature a simple carrier symmetric method for the
voltage balance of flying capacitors in flying-capacitor multilevel inverters.
The carrier-redistribution pulse width modulation (CRPWM) method was
reported as a solution for the voltage balance but it has a drawback at the
transition of voltage level. Anshuman Shukla,

et al, addressed the

implementation of a distribution static compensator (DSTATCOM) using an

10

FCMLI is presented. A hysteresis current control technique for controlling

the injected current by the FCMLI-based DSTATCOM is also discussed.
Robert Stala, et al, focused on investigations of voltage-sharing stabilization
with the use of passive RLC circuit in switch-mode flying capacitor dcdc
converters. Also a mathematical analysis of the balancing process in boost
and buckboost converters are presented. M. Hojo, et al, suggested on well
known topology of flying capacitor multilevel converter which has several
terminals of diferent dc voltage and an ac voltage terminal.This literature
proposes to utilize the topology as an integrated power conversion module.
Pavel Kobrle, et al, addressed control strategy of flying capacitors multilevel
inverters. The main issue is the analysis of the permissible switching states,
especially the possibility of the multiple commutations. Z.Oudjebour, et al,
used the stabilization of the input DC voltages of five-level flying capacitors
(FLFC) voltage source inverters (VSI) . A feedback control algorithm of the
rectifier is proposed. M.Trabelsi, et al, investigated an experimental
photovoltaic (PV) power conditioning system with line connection. The
conditioner consists of a flying capacitors multi-cell inverter fed by a dc-dc
boost converter. Mostafa Khazraei, et al, presented in this literature two
active capacitor voltage balancing schemes are proposed for single-phase
(Hbridge) flying-capacitor multilevel converters. They are based on the
circuit equations of flying capacitor converters. These methods are shown to
be efective on capacitor voltage regulation in flying-capacitor multilevel
converters. Anshuman Shukla, et al, focused on the development of
multilevel hysteresis current regulation strategies. Two such strategies have
been discussed and some modifications in their control tasks have been
proposed to achieve more reliable and improved performance.
21)
22)

2.5 Sinusoidal PWM

11

23)

Giuseppe Carrara, et al, focused on generalization of the PWM

subharmonic method to control single-phase or three phase multilevel

voltage source inverters (VSI). N. A. Azli, et al, addressed Implementation of
a regular sampled PWM technique based on a single carrier multilevel
modulation strategy on a multilevel inverter using a digital signal processor
(DSP) is presented.G.P. Adam, et al, discussed in detail the principle of
operation, carrier-based pulse width modulation and a capacitors voltage
balancing technique for three-level and five-level modular inverters. B.
Shanthi, et al, investigated on comparison of unipolar multicarrier Pulse
Width Modulation (PWM) techniques for the Flying Capacitor Multi Level
Inverter (FCMLI). This literature presents the diferent types of unipolar
PWM strategies for the chosen inverter. Moncef Ben Smida, et al, used an
original multicarrier sub harmonic pulse width modulation (PWM), called
disposition band carrier and phase-shifted carrier PWM (DBC-PSC-PWM),
method is developed to produce (n m + 1) output voltage levels and to
improve the output voltage harmonic spectrum with a wide output
frequency range. P.K. Chaturvedi, et al, presented in this literature a carrierbased closed-loop control technique has been developed to reduce the
switching losses based on insertion of no switching zone within each half
cycle of fundamental wave. Suroso, et al, suggested a five-level pulse width
modulation inverter configuration, including chopper circuits as DC
current-power source circuits using small smoothing inductors, is verified
through computer simulations and experimental tests. K.Ramani, et al,
designed a seven-level flying capacitor multilevel inverter by using sinusoidal
pulse width modulation technique. Ilhami Colak, et al, addressed

modified Sinusoidal Pulse Width Modulation (SPWM) modulator with phase

disposition that increases output waveform up to 7level while reducing
output harmonics. Wahidah Abd, et al, presented in this literature pulse

12

width modulation (PWM) for single-phase five level inverter via fieldprogrammable gate array (FPGA).
24)
25)
26)
27)

2.6 Space vector PWM

Amit Kumar Gupta, et al, presented in this literature a general

SVPWM algorithm for multilevel inverters based on standard two-level

SVPWM. The proposed method uses a simple mapping to achieve the
SVPWM for a multilevel inverter. Ahmed M. Massoud, et al, addressed two
diferent space vector modulation (SVM) techniques viz., phase-shifted SVM
and hybrid SVM, are used for multilevel inverter Pulse width modulation
generation. Amit Kumar Gupta, et al, suggested a simple space vector pulse
width modulation algorithm for a multilevel inverter for operation in the over
modulation range. The proposed scheme easily determines the location of
the reference vector and calculates on-times. scar Lpez, et al, introduced
a new space vector pulse width modulation algorithm for multilevel
multiphase voltage source converters with switching state redundancy. The
algorithm was implemented in a field-programmable gate array. Anish
Gopinath, et al, focused a view that the space vector locations of multilevel
inverters possess a fractal structure, and the properties of fractal structure
together with the simplicity of fractal arithmetic are exploited to generate the
SVPWM. The proposed method does not use any lookup tables for sector
identification. Aneesh Mohamed A. S., et al, used a generalized method for
the generation of space vector pulse width modulation (SVPWM) signals for
multilevel inverters. A new technique is proposed in this literature, by which
these two-level vectors are translated to the switching vectors of the
multilevel inverter by adding the center of the sub hexagon to the two-level
vectors. Mohan M. Renge, et al, presented in this literature an approach to

13

reduce common-mode voltage (CMV) at the output of multilevel inverter

using 3-D space vector modulation (SVM). Behzad Vafakhah, et al,
addressed a new multilevel SVPWM technique with a five-segment switching
sequence, where half-wave symmetrical PWM voltage waveforms are used to
balance the inductor common-mode dc voltages and also to avoid all
possible switching states with a high winding current ripple. Ahmed M.
Massoud, et al, suggested two discontinuous multilevel space vector
modulation (SVM) techniques are implemented for DVR control and are
shown to reduce inverter switching losses while maintaining virtually the
same harmonic performance as the conventional multilevel SVM at a high
number of levels. Gabriele Grandi, et al, introduced two carrier-based
modulation techniques for a dual two level inverter with power sharing
capability and proper multilevel voltage waveforms. Their main advantage is
a simpler implementation compared to SVM. Xu She, et al, focused a novel
3-D space modulation technique with voltage balancing capability is
proposed for a cascaded seven-level rectifier stage of SST.
28)

2.7 SHE-PWM

29)

Mohamed. S. A. Dahidah, et al, suggested solutions to the switching

transitions of a five-level SHEPWM when both the quarter- and half-wave

symmetry are abolished. Vladimir Blasko, et al, used a novel and a
systematic design approach for applying signal processing methods (like
modified adaptive selective harmonic elimination algorithms) as an addition
to conventional control. Alan J. Watson, et al, presented in this literature a
complete

Harmonic Elimination Approach that is used to balance dc link

voltages in a cascaded H-Bridge (CHB) multilevel rectifier. Mohamed S. A.

Dahidah, et al, addressed a generalized formulation for selective harmonic
elimination pulse-width modulation (SHE-PWM) control suitable for highvoltage high-power cascaded multilevel voltage source converters (VSC) with
14

both equal and non equal dc sources used in constant frequency utility
applications. Vassilios G. Agelidis, et al, focused on a five level symmetrically
defined multilevel selective harmonic elimination pulse width modulation
(MSHEPWM) strategy is reported in this paper. It is mathematically
expressed using Fourier-based equations on a line-to-neutral basis. R.N.
Ray, et al, introduced a method is presented to compute the switching
angles for selected harmonic elimination (SHE) in a multilevel inverter using
the particle swarm optimisation technique. Fanghua Zhang, et al, suggested
a selective harmonic elimination (SHE) control strategy on a three-phase
four-leg inverter is reported. Wanmin Fei, et al, used a generalized
formulation of quarter wave symmetrical selective harmonic elimination
(SHE) problems according to the rising and falling edges of the pulse width
modulation (PWM) waveforms for multilevel inverters. The SHE-PWM
equations that can eliminate harmonics from 5th to 35th with modulation
index M varying from 0 to 1.15 are formulated, and solutions are presented.
Wanmin Fei, et al, presented in this literature a novel generalized
formulation of half-cycle symmetry SHE-PWM problems for multilevel
inverters. A method to obtain initial values for the SHE-PWM equations
according to the reference modulation index M and the initial phase angle of
output fundamental voltage is proposed and investigated thoroughly. H.
Taghizadeh, et al, addressed the elimination of harmonics in a cascade
multilevel inverter by considering the non equality of separated dc sources
by using particle swarm optimization is presented. Mohamed S. A. Dahidah,
et al, focused on a new formulation of selective harmonic elimination pulse
width modulation (SHE-PWM) technique suitable for cascaded multilevel
inverters with optimized DC voltage levels. Sridhar R. Pulikanti, et al,
introduced a neutral point voltage control strategy for the three-level active
neutral

point

clamped

(ANPC)

converter

using

selective

harmonic

elimination pulse width modulation (SHE-PWM). Sridhar R. Pulikanti, et al,

15

presented in this literature a control strategy is proposed to re regulate the

voltage across the FCs at their respective reference voltage levels by
swapping the switching patterns of the switches based on the polarity of the
output current, the polarity of the FC voltage, and the polarity of the
fundamental line-to-neutral voltage under selective harmonic elimination
pulse width modulation.
30)
31)
32)
33)
34)
35)
36)

CHAPTER-3

MULTILEVEL INVERTERS

3.1 Introduction
Multilevel Inverter structures A voltage level of three is

considered to be the smallest number in multilevel converter

topologies. Due to the bi-directional switches, the multilevel VSC can
work in both rectifier and inverter modes. This is why most of the time
it is referred to as a converter instead of an inverter in this
dissertation. A multilevel converter can switch either its input or
output nodes (or both) between multiple (more than two) levels of
voltage or current. As the number of levels reaches infinity, the output
THD approaches zero. The number of the achievable voltage levels,
however, is limited by voltage-imbalance problems, voltage clamping
requirements, circuit layout and packaging constraints complexity of
the controller, and, of course, capital and maintenance costs. Three
diferent major multilevel converter structures have been applied in
industrial applications: cascaded H-bridges converter with separate dc
sources, diode clamped, and flying capacitors.
16

37)

The multilevel inverter structures are the main focus of

discussion in this chapter; however, the illustrated structures can be

implemented for rectifying operation as well. Although each type of
multilevel converters share the advantages of multilevel voltage source
inverters, they may be suitable for specific application due to their
structures

and

drawbacks.

Operation

and

structure

of

some

important type of multilevel converters are discussed in the following

sections. In a multilevel VSI, the dc-link voltage Vdc is obtained from
any equipment which can yield stable dc source. Series connected
capacitors constitute energy tank for the inverter providing some
nodes to which multilevel inverter can be connected. Primarily, the
series connected capacitors will be assumed to be any voltage sources
of the same value. Each capacitor voltage Vc is given by Vc=Vdc/ (n1), where n denotes the number of level. Inverter Structure shows a
schematic diagram of one phase leg of inverters with diferent number
of levels, for which the action of the power semiconductors is
represented by an ideal switch with several positions. A two-level
inverter generates an output voltage with two values (levels) with
respect to the negative terminal of the capacitor, while the three-level
inverter generates three voltages, and so on.
38)

Multilevel power conversion has become increasingly

popular in recent years due to advantages of high power quality

waveforms, low electromagnetic compatibility (EMC) concerns, low
switching losses, and high-voltage capability. However, it increases the
number of switching devices and other components, which results in
an increase of complexity problems and system cost. There are
diferent types of multilevel circuits involved. The first topology
introduced was the series H-bridge design. This was followed by the

17

diode clamped converter, which utilized a bank of series capacitors. A

later invention detailed the flying capacitor design in which the
capacitors were floating rather than series-connected. Another
multilevel design involves parallel connection of inverter phases
through inter-phase reactors. In this design, the semiconductors block
the

entire

dc

voltage,

but

share

the

load

current.

Several

combinational designs have also emerged some involving cascading

the fundamental topologies. These designs can create higher power
quality for a given number of semiconductor devices than the
fundamental topologies alone due to a multiplying efect of the
number of levels. The multilevel inverters are mainly classified as
diode clamped, Flying capacitor inverter and cascaded multilevel
inverter. The cascaded multilevel control method is very easy when
compare to other multilevel inverter because it doesnt require any
clamping diode and flying capacitor.
39)

Conventional two-level inverters, are mostly used today to

generate an AC voltage from an DC voltage. The two-level inverter can

only create two diferent output voltages for the load, Vdc 2 or Vdc 2
(when the inverter is fed with Vdc). To build up an AC output voltage
these two voltages are usually switched with PWM, see Figure. Though
this method is efective it creates harmonic distortions in the output
voltage, EMI and high dv/dt (compared to multilevel inverters) . This
may not always be a problem but for some applications there may be a
need for low distortion in the output voltage. The concept of Multi
Level Inverters (MLI) does not depend on just two levels of voltage to
create an AC signal. Instead several voltage levels are added to each
other to create a smoother stepped waveform, , with lower dv/ dt and
lower harmonic distortions. With more voltage levels in the inverter

18

the waveform it creates becomes smoother, but with many levels the
design becomes more complicated, with more components and a more
complicated controller for the inverter is needed. To better understand
multilevel inverters the more conventional three-level inverter, , can be
investigated. It is called a three-level inverter since every phase-leg can
create the three voltages Vdc 2 , 0, Vdc 2 , as can be seen in the rst
part of. A three-level inverter design is similar to that of an
conventional two-level inverter but there are twice as many valves in
each phase-leg. In between the upper and lower two valves there are
diodes, called clamping diodes, connected to the a neutral point in
between two capacitors.
40)

These capacitor build up the DC-bus, each capacitor is

charged with the voltage Vdc 2 . Together with another phase-leg an

output line-to-line voltage with even more levels can be obtained. To
create the zero voltage the two switches closest to the midpoint are
switched on and the clamping diodes hold the voltage to zero with the
neutral point. Now, if more valve pairs, clamping diodes and
capacitors are added the inverter can generate even more voltage
levels, see the result is a multilevel inverter with clamping diode
topology.
41)

Some of the most attractive features in general for

multilevel inverters are that they can generate output voltages with
very low distortion and dv/dt , generate smaller common-mode voltage
and operate with lower switching frequency

compared to the more

conventional two-level inverters. With a lower switching frequency the

switching losses can be reduced and the lower dv /dt comes from that
the voltage steps are smaller, as can be seen in as the number of
levels increase.
19

42)

There are also diferent kinds of topologies of multilevel

inverters that can generate a stepped voltage waveform and that are
suitable for diferent applications. By designing multilevel circuits in
diferent

ways,

topologies

with

diferent

properties

have

been

developed, some of which will be looked upon in this report. The

Multilevel inverter topologies that are investigated in this work are:
Neutral

Point

Clamped

Multilevel

Inverter

(NPCMLI),

Capacitor

Clamped Multilevel Inverter (CCMLI), Cascaded Multilevel Inverter

(CMCI), Generalized Multilevel Inverter (GMLI), Reversing Voltage
Multilevel Inverter (RVMLI), Modular Multilevel Inverter (M2I) and
Generalized Multilevel Current Source Inverter (GMCSI). The most
dominant multilevel inverters use one or more voltage sources, as the
three-level inverter, and most topologies presented in this report will
have voltage sources
43)
44)
45)
46)
47)
48)
49)

Multilevel Inverter Topologies

3.2 Diode clamped Multilevel inverter

50) The most commonly used multilevel topology is the diode

clamped inverter, in which the diode is used as the clamping device to

clamp the dc bus voltage so as to achieve steps in the output voltage.
Thus, the main concept of this inverter is to use diodes to limit the
power devices voltage stress. The voltage over each capacitor and each
switch is Vdc. An n level inverter needs (n-1) voltage sources, 2(n-1)
switching devices and (n-1) (n-2) diodes. By increasing the number of
20

voltage levels the quality of the output voltage is improved and the
voltage waveform becomes closer to sinusoidal waveform. Figure.2a)
shows a three-level diode-clamped converter in which the dc bus
consists of two capacitors, C1, C2. For dc-bus voltage Vdc, the voltage
across each capacitor is Vdc/2 and each device voltage stress will be
limited to one capacitor voltage level Vdc/2 through clamping diodes.
To explain how the staircase voltage is synthesized, the neutral point
n is considered as the output phase voltage reference point. There are
three switch combinations to synthesize three-level voltages across a
and n.
51)

1.

Voltage

level Van= Vdc/2, turn on the switches S1andS2.

52) 2. Voltage level Van= 0, turn on the switches S2 and S1 . 3.
Voltage level Van= - Vdc/2 turn on the switches S1,S2.
53) Figure.4.2 shows a five-level diode-clamped converter in which
the dc bus consists of four capacitors, C1, C2, C3, and C4. For dc-bus
voltage Vdc, the voltage across each capacitor is Vdc/4 and each
device voltage stress will be limited to one capacitor voltage level
Vdc/4 through clamping diodes
54)

21

55)
56)

FIG 3.1: Diode Clamped multilevel inverter

57)

58)

[Source: https://www.elprocus.com]

3.3 Cascaded multilevel inverter:

59)

The concept of this inverter is based on connecting H-

bridge inverters in series to get a sinusoidal voltage output. The

output voltage is the sum of the voltage that is generated by each cell.
The number of output voltage levels are 2n+1, where n is the number
of cells. The switching angles can be chosen in such a way that the
total harmonic distortion is minimized. One of the advantages of this
type of multilevel inverter is that it needs less number of components
comparative to the Diode clamped or the flying capacitor, so the price
and the weight of the inverter is less than that of the

two

types.Figure.3 shows the power circuit for one phase leg of a threelevel and five-level cascaded inverter. In a 3-level cascaded inverter
each single phase full-bridge inverter generates three voltages at the
22

output: +Vdc, 0, -Vdc (zero, positive dc voltage, and negative dc

voltage). This is made possible by connecting the capacitors. The
resulting output ac voltage swings from -Vdc to +Vdc with three levels,
-2Vdc to +2Vdc.
60)
61)

62)
63)

Fig 3.2: Cascaded H-Bridge multilevel inverter

64)

65)

[Source: https://www.elprocus.com]

4.4. Capacitor clamped inverter:

66)
67)

The structure of this inverter is similar to that of the

diode-clamped inverter except that instead of using clamping diodes,

the inverter uses capacitors in their place. The flying capacitor
involves series connection of capacitor clamped switching cells. This
23

topology has a ladder structure of dc side capacitors, where the

voltage on each capacitor difers from that of the next capacitor. The
voltage increment between two adjacent capacitor legs gives the size of
the voltage steps in the output waveform.fig shows single phase n-level
configuration of capacitor clamped inverter. An n-level inverter will
require a total of (n-1)(n-2)/2 clamping capacitors per phase leg in
addition to (n1) main dc bus capacitors. The voltage levels and the
arrangements of the flying capacitors in the FCMLI structure assures
that the voltage stress across each main device is same and is equal to
Vdc/(n-1), for an n-level inverter. The voltage synthesis in a five-level
capacitor-clamped converter has more flexibility than a diode-clamped
converter. Using the voltage of the five level phase-leg a output with
respect to the neutral point n (i.e.Van), can be synthesized by the
following switch combinations.
68)

1. Voltage level Van= Vdc/2, turn on all upper switches S1

S4 .
69)

2. Voltage level Van= Vdc/4, there are three combinations.

70)

a. Turn on switches S1 , S2 , S3 and S1 .(Van= Vdc/2 of upper

C4s Vdc/4 of C1s).

71)

b. Turn on switches S2 , S3 , S4 and S4.(Van= 3Vdc/4 of upper

C3s Vdc/2 of C4s).

72)

c. Turn on switches S1 , S3 , S4 and S3 . (Van= Vdc/2 of upper

C4s 3Vdc/4 or C3s + Vdc/2 of upper C).

73)

3. Voltage level Van= 0, turn on upper switches S3 , S4 , and

lower switch S1, S2.

24

74)

4. Voltage level Van= -Vdc/4, turn on upper switch S1 and

lower switches S1, S2and S3.

75)

5. Voltage level Van= -Vdc/2, turn on all lower switches S1 , S2 ,

S3 and S4.

76)
77)

Fig 3.3: Flying Capacitor type multilevel inverter

78)

[Source: https://www.elprocus.com]

79)
80)

3.5 Sinusoidal Pulse Width Modulation:

81)

The control principle of the SPWM is to use several

triangular carrier signals keeping only one modulating sinusoidal

signal. For a m-level inverter, (m-1) triangular carriers are needed. The
carriers have the same frequency fc and the same peak-to-peak
amplitude Ac. The modulating signal is a sinusoid of frequency fm and
25

amplitude Am. At every instant, each carrier is compared with the

modulating signal. Each comparison switches the switch "on" if the
modulating signal is greater than the triangular carrier assigned to
that switch. The main parameters of the modulation process are: The
frequency ratio k=fc/fm, where fc is the frequency of the carriers, and
fm is the frequency of the modulating signal. The modulation index
M=Ac / (m *Ac), where Ac is the amplitude of the modulating signal, A,
is the peak-to-peak amplitude of the carriers, and m'= (m- 1)/2, where
m is the number of level (which is odd). Figure.6 shows the typical
voltage generated by one cell for the inverter by comparing a
sinusoidal reference with a triangular carrier signal. A number of
cascaded cells in one phase with their carriers shifted by an angle and
using the same control voltage produce a load voltage with the
smallest distortion.

26

82)
83)

Fig 3.4: Sinusoidal pulse width modulation

84)

[Source: https://www.pantechsolutions.net]

85) The various level shifting Sinusoidal pulse width modulation

techniques are discussed below.
86) Phase Disposition:
87) In phase disposition method all the carriers have the same frequency
and amplitude. Moreover all the N-1 carriers are in phase with each
other. It is based on a comparison of a sinusoidal reference waveform
with vertically shifted carrier waveform this method uses N 1 carrier
signals to generate N level inverter output voltage. All the carrier signals
have the same amplitude, same frequency and are in phase.
88)

89)

Fig 3.5: Phase Disposition

27

90)
91) Phase Opposition Disposition:
92)
93) In Phase Opposition Disposition (POD), the carrier signal above the
zero axis all the carrier wave have same frequency, same amplitude and
in phase each other. But the below the zero axis all the carrier wave have
same frequency, same amplitude and in phase but all carrier wave have
phase shifted 180 degree compare to the above zero axis carrier
waveform.
94)
95)
96)
97)

98)

Fig 3.6: Phase Opposition Disposition

28

99)
100)
101)
102) Alternate Phase Opposition Disposition:
103)
104) In Alternate Phase Opposition Disposition PWM (APOD), every carrier
waveform is out phase with its neighbouring carrier wave by 180 degree
as shown in figure 4. All the carrier waveform have same frequency, same
amplitude and but compare one carrier waveform to neighbour carrier
waveform is phase shifted 180 degree. Odd carrier waveforms are in
phase but compare to even carrier waveform are out of phase shift 180
degree in odd carrier waveform.
105) Simulating a multilevel inverter and obtaining perform Fourier
analysis and calculating and comparing the total harmonic distortions of
diferent techniques and suggesting the best SPWM technique.
106)
107)
108)
109)

29

110)

111) Fig 3.7:

Alternate Phase Opposition Disposition modulation

112)
113) Conclusion:
114) In this chapter we have discussed about the SPWM and
various types of SPWM.
115)
116)
117)

30

118)
119)
120)
121)
122)
123) CHAPTER-4
124)

CASCADED H-BRIDGE MULTILEVEL INVERTER

125)
126)

Fig 4.1: Cascaded H-Bridge multilevel inverter

127)
128) 4.1 Introduction

31

129)

Cascaded H-Bridge multilevel converters formed by the

series connection of two or more single phase H-Bridge inverters. Each HBridge corresponds to two voltage source phase legs, where the L-L voltage is
the converter output. Therefore, a single H-bridge converter is able to
generate three diferent voltage levels4-6 . Each leg has only two possible
switching states, to avoid dc-link capacitor short-circuit. Since there are two
legs, four diferent switching states are possible, although two of them have
redundant output voltage. When two or more H-Brides are connected in
series, their output voltages can be combined to form diferent output levels,
increasing the total inverter output voltage and also its rated power. The
Single Phase n - Cascaded H-Bridge Inverter for PV applications, k dc
generators and k cascaded H-bridges arranged in a single phase multilevel
inverter topology. Each dc generator consists of PV cell arrays connected in
series and in parallel, thus obtaining the desired output voltage and current.
H bridges basically consist of four metal oxide semiconductor field efect
transistors embedding an anti parallel diode and a driver circuit. The
number k of H-bridges depends on the number n = 2k+1 of desired levels,
which has to be chosen by taking into account both the available PV fields
and design considerations. [5] Higher the number of levels the better the
sinusoidal output waveforms. However, the number of level increases the
complexity and the cost of the system while reducing its switching frequency
in comparison with two level converters. Since low voltage transistors
(typically MOSFETs) present significantly higher switching frequency than
high power transistors (typically IGBT), MLIs can operate at significantly
higher switching frequencies than two level converters. This allows the use of
smaller low pass filters. Each H-bridge can be driven by a square waveform
with a suitable duty cycle or a PWM pattern, thus resulting in a staircase
without or with PWM. In the considered single phase 230V system, the cells
are arranged into five distinct arrays, thus resulting in an eleven level
inverter, which can be considered a reasonable trade-of among complexity,
performance, and cost.

32

130)

131)
132)

Figure 4.2 Single phase structures of Cascaded inverter

133)
134)
135)

One more alternative for a multilevel inverter is the cascaded

multilevel inverter or series H-bridge inverter. The series H-bridge inverter

appeared in 1975[14]. Cascaded multilevel inverter was not fully realized
until two researchers, Lai and Peng. They patented it and presented its
various advantages in 1997. Since then, the CMI has been utilized in a wide
range of applications. With its modularity and flexibility, the CMI shows
superiority

in

high-power

applications,

especially

shunt

and

series

connected FACTS controllers. The CMI synthesizes its output nearly

sinusoidal voltage waveforms by combining many isolated voltage levels. By
adding more H-bridge converters, the amount of Var can simply increased
without redesign the power stage, and build-in redundancy against
individual H-bridge converter failure can be realized. A series of single-phase
full bridges makes up a phase for the inverter. A three-phase CMI topology is

33

essentially composed of three identical phase legs of the series-chain of Hbridge converters, which can possibly generate diferent output voltage
waveforms and ofers the potential for AC system phase-balancing. This
feature is impossible in other VSC topologies utilizing a common DC link.
Since this topology consists of series power conversion cells, the voltage and
power level may be easily scaled.
136)

The dc link supply for each full bridge converter is provided

separately, and this is typically achieved using diode rectifiers fed from
isolated secondary windings of a three-phase transformer. Phase-shifted
transformers can supply the cells in medium-voltage systems in order to
provide high power quality at the utility connection.
137)
138)
139) 4.2 Operation of CMLI.
140)

The converter topology is based on the series connection of

single-phase inverters with separate dc sources. The resulting phase voltage

is synthesized by the addition of the voltages generated by the diferent cells.
In a 3-level cascaded inverter each single-phase full-bridge inverter
generates three voltages at the output: +Vdc, 0, -Vdc (zero, positive dc
voltage, and negative dc voltage). This is made possible by connecting the
capacitors sequentially to the ac side via the power switches. The resulting
output ac voltage swings from -Vdc to +Vdc with three levels, -2Vdc to +2Vdc
with five-level and -3Vdc to +3Vdc with seven-level inverter. The staircase
waveform is nearly sinusoidal, even without filtering
141)
142)
143)

4.3 Features of CMLI

34

144)

For real power conversions, (ac to dc and dc to ac), the

cascaded-inverter needs separate dc sources. The structure of separate dc

sources is well suited for various renewable energy sources such as fuel cell,
photovoltaic, and biomass, etc. Connecting separated dc sources between
two converters in a back-to-back fashion is not possible because a short
circuit will be introduced when two back-to-back converters are not
switching synchronously. In summary, advantages and disadvantages of the
cascaded inverter based multilevel voltage source converter can be listed
below.
145)

146)

Fig 4.3: Cascaded H-Bridge multilevel inverter

35

147)

[Source: http://engineering.electrical-equipment.org]

148)
149)
150)

4.4 Advantages and Disadvantages of CMLI

151) Advantages
152)

i) The regulation of the DC buses is simple. Inverter Structure 30

153)

ii) Modularity of control can be achieved. Unlike the diode clamped

and capacitor clamped inverter where the individual phase legs must be
modulated by a central controller, the full-bridge inverters of a cascaded
structure can be modulated separately.
154)

iii) Requires the least number of components among all multilevel

converters to achieve the same number of voltage levels.

155)

iv) Soft-switching can be used in this structure to avoid bulky and

lossy resistor capacitor-diode snubbers.

156)
157)
158) 4.5 Disadvantages
159)

i) Communication between the full-bridges is required to achieve the

synchronization of reference and the carrier waveforms.

160)

ii) Needs separate dc sources for real power conversions, and thus its

applications are somewhat limited 2.4 Conclusion The aim of this chapter
has been to demonstrate the multilevel converter topologies.
161) 4.6 Conclusion

36

162)

In this chapter we have discussed about the operation,

advantages and disadvantages of cascaded h-bridge inverter in detail.

163)
164)
165)
166)
167)
168)
169)
170)
171)
172)
173)
174)
175)
176) CHAPTER-5
177) MATLAB SIMULINK
178)

5.1. Introduction to MATLAB:

179)

Developed by Math Works Inc., is a software package for high

performance numerical computation and visualization. The combination of

analysis capabilities, flexibility, reliability, and powerful graphics makes
MATLAB the premier software package for electrical engineers.

37

MATLAB

provides an interactive environment with hundreds of reliable and accurate

built-in mathematical functions. These functions provide solutions to a
broad range of mathematical problems including matrix algebra, complex
arithmetic,

linear

systems,

diferential

equations,

signal

processing,

optimization, nonlinear systems, and many other types of scientific

computations. The most important feature of MATLAB is its programming
capability, which is very easy to learn and to use, and which allows userdeveloped functions. It also allows access to Fortran algorithms and C codes
by means of external interfaces. There are several optional toolboxes written
for special applications such as signal processing, control systems design,
system identification, statistics, neural networks, fuzzy logic, symbolic
computations, and others. MATLAB has been enhanced by the very powerful
SIMULINK program. SIMULINK is a graphical mouse-driven program for the
simulation of dynamic systems. SIMULINK enables students to simulate
linear, as well as nonlinear, systems easily and efciently.
180) 5.2. Block diagram construction:
181)

At the MATLAB prompt, type SIMULINK. The SIMULINK

BLOCK LIBRARY, containing seven icons, and five pull-down menu heads,
appears. Each icon contains various components in the titled category. To
see the content of each category, double click on its icon. The easy-to-use
pull-down menus allow you to create a SIMULINK block diagram, or open an
existing file, perform the simulation, and make any medications. Basically,
one has to specify the model of the system (state space, discrete, transfer
functions, nonlinear odes, etc), the input (source) to the system, and where
the output (sink) of the simulation of the system will go. Generally when
building a model, design it first on the paper, then build it using the
computer. When you start putting the blocks together into a model, add the
blocks to the model window before adding the lines that connect them. This
way, you can reduce how often you need to open block libraries. Simulink is
a software package for modelling, simulating, and analyzing dynamical

38

systems. It supports linear and nonlinear systems, modelled in continuous

time, sampled time, or a hybrid of the two. Systems can also be multirate,
i.e., have diferent parts that are sampled or updated at diferent rates. For
modelling, Simulink provides a graphical user interface (GUI) for building
models as block diagrams, using click-and-drag mouse operations. With this
interface, you can draw the models just as you would with pencil and paper
(or as most textbooks depict them). Simulink includes a comprehensive
block library of sinks, sources, linear and nonlinear components, and
connectors. You can also customize and create your own blocks.

This

approach provides insight into how a model is organized and how its parts
interact. After you define a model, you can simulate it, using a choice of
integration methods, either from the Simulink menus or by entering
commands in MATLAB's command window. The menus are particularly
convenient for interactive work, while the command-line approach is very
useful for running a batch of simulations (for example, if you are doing
Monte Carlo simulations or want to sweep a parameter across a range of
values). Using scopes and other display blocks, you can see the simulation
results while the simulation is running. In addition, you can change
parameters and immediately see what happens, for "what if" exploration. The
simulation results can be put in the MATLAB workspace for post processing
and visualization. And because MATLAB and Simulink are integrated, you
can simulate, analyze, and revise your models in either environment at any
point.
182) 5.3. Using Simulink:
183)

To start a Simulink session, you'd need to bring up Matlab

program first. From Matlab command window, enter: >>simulink alternately,

you may click on the Simulink icon located on the toolbar as shown:

39

184)
185)
186)

Fig 5.1: figure showing Simulink Icon

Simulink's library browser window like one shown below will pop up

presenting the block set for model construction

40

187)

188)

Fig 5.2: Simulink library browser

189)

190)

To see the content of the block set, click on the "+" sign at the

beginning of each toolbox. To start a model click on the NEW FILE ICON as
shown in the screenshot above. Alternately, you may use keystrokes

41

CTRL+N. A new window will appear on the screen. You will be constructing
your model in this window. Also in this window the constructed model is
simulated. A screenshot of a typical working (model) window that looks like
one shown below:
191)

192)
193)

Fig 5.3: workspace to build model

To become familiarized with the structure and the

environment of Simulink, you are encouraged to explore the toolboxes and

scan their contents. You may not know what they are all about but perhaps
you could catch on the organization of these toolboxes according to the
category. For instant, you may see Control System Tool box to consist of the
Linear Time Invariant (LTI) system library and the MATLAB functions can be
found under Function and Tables of the Simulink main toolbox. A good way
to learn Simulink (or any computer program in general) is to practice and

42

explore. Making mistakes is a part of the learning curve. So, fear not, you
should be. A simple model is used here to introduce some basic features of
Simulink. Please follow the steps below to construct a simple model.
194)

STEP 1: CREATING BLOCKS

195)

From BLOCK SET CATEGORIES section of the SIMULINK

LIBRARY BROWSER window, click on the "+" sign next to the Simulink
group to expand the tree and select (click on) Sources

196)
197)

Fig 5.4: figure showing library blocks

43

198)

A set of blocks will appear in the BLOCKSET group. Click on

the Sine Wave block and drag it to the workspace window (also known as
model window).
199)
200)

201)
202)

Fig 5.5: How to build a model

203)
204)

Now you have established a source of your model.

205)

NOTE:
206)

It is advisable that you save your model at some point early on

so that if your PC crashes you don't lose so much time to reconstruct your
model. This is among the reasons why I prefer Linux or Unix! To save a
model, you may click on the floppy diskette icon or from FILE menu, select
Save or CTRL+S. All Simulink model file will have an extension ".mdl".
Simulink recognizes file with .mdlextension as a simulation model (similar to
how MATLAB recognizes files with the extension .m as an MFile). Continue
to build your model by adding more components (or blocks) to your model
window. We'll continue to add a Scope from Sinks library, an Integrator block

44

from Continuous library, and a Mux block from Signal Routing library.
NOTE: If you wish to locate a block knowing its name, you may enter the
name in the SEARCH WINDOW (at Find prompt) and Simulink will bring up
the specified block. To move the blocks around, simply click on it and drag it
to a desired location. Once all the blocks are dragged over to the work space
should consist of the following components:
207)

208)
209)

Fig 5.6: Modelling of simulink model

You may remove (delete) a block by simply clicking on it

once to turn on the "select mode" (with four corner boxes) and use the DEL
key or keys combination CTRL-X. STEP 2: MAKING CONNECTIONS

45

210)

To establish connections between the blocks, move the cursor

to the output port represented by ">" sign on the block. Once placed at a
port, the cursor will turn into a cross "+" enabling you to make connection
between blocks. To make a connection: left-click while holding down the
control key (on your keyboard) and drag from source port to a destination
port. The connected model is shown below.
211)

212)
213)

Fig 5.7: Simulink model of example one

A sine signal is generated by the Sine Wave block (a

source) and is displayed by the scope. The integrated sine signal is sent to
scope for display along with the original signal from the source via the Mux,
whose function is to mutiplex signals in form of scalar, vector, or matrix into
a bus.
214)

STEP 3: RUNNING SIMULATION

215)

You now can run the simulation of the simple system above by

clicking on the play button (alternatively, you may use key sequence CTRL+T,
or choose Start submenu under Simulation menu). Double click on the
Scope block to display of the scope.

46

216)

217)
218)

Fig 5.8: Scope

To view/edit the parameters, simply double click on the block of

interest.
219)

47

220)
221) 5.4 Handling of blocks and lines:
222)

The table below describes the actions and the corresponding

keystrokes or mouse operations (Windows versions).

223) Actions

224) Key

strokes

or

mouse

225) Copying a block from a library

actions
226) Drag the block to the model

with select menu

window with the left button on the

mouse OR use the COPY and PASTE
from EDIT
228) Hold down the CTRL key and

227) Duplicating blocks in a model

select the block with the left mouse

drag the block to a new location
229) Display block's parameters

230) Double click on the block

231) Flip a block

232)

CTRL-F

233)
234) Rotate a block

235)

CTRL-R

236) Changing blocks' names

237)

Click on block's label and

position the cursor to desired place

238)
239) Disconnecting a block

240) Hold down the SHIFT key and

drag the block to a new location

241) Drawing a diagonal line

242)

Hold down the SHIFT key

while dragging the mouse with the left

button
243)

48

244) Dividing a line

245)

Move the cursor to the line to

where you want to create the vertex

and use the left button on the mouse to
drag the while holding

down the

SHIFT key.
246)
247) 5.5 Annotations
248)

To add an annotation to your model, place the cursor at an

unoccupied area in your model window and double click (left button). A
small rectangular area will appear with a cursor prompting for your input. To
delete an annotation, hold down the SHIFT key while selecting the
annotation, then press the DELETE or BACKSPACE key. You may also
change font type and colour from the FORMAT menu.
249)
250)

5.6 SIMULINK EXAMPLES:

Example 2: Simulation of an Equation. In this example we will use

Simulink to model an equation. Let's consider

251)
252)

X(t)=Acos(t+)

where the displacement x is a function of time t, frequency w,

phase angle phi, and amplitude A. In this example the values for these
parameters are set as follows: frequency=5 rad/sec; phase=pi/2; A=2.
253)

where the displacement x is a function of time t, frequency w,

phase angle phi, and amplitude A. In this example the values for these
parameters are set as follows: frequency=5 rad/sec; phase=pi/2;A=2. 1.
From Simulink's library drag the following blocks to the Model Window
254)

49

255)

256)
257)

Fig 5.9: Simulink model of example 2

Double click on the blocks and enter the appropriate values as

prompted by the pop-up dialog windows. Note that the cosine function can
be selected from the pull-down menu in the pop-up window. In the
arrangement shown above, the input signal (a ramp function) is to be
displayed along with the output (displacement) via the use of the mux tool as
demonstrated earlier in this tutorial. To view the plots, double click on the
scope.
258)

3. Make sure all blocks are connected correctly then run the

simulation (CTRL+T). You may need to select the Auto scale button on the
scope display window to obtain a better display of the plots. You may find the
sinusoidal plots to be a bit "jaggy". You may want to improve the resolution
of the displayed plot by redefining the Max Step Side value ("auto" is set a
default value) in Simulation Parameters window (with keystrokes CTRL+E in
the model window). Just for fun, you may want to experiment with diferent
choice of solver. ODE45 is a default choice. You are encouraged to learn
more about the solver methods by checking out the help files in Matlab
command window. For instance, help ODE45 for parameters in non-stif
diferential equations. This example has demonstrated the use Simulink

50

with built-in mathematical functions and other supporting toolboxes to

simulate an equation. The same output/result can also be obtained with the
following set of instructions entered in Matlab command window: >>
t=(0:.01:10);A=2;phi=pi/2;omega=5;

>>xt=A*cos(omega*t+phi);

>>plot(t,xt);grid
259) 5.7 Conclusion:
260)

In this chapter we learnt the basics of MATLAB SIMULINK that

are how to start simulink and how to run simulation etc.. Next we will see
performance of UPFC by simulation process.

261)
262)
263)
264)
265)
266)
267)
268)
269) CHAPTER 6
270) MATLAB/SIMULINK MODELS
271)
272) 6.1 Introduction
273)
In this chapter we have designed a sinusoidal pulse width
modulation generator, 5-level Cascaded H-Bridge multi level inverter,
7-level Cascaded H-Bridge multi level inverter, 15-level Cascaded HBridge multi level inverter, 7-level star connected Cascaded H-Bridge
51

multi level inverter, and 15-level star connected Cascaded H-Bridge

multi level inverter.
274) 6.2 Circuit diagram of SPWM Generator
275)

276)
277)
278)

Fig 6.1: Sinusoidal pulse width modulation generator

279)
280) Circuit description:
281)
The above circuit consists of the following major
components: Sine wave, Repeating sequence, Addition/Subtraction block,
Relay, Mux and scope.

52

282)
Sine wave is used as a reference wave or the
modulating wave to achieve pulse width modulation. Amplitude of the sine
wave can be varied to vary the modulating index M i and frequency is set as
50 Hz which is same as the frequency of the output wave of the inverter.
Phase is set to be zero for a single phase multilevel inverter but in case of a
three phase or a multi phase inverter it is varied accordingly.
283)
Repeating sequence is a kind of signal generator
and it used to generate the carrier pulses i.e. the triangular pulses and
these triangular pulses are shifted accordingly by varying time values and
output values to achieve level shifting SPWM.
284)

285)
286)

Fig 5.2: Sine wave block in simulink

53

287)
288) Fig 6.3: Repeating sequence block
289)
290) Relay block returns the specified on or of value by comparing the
given input to given threshold. The on/of state of the relay is not afected
by input between the upper and lower limits.

291)
292) Fig 6.4: Relay block parameters
54

293)
294) 6.3 Circuit Diagram of various multilevel inverters
295)
296)

297) Fig 6.5: Five level Cascaded H-Bridge employing level shifting SPWM
298)
299)

55

300) Fig 6.6: Seven level Cascaded H-Bridge multilevel inverter.

301)
302)

303)
304) Fig 6.7: Fifteen level Cascaded H-Bridge multilevel inverter
305)
306)
307) Circuit description
308)
For a n level inverter the no of series connected bridges is (n1)/2. So a five level inverter consists of two full bridges connected in
series and voltage is measured across the two bridges, a seven level
inverter has 3 full bridges connected in series and a fifteen level inverter
has 7 bridges connected in series. For measuring the voltage we us a
56

voltage measurement block and for measuring the total harmonic

distortion we use the THD block. To observe the output voltage waveform
we use the Scope and to take a note of the total harmonic distortion we
use the display block. The inverter circuit for a same level multilevel
inverter remains the same for the various techniques but the pulse
generator subsystem varies accordingly.
309)
310) 6.4 Circuit diagram of 3 phase star connected Cascaded H-Bridge
multilevel inverters
311)
312)
313)

314)
315) Fig 6.8: Seven level 3 phase Star connected Cascaded H-Bridge
multilevel inverter
316)
317)

57

318)

319) Fig 6.9: Fifteen level 3-Phase Star connected Cascaded H-Bridge
multilevel inverter.
320)
321)
322) 6.5 Circuit description:
323) 3 Cascaded H-Bridge multilevel inverters are connected to a common
point forming a Star connection. The three inverters are at a phase
diference of 120 degree this is achieved by giving the phase in the sine
wave block to be 2*pi/3. The phase to neutral voltages are observed and
the THD block is used to measure the total harmonic distortion. The
three subsystems provide the gating pulses for the respective phases and
there is a phase diference of 120 degree between any two firing
networks.
324) DC Voltage Source
325) The DC Voltage Source block represents a constant
voltage source whose output voltage value is independent of the
current through the source.

58

326)
327) Fig 6.10: Dc voltage source block
328)
329) Configuration parameters:
330) The default solver needs to be modelled to observer the
high frequency carrier waves i.e. triangular waves.
331) The type of solver is variable step type and the solver is
ode23t (mod. Stif /Trapezoidal) and the Max step size is 1e-5 and Min
step size is 1e-6 and the relative tolerance of 1e-3.
332)

59

333)

334) Fig 6.11: Configuration parameters

335)
336) V-I Measurement box:
337)

The V-I measurement block is used to measure voltage and current in

volts and amperes in a designed circuit. This block outputs the voltage and currents
through scope.
338)

60

339)
340) Fig 6.12: Voltage measurement box
341)
342)
343)
344) Powergui Block
345) Environment block for Sim Power Systems models
346) Library
347) Powerlib
348) Description
349)

The Powergui block allows you to choose one of the

following methods to solve your circuit:

Continuous method, which uses a variable step Simulink solver

Ideal Switching continuous method

Discretization of the electrical system for a solution at fixed time steps

Phasor solution method

61

350)
351) The Powergui block is necessary for simulation of any
Simulink model containing Sim Power Systems blocks. It is used to
store the equivalent Simulink circuit that represents the state-space
equations of the model.
352)

You must follow these rules when using this block in a

model:

Place the Powergui block at the top level of diagram for optimal
performance. However, you can place it anywhere inside subsystems
for your convenience; its functionality will not be afected.

You can have a maximum of one Powergui block per model

You must name the block powergui

353) Graphical User Interface Tools
354) The Powergui block also gives you access to various
graphical user interface (GUI) tools and functions for the steady-state
analysis of Sim Power Systems models, the analysis of simulation
results, and for the design of advanced block parameters.
355) Dialog Box and Parameters of powergui
62

356)
357) Figure 6.13: Powergui block
358) Simulation and Configuration Options
359) To

specify

the

simulation

type,

parameters,

and

preferences, select Configure parameters in the Powergui dialog. This

opens another dialog box with the Powergui block parameters. This
dialog

box

contains

two

tabs,

Solver

and

Preferences.

The

configuration of the Solver tab depends on the option selected from

the Simulation type drop-down list.
360) Analysis Tools
361) Steady-State Voltages and Currents
362) Open the Steady-State Voltages and Currents Tool dialog
box that displays the steady-state voltages and currents of the model.
For more information, see the power steady state reference page.
63

363) Initial States Setting

364) Open the Initial States Setting Tool dialog box that allows
you to display and modify initial capacitor voltages and inductor
currents of the model. For more information, see the power initial
states reference page.
365) Load Flow and Machine Initialization
366) Open the Machine Load Flow Tool dialog box to perform
load flow and initialize three-phase networks containing three-phase
machines, so that the simulation starts in steady state. For more
information, see the power load flow reference page.
367) Use LTI Viewer
368) Open a window to generate the state-space model of your
system (if you have Control System Toolbox software installed) and
automatically open the LTI Viewer interface for time and frequency
domain responses. For more information, see the power view reference
page.
369)
370) Impedance Vs Frequency Measurement
371) Open the Impedance vs Frequency Measurement Tool
dialog box to display the impedance versus frequency defined by the
Impedance Measurement blocks. For more information, see the power
Z meter reference page.
372) FFT Analysis

64

373) Open the FFT Analysis Tool dialog box to perform Fourier
analysis of signals stored in a Structure with Time format. For more
information, see the power FFT scope reference page.
374) An example of using the FFT Analysis tool is described in
Performing Harmonic Analysis Using the FFT Tool.
375) Generate Report
376) Open the Generate Report Tool dialog box that allows you
to generate a report of steady state variables, initial states, and
machine load flow for a model. For more information, see the power
report reference page.
377) Hysteresis Design Tool
378) Open a window to design a hysteresis characteristic for
the saturable core of the Saturable Transformer block and the ThreePhase Transformer blocks (two- and three-windings). For more
information, see the power hysteresis reference page.
379) Compute RLC Line Parameters
380) Open a window to compute RLC parameters of overhead
transmission line from its conductor characteristics and tower
geometry. For more information, see the power line parameters
reference page.
381) 6.6 Conclusion
382) As MATLAB clears practical environment, we can achieve
desired result by keeping components in proper way. Suppose
component/device is to be tested then its not required to buy that
65

particular rating component. Simply one can use MATLAB. In that

way in this project, for level shifting PWM inverter modeling is done
and harmonics are analyzed.
383)
384) CHAPTER 7
385) SIMULATION RESULTS
386) Output on scope:
387) Output of a five level Cascaded H-Bridge multilevel
inverter:
388)

389) Fig 7.1: output on scope for 5 level inverter employing

Phase Disposition modulation

66

390)

391) Fig 7.2: output on scope for 5 level inverter employing

Phase Opposition Disposition modulation
392)
393)

67

394)

395) Fig 7.3: output on scope for 5 level inverter employing

Alternate Phase Opposition Disposition modulation
396)
397)
398) Output of a seven level Cascaded H-Bridge multilevel
inverter:
399)

68

400)

401) Fig 7.4: output on scope for 7 level inverter employing

Phase Disposition modulation

69

402)

403) Fig 7.5: output on scope for 7 level inverter employing

Phase Opposition Disposition modulation

70

404)

405) Fig 7.6: output on scope for 7 level inverter employing

Alternate Phase Opposition Disposition modulation
406)
407)
408)
409) Output of a fifteen level Cascaded H-Bridge multilevel
inverter:

71

410)

411) Fig 7.7: output on scope for 15 level inverter employing

Phase Disposition modulation
412)

72

413)

414) Fig 7.8: output on scope for 15 level inverter employing

Phase Opposition Disposition modulation
415)
416)

73

417)

418) Fig 7.9: output on scope for fifteen level inverter

employing Alternate Phase Opposition Disposition modulation
419) Output of 3 phase star connected seven level
Cascaded H-Bridge multilevel inverter

74

420)

421) Fig 7.10: Output on scope of a 3 phase star connected

seven level Cascaded H-Bridge multilevel inverter
422)
423)
424) Output of 3 phase star connected fifteen level
Cascaded H-Bridge multilevel inverter

75

425)

426) Fig 7.11: Output on scope of a 3 phase star connected

fifteen level Cascaded H-Bridge multilevel inverter
427) Comparative analysis of single phase inverters:
428) Modulating index:
429) The modulation index of a modulation scheme describes
by how much the modulated variable of the carrier signal varies
around its un modulated level.
430) In multilevel inverters, the amplitude modulation index
(Ma) is the ratio of reference amplitude (Am) to carrier amplitude (Ac).

76

431)
432)

Ma=

Am
( m1 ) Ac

433)
434) The frequency ratio (Mf) is ratio of carrier frequency (f c) to
reference frequency (fm).
435)

Mf =

fc
fm

436)
437) Mod

438) Phas

439) Phas

440) Alter

ulating

nate Phase

index

Disposition

Opposition

Opposition

441) Mi=0

442) 0.27

Disposition
443) 0.26

Disposition
444) 0.26

.5
445) Mi=0

43
446) 0.21

97
448) 0.20

65
449) 0.19

.6

79

92

85

450) Mi=0

447)
451) 0.21

453) 0.19

454) 0.21

.7

91

81

84

452)
455) Table 7.1: comparison of total harmonic distortion for a 5
level Cascaded H-Bridge multilevel inverter
456)
457) Mod

458) Phas

459) Phas

460) Alter

ulating

nate Phase

77

index

Disposition

Opposition

Opposition

461) Mi=0

462) 0.17

Disposition
463) 0.16

Disposition
464) 0.18

.5
465) Mi=0

89
466) 0.15

468) 0.16

47
469) 0.14

.6

12

13

67

470) Mi=0

467)
471) 0.19

473) 0.19

474) 0.17

.7

57

57

61

472)
475) Table 7.2: comparison of total harmonic distortion for a 7
level Cascaded H-Bridge multilevel inverter
476)
477)
478)
479) Mod

480) Phas

482) Phas

484) Alter

ulating

nate Phase

index

Disposition

Opposition

Opposition

481) (PDM

Disposition

Disposition

483) (POD

(APODM)

485) Mi=0

486) 0.08

M)
487) 0.08

488) 0.09

.5
489) Mi=0

254
490) 0.08

267
492) 0.08

418
493) 0.09

.6

547

933

748

494) Mi=0

491)
495) 0.13

497) 0.13

498) 0.12

.7

65

66

28

78

496)
499) Table 7.3: comparison of total harmonic distortion for a
15 level Cascaded H-Bridge multilevel inverter
500) Comparative analysis of three phase multilevel inverters
501)
502) Mod

503) R-

504) Y-

505) B-

ulating

phase

phase

phase

index
506) Mi=0.

507) 0.18

508) 0.17

509) 3.88

5
510) Mi=0.

47
511) 0.14

69
512) 0.15

e+006
513) 6.18

6
514) Mi=0.

67
515) 0.17

87
516) 0.17

2e+006
517) 5.44

6
43
7e+006
518) Table 7.4: THD of 3 phase Star connected 7 level inverter
employing APOD
519)

520) Mod

521) R-

522) Y-

523) B-

ulating

phase

phase

phase

index
524) Mi=0.

525) 0.16

526) 0.18

527) 0.18

5
528) Mi=0.

529) 0.16

93
530) 0.15

93
531) 0.15

6
532) Mi=0.

13
533) 0.19

12
534) 0.16

11
535) 0.16

57
13
14
536) Table 7.5: THD of 3 phase Star connected 7 level inverter
employing POD

537) Mod

538) R-

539) Y-

540) B-

ulating

phase

phase

phase

index
541) Mi=0.

542) 0.17

543) 0.18

544) 0.18

5
545) Mi=0.

89
546) 0.15

28
547) 0.15

24
548) 0.15

12

68

69

79

549) Mi=0.
7

550) 0.17

551) 0.17

552) 0.17

44
78
79
553) Table 7.6: THD of 3 phase Star connected 7 level inverter
employing PD
554)
555)
556)
557)

558) Mod

559) R-

560) Y-

561) B-

ulating

phase

phase

phase

index
562) Mi=0.

563) 0.08

564) 0.07

565) 0.07

5
566) Mi=0.

254
567) 0.08

765
568) 0.09

773
569) 0.09

6
570) Mi=0.

547
571) 0.13

66
572) 0.14

675
573) 0.14

65
27
28
574) Table 7.7: THD of 3 phase Star connected 15 level inverter
employing PD
575)

576) Mod

577) R-

578) Y-

579) B-

ulating

phase

phase

phase

index
580) Mi=0.

581) 0.08

582) 0.08

583) 0.08

5
584) Mi=0.

268
585) 0.08

111
586) 0.09

125
587) 0.09

6
588) Mi=0.

932
589) 0.13

501
590) 0.14

518
591) 0.14

66
47
49
592) Table 7.7: THD of 3 phase Star connected 15 level inverter
employing POD
593)

594) Mod

595) R-

596) Y-

597) B-

ulating

phase

phase

phase

index
80

598) Mi=0.

599) 0.09

600) 0.06

601) 0.06

5
602) Mi=0.

419
603) 0.09

77
604) 0.09

77
605) 0.09

6
606) Mi=0.

749
607) 0.12

605
608) 0.14

62
609) 0.14

28

63

64

610)
611) Table 7.7: THD of 3 phase Star connected 15 level inverter
employing APOD
612)
613)
614)
615)
616)
617)
618)
619)
620)
621)
622)
623)
624)
625) Conclusion
626) In this project we have analyzed the total harmonic
distortion of Cascaded H-Bridge multilevel inverter by varying the
modulation index. This analysis is done on 5 level Cascaded H-Bridge
81

Multilevel inverter, 7 level Cascaded H-Bridge Multilevel inverter, 15

level

Cascaded

H-Bridge

Multilevel

inverter,

Three

phase

star

connected 7 level Cascaded H-Bridge Multilevel inverter and Three

phase star connected 15 level Cascaded H-Bridge Multilevel inverter
and in the case of three phase inverters the analysis is done on phase
to neutral voltages.
627)
628) Future scope
629) The major disadvantage of Cascaded H-Bridge multilevel
inverters is that the switching losses are high. To overcome this
disadvantage we use modular multilevel inverters. Modular multilevel
inverters consists of several cells in parallel and higher order cells are
turned on only in the need of high voltages.
630)
631)
632)
633)
634)
635)
636)
637)
638)
639)
82

640)
641)
642)
643)
644)
645)
646)
647)
648)
649)
650)
651)

83