M.Sc.

Electronics and Communications

First Year
(Non semester)
Paper 4
Microprocessors and Microcontroller

Dear student,
You

are

welcome

to

the

M.Sc.Electronics

and

Communications

(Non-semester)

course

through

Distance

mode

offered by of our University. You

Microprocessors

have

and

Microcontroller as one of the theory

papers.

We

request

you

to

go

through the study materials which

were

prepared

by

experts

in

the

respective fields. In addition to these

study

materials

opportunities

to

you

have

acquire

further

information in the contact sessions.

With best wishes
Directorate of Distance Education

CONTENTS
UNITS

Title

UNIT

MICROPROCESSOR

1:

ARCHITECTURE

UNIT

8085

2:

PERIPHERALS

UNIT

8086

SYSTEM COMPONENTS

UNIT

8086 INTERFACING AND 8051

ARCHITECTURE

UNIT

8051

PROGRAMMING.

8085

INTERRUPTS

AND

ARCHITECTURE

AND

SYSTEM

DESIGN

AND

Lesson materials prepared by

Mr. K. Arun Venkatesh
University

Science

Instrumentation Centre
Madurai Kamaraj University
Madurai 625021.

Syllabus
M.Sc.(Electronics and
Communications) Non Semester
Paper 4 Microprocessors and
Microcontroller

UNIT I 8085 Microprocessor

internal

Architecture:

8085

architecture,

instruction

format,

addressing modes, instruction set,

stacks, subroutines, programming
examples, pins and signals, various
machine cycles, timing diagrams,
estimation

of

execution

times.

parallel I/O: Memory interfacing, I/

O

interfacing,

memory

decoding

mapped

I/O,

circuits,
I/O

Data

Transfer schemes: programmed I/

O.

UNIT II
Interrupt
Interrupt

structure
driven

in

I/O,

8085,
DMA

principles. Peripheral interfacing :

Internal

blocks,

operation,

pins

signals,

interfacing,

and

application examples for 8255PPI,

8253 Timer / Counter, 8289APIC,
8237 DMA controller. Interfacing
matrix
ADC,

keyboard,
DAC.

Serial

concepts,
communcation,

switches,
I/O

LED,
Basic

Asychronous
communication

through SID and SOD lines, 8251

USART Interfaing, examples.

UNIT

III

8086

Microprocessor
8086

family,

Architecture,

8086

Internal

Addressing

modes,

8086 Instruction set, assemblers,

programming examples, procedures
and passing parameters between
proceducers. 8086 pins and signals,
bus

cycles,

mode

minimum/Maximum

operation,

8086

based

system design: System components

bus controller, clock generator,
address
and
devices,

decoding,

bus

demultiplexing,
memory

memory interfacing.

buffering
Memory
controller,

UNIT IV
I/O

interfacing,

Interfaing

peripheral I/O devices and matrix

keyboard, stepper motor, DAC and
ADC interfaing. 8086 interrupts
Interrupt

types,

response,

procedures, and applications; DMA

principles;

UART

interfacing,

NS16550D

programming

and

applications.

Advanced microprocessors
Protected mode operation. Virtual
memory,

Mulitasking,

Special

features and overviews of 80286,

80486,
pentium

Pentium,
Pro,

Pentium

Pentium

Pentium IV processors.

MMX,
II

and

Microcontroller Intel 8051 :

Architecture hardware features,
registers,

I/O

ports,

external

memory, counter and timers, serial

I/O, interrrupts.

UNIT V
8051

Programming

set,

addressing

transfer,

Instruction

modes,

logical,

data

arithmetic

operations, jump/call instructions,

interrupt handlet.
8051 system : System design &
testing,

generating

software

and

hardware time delays,. look up

tables,

Serial

configurations,

communication
modes

programs.

Interrupt

Programming

interrupts,
interrupts,

External
serial

Timer

hardware

communication

interrrupts. 8051 programming in

C.

Text books :
1.

Ramesh

S.

Gaonkar,

Microprocessor
Programming

Architecture,
and

Applications

with the 8085.

2.

N. Mathivanan, Microprocessors,
PC

Hardware

and

Interfacing

PHI, 2005.
3.

Muhammad
Gillispie

All

2001.

Janice

The

8051

Mazidi,

microcontroller
systems,

Mazidi,

and

Pearson

embedded
education,

4.

Kenneth

J.

Ayala,

The

8051

Microcontroller Archietecture,
Programming & Applications, II
Ed., Penram International, 1996.
5.

P.S.

Manoharan, P.S.

Microcontroller
design,

based

SClTECH,

Kannan,
systen

Hyderabad,

(2005).

Reference books :
1.

D.V. Hall, Microprocessors and

Interfaing

Programming

and

Hardware, II Ed., McGraw Hill,

1999.
2.

Bary

B.

Brey,

Microprocessors

The

INTEL

8086/8088,

80186/80188,
80486,

80286,

pentium,

and

80386,
Pentium

Proprocessors, IV Ed., PHI, 2002

3.

Kenneth

J.

Ayala,

8086

Microprocessor, Programming &

Interfaing

the

PC,

International, 1995.

Penram

UNIT I
MICROPROCESSOR 8085
ARCHITECTURE
A microprocessor is a multipurpose,
programmable,

clock

driven,

register-based electronic device that

reads

binary

storage

instructions,

device

called

from

memory,

accepts binary data as input and

processes data according to those
instructions, and provides results as
output. The data manipulation and
communication is determined by the
logic design of the microprocessor,
which is called the Architecture. The
operations of the microprocessor can
be

divided

categories:

into

three

main

1.

Microprocessor

initiated

operations,
2.

Internal operations, and

3.

Peripheral or externally initiated

operations.

The microprocessor 8085 is an 8-bit

microprocessor i.e., it can accept an
8-bit binary data, manipulate it, and
gives an output.
Microprocessor 8085 bus structure
The 8085 microprocessor performs
all the input and output operations
through a set of lines called the bus.
The

microprocessor

following functions,

performs

the

1.

Memory Read: Reads the data

from the memory.

2.

Memory Write: Writes data into

the memory.

3.

I/O Read: Reads data from an

Input device such as a keyboard.

4.

I/O Write: Writes data to an

Output device such as a LCD
display.

To perform all these functions the

microprocessor uses three sets of
communication lines or buses, the
address bus, the data bus, and the
control bus.

The Address bus

The

microprocessor

8085

has

16

address lines and can address up to

64K memory locations (1K = 1024
bytes). (Each peripheral is identified
by

binary

number

called

the

address). The address bus of the

8085 microprocessor is unidirectional
(from microprocessor to peripherals).

The Data bus

The data bus is a group of eight lines
used

for

transferring

data

from

memory to the microprocessor and

vice versa. Thus the microprocessor
has

bi-directional

data

bus

permitting data flow from in and out.

Since the microprocessor 8085 is an
8-bit microprocessor, the width of the
data bus is also eight.

The control bus

The control bus comprises of signals,
which

are

synchronizing

used
the

for

carrying

microprocessor

with the peripherals. These control

signals provide the necessary timing
signal vital to the operations of the
peripherals.

Figure 1.1:CPU registers of 8085

Registers of 8085
The

microprocessor,

various

operations

temporary

to

perform

requires

programmable

some

storage

locations and the locations are called

Registers.
present

These

inside

the

registers

are

microprocessor

and can be used either as a storage

location or a programmable location
i.e., can be used by the programmer
to do arithmetic or logical operation.
The

microprocessor

has

six

8-bit

registers and are identified as B, C,

D, E, H, L, and these registers can be
combined as register pairs BC, DE,
and HL to perform 16-bit operations.

Apart

from

these

general

purpose

registers the microprocessor includes

an Accumulator, a Flag register, a
Program

counter,

and

Stack

pointer.

Accumulator
The accumulator is an 8-bit register,
which is also a part of the Arithmetic
and Logic Unit (ALU). Most of the
arithmetic

and

logical

operations

includes the accumulator as one of

the operands i.e., one data should be
stored in the accumulator and result
is stored in the accumulator.

Flag
There are five flip-flops, which are
used to indicate the status of the
result and collectively called as the
Flag register. The flip-flops are set
or reset according to the result. The
accumulator

and

flag

register

collectively called as the Program

Status Word (PSW). The five flags
are Zero (Z), Carry (CY), Sign (S),
Parity (P), and Auxiliary Carry (AC).
The register structure is given in the
figure (1.1).

D7

D6

D5

D4

AC

D3

D2

D1

D0

CY

Program Counter (Pc)

The

program

counter

is

16-bit

register, which stores the address of

the location from where the next
instruction

is

to

be

fetched

and

executed. It sequences the execution

of instructions and the content of the
program counter cannot be altered
by the programmer directly. But by
using some instructions like JUMP,
CALL,

etc.,

the

programmer

can

change the sequence of the program.

Stack Pointer (Sp)

The Stack is a temporary memory
location, which is used for storing
data during execution.

The stack is also

In

first

stack

will

Out

called

as

memory

i.e.,

last
the

point towards the lastly

stored data. The Stack Pointer is a

16-bit register and points the stored
data.

1.2. lnstruction set

An instruction is a binary pattern
designed inside the microprocessor
to perform specific task. The entire
group

of

instructions

is

called

instruction set. The instruction set of

the microprocessor can be divided
into five categories according to the
operations,

viz.,

arithmetic,

logical,

data

transfer,

branching,

machine control operations.

and

Each instruction
the operation

has
code

two
and

parts,
operand.

The operand may be a register, a

memory location, or an 8-bit or 16
bit

data

address.

instructions,

the

In

some

opcode

itself

represents the operand and in some

instructions
represented

the
by

operand
second

is

byte

or

word. Then those instructions will be

two and three byte instructions.

Data Transfer Instructions

The data transfer instructions copy
the data from one location to another
location.

The

data

instructions

are

divided

transfer
into

four

types, between registers, specific data

byte to a register or a location,

between

register

and

memory

location, and between I/O devices

and accumulator.
MOV
Rd,Rs

ruction
Copies the data from the source
CPU

register

Rs

to

destination

register Rd.

MOV

Copies the data from the memory

R, M

location M to the CPU register R.

The memory location is pointed
by the HL pair register.

MOV

Copies the data from the CPU

M, R

register R to the memory location

pointed by the HL register pair.

LDAX

Accumulator

Rp

instruction

Direct:

one

byte

Copies the data byte from the

memory location specified in the
register

pair

Rp.

may be BC and DE.

Register

pair

STAX
Rp

direct: one byte instruction

Copies the data byte from the
accumulator

to

the

memory

location specified in the register

pair BC or DE

MVI

Move

R,

instruction

8-bit

Immediate:

two

byte

Load the CPU register R with an

8-bit immediate value.

OUT

Output

8-bit

instruction

Sends

to

the

port:

two

contents

byte

of

the

accumulator to the output port

specified by the 8-bit address.

IN

Input

8-bit

instruction
Reads

from

from

port:

two

byte

the

input

port

specified by the 8-bit address and

copies to the accumulator

LXI

Load

register

pair

Immediate:

Rp,

three byte instruction Copies the

16-bit

16-bit data to the register pair

Rp.

LDA

Load Accumulator Direct: three

16-bit

byte instruction
Copies the data byte from the
memory location specified by the
16-bit

address

to

the

accumulator.

STA

Store Accumulator Direct: three

16-bit

byte instruction

Copies the data byte from the

accumulator

to

the

memory

location specified by the 16-bit

address.

Arithmetic Instructions
The 8085 microprocessor is capable of
performing

various

functions such as, addition,

arithmetic

subtraction,
decrement.

increment,
For

the

and

addition

and

subtraction one of the operands must

be in the accumulator.

ADD
R

Add: one byte instruction

Adds

the

contents

of

the

accumulator with the contents of

the CPU register R and the result
is stored in accumulator

ADI

Add

8-bit

instruction
Adds

Immediate:

the

two

contents

byte

of

the

accumulator with 8-bit data and

the

result

is

stored

in

the

accumulator

SUB
R

Subtract: one byte instruction

Subtracts

the

contents

of

the

register R from the contents of

the accumulator and the result is
stored in the accumulator.

SUI

Subtract

Immediate:

8-bit

instruction

two

byte

Subtracts the 8-bit data from the

contents of the accumulator and
the

result

is

stored

in

the

accumulator.

ADD
M

Add memory: one byte instruction

Adds the contents of the memory
location

pointed

to

register

pair

Rp

to

the

the

result

is

accumulator

and

by

the

HL

stored in the accumulator.

SUB

Subtract

instruction
Subtracts

memory:

the

one

contents

byte

of

the

memory location pointed to by the

HL

register

pair

Rp

from

the

accumulator.
INR R

Increment: one byte instruction

Increases

the

contents

register R by one.

of

the

DCR
R

Decrement: one byte instruction

Decreases

the

contents

of

the

register R by one.

INX

Increment register pair: one byte

Rp

instruction
Increases

the

contents

of

the

register pair Rp by one

DCX

Decrement register pair: one byte

Rp

instruction
Decreases

the

contents

of

the

register pair Rp by one.

INR

Increment

instruction
Increases

memory:

the

one

contents

byte

of

the

memory location pointed to by the

HL register pair HL by one.

DCRM

Decrement

memory:

one

byte

instruction
Decreases

the

contents

of

the

memory location pointed to by the

HL pair by one

Programming example 1.1:

Statement:
language

To

write

program

an
to

assembly
add

two

numbers and output the result in the

output port 10H. To add any two
numbers the accumulator A should
have one of the operands i.e., one of
the numbers. So, one of the numbers
must be loaded into the accumulator
and the other number can be loaded
into any of the CPU registers such as
B. The contents of the registers are
added with the instruction ADD and
the

result

in

the

accumulator

is

moved to the output port by OUT

instruction.

The

program

opcodes is given below.

with

the

MVI A,
A0H

3E

loads accumulator with I

data

AO

MVI B,
4FH

06

loads B with II data

4F

ADD B

OUT
10H

HLT

80

D3

Adds B to A

stores

the

result

accumulator in port

10

10H

76

Stop

in

Logical instructions
The

microprocessor

8085

can

perform logical functions tike AND,

OR,

EX-OR,

NOT

(complement),

compare and rotate. For every such

function one of the operands must be
in the accumulator.

ANA
R/M

AND: one byte instruction

Logically AND the contents of the
register

or

memory

location

pointed to by the HL pair with the

contents of the accumulator

ANI

AND

Immediate:

8-bit

instruction

two

byte

Logically AND the 8-bit immediate

data byte with the contents of the
accumulator.

ORA
R/M

OR: one byte instruction

Logically OR the contents of the
register

or

memory

location

pointed to by the HL pair with the

contents of the accumulator.

ORI

OR

Immediate:

8-bit

instruction

two

byte

Logically OR the 8-bit immediate

data byte with the contents of the
accumulator.

XRA
R/M

Exclusive-OR: one byte instruction

Logically

Exclusive-OR

the

contents of the register or memory

location pointed to by the HL pair
with

the

contents

of

the

accumulator.
XRI

Exclusive-OR Immediate: two byte

8-bit

instruction
Logically
immediate

Exclusive-OR
data

byte

the
with

contents of the accumulator.

8-bit
the

CMA

Complement

Accumulator:

one

byte instruction
Complement the contents of the
accumulator

and

the

result

is

stored in the accumulator itself.

RLC

Rotate

Left

without

Carry:

one

byte instruction
Rotates each bit of the contents of
the accumulator to the left without
carry.

RAL

Rotate

Accumulator

Left

with

carry: one byte instruction

Rotates each bit of the contents
of the accumulator to the left with
carry.

RRC

Rotate Right without Carry: one

byte instruction
Rotates each bit of the contents
of the accumulator to the right
without carry.

RAR

Rotate

Accumulator

Right

with

carry: one byte instruction

Rotates each bit of the contents of
the accumulator to the right with
carry.
CMP

Compares

R/M

register

the

contents

or

memory

of

the

location

pointed to by the HL pair with the

accumulator for less than, equal to
or more than.

CPI

Compares the 8-bit data byte with

8-bit

the

accumulator

for

less

than,

equal to, or more than.

Programming example 1.2:

Statement: To write a program to
logically OR two numbers and output
the result through a display device
connected to the microprocessor at
the address 88H. At first, as a rule
one operand must be loaded to the

microprocessor

and

is

ORed

logically

accumulator
ORI.

The

output

with
resultis

port

as

other

the

number

with

the

instruction

moved

to

in the example 1.

The program is given below.

MVI A,
45H

3E

loads accumulator with I

data

45

ORI B,
10H

F6

Logically ORs the II data

10

OUT
88H

D3

88

HLT

76

stores

the

result

accumulator in port

88H

the

in

In

this

program,

the

II

data

is

manipulated with the OR Immediate

instruction thus reducing the no of
instructions in the program than the
example 1.1.

Branch Instructions
The microprocessor is a sequential
machine i.e., it executes instructions
from one location to the next. The
branch

instructions

changes

the

course of the program sequence of

the

microprocessor.

The

branch

instructions may be conditional or

unconditional.

The

branch

instructions are classified into three

viz., Jump, Call and Return, and
Restart instructions.

JMP

Unconditional Jump: three byte

16-bit

instruction

address

The

microprocessor

jumps

unconditionally to the memory

location specified by the 16-bit
address.

JZ
16-bit

e byte instruction
The

microprocessor

jumps

to

the memory location specified

by the 16-bit address only when
the zero flag is set to one.

JNZ
16-bit

three byte instruction

The

microprocessor

jumps

to

the memory location specified

by the 16-bit address only when
the zero flag is reset to zero.

JC
16-bit

ee byte instruction
The

microprocessor

jumps

to

the memory location specified

by the 16-bit address only when
the carry flag is set to one.

JNC 16-bit

: three byte instruction

The

microprocessor

jumps

to

the memory location specified

by the 16-bit address only when
the carry flag is reset to zero

CALL
16-bit

ee byte instruction
The

program

sequence

is

changed to the location of a

subroutine

specified

by

the

16-bit address. On reading the

CALL

instruction,

microprocessor

the

stores

the

content of the program counter

in the stack and replaces it with
the 16-bit address.

RET

utine: one byte instruction

On reading this instruction, the
microprocessor
address

from

gets
the

back
stack

the
and

loads it in the program counter.

RST

instruction
These instructions are software
reset

operations.

instruction

the

On

reading

microprocessor

jumps to one of the vectored

locations on page 00H.

Programming example1.3
Statement: To write an assembly
language

program

to

add

two

numbers and output the result in the

output port 55H and if the result
exceeds

eight

bits,

01H

must

be

written to output port 56H. At first

the

data

is

stored

to

the

accumulator A and II data is added

with the accumulator A. If the result
exceeds 8-bits, the carry flag in the
flag register will be set. By checking
the carry flag by JNC instruction, 01H
will be written to the output port
56H. The program is given below.

MEMORY
ADDRESS

8000

LABEL

MNEMONICS

OPCODE

COMMENTS

MVI A, 22H

3E

Loads

8001

8002

22

ADI 99H

8003

8004

C6

accumulator
with I data

Adds the II
data

99

JNC LOOP

D2

Jumps

to

loop if carry
8005

0C

is

set

by

addition

or

next
instruction
8006

80

will

be

executed

Stores
8007

MOV C, A

4F

result

the
in

temporarily

8008

8009

MVI A, 01H

3E

Moves
to A

01H

800A

01

Outputs the
800B

OUT 56

D3

data to port
56H

800C

56

Gets
800D

MOV A, C

79

the

back
result

form C

800E

LOOP:

OUT 55H

D3

Stores

the

result

in

accumulator
in port 88H

800F

55

8010

The

HLT

example

complete

76

program

format

language program.

of

an

Stop

shows

the

assembly

Machine Control Instructions

HLT

HALT: one byte instruction

On reading this, the microprocessor
stops processing and wait.

NOP

No Operation: one byte instruction

The

microprocessor

does

not

perform any operation and is used

for providing software delay.

1.3. ADDRESSING MODES

The operands in an instruction can be
a register, a memory location, or a
immediate data. The formats used to
represent these operands are called
as

addressing

instruction

set

modes.
has

addressing modes,

the

The

8085

following

1.

Immediate addressing One of

the operands is an immediate
data byte, MVI A,#30H.

2.

Register addressing MOV B, A.

The

data

transfer

is

between

registers.
3.

Direct addressing IN 10H. The

memory

location's

address

is

specified directly.
4.

indirect addressing MOV A, M.

The

address

of

the

memory

location M is represented by HL
register pair.






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stack pointer is always loaded with

the

maximum

possible

address

to

avoid violation with other data. The

stack is both accessible to the user
and the microprocessor. Some of the
peculiar type of instructions that uses
the stack are given below.

PUSH
Rp

Store register pair in stack

Stores the content of the register
pair Rp in the stack and content of
the stack pointer is decremented
by two. Rp may be BC, DE, HL and
PSW.

POP
Rp

Retrieve register pair from stack

Copies the 16-bit data from the
memory location pointed to by the
SP and stores in the register pair
Rp. The contents of the SP is
incremented by two.

If a 16-bit data is stored in the stack

the

least

significant

byte

LSB

is

stored in the current location pointed

by SP and the SP is decremented
by one and the most significant byte
(MSB) is stored in the location. For
example, let us assume that SP is
holding 9FFFH as the starting address
of the stack and the contents of the
B and C registers are 32 and 45
respectively.

On

instruction

PUSH

reading

the

B,

the

microprocessor stores the contents of

the C register which is the LSB, to the
location

9FFFH.

Then

SP

is

decremented by one and the contents

of the register B is stored in the

location 9FFEH. While retrieving the

data, the stack retrieves by Last In
First Out. The data in the location
9FFEH is retrieved first and data in
9FFFH next. The CALL instruction also
uses the stack to store the return
address

of

the

program

before

jumping to the subroutine.

Subroutine
A

subroutine

instructions

is
that

group

are

of

written

separately from the main program to

perform

function

that

occurs

repeatedly in a program. For example

generating a multiplication table with
the microprocessor needs one

multiplying

program,

which

occurs

repeatedly for so many times. This

simple program is written separately
from the main program and is called
whenever

required.

CALL

instruction sis used to jump to a

subroutine

and

RET

instruction

is

used to jump top main program.

On reading the CALL instruction the
microprocessor stores the content of
the program counter in the stack and
the stack pointer is decremented by
two. The program counter will have
the address of the next instruction
to be executed. The microprocessor
jumps to the subroutine by storing

the address of the subroutine in the

program counter. On reading the RET
instruction,

the

microprocessor

retrieves the address that has been

stored in the stack and loads the
address to the program counter.

Programming example 1.4

Statement: To write an assembly
language

program

to

add

two

numbers with 30H and rotate to right

once and output to display devices
connected

at

20H

and

21H.

The

addition and rotation functions are

performed

by

ADI

and

RRC

instructions and are written as a

subroutine

ended

by

RET

instruction. The subroutine is caned

by the CALL instruction by the main
program.

MEMORY
ADDRESS

8100

LABEL

MNEMONICS

OPCODE

COMMENTS

MVI A, 02H

3E

Loads

the

accumulator
with
8101

8102

02

CALL SUB

CD

8103

00

8104

82

the

data

Calls

the

subroutine

After
8105

OUT 20H

D3

returning
form

subroutine,
8106

20

outputs
data to port
20H

8107

MVI A, 03H

8108

3E

Loads the II
data

03

Calls
8109

CALL SUB

CD

the

subroutine
again

810A

00

810B

82

After
810C

OUT 21H

D3

returning,
outputs
data to 21H

810D

21

810E

8200

SUB:

HLT

76

Stop

ADI 30H

C6

Subroutine

30

starts: adds
30H

to

accumulator

Rotates
8202

RRC

0F

accumulator
without
carry

Return
8203

RET

C9

main
program

to

To understand the functions of the

microprocessor,

it

is

essential

to

know the pins and signals and the

timing

of

communication

in

signals.

1.5 PINS AND SIGNALS

Figure 1.2: Pin-out diagram of 8085

these

The microprocessor 8085A is a 40 pin

device, operates with a 3-MHz single
phase clock at + 5 V power supply.
Another

microprocessor

8085A-2

version can operate with 5 MHz clock.

The

signals

of

the

8085

microprocessor can be divided into

six categories:
1.

Address bus,

2.

Data bus,

3.

Control and Status signals,

4.

Power and Frequency signals,

5.

Externally Initiated signals,

6.

Serial I/O ports.

Address Bus
The

8085

microprocessor

has

16

address lines (A 0 to A 15 ). The least

significant byte of the address lines
(A 0 to A 7 ) is multiplexed with the
data bus i.e., the lines hold the
address

at

the

first

part

of

the

machine cycle and data for the rest.

The most significant byte (A 8 to A 15 )
is unidirectional.

Data Bus
The 8085 have 8 data lines (D0 to
D7) and are multiplexed with the low
order address lines. The data bus is a
bi-directional bus and it can move

data to and fro the microprocessor.

The

multiplexed

address

and

data

bus is collectively called as AD 0 to

AD 7 .

Control And Status Signals

The

control

signals

are

used

to

synchronize the peripherals with the

microprocessor.

There

are

two

control signals viz., RD and WR and

three status signals viz.,IO/M S 1 , and

S 0 and one special signal ALE.

RD (Read): This signal indicates that

the microprocessor is reading a data
from the memory or an input device.
This is active low and is used to
generate

the

chip

peripheral devices.

select

for

the


WR (Write): This signal indicates that
the microprocessor is writing a data
to the memory or an output device.
This is also an active low signal. The
microprocessor places the data on

the data bus and asserts the WR

signal

to

indicate

the

peripheral

device that a valid data has been

placed on the data bus.

IO/M :

This

between

signal

memory

differentiates
and

an

I/O

operation. This signal is combined

with

the

generate

RD and WR
IO

and

signals

memory

to

control

signals.S 1 and S 0 : These signals are

used to indicate various operations of
the microprocessor like opcode fetch,
memory

read,

acknowledge, etc.,

Interrupt

ALE

(Address

signal

Latch

indicates

Enable):

This

whether

the

multiplexed address and data bus

hold

the

signals.
indicates

address
The

signals

positive

that

the

or

going

lines

data
pulse

hold

the

address signals and this signal can

be used to drive the address latch
circuits. The ALE signal will be active
The table 1.1 shows the status of
the control signals during various
machine cycles.

Table 1.1

Status
Machine
cycle

Control
I/

signals
S1

S0

RD = 0

RD = 0

WR = 0

I/O Read

RD = 0

I/O Write

RD = 0

WR = 0

O/
M#

Opcode
Fetch

Memory
Read

Memory
Write

Interrupt
Acknowledge


RD,WR = Z and

Halt

Hold

RD,WR = Z and

Reset

INTA = 1

Power

Supply

And

INTA = 1

Clock

Frequency
Vcc: + 5V power supply
Vss: Ground reference
X1,

X2:

crystal

of

MHz

is

connected to these pins to operate

the microprocessor with 3 MHz.
CLK (OUTPUT): This signal can be
used as a system clock for various
peripheral devices.

Externally Initiated Signals

The 8085 have five interrupt signals,
which can be used to interrupt a
program execution. They are INTR,
RST 7.5, RST 6.5, RST 5.5, and TRAP.

INTR

Interrupt request: This has the

lowest priority.

RST

Restart

7.5

Vectored
receiving

interrupts:

These

are

and

on

interrupts

the

interrupts
these

RST

microprocessor jumps to specific

6.5

location.

RST
5.5

TRAP

This non-maskable interrupt has

the highest priority.

Apart from these interrupts, the 8085

have three more externally initiated
signals

viz.,

RESET,

HOLD

and

READY.

RESET IN signal is used to reset the

microprocessor on receiving the reset
signal the program counter and the
other CPU registers will be loaded
with zero. The address and the data
pins goes to high impedance state.
RESET OUT signal is used to indicate
the

peripheral

devices

that

the

microprocessor is being reset and it

can be used to reset other devices.
HOLD signal is used for requesting
the control of the address and data
buses by external devices.

On receiving
the

the

HOLD

microprocessor

HLDA

(HOLD

gives
the

activates

Acknowledge)

the control
device. This

Direct

signal

of

the

mode

Memory Access

and

buses
is

to

called

(DMA)

and

will be discussed later.

If

slow

responding

device

is

connected to the microprocessor, the

READY signal is used to send the
microprocessor to a wait state until
the

device

activates

the

READY

signal.
Serial Ports
The

microprocessor

has

two

which can be used to implement

pins,

synchronous serial transmission, SID

(Serial Input Data) and SOD (Serial
Output Data).

1.6 8085 BUS COMMUNICATION

AND TIMINGS
The

signals,

which

are

discussed

above, can be easily understood by

examining

the

bus

communication

and timings of the microprocessor.

Among all other communications the
opcode

fetch

is

important.

The

opcode fetch involves the reading of

the opcode from the memory and
executing.

Suppose for example if an opcode

like 78H is stored in the location
8100H

of

memory

device.

The

opcode fetch machine cycle lasts for

four T-states. Each T-state precisely
equals to one clock period.
Step 1:

In

the

microprocessor

first

places

T-state
the

the

higher

order address 81H in the higher order

address lines A 15 to A 8 . The lower
order address 00H is placed in the
lower order multiplexed address lines
AD 7 to AD 0 . Then the microprocessor
activates the ALE signal to high and

the status signal IO/M signal to low.

Step 2: By the next T-state, the

microprocessor deactivates the ALE
signal

and

activates

the

control

signal RD to low. This control signal

RD enables

the

memory

and

the

opcode will be placed on the data bus

by the memory.
Step 3: After the opcode has been
placed

on

the

data

bus,

the

microprocessor de-activates the RD

signal and this makes the data bus to
go to high impedance state.
Step

4:

Then

the

microprocessor

places the opcode in the instruction

decoder and the task is carried out.

Demultiplexing

The

Address

Data Bus
The multiplexed address data bus
(AD 7 to AD 0 ) holds the address for
the first T-state and data bus for the
rest.

So

it

is

necessary

to

de-

multiplex the address and data bus.

The figure shows the schematic of
de-multiplexing

the

Address

data

bus. The bus is connected to a latch

74LS373.

Figure 1.3: De-multiplexing the address and data

buses

The output of the latch will change

according to the input if the gate
enable signal G is high. If the signal
G is low, it does not change the
output, even the input changes. The
gate signal G of the latch is driven by
the signal ALE and the Output control
signal OC is enabled by connecting
to ground. The latch 74LS373 latches
the address whenever the ALE signal
goes high. If the ALE signal goes low,
the latch will hold the previous data.
At first part of the machine cycle,
the ALE signal is activated and the
address data bus holds the address
signals (A 7 to A 0 ). Now the latch will
act as a buffer and holds the address
lines. In the next pert of the machine

cycle, the ALE is de-activated, but

the latch will hold the address lines
till the ALE signal is activated again.

Generating Control Signals

The microprocessor uses the three

control signals RD, WR, and IO/M to

control

the

read

and

write

operations. The microprocessor has

to read and write both the memory
and the I/O devices. So it requires
four signals, which are decoded from
the above three control signals. The

IO

/ M signal goes low for a memory

related operation and it goes high

for an I/O related operation. The

RD and WR

signals

goes

low

for

reading and writing a memory or an

I/O device respectively. But only one
will be active at a time.

Figure 1 .4: Decoding the Memory and I/O control

signals

The figure shows the decoding of the

control
signals

signals.
are

signal

to

MEMR

and

The

OR-ed
generate
memory

RD and WR
the

IO/M

memory

read

with

write

MEMW

signals. Then the IO/M is inverted

and is again OR-ed with the RD and
WR signals to generate I/O read and
I/O write signals respectively.

1.7 The 8085 Machine Cycles

A machine cycle is defined as the
time

required

for

completing

one

operation of accessing the memory,

I/O, or acknowledging an external
interrupt. This may take three to six
T-states.
external

The

microprocessor

communication

functions

can be divided into three categories:

1.

Memory Read and Write

2.

I/Q Read and Write

3.

Request Acknowledge

These primary functions are further

divided into various machine cycles
and are tabulated in the Table 1.1.
The first operation in any instruction

is Opcode Fetch. The microprocessor

reads the instruction and executes
it,

in

this

machine

cycle.

The

microprocessor uses the address and

data buses to get the instruction and
is a memory related operation so that
the

status

signal

IO/M#

remains

high.
The opcode fetch machine cycle is
discussed

already

in

the

bus

communication and timing. The other

important
Memory

machine
Read

machine cycles.

and

cycles
Memory

are
Write

Memory Read machine cycle

The memory read machine cycle can
be best explained, if a two-byte or
three-byte instruction is examined.
Even-though

the

opcode

fetch

machine cycle also deals with reading

the memory, it is considered as a
different machine cycle. Also it has 4
T-states while Memory Read machine
cycle has 3 T-states.
For example consider the instruction
(MVI

A,

54H).

It

is

two

byte

instruction and has opcodes (3E, 54)

and are loaded as shown in below.
MEMORY
ADDRESS

2000

LABEL

MNEMONICS

MVI A, 32H

OPCODE

3E

COMMENTS

Loads

the

accumulator
2001

32

with 32H

The opcode 3E is fetched first and on

reading it, the microprocessor knows
the next memory location will hold
the data that is to be loaded to the
accumulator.

The

next

location

is

read by Memory read machine cycle.

Figure1.5: Timing diagram for Opcode Fetch and

Memory Read machine cycle.

In the first T- state, the ALE signal

is enabled high and the higher order
address 20H will be placed on the
address lines A 15 to A 8 and the lower
order address 01H will be placed on
the multiplexed Address and Data
bus AD 7 to AD 0 . The address will be
acquired from the Program Counter
previously and will be incremented to
2002H after it has been loaded to the
address lines. On receiving the ALE,
the latch latches the address lines.
On the rising of the second T-state,
the ALE signal is disabled first and
the data bus will be activated as an

input port. The memory places the

data in the location 2001H on the
data bus. In the third T-state, the
microprocessor will read the data in
the

data

bus

and

stores

in

the

accumulator.

Estimating the execution time

To estimate the execution time of an
instruction,

the

no

of

T-states

required for the instruction is to be

known. The execution times of an
instruction

can

be

estimated

as

follows.
For example, the instruction MVI A,
32H

requires

two

machine

cycles

(Opcode Fetch and Memory Read).

The Opcode Fetch cycle will take 4

T-states and the Memory Read cycle
will take 3 T-states.
Assume the Clock Frequency f =
2MHz.
One T-state = 1 / Clock Frequency =
1 / f = 0.5s.
Execution time for Opcode Fetch:
(4T) x 0.5 = 2s.
Execution time for Memory Read:
(3T) x 0.5 = 1.5s.
Execution time for Instruction MVI A,
54H: (7T) x 0.5 = 3.5s.

Figure1.6 (a): R/W Static Memory

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to can be read as well as be written

at

various

instants.

The

memory

device shown in the figure is an 8-bit

memory having 2048 locations and
has 11-bit wide address lines. It also
has 8-bit wide input and output data
lines.

The

memory

device

three

control signals CS, WR and RD. The

chip enable signal CS is used for

enabling the device and if this signal
goes low, the memory will be ready
to accept or deliver data from or to
the data bus. The control signal RD
is used for enabling the output buffer
of the memory device. The control
signal WR must be enabled to write
into the memory.

Figure 1.6 (b): EPROM Memory

The

figure

(b)

shows

an

EPROM

having 4096 locations and having

only two control signals CE and RD

This

is

because

the

data

in

the

EPROM cannot be altered but can be

read. Once it has been programmed,
the

EPROM

will

store

the

data

permanently and is erased only by

opening a window provided on the

chip

and

passing

UV

rays.

The

interfacing of both the devices are

same except the EPROM does not
require WR signal
The interfacing of the memory device
is done as follows.
1.

Since the R/W memory has 2048

locations, it needs 11 address
lines A 10 to A 0 . So those address
lines will be connected to the
address lines of the chip.

2.

The remaining 5 lines are used

to give the CS signal to the

memory. Necessary care should
be taken that the logic provides

CS

signal

only

to

specific

combination.

Suppose

the

memory chip occupies then first

2048 locations of the total 64K
memory, the address lines A 15 to

A11 will remain low for all the first

2048

locations.

Whenever

the

lines A 15 to A 11 goes low, the CS

signal should be activated.
3.

Since it is a memory related

operation the (IO/M will stay low.
So it is essential to decode the

IO/M, RD, and WR signals to give

MEMRS and MEMW signals.

4.

For an EPROM device, only the

MEMR signal is enough and is
connected to OE line. But for the

R/W device, the MEMR signal is

connected to OE line and MEMW
signal is connected to WE line.
The interface diagram is shown
in the figure.

Figure 1.7 (a): decoding circuit for the RAM 6116

(2048 x8)

Figure 1.7 (b): decoding circuit for the EPROM 2732

(4096 x8)

For Memory Read machine cycle, the

microprocessor places the address on

the address bus and the CS signal

wilt be generated by the decoder

circuit. Then it activates the IO/M

signal to low to indicate it is a
memory operation. After the first Tstate and address has been latched,
the data bus goes to input state. Now
the RD signal is activated low and

the MEMR signal will be generated.

It enables the output of the EPROM
or R/W memory device. The memory
device

outputs

the

data

on

the

location specified by the address. The

RD signal is de-activated and the

data

is

inputted

into

the

microprocessor before the end of the

third T-state.

Figure 1.8a: Timing diagram for Memory Read

machine cycle

In the Memory Write machine cycle,

the

microprocessor

places

the

address on the address bus. The

address lines A 15 to A 11 generates

the CS signal by the decoder circuit.

The IO

/M

signal is activated and

goes low, since it is a memory related

operation. By the next T-state, the
microprocessor puts the data on the

data bus and enables the WR signal

to go to low. This generates the

control signal MEMW by the address

decoder.
In the next T-state, the memory
stores the data in the data bus on
the location specified by the address
lines

in

the

microprocessor

data
disables

bus.

The

the

WR

signal before the end of the third Tstate.

Figure 1.8b: Timing diagram for Memory Write

machine cycle

Address Decoding Circuits

The memory address of the EPROM
chip ranges form 0000H to 0FFFH.
The address lines A15 to A12 will be
low and must be used to generate the


CE signal. The address lines A11 to
A0 can vary from all zeros to all ones
covering 4K memory.
The figure 1.9a shows a 4 input OR
gate which can be used to generate

low active CE signal when all the

inputs goes low. The address lines
A 15 to A 12 is connected to the 4
inputs

and

the CE

signal

will

generated.

Figure 1.9 a & b: Decoding by NAND gate & a 3 to8

decoder

be

Another

method

programmed

is

using

decoder

pre-

such

as

74LS138 octal decoder. The address

lines are connected as shown in the
figure 1.9b. If all the address tines
A 15 to A 12 goes low, the O 0 will go
low. This output O 0 can be connected

to the chip enable CE signal of the

memory

device.

microprocessor

is

Suppose

the

reading

the

location 0FFFH of the memory chip.

The

microprocessor

places

the

address 0FFFH on the address bus.

The higher order nibble A15 to A12
go all low and the decoder generates
CE signal for the memory chip.

The rest of the address lines A 11

to A 0 are directly connected to the
memory

chip

decoder

in

decodes

the

and
the

the

internal

memory

address

chip

and

the

location FFFH is enabled for access.

1.9 I/O Interfacing

I/O Instructions
The 8085 have two instructions to
carry out the data transfer between
the processed and the I/O device,
viz., IN and OUT. The IN instruction
inputs the data from an input device
specified

by

the

8-bit

address

following the opcode and stores the

data in the accumulator.

The

OUT instruction

data

in

output

outputs

the accumulator

to

the
an

device specified by the 8-bit

address.
The executions of the OUT and IN
instruction are described below.

OUT instruction:
This is a two byte instruction, which
copies the data in the accumulator
and transfer the data to the output
port specified by the 8-bit address
following the opcode. Suppose for an
example,

assume

having the address

an

output

port

01H

is

interfaced

microprocessor.

If

the

to

the

output port

is designed as a LED display, then

it will display the contents of the
accumulator.
MEMORY
ADDRESS

2050

LABEL

MNEMONICS

OPCODE

COMMENTS

OUT 01H

D3

Copies

2051

contents

01

the
of

the
accumulator
and

stores

in

the

output port
01H.

The execution of an OUT instruction

is as follows. The OUT instruction has
three machine cycles, Opcode Fetch,
Memory

Read

(to

read

address), and I/O write.

the

port

Like

every

instruction,

the

first

machine cycle is the Opcode Fetch.

In

the

first

microprocessor

machine
places

cycle,
the

the

address

2050 on the address bus and enables

the ALE signal in the first T-state. In
the second T-state, the lower order
the RD and IO/M signal are activated
low and this provides MEMR signal
for reading the memory. The opcode
will be placed on the data bus and it
will be read by the microprocessor in
the third T-state. The microprocessor
places the opcode in the instruction
register and will be executed before
fourth T-state.

On reading the opcode D3H, the

microprocessor knows that the next
location will hold the address of the
port. Then the next machine cycle
will be the Memory Read. In the first
T-state, the microprocessor places
the address 2051 on the address bus
and activates the ALE signal. Then

in the next T-state, the RD and the

IO

/ M signals are activated low. Thus

the

MEMR

signal

is

once

again

activated to read the data from the

memory. In the third T-state, the
memory places the port address 01H
stored in the location 2051H on the
data bus.

In

the

third

machine

microprocessor
address

01H

places
on

both

cycle,
the

the
same

higher

and

lower order address lines In the first

T-state. In the second T-state, the
microprocessor deactivates the ALE
signal and places the content of the
accumulator in the data bus and

activates the WR to low and the IO/M

signal to go high. This produces the

IOW signal which will be explained

later.

Thus

the

content

of

the

accumulator is sent to the output

port.

Figure 1.10: Timing for the execution of OUT

instruction

IN Instruction:
This is a two-byte instruction, which
copies the data from an input device
and stores in the accumulator. The
input device may be a keyboard, a
switch,

or

an

Analog

to

Digital

Converter (ADC). The first byte is

the hexadecimal opcode (DBH), and

the second byte specifies the port
address.

The

address

of

an

I/O

device may be specified from 00H to

FFH.
MEMORY
ADDRESS

2065
2066

LABEL

MNEMONICS

OPCODE

COMMENTS

IN 84H

DB

Copies

the

84

data

the

in

input
and
the

port
stores

data

in

the
accumulator.

Similar to the OUT instruction, the IN

instruction also have three machine
cycles, Opcode Fetch, Memory Read,
and I/O Read. The first two machine

cycles

are

as

same

as

the

OUT

instruction. In the I/O Read machine

cycle, the microprocessor places the
address 84H on the both of the
higher and lower order address lines

and activates the IO/M signal high in

the first T-state. In the second T
state, the RD signal is activated low

and the IOR signal goes low as a

result. Then the output port places
the data in the data bus and the
microprocessor reads the data before
the end of the fourth T-state.

Figure 1.11: Timing for the execution of IN instruction

Decoding Circuit

The figure 1.12 shows the interfacing

diagram of an output port interfaced
to

the

microprocessor.

Since

the

output port is represented by an 8-bit

address,

the

lower

order

address

lines A 7 to A 0 are enough to decode

the address. The address lines A 7 to
A 0 are connected to an 8 input NAND
gate with A 7 to A 1 inverted, which


gives low IOADR signal 01H. The

control signal IOW is generated by a

two input NAND gate with inputs as

IO/M and inverted WR signals. The

gate G 2 combines these two signals

IOADR and IOW to generate IOSEL

signal. The IOSEL signal is used as a

latch enable of the output port. The
Latch connects the LEDs to the data
bus. When it is enabled, it outputs
the data in the data bus to the LEDs.

Figure 1.12: interfacing of a LED port to 8085

Input Interfacing
The address lines are decoded using

an 8-input NAND gate. When the

address lines are high, the output of

the NAND gate goes low to deliver

the control signal, IOADR. To decode

84H, the input lines A 0 -A 7 except A 2
and A 7 are inverted. The Gate G 2

gives out IOSEL pulse only when the

signals IOADR and IOR signals arte

active. This IOSEL enables the buffer
which connects the DIP switches and
the data bus.

Figure 1.13: Interfacing of an8-key input port to 8085

Memory Mapped I/O

In I/O mapped I/O, the input and
output devices are assigned 8-bit
address. In memory mapped I/O, the
I/O devices are assigned a 16-bit
address

and

are

identified

as

memory location. This enables the

microprocessor to transfer data to

and

from

the

I/O

devices

using

memory related instructions (such as

LDA, STA, etc), in I/O mapped I/O,
the I/O devices are communicated
through only two instructions and in
memory

mapped

I/O,

the

microprocessor is equipped with no of

instructions to communicate with the
I/O devices.
When the I/O device is connected as
a

memory

location,

the

STA

instruction stores the contents of the

accumulator

to

the

I/O

device

specified by the 16-blt address. The

LDA

instruction

loads

the

accumulator with the data in the I/

O

connected

specified

by

16-bitaddress. But if the I/O device is

connected as a memory location, the

MEMR and MEMW signals

should

be

used to enable the I/O device instead

of IOR and IOW signals.

Execution Of Memory Related

Instructions
The memory related data transfer is
executed in the same way as IN and
OUT instructions. But the memory
related instructions points to 16-bit
address

while

instructions

the

have

IN

8-bit

and

OUT

immediate

address. The instructions LDA and

STA

require

machine

cycles

to

execute while the I/O instructions

require three machine cycles.

For example, an output device is

connected as a memory mapped I/
Oat the
address 8000H. To output a data in
the accumulator to the device STA
8000H can be used instead of OUT
instruction. The first machine cycle
is

the

Opcode

microprocessor

Fetch.
reads

Then

the

the

address

8000H in two memory read machine

cycles. The last machine cycle is the
Memory Write, the microprocessor
writes to the I/O device by asserting

MEMW signal.

UNIT II
8085 INTERRUPTS AND
PERI PHERALS

2.1 Interrupt Structure In 8085

The

8085

has

non

maskable

interrupt (TRAP) and four maskable

interrupts (INTR, RST5.5, RST 6.5,
RST 7.5). All these interrupts are
controlled by the Interrupt enable
flip-flop and can be controlled by the
user

at

any

time

by

setting

or

resetting. The interrupt allows the

microprocessor

to

respond

to

external devices connected to it, only

on demand and the microprocessor
is free to perform its operation until
the interrupt arrives. The interrupt

structure can be best explained by

considering

the

INTR

interrupt

request. The microprocessor checks

the interrupt lines before executing
each instruction and if any of the
interrupts

is

set,

microprocessor
interrupt

connected

devices
to

the

to

the

routines.

Slow

jumps

service

responding

then

the

like

ADC

are

microprocessor

through the interrupt lines and the

microprocessor can perform its own
operation until the interrupt comes.
If it comes, the microprocessor will
perform
Each

interrupt

interrupt

will

service
have

routine.
its

own

vectored location except INTR line

and the microprocessor will jump to

the address specified in the location.

So the interrupt service routine must
be written in the specified location.
The addresses of the subroutines are
written

in

the

vectored

locations.

Suppose for example, consider an

ADC

connected

to

the

microprocessor. The converted digital

data from the ADC must be read after
it gives EOC (End Of Conversion)
signal to the microprocessor. So the
microprocessor will monitor the EOC
fine continuously and has to wait
until the EOC signal appears. If the
EOC line is directly connected to any
of

the

interrupt

lines.

The

microprocessor need not wait in a

single loop and it can do its own

process. At once the interrupt comes

from the ADC the microprocessor
jumps to the subroutine where the
instructions for inputting the data
form the ADC will be return. The
interrupt process of the INTR takes
place as follows.
1.

The interrupt process must be

enabled

by

the

user

by

the

instruction El. All the interrupts

except TRAP can be enabled or
disabled

by

using

El

or

Dl

instruction.
E1 (Enable Interrupt): One byte
instruction
The instruction sets the interrupt
enable flip-flop and enables the
interrupt process.

D1 (Disable Interrupt): One byte

instruction
This

instruction

interrupt

enable

resets

the

flip-flop

thus

disabling the interrupt.

2.

The microprocessor checks the

interrupt

line

INTR

each

and

every time before executing an

instruction.
3.

If the INTR line is high, the

interrupt

is

enabled

microprocessor

and

finishes

the
the

current instruction. It disables

the interrupt enable flip-flop and

activates the INTA signal The

microprocessor will not respond
to any of the interrupt until the
interrupt

enable

enabled again.

flip-flop

is

4.

Since the INTR request has no

vectored address, the INTA signal

can be connected to a buffer
which

delivers

instruction

so

microprocessor

the

RST

that

the

can

jump

to

vectored locations of the RST

instruction. If RST instruction is
executed,

the

microprocessor

will jump to the vectored location

in

the

page

microprocessor

0
and

of

the
starts

executing the instruction at the

memory location.
5.

When the microprocessor reads

the RST instruction, it saves the

address of the next instruction to

be performed in the stack and
jumps to the vectored location of
the RST instruction.
6.

The

program

to

satisfy

the

interrupt request must be written

in the specified location as a
subroutine.

This

subroutine

is

called as the Interrupt Service

Routine.
7.

Since

the

microprocessor

disables the interrupt enable flipflop

when

interrupt,

it

the

receives
service

the

routine

should include El at the end.

8.

The subroutine should also have

RET instruction at the end to
return from the subroutine.

Execution of RST Instruction

The

8085

have

eight

restart

instructions RST 0 to RST 7. These

instructions

are

instructions,

one-byte

which

CALL

transfer

the

microprocessor to jump to a specified

location

in

the

page

00H.

The

vectored locations are given in the

table 2.1. The RST instruction is
much similar to the CALL instruction
and on reading the RST instruction;
the

microprocessor

stores

the

address of the next location to be

executed

in

the

stack

execution

is

vectored

address.

microprocessor
instruction

at

transferred

the

to

the

When

the

the

RET

reads
the

and

end

of

the

subroutine it jumps back to the main

program by reading the address in
the

stack.

So

one

of

these

instructions is inserted to the system

by external hardware as shown in the
figure.
Table2.1

Hex

Call Location

Code

Address

RST 0

C7

0000

RST 1

CF

0008

RST 2

D7

0010

RST 3

DF

0018

RST 4

E7

0020

Mnemonics

RST 5

EF

0028

RST 6

F7

0030

RST 7

FF

0038

The execution of the RST instruction

is described below.
The microprocessor on receiving the
INTR signal, sends an acknowledge

signal INTA This acknowledging signal

is used to enable the tri-state buffer:

Figure 2.1: Circuit implementing RST 5 instruction

The

buffer

puts

EFH,

the

corresponding opcode of the RST 5

instruction, in the data bus. The next
two

machine

Memory

Write

cycles

will

machine

be

the

cycle

for

storing the memory address in the

Stack. The microprocessor places the
address SP-1 in the address bus and
places the lower order address of the
next instruction to be executed in
the

data

bus

and

enables

the

IO/M and WR for MEMW signal. In the

next Memory Write machine cycle the
microprocessor

places

the

higher

order address in the data bus and

places
address

the

address

bus.

These

SP-1
two

in

the

machine

cycles store the address of the next

instruction in the Stack. The next

instruction cycle is transferred to the
location 0028H. The service routine
may exist any where in the memory,
but JMP instruction must be written
in the location 0028H to transfer the
execution to the service routine.

Figure 2.2: Timing of the execution of RST 5

instruction

8085 Vectored Interrupts

The 8085 have five interrupt lines,
except the INTR line, the TRAP, RST
5.5, RST6.5, and RST 7.5 vectored
to specific locations on page 00H
without any hardware. The vectored
locations of the interrupts are given
below.
Table 2.2

Interrupts

Call Locations

TRAP

0024H

RST 7.5

003CH

RST 6.5

0034H

RST 5.5

002CH

The TRAP has the highest priority

followed by RST 7.5, RST 6.5, RST
5.5, and INTR. But the TRAP has less
priority than HOLD.

Trap
The TRAP is a non-maskable interrupt
(NMI) that is it cannot be masked
by

the

DI

(Disable

Interrupt)

instruction. It is positive level and

edge sensitive i.e., that the input
should go high and stay high. When
the interrupt is triggered the program
execution is transferred to location
0024H. Since the TRAP cannot be
masked, it can be used for some
critical events such as power failure
and emergency shut off.

RST 7.5, RST 6.5, and RST 5.5

These maskable interrupts can be
enabled

or

disabled

by

program

control instructions El and Dl. The

restart
using

interrupts
SIM

can

be

instruction.

masked

SIM:

Set

Interrupt Mask
This is a one-byte instruction and it
uses the contents of the accumulator
for

its

operation.

multipurpose
mask

or

This

instruction,
unmask

the

is

used

to

restart

interrupts and also for Serial data

transmission. The bit definition is
given below.

D7

D6

D5

D4

D3

D2

D1

SOD

SDE

XXX

R7.5

MSE

M7.5

M6.5

D0
M5.5

The SIM instruction is used to mask

or unmask the restart interrupts RST
7.5, RST 6.5, and RST 5.5 by setting
or resetting the bits D 2 , D 1 , and D 0
respectively. The bit D 3 is used for
enabling or disabling the mask. When
it is set, the mask is enabled and
when it is reset, the mask will be
disabled and the bits D 2 , D 1 , and D 0
are ignored.
The RST 7.5 flip-flop can be reset by
software. By resetting the D 4 bit, the
RST 7.5 flip-flop can be disabled so
that the interrupt in the line can be
override without servicing.

The

same

serial

instruction

data

is

used

for

Bit

D7

transmission.

(SOD: Serial Output Data) is used to

output a data bit by bit. The bit D 6 is
set or reset to enable or disable the
serial output operation respectively.

2.2 Direct Memory Access (Dma)

The Direct Memory Access (DMA) is
used for some typical applications
where

faster

data

transfers

are

required. When the microprocessor

controlled data transfer is too slow,
the DMA is generally used. The 8085
microprocessor
available

for

communication:

has
this

two
type

HOLD

pins
of

I/O

(Hold)

and

HLDA (Hold Acknowledge). If any of

the external devices requires faster

data transfer with memory device it
activates

the

HOLD

signal.

On

reception of the HOLD signal the

microprocessor puts the address and
data buses in high impedance mode
and delivers the control of the buses
to the external device. Then it gives
out HLDA signal to inform that it has
recognized the HOLD signal and the
external device can use the address
and data buses.
HOLD: This is an active high input
signal to the 8085 and on receiving
the

signal

the

microprocessor

releases the control of the buses to

the device. The microprocessor will
regain the control of the buses after
the HOLD signal goes low.

HLDA: This is an active high signal

delivered by the microprocessor to
acknowledge the device that it has
accepted the request.
Normally a DMA controller will be
used for managing the data transfer
between the device and the memory.

DMA Controller 8237

The 8237 is a programmable Direct
Memory Access controller. It has four
channels and each can transfer 64K
bytes of data. The DMA controller
operates in two modes: (slave mode)
it is treated as an I/O device when

the microprocessor is in control of

the buses, and (master mode) it
gains

control

requesting

of

the

through

buses

HOLD

by

signal.

Many of the input signals in the I/O

mode will become output signals in
the master mode. It should act as a
link between the microprocessor and
the external device.
The

8237

have

four

independent

channels CHO to CH3. Each channel

have two 16-bit registers: Memory
Address Register for storing the
starting address of the byte to be
copied and Count Register to load
the count of the no of data bytes
to be transferred. So these eight
registers

are

accessed

by

the

microprocessor by using four address

tines A 3 A 0 . The last eight registers
are used to write commands or read
status.
The DMA signals are divided into two
groups:
1.

one group of signals Used for

interfacing

with

the

microprocessor;
2.

the second group of signals use

for

communicating

with

the

peripherals.
DREQ0 DREQ3 DMA Request:
These are four independent input
signals generated by the peripheral
devices such as floppy disks and hard

disk. To get DMA service, a request

is generated by the peripheral by
activating

the

DREQ

line

of

the

channel.
DACK0

DACK3

Acknowledge:
acknowledge

These

signals

DMA

are

the

generated

by

the microprocessor to acknowledge

the HOLD request by the peripherals.
AEN and ADSTRB Address Enable
and Address Strobe: These are active
high output signals that are used to
latch a high order address byte to
generate 16-bit address.

MEMR and MEMW Memory Read and

Memory

Write:

These

are

output

signals used during the DMA data

transfer

to

write

and

read

from

memory.
A 3 A 0 and A 7 A 4 Address: A 3
A 0 are bi-directional address lines.
They are used as inputs to access
control

registers,

when

the

DMA

controller is in Slave mode. During

the DMA cycle, along with A 7 to A 4
address lines are used as output lines
to generate low order address.
HRQ and HLDA Hold Request
and Hold Acknowledge: HRQ is an
output signal used to request the
microprocessor control of the system
bus. After receiving the HRQ, the
microprocessor

completes

the

bus

cycle in process and issues the HLDA

signal.

Figure 2.3: Interfacing diagram 8237 DMA controller

to 8085

DMA Execution
The process of DMA transfer from the
peripheral to the system memory
under the DMA controller can be
classified under two modes: the slave
mode and the master mode.

Slave Mode In the slave mode, the

DMA controller is identified as an I/O
device as follows.
1.

The

MPU

selects

the

DMA

controller through Chip Select.

2.

The MPU writes the control words

in

the

channel

registers,

command and status registers by

using the address lines and IOW
and IOR.
Master Mode During the DMA cycle,
the

DMA

controller

works

in

the

master mode.
1.

When the peripheral needs DMA

data transfer, it sends high DRQ
signal in one of the channels
connected to it.

2.

When the DRQ signal is set, the

DMA

controller

enables

the

channel and sets the HRQ signal.

The HRQ signal is connected to
HOLD signal of the 8085.
3.

In the next machine cycle, the

MPU releases the control over
the address and data buses and
sends the HLDA signal to the
8237.

4.

After receiving the HLDA signal,

the DMA asserts AEN (Address
Enable) signal high. The high
AEN signal disables the latch 2

which

disconnects

the

microprocessor from the address

and data buses. And it enables
the latch 1 which connects the
DMA controller to the address
and

data

buses.

The

ADSTB

signal of the 8237 is connected

to the Latch Enable of the latch
1 which latches the higher order
address

from

the

multiplexed

address and data bus DB0 to

DB7.
5.

After

getting

the

complete

control over the buses, the DMA

controller sends DACK signal to
the peripheral.

6.

The

DMA

uses

the

signals

IOR, IOW, MEMR, MEMW

to

control the data transfer.

7.

After

the

complete,
asserts

data
the

the

transfer

DMA
EOP#

is

controller
(End

Of

Process) line low to inform the

peripheral that the data transfer
is

complete.

After

the

data

transfer is complete, the DMA

controller

releases

signal,

and

microprocessor

the

HOLD

then

the

regains

the

control of the buses.

2.3 8255a Programmable

Peripheral Device
The

8255A

is

widely

used,

programmable, parallel I/O device. It

can be programmed for simple and
Interrupt I/O. The 8255A has 24 I/
O pins dedicated for parallel I/O lines
and these lines are grouped into
three ports: PORT A, PORT B, and
PORT C. Among these ports, A and
B are programmed as 8-bit parallel
ports,

while

the

port

can

be

programmed either as individual bits

or as grouped into two four bit ports
C UPPER (C U ) and C Lower (C L ). The
8255A ports can be programmed by
writing a control word in the control
register.

The functions of the ports can divide

into two mode: Bit Set/Reset (BSR)
mode and I/O mode. The BSR mode
is used to set or reset the individual
bits of port C. The I/O mode can be
further classified into three modes:
Mode 0, Mode 1, and Mode 2. In Mode
0, all ports are configured as simple
I/O ports. In Mode 1, the ports are
programmed for data transfer with
handshake signal. The data transfer
is done by the ports A and B and
handshaking is done through port C.
In Mode 2, the port A is programmed
as a bi-directionai port using some
pins of port C for handshaking and
the remaining pins of port C and port
B are used in Mode 0 and Mode 1.

Block Diagram Of 8255A

Figure 2.4: Internal block diagram of 8255A

Programmable Peripheral interface

The block diagram of 8255A in the

figure 2.4 shows two 8-bit ports (A
and B), two 4-bit ports (C U and C L ),
a data bus buffer, and control logic.

Control Logic
The control section has six lines.
Their functions are as follows.

RD (Read): The Read signal enables

the read operation. This is an active
low input signal from the MPU and
is used for reading the data in the
ports.

WR (Write). This is an active low

input from the microprocessor, which
writes data into the selected ports.
RESET (Reset): This is an active high
signal used for resetting the control
register and sets all ports in the input
mode.

CS , A 0 and A 1 : The CS (Chip Select)

signal is used to enable the device

and

is

normally

connected

to

decoded address. The A 0 and A 1

signals are used to select one of the
three ports or the control register.
The table shows the address of the
control register and ports.
Table 2.3

CS

A1

A0

Selected

Port A

Port B

Port C

Control Register

8255A not enabled

Control Word
The control register can be used to
program the ports in four different
modes. The Bit D7 of the control
register is used to program the port
C in BSR mode. If D7 is set, the
ports are programmed in I/O mode
and if the bit is reset, the ports are
programmed in BSR mode. In the I/
O mode, the other 7 bits are used
for programming the ports in Mode 0,
1, and 2. The content of the control
register is shown in the figure.
D7

1/O=1

BSR=0

D6

D5

Port

Port

mode

mode

D4

Port

D3

Port

C
(upper)

D2

Mode

Selection

D1

D0

Port

Port

mode

(lower)

D6, D5, configures port A in Mode 0,1, 2.

D6 D5:

00H = Mode 0

01 H = Mode1

1XH= Mode 2

D4

= 1 Port A is input

= 0 Port A in output

D3

= 1 Port C upper is input

= 0 output

D2:

0 = Mode 0

1 = Mode 1

D1

= 1 Port B input

= 0 output

D0

= 1 Port C lower input

= 0 output

The modes are explained below.

BSR (Bit Set/ Reset) Mode

The BSR mode is applicable only to
port C. Each bit of the port C can
be set or reset individually by writing
an appropriate control word. The bit
D7 of the control register is reset to
program the chip in the BSR mode.

The bit definition of the control word

for BSR mode is given below.

D7

D6

D5

D4

D3

D2

D1

D0

S/R

D7 bit is reset for BSR mode

D3, D2, D1: indicates the bit of the
port C that is being selected.

000 = Bit

001= Bit

010 = Bit

011= Bit

100 = Bit

101 = Bit

110 = Bit

111 = Bit

D0

= 1: Set

0: Reset

In BSR mode, individual bits of port C

can be used for applications such as
an ON/OFF switch.

Mode

0:

Simple

Input

or

ports

are

Output
In

this

mode,

the

configured for simple input or output

operation. The ports A and B are
programmed as two 8-bit I/O ports
and the port C is configured as two
4-bit ports. The features of this mode
are as follows.
1.

Outputs are latched. So even if

the input is removed the data in
the output port never changes.

2.

Inputs are not latched. If the

input changes, the input port
data correspondingly changes.

3.

Ports do not have handshake

signals.

Mode 1: Input or Output with

handshake In mode 1, the 8255A
exchanges handshake signals with
the

peripherals

while

transferring

data. These handshake signals are

used for indicating the status of the
data in the lines through which data
is transferred. The features of this
mode are as follows.

1.

The ports A and B function as

8-bit I/O ports. They can be
configured

as

either

input

or

output ports.
2.

Each ports uses three tines from

port C for handshaking with the
peripherals. The remaining two
lines of the port C can be used
for simple I/O functions.

3.

Input and Output are latched.

Even the input is removed; it
does not change the data being
read.

4.

Interrupt logic is supported.

In Mode 1, six lines of the port C

are used for handshaking but those
lines will be different for input and

output operation. So it is important

to

discuss

the

input

and

output

operation separately.

Mode 1:Input Control Signals

Figure 2.5: 8255A mode - 1: input configuration

The figure 2.5 shows the associated

signals for handshaking and input
operation.

Port

uses

the

three

signals PC 3 , PC 4 , and PC 5 , Port B

uses the three lower signals PC 2 ,
PC 1 ,and PC 0 . The pin functions are as
follows.

STB (Strobe Input): This signal is

generated
indicate

by
the

the

peripheral

8255A

that

it

to
has

transmitted a data and the data lines

carries that valid data. The 8255A
responds

to

the

STB

signal

by

asserting the IBF and INTR signal.

IBF (Input Buffer Full): This signal is

generated by the 8255A on response
to the STB signal. This indicates the

peripheral

that

the

8255A

has

accepted the data and it is reading

the

data.

The

peripheral

will

not

transmit the next data until the IBF is

de-activated.
INTR (Interrupt Request): This is an
output signal from the 8255A to the
MPU indicating that the 8255A has
received

valid

data

and

the

microprocessor can read from it. This

signal

is

reset

when

the

microprocessor sends the RD signal

i.e.,

it

reads

the

data

from

the

8255A.
INTE (Interrupt Enable): This is an
internal flip-flop used to enable or
disable the INTR request generation.

This bit is reset to ignore the data

from the 8255A. The two flip-flops
INTE A

and

disabled

INTE B

through

are
PC4

enabled
and

or
PC2

respectively.

Mode

1:

Output

Control

Signals

Figure 2.6: 8255A mode 1: Output configuration

Figure 2.6 shows the control signals

when ports A and B are configured
as output ports. The signals are as
follows.

OBF (output Buffer Full): This signal

goes low to indicate the peripheral
that the MPU has sent a valid data
in the output latch of the 8255A and
It is ready to read. The signal goes
to high again when the peripheral
finishes reading the data and sends

an ACK signal.

ACK (Acknowledge): This is an input

signal generated by the peripheral
device indicating that it has read a
data.

INTR

(Interrupt

Request):

This

signal is generated by the 8255A to

the microprocessor after it receives
the ACK signal from the peripheral
device. It requests the MPU to send
the next data.
INTE (Interrupt Enable): This signal
is to enable or disable internal flipflop to generate INTR signal.
PC 4,5 : These lines are used as input
or output.

Mode 2: BI-Directional Mode

In this mode, the port A is used as a
bi-directional port and it uses five
pins of the port C for handshaking

The port B is either operated in mode

0 or mode 1. The remaining bits of
the port C are used as simple I/O
lines.

This

mode

is

used

in

applications as data transfer between

computers or floppy disk.

Interfacing a Matrix Keyboard

Figure 2.7: Interfacing a matrix keyboard to 8255A

The figure 2.7 shows the interfacing a matrix
keyboard with 20 keys. The keyboard has five rows
and four columns. These 20 keys are used to
represent sixteen hexadecimal numbers from 0 to F
and the remaining four keys can be used to represent
some functions like reset, store, execute, etc. The
rows are connected to the Port C of the 8255, which is
interfaced to the microprocessor. The columns are
connected to the Port B of 8255.

Procedure
The rows are grounded by sending
00H to the port C. When a key is
pressed, the column connected to
port B is grounded and will be read as
0.
The procedure of finding the key
pressed is given below.
1.

Check whether all keys are open.

The program sends 00H to port C
grounding all the rows. It reads
the input port B for the release
of previous key. If the key is not
released, it will wait in a loop.
Then it goes to a delay loop
called key debounce for 10ms.

This is important, because during

the key release the mechanical
key may debounce.
2.

Check a key closure.

The program then checks for a
key closure. If none of the keys
is pressed, the program waits in
a loop until any of the keys is
pressed. If none of the keys is
pressed, the port B will be read
00001111B. if any of the keys is
pressed, the particular column,
where the key is, will go low and
the

port

will

be

read

for

example 00001110B.
3.

identify the key.

If the port B is read other than
00001111B, it means that a key

is pressed. The program grounds

the first row is grounded and the
key is found by checking each
column. There are two loops the
outer loop grounds one row at a
time and the inner loop checks
the

key

by

scanning

each

column.
4.

Finding the key pressed.

A

counter

is

incremented

initialized

for

every

and

column

check. The program will make

one row zero and check the four
columns.
another

Then
row

it

and

grounds

checks

the

columns. The matrix keyboard

has five rows and four columns.
Once

the

key

is

found

the

counter is stopped and the count

value corresponds to the key.
Program is given below
START:
MOV A, 82H
OUT CNTRL PORT
PUSH B
PUSH D
SUB A
MOVE, A
OUT PORTC
KEYREL:
IN PORTB
ANI 00001111B
CPI OFH
JNZ KEYREL
CALL KYDBONCE
KEYCHEK: IN PORTB
ANI 00001111B
CPI OFH
JZ KEYCHEK
CALL KYDBONCE
MVI A, 7FH
MVI B, 05H
NXTROW:
RLC
MOV D, A
OUT PORTC
IN PORTB
ANI 00001111B
MVIC,04H
NXTCOLMN: RAR
JNC CODE
INR E
DCR C

; control word for configuring 8255

; output to control port of 8255
; saving the values in B and D in stack
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;

loading zero in A
initialing the key code counter
ground all the rows
get the values from port B
masking the higher order 4 bits
check whether port B is all one
If not, execute again
call 10 ms delay (key debounce)
input from port B
mask higher order 4 bits
check any bit of port B gone zero
if not, execute again
give a 10ms delay
load value to ground one row at a time
row counter
rotate A to ground one row
save the value in D
output to port C
input from port B
mask higher 4 bits
column counter
get the D 0 bit to carry
if carry not set, go to code
increment key counter
decrement column counter

JNZ NXTCOLMN
; if any column left, go to next column
MOV A, D
; get back the scan code
DCR B
; decrement the row counter
JNZ NXTROW
; if any row left, go to next row
JMP KEYCHEK
; if no key pressed go to fresh key check
CODE:
MOV A, E
; get the code from E to A
POP D
; get back the values from stack to D, B
POP B
RET
; return to main program
DBONCE:
PUSH B
; store values of B, PSW to stack
PUSH PSW
LXI B, COUNT
; initialize B with delay count for 10ms
LOOP:
DCXB
; decrement B
MOV A, C
; get C value to A
ORAB
; OR A with B, if both B and C zero
JNZ LOOP
; jump if not zero, to loop
POP PSW
; get back values from stack to PSW, B
POP B
RET
; return to main program

Double click this page to view clearly

Interfacing switches and LED

Figure 2.8: Interfacing DIP switches and LED to 8255A

The

figure 2.8 shows the connection of

DIP switches and LED to 8255, which
turn

connected

to

microprocessor

8085. The switches are connected to

the port A and port C lower pins of
the 8255. The LED are connected to
the port A and port C upper pins of
the 8255. The 8255 connected to the

microprocessor as follows. The lower

address lines A1 and A0 connected
to address tines of 8255. The other
address lines are decoded to supply

the CS signal. The 8255 is connected

as a memory mapped I/O for that

the MEMR and MEMW pins from the

microprocessor is connected to the

RD and WR pins of the 8255. The

RESET

OUT

signal

from

the

microprocessor is connected to the

RESET of the 8255. The objective of
the program is to read the switches
and output the data in the LEO ports.
The 8255 is initialized as follows.
Port A output. Port B input. Port C
upper output. Port C lower input.

All the ports can be initialized in

mode 0 simple I/O mode. The
control word is 83H.

The program is listed below.

START:

MVI A, 83H
STA8003H
LDA 8001H
STA8002H
LDA 8002H

;
;
;
;
;

load the control word to A

load into the control port of 8255
get value from switches connected to port A
store value to LED connected to port B
get value from switches connected to port C L

ANI OFH
RLC
RLC
RLC
RLC
STA 8002H
HLT

; mask the higher bits of the value

; rotate four times to get value in lower to
; higher bits

; store the result in port C

; stop

Interfacing an ADC

Figure 2.9: Interfacing an ADC (AD570) to 8255A

Double click this page to view clearly

AD570 is a successive approximation

type,

8-bit,

compatible

ADC.

microprocessor
The

start

of

conversion signal is supplied through

the line B/C The start of conversion

is supplied as a positive goinsg pulse
signal atthe B/C line through port C 0 .
The end of conversion is monitored

through the B/C signal. DATAREADY

When

this

signal

goes

low,

it

indicates that the conversion is over.

The DATAREADY signal is connected

to port C 7 . The circuit connections
are shown in the figure. The 8255
is connected to the microprocessor
at the address 8000H. The address
lines A1 and AO are connected to the
address lines of the 8255. The 8255
is connected as memory mapped I/O.

The ports of the 8255 are initialized

as follows.
Port A - input. Port C upper - input.
Port C lower - output.
The control word is 98H.

The program is listed below.

START:

LXI
MVI
MOV
MVI

H,
A,
M,
A,

8003H;load memory pointer with address of 8255

98H
; load control word for 8255
A
; store in 8255 control port
01H
; configure port C in BSR mode and set PC 0

MOV M, A
; store in control port
CALL DELAY ; wait or some time
MVI A, OOH
; reset PC 0 to give the pulse to B/C#

READ:

MOV M, A
DCX H
MOV A, M

; store in control port

; decrement pointer to address port C
; get value from port C to monitor PC 7

RAL

; rotate to get PC 7 to carry

JC READ
LDA 8000H
HLT

; if carry set, execute the loop again

; get the converted value from the port A.

Double click this page to view clearly

Interfacing a DAC

Figure 2.10: Interfacing a DAC 1408 to 8085

The circuit shows the design of an

output port having address FFH and
has

DAC

connected

to

it.

The

output port has a latch connected to

the data bus and the output of the
latch is connected to the DAC input.
The DAC 1408 is an 8-bit, bipolar,
current output DAC, with a settling
time around 300ns.

The

address

consists
gate

of

and

decoding

an

eight

an

OR

circuit

input NAND
gate.

The

address lines and the IOW signals

are connected to the gates as shown
in the figure and the output is used
to enable the latch. If the latch is
enabled, the data in the data bus will
be latched to the DAC. The DAC then
converts the digital data into current
and is converted to voltage by the
op-amp current to voltage circuit. In
this circuit, the DAC is configured in
unipolar, 0 10 V range. The output
voltage for an input of OOH will be

0V and for FFH, it will be 10V. The

program

to

generate

triangular

wave in the DAC output is listed

below.
START:
UPRAMP:

MVI A, 00H
OUT FFH

NOP
NOP
NR A
CPI, OFFH
JNZ UPRAMF
DWNRAMP: OUT FFH
NOP
NOP
DCRA
JNZ DWNRAMP
JMP UPRAMF

; initialize for zero output

; output at the port FFH
; give delay for settling time of DAC
;
;
;
;
;

increment A
compare whether DAC o/p reached full scale
if no, go to up ramp
output at port FFH
give delay for settling time of DAC

; decrement A
; check DAC o/p zero, if not go to down ramp
; repeat the whole process continuously

2.4 TThe
he
h e 825
8
8254
Counter
The
timer/
time

8254

programmable

counter
delays

and

generates
can

be

interval
accurate
used

for

generating real time clocks, an event

counter, a digital one shot, a square

Double click this page to view clearly

wave

generator

waveform
includes

and

generator.
three

counters

The

identical

that

complex

can

8254
16-bit
operate

independently in six modes. It is a

24 pin device and requires a +5V
power

supply.

16-bit

value

is

loaded to the counter and is operated

either in binary or BCD count. The
8254 is pin to pin compatible to the
8253, but 8254 operates higher clock
frequency (DC to 8 MHz) than 8253
(DC to 2 MHz).

Block diagram of 8254

Figure 2.11: Internal block diagram of 8254

The block diagram is shown in the

figure 2.11, it includes three counters
(counter 0, 1, and 2), a data bus
buffer, a Read/Write control logic,
and a control register. Each counter

has two input signals CLOCK (CLK)

and GATE and one output signal
OUT.

Data Bus Buffer

This

tri-state,

8-bit,

bi-directional

buffer is connected to the data bus to

the MPU.

Control Logic

The control section consists of RD,WR

A 0 , A 1 , and CS. The RD signal is used

for reading the data in the counter

registers and status. The WR signal is

used for writing control word into the
control register and count in one of

the counters. The CS signal is used

for enabling the chip. The Address

lines A0 and A1 are used to select
one

of

the

counters

and

Control

register. The bit definition is given

below.

A1

A0

Selection

Counter

Counter

Counter

Control
Reg.

Control Register
This

register

is

used

to

write

command word describing the mode

of operation, counter selection, etc.
The bit definition is given below.

D7

D6

SC1

SC0

D5

D4

RW1

RW0

D2

D2

M2

M1

SC Select Counter
SC1: SCO

Select Counter 0

Select Counter 1

Select Counter 2

Read Back Command

D1

M0

D0

BCD

RW Read/Write
RW1: RW0

Counter Latch Command

Read/Write

least

significant

byte

only

Read/Write most significant byte

only

Read/Write feast significant byte

first, then most significant byte.

M Mode
M2: M1: M0

Mode 0

Mode 1

Mode 2

Mode 3

Mode 4

Mode 5

BCD

Binary Counter 16-bits

Binary Coded Decimal (BCD) counter (4

Decades)

Mode
The 8254 can operate in six modes
and the GATE signal is used to enable
or disable the counting.
Mode 0: in this mode, initially the
OUT is low. The count value in the
counter will be decremented every
clock

cycle

and

when

the

count

reaches zero, the OUT goes high. The

OUT remains high unitl new value is
written.
Mode 1: In this mode, the OUT is
initially high. If the GATE signal is
enabled, the OUT signal goes low and
it goes high again at the end of the
count.
Mode 2: In this mode, the timer
generates a pulse equal to the clock

period at a given interval. When a

count is loaded, the OUT stays high
until the count reaches 1 and then
it goes low for one clock period. The
count

value

automatically,

is

generating

reloaded
train

of

pulses.
Mode 3: When the count is loaded
the OUT is high, the count value is
decremented by two and when it
reaches

zero

the

OUT

signal

is

toggled. Then the count is reloaded

and the process repeats, generating
a square wave.
Mode 4: In this mode, the OUT is
initially high and it goes low at the
end of the count. To get continuous
output the count must be reloaded
manually.

Mode 5: In this mode, the count is

triggered by a rising edge (low to
high) in the GATE. The process is as
same as the mode 4.

Write Operations
The counter is initialized as follows.
1.

Write a control word into the

control register.

2.

Load the tow order byte of a

count in the counter register.

3.

Load the high order byte of the

count in the counter register.

To

start

Clock

and

enabled.

the

counter

Gate

signal

appropriate
should

be

Read Operations
The count value in the counter is read
in two methods. One in which the
counter is stopped by disabling the
GATE signal or the CLOCK input. The
count value is read two I/O read
operations for LSB and MSB of the
counter. In the second method, the
counter is read while it was running.
This method is made possible by
writing appropriate control word in
the control register.

2.5 The 8259a Programmable

Interrupt Controller
The

8259A

is

programmable

interrupt controller and can

1.

Manage

eight

according

to

interrupts

the

instructions

written in its control register.

When interfaced to 8085, the
8259A controls eight interrupt
lines and give one interrupt to
8085.
2.

Vector

any

interrupt

to

any

location unlike the 8085 vectors

the interrupts to the page 00H.
But the vectored locations must
be

spaced

locations

at
and

four
must

or

eight
be

in

sequence in any where in the

memory.

3.

Allocate eight different priorities

to

the

eight

interrupts

in

variety of modes such as fully

nested mode, automatic rotation
mode,

and

specific

rotation

interrupt

request

mode.
4.

Mask

each

individually.
5.

Read

the

status

of

pending

interrupts, in-service interrupts,

and masked interrupts.
6.

Be configured to recognize edge

or level triggered interrupts.

7.

Can be expanded to maintain 64

interrupts

and

64

interrupts

priority levels Block diagram of

the 8259a

Figure 2.12: Internal block diagram of 8259A

Figure 2.12 shows the internal block

diagram of the 8259A PIC. It consists
of: a Control Logic, a data bus buffer,
Read/Write
(IRR,

ISR,

Logic,
and

three

registers

IMR),

resolver, and cascade buffer.

priority

Control Logic
This block have two pins: INT and

INTA. The (NT is connected to the

interrupt
Whenever

INTR
the

pin

of

8259

the
detect

MPU.
an

interrupt, this signal goes high. The

INTA. signal is an input form the

microprocessor

which

microprocessor

has

informs

the

accepted

the

interrupt.

Read/Write Logic

This line have four pins: CS, RD, WR
and A 0 . The A 0 signal is used to
select write or read the command or

status. The RD and WR signals are

used along with CS# to write or read
the 829A chip.

Interrupt

Registers

and

Priority Resolver
The interrupt Request Register (IRR)
registers

all

the

eight

interrupt

requests in its eight lines.

The Interrupt Service Register (ISR)
stores ail the interrupts that are
currently being serviced.
The Interrupt Mask Register (IMR)
stores the masking of the bits of the
interrupt tines to be masked.
The Priority Resolver decides which
interrupt is to be sent to the MPU
based on the above three registers.

Interrupt Operation
The 8259 must be initialized before
starting an interrupt operation. The
8259A requires two types of control
words: Initialization Command words
(ICW)

and

Operational

Command

Words (OCW). The ICWs are used to

initialize with proper conditions and
specify RST vector addresses. The
OCWs

are

used

to

set

priority,

masking, status read operations, etc.

The following operations take place if
an interrupt arrives after the 8259A
is initialized.
1.

The IRR stores all the interrupt

requests.

2.

The priority resolver checks IRR,

ISR, and IMR and decides which
one of the interrupt requests is

to be sent to the 8085. It sets

the INT line after taking decision.
3.

The

8085

acknowledges

by

activating INTA signal.

4.

After the 8259 receives the INTA

signal, the corresponding bit in
the ISR is set to indicate the
interrupt is being served. Then
the

opcode

for

the

CALL

instruction is placed in the data

bus.
5.

When the MPU fetches the CALL

instruction,

it

gives

two

INTA

signals in the data bus.

6.

On receiving the INTA signals,

the 8259 places the address of
the vectored locations LSB first
in the data bus.

7.

During the third INTA signal, the

ISR is reset by giving Automatic
End Of Interrupt instruction or by
a command End of Interrupt.

2.6 Serial I/O

Basic Concepts
In the parallel mode of transmission
of data, the processor first enables
the peripheral by sending a control
signal and uses the entire data bus
to write or read data to or from the
peripheral. So it is necessary to get
all the data bus fines and the control
signals to peripheral. In serial mode

of data transfer, the microprocessor

uses

two

lines

to

transfer

data:

transmit and receive and two lines

to

enable

the

microprocessor

device.
selects

First
the

the

device

through chip select and the control

signals Read to receive data and
Write to transmit data.
To communicate with a peripheral
through serial transmission, the data
need to be encoded with translation
codes. The commonly used code is
the ASCII, the American Standard
Code for Information Interchange.
ASCII is a 7-bit code from 00H to 7FH
can be assigned to a letter, a decimal
number, a symbol, or a machine
command. For example, numbers 0

to 9 are represented by 30H to 39H

and

capital

letters

to

are

represented by 41H to 5AH. If a data

byte 1AH is to be coded, it results
two ASCI I codes, 31H and 41H.

Synchronous

and

Asynchronous Transmission
Serial communication can be done in
two

ways:

either

Asynchronous

Synchronous

or

modes.

In

synchronous mode, the transmitter

and

receiver

are

synchronized

by

some clock signal. The block of data,

to be transmitted, is transmitted with
the synchronization information. This
format is very effective when used
for very high-speed transmission. In

Asynchronous

mode,

the

data

is

transmitted in fixed rate called baud

rate.

The

bit

time

the

delay

between any two successive bits is

calculated as follows.
Assume the baud rate is 1200.
1200 bits = 1 second. For 1 bit = 1/
1200 =0.83 ms.
The data is first framed with start
and stop bits and transmitted. The
receiver

will

also

work

on

the

particular baud rate. On receiving the

start bits, the receiver knows that
the transmitter is transmitting data
through the lines. The receiver stops
receiving

the

data

when

it

has

received the stop bit. But when the

stop bit is not received at expected

time, the receiver raises the framing
error signal to the CPU of the system.
THE 8085 SERIAL I/O LINES: SOD
AND SID
The 8085 has two pins: SID and SOD
for serial reception and reception.
These two lines are controlled by two
instructions: RIM and SIM, which are
used
serial

for

two

and

different

interrupt.

purposes:
The

two

instructions are used to read and

mask the status of each interrupt.
And also they are used to send and
read data to and from the SID and
SOD lines.

The following program discusses the

operation of SIM instruction.
MVI A, 80H

; set D 7 in the accumulator = 1

RAR

; set D 6 = 1 to enable serial data output

SIM

; output D 7

The D6 bit is set to enable the serial

data out. Once it has been enabled,
the

SIM

instruction

transmits

the

data in the D7 bit through the SOD

line.
The RIM instruction reads the SID
line and places it in the bit D 7 of the
accumulator.

Double click this page to view clearly

The

8251a

Programmable

Communication Interface

Figure 2.13: Internal block diagram of 8251A

The 8251A is a programmable chip

designed

for

asynchronous

synchronous
serial

and
data

communication. It has five sections:

Read/Write
Transmitter,

Control
Receiver,

Logic,
Data

Bus

Buffer,

and

Modem

Control.

The

control logic interfaces the chip with

the MPU, determines the operation
of the chip according to the control
word written to it. The transmitter
section converts the parallel data
form the MPU and converts to Serial
data and sends to external devices.
The receiver section converts the
serial data from the external devices
to parallel data. The modem control
is

used

to

communication

establish
through

data
modem

through telephone lines. The 8251A

includes the interfacing signals, the
control
register.

register,
The

and

functions

the
of

status
various

blocks are described as follows.

Read/

Write

Control

Logic

And Registers
Input Signals

CS Chip Select: When this signal

goes low, the 8251A is selected by
the MPU for communication. This is
usually

connected

to

decoded

address bus.

C/D Control/Data: When this signal

is high, the control register or the
status register is enabled, and when
this signal is low the MPU accesses
the data buffer.
WR Write: When this signal goes
low, the microprocessor is writing a
data byte into the control register or
data buffer.


RD Read: This is an active low
signal used to read the data from the
data buffer or the status from the
status register.
RESET This is active high signal and
a high in this line resets the chip.
CLK Clock: This is a clock input.
The

clock

is

communication

necessary
with

for
the

microprocessor.
Control Register This is a 16-bit
register
bytes:

having
one

is

two
called

independent
as

mode

instruction and the second is called

as command instruction.

Status Register This is also a 16-bit

register and has the status of the
chip. The control and status register
have

same

address

and

are

differentiated by the RD# and WR#

signals.
Data Buffer This is bi-directional
register can be addressed as an input
or an output port. The chip stores the
data from the peripheral in the data
buffer and also the MPU stores the
data to be transmitted in the data
buffer.

Transmitter Section
The transmitter section accepts the
parallel data from the MPU and
converts into serial data.

The transmitter

section

two

registers:

and

an output register. The buffer

register

is

contains

used

buffer

for

register

holding

the

data from the MPU and the output

register converts the

parallel

data

into serial data. The MPU writes the

data, which is to be transmitted
the

data

output
whenever
of

data,

buffer. Whenever

register
it

is

empty

to
the
i.e.,

completes the transfer

the

data

buffer transfers

the data stored in it, to the output

register.
provide

The
the

output

register will

necessary

start

and

stop bits to the data to inform the

beginning

and

respectively.

end

of

the

data

TXD Transmit Data: Serial bits

are transmitted on this line.

TXC Transmitter Clock: This input

signal controls the rate at which the
data is transmitted by the USART.
TXRDY Transmitter Ready: This
signal indicates the MPU that the
transmitter

has

finished

the

transmission and is ready for another

data. This signal is reset when the
MPU writes a new data to the chip.
TXE
signal

Transmitter
indicates

that

Empty:
the

This

output

register is empty. And this signal will

be reset when the data is transferred
from the buffer to output register.

RECEIVER SECTION

The receiver accepts the data from

the RXD line from a peripheral and
converts them into parallel data. This
section

has

two

registers:

the

receiver input register and the buffer

register.
When the RXD line goes low, the
control logic checks for another half
a bit time. If it remains low, it takes
it as start bit and samples eight bits
and toads into the buffer register.
The parallel data will be transferred
to MPU if requested.

RXD Receive Data: This is an

input terminal, which receives the
bits

serially

and

converts

to

the

parallel data.

RXC Receiver Clock: This is a

clock signal, which controls the data
flow rate.
RXRDY Receiver Ready: The line
is used to indicate the receiver is
ready.

UNIT III
8086 ARCHITECTURE AND
SYSTEM COMPONENTS

3.1 8086 Microprocessor

The Intel 8086 microprocessor is a
16-bit processor. The 8085 is a 8-bit
processor

and

it

can

perform

operations on 8-bit data so that it has

8-bit wide registers and 8-bit wide
data

bus.

Being

a16-bit

microprocessor, the 8086 have 16-bit

wide registers, and a 16-bit wide
data bus so that it can store or read a
16-bit data to and fro the memory in
one machine cycle. The address bus
is 20-bit wide and can address up to
2

20

= 1 MB memory locations.

Internal Architecture of 8086

Figure 3.1: Internal architecture of 8086

The internal architecture is shown in

the figure 3.1. The microprocessor
has mainly two parts: Execution Unit
(EU) and the bus interface unit (BIU).

EXECUTION UNIT (EU)

The

EU

contains

an

instruction

decoder, 16-bit arithmetic and logic

unit (ALU), a 16-bit flag register,
eight 8-bit general-purpose registers
and two index registers.
The Instruction decoder decodes the
instruction fetched by the BIU and
the EU executes it.
The

Arithmetic

and

Logic

Unit

performs the various operations like

addition, subtraction, multiplication,
division and loci operations like AND,
OR, XOR, and rotation.
The Flag register is 16-bit wide,
indicates the status of the results in

arithmetic and logic operations. This

is similar to flag register in 8085, but
the 8086 uses 9-bits, of which six are
used for checking out the status of
the result. The six conditional flags
are carry flag (CF), parity flag (PF),
Auxiliary flag (AF), zero flag (ZF),
sign flag (SF), and overflow flag
(OF). The other three flags are trap
flag (TF), interrupt flag (IF), and
direction flag (DF).
There are totally eight 8-bit wide
General-purpose

registers.

These

registers are AH, AL, BH, BL, CH,

CL, DH, and DL. These registers are
used as individual registers as well
as 16-bit register pair with other
registers. The AL and AH registers

are combined to form AX pair and is

called the Accumulator.
The EU contains four 16-bit registers:
stack pointer (SP), base pointer (BP),
source index (SI), and destination
index (Dl).
BIU
The

BIU

controls

all

the

bus

operations. It sends out the address

and the data in the address and data
buses to access the memory and the
I/O devices.

The Queue
The BIU contains six registers used
as

temporary

storage.

These

registers work as first in first out.

The BIU fetches the instructions and
loads in the queue. The EU executes
the instructions one by one from the
queue

while

BIU

fetches

the

instructions and loads the queue.

This minimizes the time required and
the method is called pipelining.

Segments and offsets

The 8086 microprocessor has 20-bit
address bus and can address up to
1MB. The total memory is divided
into 4 segments viz: Data, Code,
Stack,

and

Extra

segments.

Each

segment is 64k wide and is addressed

by a 16-bit segment address. Each
location in a segment is addressed

by another 16-bit address, which is

called

the

offset

address.

Each

location in the 1 MB memory will

have a 16-bit segment and 16-bit
offset address. The 20-bit physical
address

will

be

calculated

by

multiplying the segment address by

16 and adding the offset address to
it.

Segment registers
The BIU has four segment registers
viz: Code, Stack, Data, and Extra
segment registers.
Code segment CS: The instructions
are loaded into the Code segment
and the segment is identified by the

CS register. The BIU has a instruction

pointer IP and it holds the offset
address to the next instruction that is
to be executed. The 20-bit address of
the instruction is calculated using the
CS and IP.
SS register: The stack is a set of
memory locations used for storing
temporary data and addresses. The
SS

register

holds

the

segment

address of the stack and the offset

address is pointed by another 16-bit
register SP.
DS register: The data segment is
used to store data. The segment
address

of

the

data

segment

is

loaded in the DS register. The offset

address of a data in the data segment

can be pointed by any of the registers
such as, SI, Dl, BP, etc.
ES register: The ES register is an
additional

data

segment

used

for

storing data. The address is loaded to

the ES and the offset can be pointed
by

some

of

the

general-purpose

registers.

Advantages

of

the

segmentation scheme
The memory of the 8086 is 20-bit
wide

and

with

the

help

of

the

segmentation scheme, the address

can

be

registers.

pointed

by

two

16-bit

The programs are re-locatable, i.e.,

the

jump

instructions

uses

the

relative address and not the absolute

address.

So

the

program

can

be

loaded any where in the memory by

simply

changing

the

segment

registers.

3.2 Addressing Modes

The addressing modes of the 8086 is
divided into nine types,
1.

Immediate addressing mode

2.

Memory addressing mode

3.

Register addressing mode

4.

Direct addressing mode

5.

Register
mode

Indirect

addressing

6.

Based addressing mode

7.

Indexed addressing mode

8.

Based Indexed addressing mode

9.

Port addressing mode

Immediate addressing mode

The 8-bit or a 16-bit data is provided
in the instruction itself. The data will
be present next to the instruction
code in memory. E.g. MOV AL, 12H,
which copies the 8-bit data to the AL
register.
MOV CX, 1234H, which copies the
16-bit data 1234H to the CX register.

Register addressing mode

The data is specified as a register
and register holds the data to be
manipulated.
e.g.

MOV

CX,

AX

copies

the

contents of the AX register to the CX

register.
MOV DL, BH copies the contents
of

the

BH

register

to

the

DL

register.

Memory addressing mode

One of the operands in an instruction
is a memory location. The address
of

the

memory

location

can

be

represented in one of 24 ways. The

segment address is derived from any

of the segment register and the

execution unit provides the offset
address.
E.g. MOV [BX], AX copies the
content of AX to the memory location
pointed by the BX register.

Direct addressing mode

The

16-bit

memory
represented

offset
location
as

address
is
part

of

directly
of

the

instruction.
E.g. MOV AX, [1234] copies the
contents of memory location 1234H
to the AX

Register indexed addressing

mode
In this mode, one of the base and
index registers (BP, BX, SI, Dl) is
used to hold the address of a memory
location.
E.g.

MOV

contents

AX,
of

[SI]

the

Copies

memory

the

location

pointed by the SI to the AX.

Based addressing mode

In

this

mode,

the

address

is

calculated by adding the 8-bit or

16-bit value and the content of base
register in the instruction.
E.g. MOV AX, d8 [BX] or MOV AX, d16
[BX]. The value d8 or d16 is added

with the BX register and the

memorylocation pointed by the
resulting
address is accessed and the content
is transferred to the AX.

Indexed addressing mode

The memory location is pointed by
any of the index register such as SI.
E.g.

MOV

AX,

[SI].

Copies

the

contents of the memory pointed by

the SI register to the AX.

Based

indexed

addressing

mode
The memory location is calculated by
adding an 8-bit or 16-bit, the content
of the base register and the content
of index register.

E.g.

MOV

AX,

d8[SI][DI].

The

address is calculated by adding the

8-bit d8 or 16-bit data d16, to the
SI and Dl and the resulting memory
location is accessed.

Port addressing mode

This mode uses an 8-bit address to
access the I/O devices. The address
of the device is directly given in the
instruction.
E.g. IN AL, 02H. The I/O device
having
accessed

the

address

and

the

of

02H

content

transferred to the AL register.

is
is

3.3 Instruction Set

The instruction can be divided into
six types: data transfer, arithmetic,
bit

manipulation,

string,

branch

control, iteration control, interrupt,

and processor control instructions.

Data transfer instructions

The

data

transfer

transfer

data

instructions

between

registers,

memory locations and I/O devices.

Some

of

the

data

transfer

instructions are listed below.

MOV

Copies

data

from

destination,

destination to source

source
PUSH

Stores the word data in the

source

source
stack

in

the

stack,

pointer

decremented by 2.

the
is

POP

Retrieves

destination

from the stack and toads

into

the

the

word

data

destination

register. The stack pointer

is incremented by 2.

XCHG

Exchanges the data in the

destination,

destination and source

source

XLAT

Translates from one code to

another. On condition that
the BX is pointing a look
up

table.

This

instruction

simply adds the contents of

the location pointed by BX
with AL and stores the data
in AL.
LEA

Computes

the

effective

register,

address of the source and

source

stores in the register.

LDS

Copies

two

consecutive

register,

words

memory

pointed by the register and

from

the

memory

store the least significant

word

in

register

the

specified

and

the

most

significant word in the DS

register.

LES

Copies

two

register,

words

memory

stores in the register and

from

consecutive
memory

and

the ES register.

IN AL, dd

Copies the byte content of

the input device specified
by

the

address

ddH

and

stores it in AL.

OUT DX, AX

Copies the word in AX and

outputs

to

the

output

device specified by the DX

register.

Arithmetic instructions
The

arithmetic

perform

instructions

addition,

multiplication,

and

can

subtraction,
division.

These

instructions change the contents of

the

flag

register.

The

arithmetic

operations are listed below.

ADD

The contents of the source

destination,

and

source

are added and the result is

destination

stored

in

the

registers

destination

register.

ADC

The contents of the source

destination,

and destination are added

source

with carry and the result is

stored

in

register.

the

destination

INC

The

content

destination

destination

of

register

the
is

incremented by one and the

result

is

stored

in

the

destination register.

AAA

ASCII adjust after addition.

The result in the AL register
is adjusted to ASCII.

DAA

The result in the AL register

is adjusted to BCD while
doing BCD addition.

SUB

The content of the source

destination,

register is subtracted from

source

the destination register and

the result is stored in the
destination itself.

SBB

The contents of the source

destination,

is

source

destination with borrow and

subtracted

from

the

the result is stored in the

destination

DEC

The

content

of

the

destination

destination

register

decremented

by

one

is
and

the result is stored in the

destination.

AAS

The result in the AL after

subtraction is adjusted to
ASCII.

DAS

The result in the AL after

subtraction is adjusted to
BCD.

NEG

Computes

destination

complement of the contents

in

the

stored

the

destination
in

the

2's

and

is

destination

register.
MUL source

Multiplies the content of the

source with AL and stores
the result in AX register for
8-bit
16-bit
content

multiplication.
multiplication,
of

the

source

For
the
is

multiplied with the AX and

result is stored in the AX
and DX registers.

IMUL

This

performs

the

signed

multiplication.

AAM

ASCII

adjust

after

multiplication.
instruction

This

perform

the

operation only on the AL.

DIV source

Divides the AL or AX by the

source

and

stores

the

quotient in AL or AX and the

remainder in AH or DX

IDIV

Perform signed division

AAD

ASCII adjust after division.

Bit manipulation Instructions

The

bit

manipulation

instructions

perform operations like logical AND,

OR, NOT, and X-OR functions, and
compare,

test,

rotate,

and

shift

functions.

NOT

Inverts the contents of the

destination

destination and stores the

result

in

destination

register

AND

Logically ANDs the contents

destination,

of source and destination

source

and the result is stored in

the destination register

OR

Logically ORs the contents

destination,

of

source

destination and stores the

the

results

in

source

the

and

destination

register.

XOR

Logically XORs the contents

destination,

of

source

destination and stores the

the

results

in

source

the

and

destination

register.

TEST

Logically ANDs the contents

destination,

of

source

destination

the

source
and

and

registers

are not altered. Only the

flags are altered.

SHL

The

content

of

destination,

destination

count

shifted to left side by count

register

times. Puts 0's in LSB

the
is

SAL

The

content

of

the

destination,

destination

count

shifted to left side by count

register

is

times. Copies the old LSB in

the LSB position.

SHR

The

destination,

destination

count

shifted
count

content

to

of

the

register
right

times.

is

side

Puts

by

0s

in

MSB

SAR

The

content

destination,

destination

count

shifted

to

of

the

register
right

is

side

by

count times. Copies the old

MSB in the MSB position.

ROL

The

content

destination,

destination

count

rotated

register

through

count times.

of

left

the
is
by

RCL

The

destination,

destination

count

rotated
count

content

of

register

through
times

the
is

left

by

through

the

carry flag.

ROR

The

content

destination,

destination

count

rotated

of

register

through

right

the
is
by

count times.

RCR

The

destination,

destination

count

rotated
count

content

of

register

through
times

the
is

left

by

through

the

carry flag.

String Instructions
String is a series of ASCII codes in
the memory. The String instructions
perform string operations like copy,
compare, load, and store functions.

MOVS/

Copies the CX number of bytes/

MOVSB/

words from DS:SI into ES:DI

MOVSW

CMPS/

Compares

the

CX

CMPSB/

bytes/words

CMPSW

ES:DI The zero fag wilI be set if

from

number
DS:SI

of

into

the two strings are alike.

LODS/

Copies a string byte from string

LODSB/

location pointed to by SI in DS

LODSW

to AL

STOS/

Copies a string byte from AL to

STOSB/

a location pointed to by SI in

STOSW

DS.

SCAS/

Compares byte or word in AL/

SCASB/

AX with byte or word in ES:DI

SCASW

Branch Control Instructions

The branch instructions are used to
transfer the execution of the program
to

various

instructions

locations.
are

The

branch

classified

into

conditional and un-conditional jump

instructions.

JMP addr

Unconditional

jump

instructions. The addr is 8-bit

and

16-bit

displacement

or

segment.offset.

JA/JNBE

Jump if above/ jump if not

below or equal.

JAE/JNB/

Jump if above or equal/ jump

JNC

if not below/ jump if no carry.

JB/JC/

Jump if below/ jump if carry/

JNAE

jump if not above or equal.

JBE/JNA

Jump if below or equal/ jump

if not above.

JCXZ

Jump if CX is zero.

JE/JZ

Jump if equal/jump if zero.

JG/JNLE

Jump if greater/jump if not

less than or equal.

JGE/JNL

Jump if greater than or equal/

jump if not less than.

JL/JNGE

Jump if less than/ jump if not

greater than or equal.

JLE/JNG

Jump if less than or equal/

jump if not greater than.

JNE/JNZ

Jump if not equat/jump if not

zero

JNO

Jump if no overflow flag is set

JNP/JPO

Jump if no parity/ jump if

parity or overflow

JNS

Jump if not signed

JO

Jump if overflow

JP/JPE

Jump if parity/ jump if parity

even

JS

Jump if signed

CALL

Call subroutine in the address

procedure

specified by procedure.

RET

Return form subroutine.

The CALL instruction works as same

as in 8085. On reading the CALL
instruction,

the

microprocessor

stores the content of the instruction

pointer IP in the stack. The stack

pointer

SP

is

updated.

Then

the

microprocessor jumps to the location

specified in the instruction. At the
end of the subroutine RET instruction
should be present. On reading the
RET instruction, the microprocessor
retrieves the address from the stack
and jump to the main program.

Iteration control instructions

The

iteration

control

instructions

execute a series of instructions many

times until a condition is achieved.

LOOP

Decrements

CX

register

and

label

branches to address specified

by label, when CX is not equal
to zero.

LOQPZ

Decrements

CX

register

and

label

jumps to address specified by

label, if CX not equal to zero
and ZF = 1.

IOOPNE/

Decrements

CX

register

and

LOOPNZ

jumps to address specified by

label

label, if CX not equal to zero

and ZF = 0.

JCXZ

If CX is zero branch to label.

label

Interrupt Instructions
The interrupt instructions branch the
execution to some subroutines in the
memory. These instructions provide
software interrupts.

INT

Executes

the

interrupt

service

type

routine for the particular interrupt

type.

INTO

Executes

the

interrupt

service

routine on overflow flag is set.

IRET

Return

from

interrupt

service

routine.

Processor control instructions

The processor control instructions set
or

reset

the

carry,

direction

interrupt flags in flag register.

STC

Set CF

CLC

Clear CF

CMC

Complement CF

STI

Set IF

CLI

Clear IF

and

 
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Editor
Editor is used to type the assembly
language

programs

and

the

file

should be stored with the extension

.ASM.

Assembler
The assembler reads the text form
typed

programs

and

coverts

into

binary codes and creates two files

with extension .OBJ and .LST.

Linker
The linker produces the .EXE file with
the help of .OBJ files. The executable
files can be loaded into the memory
and executed.

Debugger
The debugger program enables the
program

to

be

loaded

into

the

memory and be executed. Using the

debugger suitable breakpoints can be
introduced.

Assembler Directives
The

MAS

assembler

instructions,

needs

excluding

some
the

instructions of the processor, to be

added

to

the

program.

These

instructions are called as assembler

directives.
shows

The
simply

example

program

loading

accumulator with the data.

the

Example 1.
DATA
VALUE
DATA
CODE
START:

CODE

SEGMENT
DB 1AH
ENDS
SEGMENT
ASSUME
MOV AX,
MOV DS,
MOV AL,
INT 03H
ENDS
ENDS

CS: CODE, DS: DATA

DATA
AX
VALUE

START

SEGMENT and ENDS

The assembler directives SEGMENT
and ENDS are used to group data
items or instructions in the program.
Group

of

statements

contained

between the two directives is called

a logical segment. The statements

Double click this page to view clearly

DATA
create

SEGMENT
one

and

DATA

ENDS

and

CODE

segment

SEGMENT and CODE ENDS create

another segment and are allocated
with different memory locations. The
DATA segment contains the data and
the

CODE

segment

contains

instructions.

DB, DW, DD
The define byte DS, define word
DVV and define double word DD
directives are used to assign names
to variables of 8-bit, 16-bit, and
32-bit

data.

For

example

DB

instruction allocates a byte memory.

EQU: This directive is used to assign

names to constants.
ASSUME: This directive informs that
the logical segments contains the
code, data, and stack segments.
LABEL: This

directive

is

used

to

assign a name to an address.

END:

This

directive

stops

the

assembler from further coding.

PROC and ENDP:

The

procedure

directive PROC is used to inform the

start of a subroutine. The directive
ENDP is used to inform the end of a
subroutine.

EXTERN,

PUBLIC,

and

GLOBAL:

EXTERN informs the assembler that

the labels or names are found in
some other modules. PUBLIC informs
the assembler that the names or
labels following it can be used by
other modules. GLOBAL can be used
in the places of EXTERN and PUBLIC.
OFFSET:

OFFSET

informs

the

displacement value from the start of

the segment. PTR: PTR is used to
specify

the

type

of

the

pointer

whether it is byte pointer or word

pointer.

Programming example 2:
The program to find the largest in a
string of numbers is given below.
DATA

SEGMENT
LENGTH
DW 0005H
VALUES
DB 00H, 07H, 02H, 03H, 09H
LARGE
DB 1 DUP (0)
DATA ENDS
CODE SEGMENT
ASSUME DS: DATA, CS: CODE
START:
MOV AX, DATA
; transferring the segment address to AX
MOV DS, AX
; transferring from AX to DS
MOV CX, LENGTH
;initializing CX register with length
MOV SI, OFFSET VALUES;loading the starting address of
;string to SI
MOV AL, BYTE PTR [SI]; getting I value to AL
LOOP1:
INC SI
; incrementing the pointer
CMP AL, BYTE PTR [SI]; compares I value with II value
JNC LOOP2
; if 1 value > II value go to LOOP2
MOV AL, BYTE PTR [SI]; or replace the 1 value with II value
LOOP 2:
LOOP LOOP1
; stay in loop until CX = 0
MOV LARGE, AL ; when the loop is over, transfer the ;value in AL in LARGE
INT 03
; break
CODE ENDS
END START

Programming example 3:
The program to find whether two
strings are matching is given below.

Double click this page to view clearly

If the two strings are matching, OFFH

must

be

loaded

to

the

location

RESULT and if not, 00H must be

loaded to it.
DATA

DATA

SEGMENT
STRING1
STRING2
LENGTH
RESULT
ENDS

DB
DB
DB
DB

01, 02, 03, 04, 05

01, 02, 03, 04, 05
05
?
; allocates one byte location for resuit

CODE

SEGMENT
ASSUME CS: CODE, DS: DATA
START:
MOV AX, DATA
; stores the segment address in AX and
MOV DS, AX
; then to DS
MOV SI, OFFSET STRING1 ; loading address of the I string
MOV DI, OFFSET STRING2 ; loading address of the II string
MOV CL, LENGTH
REPE CMPSB
JNZ
MOV
INT
LOOP1:
INT
CODE ENDS
END

;
;
;
LOOP1
;
RESULT, 0FFH
;
03H
;
MOV RESULT, 00H;
03H
;

loading the length of the strings

compares two strings from star to
end and if equal zero flag will set
if zero flag is not set, go to LOOP1
if not set, load OFFH to result
break
load 00H to result
break

START

Double click this page to view clearly

Programming example 4:
The program for reversing the bits of
a byte is given below.
DATA

SEGMENT
VAL
DB0A3H
DB 1 DUP (0)
REV
DATA ENDS
CODE SEGMENT
CS: CODE, DS: DATA
ASSUME
START:
MOV AX, DATA
MOV DS, AX
MOV CX, 0008H
SUB BL, BL
MOV AL, VALUE
LOOP1:
ROR AL, 01H
RCL BL,01H
LOOP LOOP1
MOV REV, BL
INT 03H
CODE ENDS
END
START

3.5 Passing Of Parameters

Through Procedures

Procedures are sub programs that are

called from the main program. The
procedures receive parameters from

Double click this page to view clearly

main program, process, and send

back the processed data to main
program. Parameters can be passed
in four methods: through registers,
through memory locations, through
pointers in register or through stack.
Passing

parameters

registers:

Program

square

of

number

through

to
by

compute
passing

parameters through registers is given

below.

Programming example 5:
DATA

SEGMENT
VALUE DW 0123H
SQUARE
DW 2 DUP (0)
DATA ENDS
STACKSEGMENT STACK
DW
20 DUP (0)
TOP_OF_STACK
LABEL WORD
STACKENDS
CODE SEGMENT

Double click this page to view clearly

ASSUME

CS: CODE, DS: DATA

START:
MOV AX, DATA
MOV DS, AX
MOV AX, STACK
MOV SS, AX
MOV SP, OFFSET TOP_OF_STACK
MOV AX, VALUE
CALL SQUARE
MOV SI, OFFSET SQUARE
MOV WORD PTR [SI], AX
INC SI
INC SI
MOV WORD PTR [SI], DX
INT 03H
SQUARE
PROC NEAR
PUSHF
MUL AX
POPF
RET
SQUARE
ENDP
CODE ENDS
END
START

In this program, square of a data

stored in VALUE is computed. The
stack is to be initialized so that on
calling

the

microprocessor

subroutine

the

can

the

store

addresses in the stack. At first, the

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data is loaded into the accumulator

AX and the subroutine is called using
CALL instruction. In the subroutine,
the content of the flag register is
saved in the stack and retrieved back
on returning to the main program.
The MUL AX instruction multiplies the
AX with itself. The result is stored
in AX and DX. Then the sequence
is return to the main program. Thus
the data are transferred through the
registers AX and DX.
Passing Parameters Through Memory

Programming example 6:
CODE SEGMENT
ASSUME

CS: CODE, DS: DATA, SS: STACK

START:
MOV AX, DATA
MOV DS, AX
MOV AX, STACK

Double click this page to view clearly

MOV SS, AX
MOV SP, OFFSET TOP_OF_STACK
CALL SQUARE
INT 03H
SQUARE
PROC
NEAR
PUSHF
PUSH AX
MOV AX, VALUE
MUL AX
MOV SI, OFFSET SQUARE
MOV WORD PTR [SI], AX
INC SI
INC SI
MOV WORD PTR [SI], DX
POP AX
POPF
RET
SQUARE
ENDP
CODE ENDS
END
START

The

values

memory.
values

In
are

are

passed

the

subroutine,

retrieved

through

from

the
the

memory, loaded into the AX register

and then multiplied. The result is
again stored in the memory.

Double click this page to view clearly

Passing Parameters Through

Pointers
Programming example 7:
CODE SEGMENT
ASSUME

CS: CODE, DS: DATA, SS: STACK

START:
MOV AX, DATA
MOV DS, AX
MOV AX, STACK
MOV SS, AX
MOV SP, OFFSET TOP_OF_STACK
MOV SI, OFFSET VALUE
MOV DI, OFFSET SQUARE
CALL SQUARE
INT 03H
SQUARE
PROC
NEAR
PUSHF
PUSH AX
MOV AX, WORD PTR [SI]
MUL AX
MOV WORD PTR [DI], AX
INC DI
NC DI
MOV WORD PTR [DI], DX
POP AX
POPF
RET
SQUARE
ENDP
CODE ENDS
END
START

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The pointers are initialized to point at

the location VALUE and SQUARE. And
then the subroutine is called from the
main program.

Passing Parameters Through

Stack
CODE

SEGMENT
ASSUME CS: CODE, DS: DATA, SS: STACK
START:
MOV AX, DATA
MOV DS, AX
MOV AX, STACK
MOV SS, AX
MOV SP, OFFSET TOP_OF_STACK
MOV AX, VALUE
DEC SP
DEC SP
PUSH AX
CALL SQUARE
POP AX
POP DX
MOV SQUARE, AX
MOV SQUARE + 2, DX
INT 03H
SQUARE
PROC
NEAR
PUSHF
PUSH AX
PUSH BP

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MOV BP, SP
MOV AX, [BP+8]
MUL AX
MOV WORD PTR [BP+8], AX
MOV WORD PTR [BP+10], DX
POP BP
POP AX
POPF
RET
SQUARE
ENDP
CODE ENDS
END
START

The values are passed by pushing the

data into the stack in main program
and

are

retrieved

from

the

subroutine.

3.6 8086 Pins And Signals

The

microprocessor

8086

has

20

address lines to support its 20-bit

addressing

mode.

Among

the

20

address lines, the lines A 0 to A 15 are

multiplexed with data lines D 0 to D 15 .

Double click this page to view clearly

The microprocessor can be operated

in two ways: maximum and minimum
mode. The maximum mode is chosen
in

multiprocessor

single

systems

processor

microprocessor

is

and

systems,
operated

in
the
in

minimum mode. The microprocessor

is housed in a 40-pin DIP package as
shown in the figure 3.2.

Figure 3.2: Pins and Signals of 8086 Common Signals


MN/MX:

Logic

high

selects

the

minimum mode and logic low selects

the maximum mode operation
AD 0 AD 15 : Multiplexed address
and data lines. When ALE is high, the
lines carry address lines and when
ALE is low, the lines carry data lines.
A 16

/S6

A 19 /S3:

Multiplexed

address and status pins. When ALE

is high, the lines carry address lines
and when ALE is low, they carry
status lines.

BHE/S7:

Multiplexed

Bus

High

Enable/ Status line. It works as same

as above. BHE will be active if the
microprocessor
memory bank.

accesses

the

high


RD:

This

line

goes

low,

if

the

microprocessor reads a data from

memory or I/O device.
READY:

The

communicates
responding

microprocessor
with

external

the
devices

slow
using

this signal.
NMI, and INTR: The Non-Maskable
Interrupt and interrupt request. On
receiving the interrupts from these
lines the microprocessor jumps to
specific location. The NMI cannot be
masked and INTR can be masked
using program.


TEST: When this line is high the
microprocessor

reads

the

WAIT

instruction as NOP. When this line

is low, the microprocessor will wait,
while executing it, until the signal
goes high.
RESET: Resets the microprocessor
and the instruction pointer is loaded
with zero. CLK: The clock signal
provides

the

clock

required

for

microprocessor operation.
V cc , and GND: The supply +5V and
ground lines.
Minimum mode signals

M/IO: This signal goes low for I/

O read or write and goes high for
memory related operations.

WR: This signal goes low, if the

microprocessor writes a data into the
memory or an I/O device.
ALE: This signal goes high if the
multiplexed address, data and status
lines holds the address. This signal is
used as a latch enable signal.

DT/R::

This

signal

indicates

the

direction of data flow. When high, the

data is from microprocessor to I/O
devices and vice versa.


DEN: This signal enables the external
data bus buffers for data activity on
AD15 to AD0.

INTA: This pin is asserted as an

acknowledgement

to

the

INTR

request from the peripheral.

HOLD, and HLDA: These two are
used for DMA access. The peripheral
will send its request through HOLD
and

the

microprocessor

will

acknowledge it through HLDA.

Maximum mode signals

RQ/GT1,RQ/GT0: In multiprocessor
systems, the other processors sends
their requests for the bus control
through this request lines and the
microprocessor gives granted signals
through the same lines.

QS1

QS0:

The

microprocessor

indicates the queue status in these

lines.

S2, S1, S0 The status lines indicate
the type of current bus cycle.
S2:S1:S0

BUS CYCLE

000

Interrupt acknowledge

001

I/O read

010

I/O write

011

Halt

100

Opcode Fetch

101

Memory Read

110

Memory Write

111

Inactive

Lock: The lock signal prevents other

bus masters gaining control of the
system buses.

Bus cycles
The

microprocessor

instruction

and

fetches

executes

it,

an
the

period taken to complete execution is

an instruction cycle. The operation of
memory read is as follows.
The

microprocessor

places

the

address A19 A0 on the multiplexed

address

bus

and

enables

the

ALE

signal in the first T state. Then in

the next T-state, the RD# signal is
asserted
operation.

as

it

is

memory

read

The DT/R# signal is maintained low

since the data transfer is towards
microprocessor. The DEN# signal will
be kept low for the reading period.
The operation of memory write is as
follows.
The

microprocessor

places

the

address A19 A0 on the multiplexed

address bus and enables the ALE
signal in the first T state. Then
in the next T-state, the WR# signal
is asserted low as it is a memory
write operation. The DT/R# signal is
maintained

high

since

the

data

transfer is towards microprocessor.

In the second T-state the data, which
has to be written, is placed on the
data bus.

Figure 3.3: Timing of Memory Read and Memory Write

machine cycles

3.7 Basic System Components

The

microprocessor

based

system

needs several components like clock

generator,

buffers,

latches,

bus

controllers, and decoders.

Clock Generators
The

clock

generator

provides

the

CLK, RESET, and READY signals. The

figure

shows

the

clock

generator

8284 connected to the MPU.

Figure 3.4: Interfacing Clock generator 8284A to 8086

Two pairs of Ready (RDY1 and RDY2)

signals

and

(AEN1 and AEN2)

Address

Enable

control

READY

input. If one of the two signals in

both input pairs is made inactive, the
READY output goes low.
The X1 and X2 pins are connected to
a crystal.
The OSC is the buffered oscillator

output.
CLK and PCLK are the clocks used
for microprocessor and peripherals
respectively.
EFI permits the usage of external
frequency inputs.
F/C selects the crystal or external
frequency input.
CSYNC

is

used

to

provide

synchronization if EFI is used.

RES and RESET are used to provide
the reset input for the MPU.

Bus

buffering

and

de-

multiplexing circuits
The

bus

buffering

and

de-

multiplexing circuit is shown in the

figure. The microprocessor places the

address in the multiplexed address

bus and asserts the ALE signal. The
ALE signal enables the buffers the
U5, U4, and U3 (74LS373) to latch
the address lines and the BHE line.
The bus AD15 to ADO is connected
to two bi-directional buffers U1 and
U2

(74LS245).

These

buffers

are

controlled by the DT/R and DEN lines.

When the DIR pin is maintained high,
the buffer acts as a output port and
when it is maintained low, it act as
a input port. The control signals IOR,

IOW MEMR, and MEMW are generated

by the decoding the signals M/IO,

WR and RD
buffer

using

(74LS244)

decoder (74LS138).

unidirectional

and

an

octal

Figure 3.5: Bus buffering and Decoding of 8086

Bus controller
Inthe maximum mode, the control
signals

such

as

INTA , ALE , DEN, DT/R, M/IO, WR and
HOLD

are

not

available.

bus

controller 8288 is used to generate

these control signals using the status
signals

S2, S1, S0

.The

8288

generates two types of signals viz:

command

signals

(MRDC, MWTC, IORC and IOWC)

and

IOWC using the status signals, and

the

control

signals

(DT/R,DEN,ALE, MCE/PDEN) using the
AEN, CLK, CEN, and IOB inputs from
the

MPU.

The

bus

controller

is

connected to the MPU as shown in the

figure.

Figure 3.6: Interfacing 8288 bus controller to 8066

Address Decoding
The

address

decoding

in

microprocessor based system can be

done in various ways such as using
simple decoder, PROM decoder, and
PAL decoder. Simple Decoder
The method uses a simple decoder
like 74LS138 (3 to 8 decoder), which
requires three inputs and gives out
eight outputs. The figure shows the
address decoding by 74LS138. The
signals A19 to A16 are used to enable
the chip's gate enable signals. The
lines A15, A14, A13 are used to
generate the chip enable signals for
the addresses as shown in the figure.

Figure 3.7: Address decoding by 3 to 8 decoder

PROM Decoder
The

PROM

is

programmable

memory, where the address decoding

logic can be programmed. The PROM
shown the figure needs eight address
inputs to address its 256 locations
and the width of data lines is 4-bit.
Each location is used to enable 4K
address
connected

lines.
to

The
chip

outputs
enable

memory devices.
256 x 4 PROM

of

are
the

Figure 3.8: Address decoding by 256 x 4 PROM

memory chip

PAL Decoder
PAL

is

programmable

array

logic,

which is used for address decoding.

One such device is PAL16L8 and it
has 10 inputs and 2 outputs and 6 bidirectional (tri-state) lines, which

can be programmed either as inputs

or

outputs.

The

chip

can

be

programmed to generate the output

as below.

Y0=A 19A 18A 17A 16A 15A 14

Y1=A 19A 18A 17A 16A 15A 14

Y2=A 19A 18A 17A 16A 15A 14

Y3=A 19A 18A 17A 16A 15A 14

Figure 3.9: Address decoding by PAL decoder

3.9 Memory Devices And

Interfacing
The

memory

devices

are

broadly

classified into two categories, Read

Only Memories (ROM), and Random
Access Memories (RAM). The ROM
devices once programmed can store
the data for a lifetime and it does not
need any power supply to retain the
data that has been stored into it. The
RAM devices need power to retain the
data that has been loaded to it and
when the power is switched OFF, it
loses the data.

EPROM interfacing
The ROM devices can be programmed
in the factory while manufacturing
and

it

again.

cannot

be

EPROM

is

Electrically

reprogrammed
a

one-time

Programmable

ROM

device, which can be programmed by

the user at any time using a device
called programmer. The figure shows
the interfacing of 4 EPROM having
size of 4K x 8bit. Each device needs
12 address lines to address in 4K
memory. And gives out an 8-bit data
output. The address lines A12 to A1
is connected to the address inputs
of the memory devices. Since the
memory is divided into odd and even
banks, two OR gates are used to

generate

HMEMR and

two

LMEMR,

signals,
using

the

signals, BHE,MEMR and A0. The other

address lines A13 to A19 are used to
generate the chip enable signal using
the 74LS138 as shown in the figure
3.10.

Figure 3.10: Interfacing 4K x 8 EPROM to 8086

SRAM interfacing
The RAM is divided into two types,
static and dynamic RAM (SRAM and
DRAM). The SRAM uses a flip-flop to
store a bit of binary data. The SRAM
is speed as compared to the DRAM
but it is very costly and bulky. The
figure

shows

type

of

SRAM

connected to the MPU. It has 14

address lines and 8 bi-directional
data lines. The address ling address
lines to provide the CE signal for the
chips.

The

signalnes

are

MEMR

and

connected

MEMW
to

the

address lines (A14 to A1) from the

MPU. The data lines are connected to


the data bus. The signals BHE and AO
are used along with the remainis are

used to provide OE and WE signals.

DRAM interfacing
The DRAM uses a tiny capacitor to
store a bit of binary data and needs
to be refreshed periodically. DRAM
interfacing needs a DRAM controller
to read, write, and refresh. Intel
82C08 is a DRAM controller, that can
control two banks of 256K x 16 wide
DRAM chips. It contains a refresh
counter, refresh timer, and address
multiplexer to select the rows and
columns and refresh address. The
DRAM is connected as shown in the
figure.

Figure 3.12: Interfacing 256K x 8 DRAM to 8086

UNIT IV
8086 - INTERPACING AND
8051 - ARCHITECTURE

4.1 I/O Interfacing

The I/O devices are interfaced either
as an I/O location or a memory
location,

which

is

called

as

I/O

mapped I/O or memory mapped I/O.

Memory mapped I/O: In this mode,
the I/O devices are connected as a
memory location which are driven by
the memory related control signals
like MEMR and MEMW.
I/O mapped I/O: The I/O devices are
addressed by a 16-bit or an 8-bit
address and are driven by the I/O

related control signals, IOR and IOW.

The data is transferred to and fro
the I/O devices by the IN and OUT
instructions. The following sections
discusses

the

connection

of

I/O

devices in i/O mapped I/O.

INTERFACING DAC TO 8086

AD558 is an 8-bit DAC from Analog

Devices. The DAC has ah internal
8-bit

latch,

R-2R

ladder

network,

onboard precision reference voltage,

and

an

internal

op-amp.

It

is

microprocessor compatible and has

Chip Select C S and Chip Enable

CE
terminals. When these terminals go
low, the DAC is selected and the

binary data in the input is converted

to

analog

voltage.

The

range

of

output is programmable through the

Select and Sense pins. The figure 4.1
shows the interfacing of the DAC to
the 8086-based system.

Figure 4.1: Interfacing a DAC (AD558) to 8086

A PAL decoder is programmed to

decode an address FEH to the DAC.
The PAL is programmed to give the

device

selection

signal

at

its

Y0

output. The condition is given below.

Y0=A7A6A5A4A3A2A1A0
The decoder output is connected to

the CS and IOW and the CE signal is

connected

to

the

CE

signal.

The

program, which accesses the DAC to

generate a triangular wave, is given
below.

Example program 1:
Assume

the

initialization

segment

registers

has

already.

L00P1:

MOV
OUT
INC
CMP

AL, 00H
0FEH, AL
AL
AL, 0FFH

of

been

the
done

L00P2:

JNZ
OUT
DEC
JNZ
JMP

LOOP1
0FEH, AL
AL
LOOP2
LOOP1

Interfacing ADC TO 8086

The

AD574A

is

microprocessor

compatible and can be interfaced in

stand-alone

configuration,

if

the

system has dedicated input ports. It

can also be interfaced to the system
bus directly.

Stand-alone configuration
The figure shows the connection of
the ADC to the MPU in the stand
alone mode. The CE and 12/8 are

connected to +5V and CS and A0 to

ground. The 12/8ls given high input

to inform the conversion is a full

12-bit

conversion.

remains

in

through

out

conversion

full
the

starts

So

the

operating
process.
when

the

chip
mode
The

12/8

signal goes low. The R/C signal along

with the decoded output from the PAL
decoder enables the latch to the put
the data in the data bus. The STS
signal is connected to the data bus to
read the status of the ADC to check
whether the conversion is over or

not. The BHE is activated low, the

MPU reads the status of the ADC and
if

the

conversion

is

over,

the

converted is read through the data

bus. The input condition of the PAL
decoder is given below.


Y0=A 7A6A5A4A3A 2A 1A0 BHE

Y1=A 7A6A5A4A 3A2A 1A0 IOR

Figure 4.2a: Interfacing an ADC (AD574A) to 8086

(a) Stand Alone configuration
(b) Direct connection

Direct configuration
The figure shows the connection of
the

ADC

connection.

to

the

MPU

The

PAL

in

direct
decoder

connects the ADC to the MPU at the

address 40H. So an I/O write to the

address 40H triggers the start of

conversion. The STS pin is connected
in such a way that the I/O read from
the 42Htranfers the STS pin status
in the DO bit position. The input
conditions for the PAL decoder are
given below.

Y0=A 7A6A5A4A3A 2A 1A0 BHE

Y1=A 7A6A5A4A 3A2A 1A0 IOR

Example program 2:
Program to input a converted data
from the ADC is given below.
DATA

DATA
CODE

SEGMENT
ADC
DATA_PORT
STATUS_PORT
DIGI_DATA
ENDS
SEGMENT

EQU 40H
EQU 40H
EQU 42H
DW DUP (0)

ASSUME

CS: CODE, DS: DATA

START:
OUT ADC, AX
LOOP1:
IN AL, STATUS_PORT
ROR AL, 1
JC LOOP1
IN AX, DATA_PORT
MOV CL, 04
SHR AX, CL
MOV DIGI_DATA, AX
INT 03H
CODE ENDS
END
START

Interfacing Stepper Motor To

8086

Figure 4.3: Interfacing a Stepper motor to 8086

The figure shows the connection of a

stepper motor to the MPU. A stepper
motor

used

here

consists

of

two

stators (electro magnets) and a rotor

(permanent magnet). The rotor is
driven

by

the

magnetic

fields

produced by the stators. The coils

of the stepper motor are connected
to current drivers and these current
drivers consist of NPN Darlington pair
of transistors. These transistors are
driven by the digital output of the
MPU. A diode is connected in reverse
across

each

coil

to

protect

the

transistors form the back voltage. A

PAL decoder is used to decode the
address F0H to the stepper motor
interface.
below.

The

condition

is

given

Y0 = A7 x A6 x A5 x A4 x A3 x A2 x
A1 x AO x IOW

Example program 3:
The program to control the
stepper motor is given below.

L1:

L2:

MOV
MOV
ROL
OUT

CX, 2000
AL, 0CCH
AL, 01H
0F0H, AL

;
;
;
;

counter value for 10 rotations

initial value for the stepper motor
rotating the AL to left
output to the stepper motor

CALL DELAY
; wait for some time
DEC CX
; decrement the count value
JNZL1
; if count is not zero repeat from L1
MOV CX, 2000
; re-initialise counter for counter clockwise
ROR AL, 01H
; rotate AL to right
OUT 0F0H, AL
; output AL to motor
CALL DELAY
; wait
DEC CX
; decrement counter
JNZL2
; if counter is not zero repeat L2
INT03H

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This

program

rotates

the

stepper

motor 10 times in clockwise and

counter clockwise.

Interfacing a matrix keyboard

to 8086
The figure 4.4 shows the interfacing a
matrix keyboard to 8255A, which has
been interfaced to 8086. The 8255A
occupies lower I/O bank and has the
addresses 80H, 82H, 84H, and 86H.

Figure 4.4: Interfacing a matrix keyboard to 8086

Procedure:
The keyboard has twenty keys from
0 to F and other functional four keys
(store, execute, etc) arranged in five
rows and four columns. The rows are
connected to the port C and the
columns are connected to the port B
of the 8255A. The rows are grounded
by sending 00H to port C. If any
of the keys is pressed, then the
corresponding column of port B will
be read 0.
The steps involved in the program
are given below.

1.

The program sends 00H to port

C

and

whether

checks
any

of

the

keyboard,

the

keys

is

pressed, by monitoring the port

B. If none of the keys is pressed,
port B will be read 00001111B.
For example, if a key from the
first column is pressed, then the
port B wifi read 00001110B. If
the port B value is 0FH, the
program

waits

until

key

is

pressed.
2.

If the port B is read a value other

than 0FH, the program assumes that
a key has been pressed.

The program sends zero to one

row at

time

and

reads

the

value in port B. If the port value

does not change from 0FH, then
it

sends zero

counter
the

will be

total

counted.
counter

to

no
The

next

row.

initialized
of
value

corresponds

and

loops

is

in

the

to

the

position of the key.

Program
DATA SEGMENT
CNTRLPORT DB 86H
PORTA
PORTB

;control port address

DB 80H
DB 82H

; port A
; port B

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PORTC

DB 84H

; port C

CNTRWRD DB 82H
; control word for port C-O/P port B-I/P
KEY
DB 1 DUP (0); key code (result)
DATA ENDS
STACK SEGMENT STACK
DW
20 DUP (0)
TOP_OF_STACK LABEL WORD
STACK ENDS
CODE SEGMENT
ASSUME CS: CODE, DS: DATA
START:
MOV AX, DATA
MOV DS, AX
MOV AX, STACK
MOV SS, AX
MOV SP, OFFSET TOP_OF_STACK
MOV AL, CNTRLWRD
OUT CNTRLPORT, AL

; configuring 8255A

MOV BH, KEY

SUB AL, AL

; initialize the key counter

; load zero in AL

OUT PORTC, AL

; send to port C

KYNTPRES: IN AL, PORTB; input from port B

AND AL, #00001111B ; mask higher order bits D 7 to D 4
CMP AL, #00001111B ; compare with 0FH
JZ KYNTPRES
; if no key pressed, stay in loop
CALL DEBOUNCE
; if key pressed, wait for some time
MOV AL, #07FH
MOV BL, 05H
NEXTROW: ROL AL,1

; initialize row counter

; rotate once to make a bit in AL zero

MOV DL, AL
OUT PORTC
IN PORTB
AND AL, #00001111B
MVI CL, 04H
NXTCOLMN:ROR AL, 1
JNC CODE

CODE:

;
;
;
;
;

store value in AL for future use

send zero to any of the rows
read from port B
mask higher order bits
column counter

; check D 0 bit for zero

; if zero, the value in BH is key code

INC BH

; increment key code

LOOP NXTCOLMN
MOV AL, DL
DEC BL

; go for next column

; get back value from DL to AL
; decrement row counter

JNZ NXTROW
JMP KYNTPRES

; if all columns not finished goto nxtrow

; start fresh scanning

MOV KEY, BH
INT 03H

; store the code to KEY

DEBOUNCE PROC NEAR

PUSHF
PUSH AX
PUSH CX
MOV CX, #0FFFFH
LOOP HERE
POP CX
POP AX
POPF
RET
DEBOUNCE ENDP
CODE ENDS
END START

; delay for some time

HERE:

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4.2 INTERRUPTS
The

microprocessor

interrupted

in

the

may
middle

be
of

program to handle some emergency

tasks. When an interrupt occurs, the
microprocessor

completes

the

execution of the current instruction

and jumps to the interrupt service
routine, executes the instructions in
the service routine and return to the
main program. The interrupt may be
generated by external devices and
also internally.

Interrupt Vector Table

The microprocessor reserves the first
1024 locations from 0000:0000H to
0000:03FFH

to

hold

the

starting

addresses of the interrupt service

procedures. The starting address of
an

interrupt

service

procedure

is

called as interrupt vector. And the

first 1024 locations of the memory
is called interrupt vector table. The
interrupt vector table can hold 256
interrupt

vectors.

Each

interrupt

vector is of 4-byte width, which is

used to store the segment address
(CS) and offset address (IP) of the

interrupt

service

procedure.

The

vector is identified by a type number

0 to 255. The vector of type 0 is
stored in the locations 0000:0000H
0000:0003H.

Figure 4.5: Interrupt vector table

Response

of

to

8086

Interrupts
The microprocessor will check if any
interrupt is active at every the end
of

every

instruction.

When

the

processor detects an active interrupt,

the

following

sequence

of

events

occurs.
1.

The content of the flag register is

stored in the stack

2.

The interrupt flag is cleared to

disable

any

further

interrupt

through INTR.
3.

The TRAP flag is reset to disable

single step function.

4.

Contents of CS and IP registers

are stored in the stack.

5.

Then the address of the interrupt

service
from

procedure
the

vector

is

obtained

table

and

segment and offset address is

loaded into CS and IP registers
are filled.
6.

Interrupt

service

procedure

is

executed.
7.

When the processor encounters

the IRET instruction at the end
of

the

procedure,

microprocessor

retrieves

the
the

return address from the stack.

8.

The content of the flag register is

popped back from the stack.

8086 Interrupt types

The 8086 interrupts are classified
into three types. They are

Predefined interrupts

Software interrupts

Hardware interrupts

Predefined Interrupts
Interrupt types 0 to 31 have been
defined as predefined interrupts and
only the interrupt types 0 to 4 are
used in 8086. The rest are reserved
for

future

applications.

The

first

interrupt types are Divide by zero

(type 0), Single step interrupt (type
1), Non-maskable interrupt (type 2),
Breakpoint

interrupt

(type

Overflow interrupt (type4).

3),

Software Interrupts
The

microprocessor

can

be

interrupted using software interrupt

instruction INT, which is followed by
the

type.

This

is

instruction

and

on

reading

instruction,

the

two

byte
this

microprocessor

executes in the same manner as

same as the hardware interrupts.

Hardware interrupts
The microprocessor has two interrupt
lines, Non-Maskable Interrupt (NMI)
and

Interrupt

Request

(INTR).

Whenever the NMI pin is activated,

the

microprocessor

executes

the

service procedure for the type 2. The

NMI cannot be masked and has the
highest priority over INTR and can
be used to save critical data during
some unwanted situations like power
failure.

INTR
The external devices, which require
immediate

attention

of

the

microprocessor, can send a interrupt

request to this line. Logic high to this
pin activates the interrupt and can
be enabled or disabled by setting or
resetting the IF bi in the flag register.

Example program 5:

Figure 4.6: Illustrating the INTR operation

Consider an ADC is connected to the

microprocessor

as

shown

in

the

figure. The end of conversion from

the ADC is connected to one of the
eight

inputs

of

the

interrupt

controller, which in turn connected to

the INTR pin of the microprocessor.
The ADC is connected at the address
40H through a PAL decoder. The
condition to be written to the PAL
decoder s given below.

Y0=A 7A 6A 5A 4 A 3A 2A 1A 0 BHE



Y0=A 7A 6A 5A 4 A 3A 2A 1A 0
The program is given below.
; Data segment
ADC
DATA_PORT

EQU

40H
EQU 40H

----------------DIGI_DATA

DW DUP (0)

FLAG

DB 00

; Initialising 8259A
--------------------------------; Saving the interrupt vector in the vector table, interrupt type 08H
MOV AX, 0000H
MOV ES, AX
MOV WORD PTR ES: 0022H
MOV WORD PTR ES: 0020H
; Enable INTR interrupt
STI
; Start of Conversion
OUT ADC, AX
; Do nothing but branch to ISR on interrupt
HERE:
CMP FLAG, 00H
JNZ HERE
CLI
INT 03H
ACQUIRE:
PUSH AX
PUSH CX

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IN AX, DATA_PORT
MOV CL, 04H
SHR AX, CL
MOV DIGI_DATA, AX
MOV FLAG, 01H
POP CX
POP AX
IRET

4.3 Direct Memory Access

In

microprocessor,

the

data

is

transferred between I/O and memory

devices through the microprocessor
only. This process takes lot of time.
The direct memory access technique
provides faster rate of data transfer
between I/O devices and memory.
DMA controlled data transfer from I/
O to memory is called as DMA write
and from memory to I/O is called as
DMA read.

The 8086 have two pins, HOLD and

HLDA to support DMA operation. The
external devices, which require DMA
access, request the microprocessor
through

HOLD

microprocessor
signal

every

receiving

signal.

checks
clock

The

the

cycle

HOLD

and

on

the

HOLD

signal,

the

microprocessor

gives

away

the

control of the address and data buses

to the external device and asserts
the HLDA (Hold Acknowledge) signal.
On reading the HLDA signal, the DMA
controller

sends

signal,

which

disconnects the microprocessor from

the address and data buses. The DMA
controller may have two or more DMA
channels and the I/O devices sends

request to these channels. The DMA

controller,

on

receiving

the

HLDA

signal, it sends out the DACK signal

to the I/O device. After the data
transfer

is

complete,

the

DMA

controller releases the address and

data buses and disables the HOLD
signal.

Figure 4.7: DMA operation

Universal

Asynchronous

Receiver Transmitter (UART),

PC16550D
The PC-AT system uses the 16550

UART for the serial transmission and

reception. The internal block diagram
is shown in figure. The PC16550D has
two

independent

receiver

transmitter

divisions

for

and
serial

communication. Each division has a

FIFO with a capacity of 15 bytes.
It can also be used to communicate
with the modem. The UART has a
baud rate generator that divides the
clock frequency by a 16-bit number.
The UART operates at baud between
0

to

1.5MB.

parallel

to

The

serial

UART

performs

conversion

and

serial to parallel conversion and also

it places and detects the stop bits,
even, odd, or odd parity.

Figure 4.8: Internal block diagram of PC16550D

UART

Figure 4.9: Pins and Signals of PC16550D UART

Pin and Signals

The PC16550D UART is housed inside
a

40-pin

DIP

or

44-pin

plastic

leadless chip carrier. The pins and

signals are given below.
D7- D0: The bi-directional data lines
is used for communicating with the
PC.

A0, A1, and A2: The address lines

are used to select one of the internal
register of the UART.
CS0, CS1, and CS2: These

chip

select signals enable communication

between

the

UART

and

the

microprocessor.
ADS: the positive edge in the line
latches the address lines and chip
select signals. MR: (Master reset)
high in this line resets al registers in
the UART.

RD, and RD when RD is high or RD#

is low, the MPU reads data from the
status information or data from the
selected register.

WR,

WR

and

These

signals

are

activated when the MPU is writing a

data to the UART.

DDIS The Driver Disable signal goes

low, whenever the microprocessor is
reading data from the UART.

TXRDY and RXRDY

used

to

transfer

these
data

lines
by

are
DMA

techniques.
XIN, and XOUT: the External crystal
input and External crystal output are
used for providing clock to the chip.
SIN, and SOUT: the Serial input and
Serial output lines used for sending
and receiving serial data.

RCLK: The receiver clock input is

clock input t the receiver section.

BAUDOUT : this is an output line from

the UART.
Modem control signals

RTS: When

this

signal

is

low,

it

informs the modem or data set that

the UART is ready to exchange data

CTS : when the modem is ready to

send

data

it

sends

low

signal

through this line.

DTR: When the UART is ready to

establish

communication

signal goes low.

link,

this


DSR : When the modem is ready to
establish

communication

link,

it

sends a low in this line.

DCD when the data carrier is detected

by the modem or data set, this line
goes low.
RI: when the ring indicator is low,
it indicates that a telephone ringing
signal

has

been

received

by

the

modem or data set.

OUT1, and OUT2: these lines can be

used to provide signals to a modem
or data set.

Internal registers
The

internal

registers

are

listed

below.
Table 4.1
Address
Register

Function
DLAB

A2

A1

A0

(Read)
RBR

Holds

the

byte

received in

(Write)
THR

holds

the byte to be
transmitted

Enables
lER

five

types of UART
interrupts

IIR

(Read)
Indicates

the

pending
interrupts

(Write) Enables
FCR

clears

sets

FIFO,
trigger

level/ DMA type

Format
LCR

of

asynchronous
communication,
MSB = DLAB

MCR

Controls

the

interface

with

modem

Holds

the

status
LSR

information
concerning
data transfer

MSR

Provides
status

the
of

control

lines

form modem

Holds
SCR

temporary
data, does not
control UART

Holds
DLL

of

LS

divisor

baud

byte
for
rate

generator

Holds MS byte
DLM

of

divisor

baud

for
rate

generator

Example program 6:
Suppose the UART is connected at
the address from 80H to 8EH. The
device has a clock input of 3.072MHz.

Then the divisor for the baud rate

9600 is = Frequency input / (baud
rate x 16) = 20.
The program is given below
; Data segment
LSB_DL EQU 80H
; divisor latch-LSB
MSB_DL
EQU 82H
; divisor
FCR

EQU 80H

latch-MSB

; FIFO control register

LCR
LSR

EQU 80H
EQU 80H

; line control register

; line status register

THR
RBR

EQU 80H
EQU 80H

; transmitter hold register

; receiver buffer register

; Initialising the 16550

MOV AL, 10001010B
OUT LCR, AL

; set D7 (DLAB) to access DL

; load control word into LCR to enable DL

MOV AL, 20
OUT LSB_DL, AL
MOV AL, 00
OUT MSB_DL, AL
MOV AL, 00001010B

; load LS divisor byte into DL

; load MS divisor byte into DL
; communication format: 7-bit data, 1 ;stop bit, odd parity

OUT LCR, AL

; load the control word for the required ;format into LCR

MOV AL, 00000111B

OUT FCR, AL
INT 03H

; FIFO control word

; load into FIFO control register

Transmitting data
The line status register is checked
before transmitting a data through
the PC16550D. The data is loaded in
the THR to start transmit the data.

Double click this page to view clearly

CHECK:

IN AL, LSR
AND AL, 20H

; read line status register

; test D5 bit

JZ CHECK
MOV AL, AH
OUT THR, AL

; if not ready check repeatedly

; get the data to be transmitted
; send data to transmitter hold register

INT 03H

Receiving the data

The LSR is checked before reading
the data byte from the receiver buffer
register. It indicates whether new
data has been received or not.
CHECK:

IN AL, LSR
AND AL, 01H
JZ CHECK
AND AL, 00001110B
JNZ ERROR
IN AL, RBR
INT03H
ERROR: -------

;
;
;
;

read line status register

test DO bit
if not, check repeatedly
test overrun, parity, framing error

; read data from receiver buffer register

; break point
; error detection routine

----------INT 03H

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4.4 Advanced Microprocessors

After 8086, Intel corp. has introduced
various

advanced

processors

improving the capabilities. The next

advanced popular microprocessor to
the 8086 is the 80286, which has
24-bit address lines and 16-bit data
lines.

After

that,

80386,

80486,

Pentium, Pentium-MMX, Pentium-pro,

Pentium-ll,

Pentium-Ill,

Pentium-IV

processors are introduced.

Protected Mode Operation

The most important advancement of
the 80286 and the above processors
is their projected mode operations.

Advanced

microprocessors

can

operate in real, protected, and virtual

real modes.

Limitations

of

real

mode

operations
The

8088

operate

and

only

in

8086
real

processors
mode.

The

limitations 01 this mode are

1.

The processor can access only

1MB

of

memory.

The

1MB

memory space is referred to as

the real mode memory.
2.

Real mode operation allows only

a single program to run at a time
under

unitasking

system such as DOS.

operating

Features of Protected mode

operations
The

80286

follow

real

and

above

and

processors

protected

mode

operations. The features of this mode

are
1.

The processor can access above

1

MB

memory

space

catted

extended memory.
2.

It supports virtual memory.

3.

It allows multitasking

Memory

addressing

in

Protected mode
In real mode, a logical address has a
segment address and an offset

address to access a memory location.

Using these, the physical address is
computed. ln protected mode also,
the logical address has a segment
and

an

offset

address.

The

computation of the physical address

is as follows.
In this mode, a segment is described
by

segment

descriptor.

The

segment descriptor contains the base

address, size, and access rights of
the segment and its size is 8 bytes.
Two descriptor tables are present to
describe the segments, global and
local descriptor table. In protected
mode, the segment register will not

contain the segment address abut it

contains

the

segment

selector.

It

points to one of the two tables. The

microprocessor holds the base and
limit

of

descriptor

tables

in

its

internal global and local descriptor

table

registers,

which

are

not

accessible to users. The integrated

memory management unit (MMU) in
the processor computes the physical
using offset and the segment address
in the descriptor.

Multitasking
The

protected

mode

supports

multitasking, also in which multiple

programs can co-exist in memory and
simultaneously. The MMU provides

protection to the multiple tasks in

memory from interfering with each
other. If an operating system allows
multiple

programs

to

execute

simultaneously. It is usually achieved

by time slicing. Each program will
be provided with predefined period
of time and the program will be
executed for that limited period of
time.

Then

the

execution

will

switched to the next program and so

on.

Overview

Of

The

Advanced

Microprocessors
80286
The features of the 80286 processor
are as follows.

1.

It has 16-bit data bus and 24-bit

address bus

2.

It can access 16 MB memory

3.

It includes memory management

hardware

4.

It supports protected mode

80386
The features of the 80386 processor
are as follows.
1.

It has 32-bit internal registers

and 32-bit arithmetic logic unit

2.

It has 16-bit instruction queue.

3.

It supports multitasking

4.

It supports virtual real mode in

which

multiple

real

mode

applications work
simultaneously

under

multitasking

system.

80486
The features of the 80486 processor
are as follows.
1.

It has a 32-bit data bus, 32-bit

address bus.

2.

It

has

parity

checker/

generator.
3.

It has built-in math coprocessor

4.

It

has

reduced

instruction

execution time.
5.

Built-In-Self-Test is present

Pentium processor
The

features

of

the

Pentium

processor are as follows.

1.

It has 32-bit internal registers

and 64-bit data bus.

2.

It includes two 8KB L1 cache

memories and supports L2 cache
up to 512 KB.

3.

It

allows

two

pipelines

for

executing two instrcutions at a

time.
Pentium-MMX
multimedia
handle,

supports
applications,

video,

audio,

graphics information.

and
and

The Pentium-Pro processor has

36-bit

address

bus

and

can

address up to 64 GB memory
locations.

4.5 Microcontroller 8051

Introduction
The

microprocessor

purpose

digital

processing

is

computer

unit.

generalcentral

Normally

microprocessor will have arithmetic

and

logic

unit

(ALU),

program

counter, a stack pointer, some CPU

registers,

clock

source,

and

interrupt logic. The microcontrollers

are tiny microcomputers which can
have almost ail the peripherals that

are needed by a computer to work.

A microcontroller will have a ROM,
RAM,

parallel

counters,

clock

microcontrollers

I/O,

Serial

circuits,
can

etc.,

be

I/O,
The

called

dedicated microprocessors developed

to meet a single mode of operation.
The

microcontrollers

read

data,

perform limited calculations on the

data based on the program that has
been written in the ROM and gives
the

output

to

control

specific

application. The microcontroller will

have reduced instruction set than the
microprocessor and can function as
a single chip computer without any
additional

peripherals.

But

the

microprocessor

needs

all

the

peripherals to be attached to it.

Figure 4.10: Internal block diagram of 8051

microcontroller

Microcontroller 8051
The 8051 is a 8-bit microcontroller,
having an internal ROM and RAM, I/

ports

with

programmable

pins,

Timers and counters, and Serial data

communication.

The

architecture

consists of these specific features:

Eight-bit CPU with registers A

and B.

Sixteen-bit program counter (PC)

and data pointer (DPTR).

Eight-bit program status word

(PSW)

Eight-bit stack pointer

Internal ROM or EPROM

Internal RAM of 128 bytes

Thirty

two

input/output

lines

arranged as ports P0 P3.

Two 16-bit timer/counters: T0

and T1

Full duplex UART serial port.

Control registers: TCON, TMOD,

SCON, PCON, IP and IE.

Two external and three internal

interrupt sources.

Oscillator and clock circuits.

CPU Registers
The 8051 contains an accumulator A
and

general

purpose

register

B,

Program Counter and Data pointer,

Flag

register

and

Program

status

register.

Program

counter

and

pointer
The 8051 contain two 16-bit
registers:

Data

the

program

data

counter

pointer

(PC)

(DPTR).

and
The

program counter is used to hold the

address of the next instruction to be
executed.

The

program

counter

cannot be modified directly by the

user. But it can be modified by using
some call and jump instructions. The
program

counter

incremented
instruction.
made

up

is

after
The

of

automatically
fetching

DPTR

two

8-bit

register

an
is

registers,

named DPH and DPL. The DPTR can

be used point an array and can be
decremented and incremented.

Registers A and B
The

8051

contain

34

general

purpose, or working registers. Two of

these, registers A and B, hold results
of

many

math

and

instructions,
logical

particularly

operations.

The

other registers are arranged as part

of internal RAM in four banks, B0-B3,
of eight registers and comprise the
mathematical core. The Accumulator
A is used to hold the result of all of
the arithmetic and logical operations.
It is also used for all data transfers
between CPU, memories and ports.
The B registers is sued with the A
register
division.

for

multiplication

and

Flags

and

Program

Status

Word (PSW)
Flags are 1-bit registers provided to
store the results of arithmetic or a
logical operation. The content of the
flags

can

be

altered

by

some

instruction by the user. These flags

are arranged and addressed and are
present in the PSW and the Power
control register (PCON). The 8051
has

four

indicate

math
the

flags

result

which
of

can
math

operation and three general purpose

flags that can be set or reset by the
user at any time. The math flags are
Carry

(C),

Auxiliary

Carry

(AC),

Overflow (OV), and Parity (P). USER

flags are F0, GF0, and GF1, which

can be used by the user to record
an event. The program status word
is shown in the figure. The PSW
contains

the

math

flags,

user

program flag F0, and the register

select bits that identify which of the
four general purpose register banks
is currently in use by the program.
The remaining two user flags, GF0
and GF1, are stored in PCON. The
PSW bit definition is given below.

CY

AC

FO

RS1

RS0

OV

Internal memory
Every computer must have a memory
to store the instruction and data that
are to be manipulated. Unlike the
microprocessor, the microcontrollers
may

have

some

internal

memory

embedded into it. The microcontroller

8051 has an internal RAM, which is
128 bytes in size, and an internal
ROM. The size of the RAM and ROM
memories

may

vary

with

the

manufacturer and model of the chip.

Internal RAM
The

common

8051

microcontroller

contains 128 bytes of internal RAM.

But the memory is organized into
three distinct areas:

1.

Thirty-two bytes from address

00H to 1FH are reserved for the
32 working registers, which are
further divided into four banks
of eight registers. The registers
can be accessed by their names
are locations. The four register
banks are made up of registers
R0 to R7.

2.

A bit addressable area of 16

bytes

occupies

RAM

byte

addresses 20H to 2FH, forming a

total of 128 addressable bits. The
addressable bits are very useful,
when the binary data is recorded
or processed.

3.

A general purpose RAM area from

30H to 7FH is available and can
be used to store data or results.

The Stack Pointer

The stack is a memory that can be
used to store data and/or addresses
temporarily by

the

microcontroller

and retrieved back quickly. Since the

data is to be stored and retrieved
frequently it requires a RAM memory.
The stack uses the top of the internal
RAM at 7FH. The stack pointer is 8-bit
wide and is used to store the address
of the stack. The stack operation is
same as the microprocessor based
system.

Special

Function

Registers

The

8051 operations that do not use the

internal

128-byte

RAM

addresses

from 00H to 7FH are done by a group

of special function registers SFR and
are shown in the table. The SFR uses
the addresses between 80H and FFH.
Table 4.2

Name

Function

Internal RAM
address (HEX)

Accumulator

0E0

Arithmetic

0F0

Addressing
DPH

external

83

memory

Addressing
DPL

external
memory

82

IE

IP

P0

PI

P2

P3

PCON

PSW

interrupt enable
control

0B8

priority

Input/output
port latch

input/output
port latch

input/output
port latch

input/output
port latch

Power control

Program
word
Interrupt

0A8

status

80

90

0A0

0B0

87

0D0

SCON

SSUF

SP

TMOD

TCON

TL0

TH0

TL1

TLO

Serial

port

control

Serial port data

buffer

Stack pointer

Timer/counter
mode control

Timer/counter
control

Timer 0 low byte

Timer

high

byte

Timer 1 low byte

Timer
byte

high

98

99

81

89

88

8A

8C

8B

8D

INTERNAL ROM

Normally the 8051 controllers have

4K bytes of internal ROM to store
programs, data, look up tables, etc.
when

the

internal

addresses
memory

exceed

capacity,

the
the

microprocessor automatically fetches

the data from the external memory,
if provided. The internal ROM can be
selected using a pin assigned EA. The
memory can be selected by the user.

I/O Ports
The microcontroller has four 8-bit
ports,

which

can

be

used

for

transferring data to and from the I/

O devices. The ports are assigned as
Port 0 to Port 3.

Port 0
Port 0 pins may serve as Inputs,
outputs, or when used together, as
a bidirectional low order address and
data bus for external memory. When
a pin is to be used as an input, logic
1 must be written to the port 0 latch,
thus

switching

off

the

output

transistors shown in the figure. Then

the port goes to high impedance
state and the device is connected to
the port. When used as an output,
the logic 0 written to it will turn on
the lower FET grounding the pin.

When these latches are programmed

to 1, the pins will float. So external
pull-up

registers

are

needed

to

provide the logic 1 to this pin.

Port 1
This

port

functions.

does
So

the

not

have

output

dual

latch

is

connected directly to the gate of the

lower FET, which has internal pullup. It has eight pins and can be used
either as input or output port.

Figure 4.11a: Port pin circuits of ports 0 and 1

Figure 4.11b: Port pin circuits of ports 2 and 3

Port 2
The port 2 may be used as an input
or output port similar as the port
1. But the port 2 has an alternate
function of providing higher order
address byte in conjunction with the
port 0.

Port 3
The port 3 can be used as input or
output port. Additionally, the port 3
has some special functions like serial
input and output, external interrupts,
timer

inputs

etc.

The

additional

functions are listed in the table.

Table 43

Pin

P3.0

Alternate use

RXD

P3.0
TXD

P3.0

INT0

P3.0

INT1

P3.0 T0

P3.0 T1

P3.0

WR

P3.0
RD

Serial data input

SBUF

Serial data output

SBUF

External interrupt 0

TCON.1

External interrupt 1

TCON.3

External timer input 0

input

External timer input 1

input

External

memory

writpulse

SFR

External
reapulse

memory

TMOD

TMOD

--

--

4.6 Pins and signals

The

important

pins

and

their

description is given below.

Vcc: Vcc provides supply voltage to
the chip. The voltage source is +5V
GND: Ground
XTAL1 and XTAL2: The 8051 has
on chip oscillator but requires an
external clock to run it. Most often a
quartz crystal oscillator is connected
to

inputs

XTAL1

and

XTAL2.The

quartz crystal oscillator connected to

XTAL1 and XTAL2 also needs two

capacitors of 33-pF values. One side

of each capacitor is connected to the
ground.
RST: Pin 9 is the RESET pin. It is
an input and is active high (normally
low). Upon applying a high pulse to
this pin, the micro controller will
reset and terminate all

activities.

This is often referred to as a poweron reset.

EA: The 8051 family members come

with on-chip ROM to store programs.
In

such

cases,

the

EA

pin

is

connected to Vcc. EA which stands for

external access. It is an input pin
and must be connected to either Vcc
or GND.

Port 0: Port 0 occupies a total of

8 pins. It can be used for input or
output. To use the pins of port 0
as both input and output ports, each
pin must be connected externally to
a pull-up resistor. This is due to the
fact that port 0 is an open drain.
Port 1: Port 1 occupies a total of
8 pins. it can be used as input or
output. In contras to port 0, this port
does not need any pull-up resistors
since it already has pull-up resistors
internally.

Upon

reset,

port

is

configured as an output port. To

make port 1 an input port, it must
programmed as such by writing 1 to
all its bits.

Port 2: Port 2 occupies a total of 8

pins. It can be used input or output.

Just like P1, port 2 does not need
any pull-up resistors since it already
has pull-up resistors internally. Upon
reset, port 2 is configured as an
output port. To make port 2 an input
port, it must programmed as such by
writing 1 to all its bits.
Port 3: Port 3 occupies a total of
8 pins. It can be used as input or
output. Port 3 also does not need any
pull-up resistor. This is not the way
it is most commonly used. Port 3 has
the additional function of providing
some

extremely

important

signals

such as interrupts, serial port pins,

timer inputs.

4.7 External Memory

When the internal ROM and RAM
memory

is

not

sufficient

to

load

program and data, external memory

can be added and the microprocessor
can be programmed to access the
external

memory

instead

of

the

internal memory. Figure shows the

connection between the 8051 and the
external memory consists of a 16K
EPROM memory and 8 K static RAM
memory.

Figure 4.12: Interfacing EPROM and RAM to 8051

The

address

and

data

lines

are

provided by the port 0 and port 2.

The

microcontroller

has

16-bit

address and 8-bit data lines. The

lower order address A7 A0 and the
8-bit

data

multiplexed

lines
as

in

D7

D0

are

8085

and

are

provided by the port 0. The pin 30 of

8051supplies the ALE signal required
for

latching.

provide

the

The

pin

WRand

16

RD

and

17

signals

respectively. These signals are used

to write and read the data into and

from the RAM. The PSEN (Program

Select Enable) is kept low to control
the ROM to place the byte in the data
bus.

4.8 Counters And Timers

The 8051 has two 16-bit free running
counters T0 and T1. The counters are
divided into two 8-bit registers called
the timer low (TL0, TL1) and high
(TH0,

TH1).

The

counters

are

controlled by two registers: timer

mode control register (TMOD), the
timer/counter

control

register

(TCON).
The

bit

definitions

of

registers are given below.

the

two

Timer control TCON register

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

TF1: Timer 1 overflow flag. This flag

will be set every time the timer 1
overflows

from

FFFFH

to

0000H.

Cleared when processor vectors to

interrupt service routine.
TR1: Timer 1run control bit. Set to
one by program to enable timer to
count. Cleared to halt.

TF0: Timer 2 overflow flag. This flag

is set when the timer 1 overflows
from all ones to zeros. Cleared when
the processor vectors to interrupt
service routine.
TR0: Timer 0 run control bit. Set to
one to start timer to run and cleared
to stop.
IE1: External interrupt 1 edge flag.
Set to 1 when a high to low edge
signal is received in port pin P3.3.
Cleared by processor.
IT1: External interrupt 1 signal type
control bit. If set to one, a falling
edge in the interrupt-1 trigger the
interrupt. If reset, a low level signal

triggers the interrupt. IE0: External

interrupt 0 edge flag.
IT0: External interrupt 0 signal type
control bit.

Timer mode control (TMOD)

register

Gate

C/
T

M1

MO

Gate

C/
T

M1

M0

Gate OR gate enable bit. It is used to

enable the timer 0/1 to run or stop.
C/T: If set the timer 1/0 counts the
pulses from the external input pins
P3.5 and P3.4.

M1 and M0: used to select one of the

four timer modes: mode 0 to mode 3.

Timing
If a counter is programmed to be a
timer, it will count the internal clock
of

the

twelve.

microprocessor
Suppose

divided
if

by
the

microprocessor has a 12 MHz clock,

the timer value will be incremented
every 1 microsecond (1/ (12 MHz
/12).

Timer modes
The timers can be programmed to
operate in four modes: mode 0,1,2,
3.

In timer mode 0, the timer high

register THX acts as an 8-bit counter
and TLX as a 5-bit counter. So it will
be a 13-bit counter. The timer flag
will be set when the THX goes all
ones to zeros.
In

timer

mode

1,

the

timer

low

register is used. It acts as a fuff 8-bit

counter.
In

timer

mode

2,

the

timer

is

configured as a 8-bit counter. The

timer low register is used as the
counter and the timer high register
is used for loading the count value.
Whenever the low register (TLX) goes
zero,

the

count

value

will

be

automatically reloaded from the high

register (THX). This mode is also
called as auto-reload mode.

In timer mode 3, a single timer will

act as two different 8-bit counters.
Only one of the timers must be
operated in this mode. Because the
timer configured in mode 3, uses
both timer overflow flags. The other
counter can be used for some other
application.

Counting
In timing, the clock source is derived
from the system oscillator through
divide by 12 circuit. When the timer/
counter is used in counting mode,
the clock is derived from the external

pins P3.4 and P3.5 to counter 0 and

counter 1 respectively. The control
bit C/T in the TMOD register must be
set to 1 to configure the timers as
counters. The input pulse on TX is
sampled during P2 of state 5 every
machine

cycle.

high

to

low

transition will increment the counter

by one. Each transition must be held
constant

for

atleast

one

machine

cycle to ensure reliable counting. But

this

takes

oscillator.

24
With

pulses
6

MHz

from

the

oscillator

frequency the maximum of 250kHz

can be counted. The counter mode is
shown below.

Figure 4.13: Timer/Counter control logic

4.9 Serial I/O

The 8051 have an in-built UART serial
communication interface. The UART
of the 8051 has a buffer register
called as SBUF, which is used to hold
the data to be transmitted, and also
the received data. It has two control
registers (SCON and PCON) to control
the data transfer.

SCON register
7

SM0

SM1

SM2

REN

TB8

RB8

TI

RI

SM1 :SM0: These two bits are used

to select one of the four modes.
Mode 1 shift register; baud = f/
12, Mode 2 8 bit UART; baud
= variable, Mode 2 9-bit UART;
baud = f/32 or f/64, Mode 2 9-bit
UART; baud = variable.
SM2: Set or Cleared by program to
enable

multiprocessor

communication mode. REN: Receive

Enable. Set to one to enable data
reception. Cleared to disable.

TB8: Transmitted bit 8. Set/Cleared

by program in modes 2 and 3.
RB8: Received bit 8
TI: transmit interrupt flag. Set to one
when the UART finishes transmission.
RI: Receive interrupt flag. Set to one
when the UART receives a data.

TCON register

SMOD

GF1

GF0

PD

IDL

SMOD: serial baud rate modify bit.

Set to one by program to double
baud rate. Cleared to zero, to use the
actual baud rate from timer 1.

Data Transmission
Transmission

of

the

data

through

serial port may begin at once the

data has been written into the SBUF
register. Tl will be set to one, when
the UART finishes the transmission of
data. If the data is overwritten in the
SBUF register before the flag is set,
the result will be wrong.

Data Reception
Reception of data wilt be enabled by
setting the REN bit to one. When the
UART receives a data, it sets the Rl.
The Rl bit must be reset before the

next data is received. Because, after

the data has been received only, the
Rl bit will be set and it will be
transferred to SBUF. If it is not
cleared then the SBUF will retain the
old value.

UNIT V
8051 - SYSTEM DESIGN
AND PROGRAMMING

5.1 Addressing Modes

The way the data is transferred from
source

to

destination,

which

are

specified in the mnemonic determine

the addressing modes. There are four
addressing

modes:

immediate,

register, direct, and direct addressing

mode.

Immediate Addressing Mode

The simplest way of transferring data
is

to

specify

instruction

the

itself.

microprocessor

data
When

executes

in

the
the
an

immediate

mode

instruction,

it

automatically read the next byte to

transfer

the

data.

The

immediate

data must be preceded by a #

symbol

to

indicate

immediate
symbol

data
is

not

that

it

transfer.

is

If

a
the

included,

the

instruction will not work properly.

E.g. MOV A, #02H. Transfers 02H to
A.

Register Addressing Mode

The data transfer is between two
registers

or

register

and

some

location in memory. The registers are

A, B, DPTR, and R0 to R7. MOV
instruction does not alter the content

of the source. A copy of data is stored

in the destination address.
E.g. MOV A, Rr. Transfers the data in
the Register Rr to A.

MOV

A,

#8-bit

MOV A, Rr

MOV Rr, A

MOV Rr,
#8-bit

MOV

DPTR,

#16-bit

8-bit data is stored in A

The content of Rr (R0 to

R7) is stored in A

Content of A is stored in Rr

8-bit data is stored in Rr

16-bit
DPTR

data

is

stored

in

Direct Addressing Mode

All 128 bytes of internal RAM and the
SFRs may be addressed directly using
a single byte address to each RAM
location. Internal RAM uses 00H to
7FH and the SFRs uses 80H to 0FFH.
The addresses of the RAM location
and

SFRs

are

representing
The

the

addresses

specified

by

the

address

directly.

should

not

be

preceded with # symbol.

E.g. MOV A, #30H can also be written
as MOV 0E0H, #30H.

MOV

A,

Content

of

the

location

8-bit

specified by the 8-bit address

add

is transferred to A

MOV

Content of A is transferred to

8-bit

the location specified by the

add, A

8-bit address

MOV Rr,

Content

8-bit

specified by the 8-bit address

add

is transferred to Rr

MOV

Content of Rr is transferred to

8-bit

the location specified by the

add, Rr

8-bit address

MOV

8-bit

the

location

8-bit immediate value is stored

8-bit
add,

of

in

the

address

specified

by

8-bit address

MOV
8-bit

Content of location specified by

add1,

8-bit

8-bit

location specified by addr1

add2

add2

is

transferred

to

Indirect Addressing Mode

If

the

data

is

transferred

to

memory location, the address of the

location can be loaded into a pointer
and the data can be transferred. In
8051, the registers R7 to R0 and
DPTR can be used as pointers and
can be used to transfer data. The
pointers should be followed by a @
symbol, to represent that it is a
memory pointer. The registers R0 to
R7 can be used to point the internal
RAM

only

and

if

external

data

transfer is needed, the DPTR can be

used.

MOV
@Rp,
#8-bit

8-bit immediate value is stored in

the location pointed to by Rp

MOV
@Rp,
8-bit
add

MOV
@Rp,
A

MOV
8-bit
add,
@Rp

MOV
A,
@Rp

Content of location specified by

the 8-bit address is transferred
to location pointed by Rp

Content of A is transferred to the

location pointed to by the Rp

Content of location pointed to by

Rp

is

stored

in

the

location

specified by 8-bit address

Content of location pointed to by

Rp is stored in A

Logical Instructions
The 8051 performs various logical
operations like OR, AND, EX-OR, and
NOT and rotate, swap, clear, and
complement.

ANL
A,
#8-bit

ANL
A,
8-bit
add

AND each bit of content of A with

8-bit immediate value

AND each bit of content of A with

the content of location specified
by 8-bit address

ANL

AND each bit of the content of A

A, Rr

with content of Rr

ANL
A,
@Rp

AND each bit of content of A with

the location pointed to by Rp

ANL

AND each bit of the content of

8-bit

location

add, A

address with the content of A

specified

by

8-bit

ANL

AND

8-bit

location

add,

address

#8-bit

value

ORL
A,
#8-bit

ORL
A,
8-bit
add

each

bit

of

content

specified
with

8-bit

by

of

8-bit

immediate

OR each bit of content of A with

8-bit immediate value

OR each bit of content of A with

the content of location specified
by 8-bit address

ORL

OR each bit of the content of A

A, Rr

with content of Rr

ORL
A,
@Rp

OR each bit of content of A with

the location pointed to by Rp

ORL

OR each bit of the content of

8-bit

location

add, A

address with the content of A

specified

by

8-bit

ORL
8-bit
add,
#8-bit

XRL
A,
#8-bit

XRL
A,
8-bit
add

OR each bit of content of location

specified by 8-bit address with
8-bit immediate value

EX-OR each bit of content of A

with 8-bit immediate value

EX-OR each bit of content of A

with

the

content

of

location

specified by 8-bit address

XRL

EX-OR each bit of the content of

A, Rr

A with content of Rr

XRL
A,
@Rp

EX-OR each bit of content of A

with the location pointed to by Rp

XRL

EX-OR each bit of the content

8-bit

of

add, A

address with the content of A

location

specified

by

8-bit

XRL

EX-OR

8-bit

location

add,

address

#8-bit

value

CLR A

each

of

specified
with

8-bit

content
by

of

8-bit

immediate

Clear the content of A. zeros will

be loaded to A

Complement
CPL A

bit

the

content

of

i.e., ones to zeros and zeros to

ones

Rotate and Swap

The

rotate

and

swap

instructions

uses the contents of the accumulator

and it cannot be used with other
registers.

Content of A is rotated to left one

RL A

time. MSB goes to LSB and LSB

shifts to D1 position.

Content of A is rotated through

RLC

the carry to left one time. MSB

goes to carry and carry goes to

LSB.

Content of A is rotated to right

RR A

one time. LSB goes to MSB and

MSB shifts to D6 position.

Content of A is rotated through

RRC

the carry to right left one time.

LSB goes to carry and carry goes

to MSB.

The
SWAP
A

nibble

positions

of

are

interchanged. Lower nibble goes

to the place of higher nibble and
higher

nibble

goes

to

lower

nibble. One nibble is 4 bits.

Arithmetic Instructions
The arithmetic instructions perform
operations

like,

increment,

decrement,

addition,

subtraction,

multiplication, and division, decimal

adjust.

INC A

INC Rr

Content of the accumulator A is

incremented by one.

Content of the register Rr is

incremented by one.

INC

Content of location specified by

8-bit

the

add

incremented by one.

INC

Content of DPTR is incremented

DPTR

by one.

INC

Content of location pointed by

@Rp

Rp is incremented by one.

DEC A

8-bit

address

is

Content of the accumulator A is

decremented by one.

DEC Rr

Content of the register Rr is

decremented by one.

DEC

Content of location specified by

8-bit

the

add

decremented by one.

DEC

Content of location pointed by

@Rp

Rp is decremented by one.

ADD

A,

#8-bit

ADD

8-bit
add

address

is

Content of A is added with 8-bit

immediate value and the result
is stored in A.

A,

Rr

ADD

8-bit

Content

of

is

added

with

content of Rr and the result is

stored in A.

A,

Content

of

is

added

with

content of location specified by

8-bit address and the result is
stored in A.

Content
ADD

A,

@Rp

of

is

added

with

content of location pointed to

by Rp and the result is stored
in A.

Content

of

and

is

added

8-bit

with

ADDC A,

carry

immediate

#8-bit

value and the result is stored in

A.

ADDC A,

Content

8-bit

carry and content of Rr and the

add

result is stored in A.

Content
AD

DC

A, Rr

of

of

is

is

added

added

with

with

carry and content of location

specified by 8-bit address and
the result is stored in A.

Content of A is subtracted by
ADDC A,

carry and content of location

@Rp

pointed to by Rp and the result

is stored in A.

SUBB
A,#8-bit
add

Content of A is subtracted by
carry

and

8-bit

immediate

value and the result is stored in

A.

SUBB A,

Content of A is subtracted by

8-bit

carry and content of Rr and the

add

result is stored in A.

Content of A is subtracted by
SUBB A,

carry and content of location

Rr

specified by 8-bit address and

the result is stored in A.

Content of A is subtracted by
SUBB A,

carry and content of location

@Rp

pointed to by Rp and the result

is stored in A.

Content of A is multiplied by
content
MUL AB

order

of

byte

B
of

and
the

the

lower

result

is

stored in A and higher order

byte of the result is stored in
B.

Content

of

is

divided

by

content of B and the quotient is

DIV AB

stored in A and the reminder is

stored in B.

Adjust the sum of two packed

BCD

DA A

numbers

register;

leave

found
the

in

adjusted

number in A.

Jump And Call Instructions

The

jump

directly

and

alter

the

call

instructions

content

of

the

instruction pointer and changes the

sequence of the program to start
from a different location. The jump
instructions can have one of three
ranges:

Relative

range,

Short

absolute range, and Long absolute

range. The relative address range is

of 256 bytes wide, the jump may

occur up to 127 locations forward and
128

bytes

backward.

In

short

absolute range, the 64K memory is

divided

into

32

occurs

within

pages

the

and

page.

jump

In

long

absolute range, the jump can occur

to any location from 0000H to FFFFH.

Unconditional jumps

Jumps to the location formed

JMP

by adding the A to DPTR. The

@A+DPTR

address can be anywhere in

the memory.

AJMP
sadd

Jump
address

to

short
within

absolute
the

represented by sadd

page

Jump
LJMP Iadd

to

long

absolute

address (ladd) any where in

the memory

SJMP add

Jump

short

relative

address

Do

NOP

to

nothing.

Just

wait

and

goes to the next instruction.

Conditional jumps

JC

Jump to relative address radd, if

radd

carry is set

JNC

Jump to relative address radd, if

radd

carry is reset

JB
radd

b,

Jump to relative address radd, if

the addressable bit is set.

JNB b,

Jump to relative address radd, if

radd

the addressable bit is reset.

JBC b,
radd

CJNE
A,
8-bit
add,
radd

CJNE
A,
#8-bit,
radd

Jump to relative address radd,

if the addressable bit is set and
clear the addressable to 0.

Compare the content of A with

content of location specified by
8-bit address and if not equal,
jump to relative address.

Compare the content of A with

8-bit immediate data and if not
equal, jump to relative address.

CJNE

Compare the content of Rn with

Rn,

the 8-bit immediate data and if

#8-bit,

not

radd

address.

CJNE

Compare the content of A with

@Rp,

content of location pointed to by

equal,

jump

to

relative

#8-bit,

Rp and if not equal, jump to

radd

relative address.

DJNZ

Decrement Rn by one and if Rn

Rn,

is

radd

address

DJNZ

Decrement the content of the

8-bit

location

add,

address and if content is not

radd

zero, jump to relative address

JZ

Jump if zero flag is set, to the

radd

relative address

JNZ

Jump to the relative address, if

radd

the zero flag is reset

not

zero,

jump

specified

to

by

relative

8-bit

CALL and RET Instructions

The CALL and RET instructions are
used to call a subroutine and return
from the subroutine. On reading the

call instruction, the content of the

instruction pointer is pushed into the
stack and the processor jumps to the
address specified in the instruction.
On reading the RET instruction, the
processor retrieves the address from
the stack and return to the main
program.

ACALL

Call the subroutine specified by

sadd

the short absolute address sadd.

LCALL

Call the subroutine specified by

ladd

the long absolute address ladd

RET

Returns from to subroutine

5.2 Interrupts
Interrupts

may

be

generated

by

internal chip operations or external

sources. In both ways, the processor
calls

an

subroutine

interrupt-handling
located

predetermined

absolute

at

address,

which is called as the vector table.

There are five sources which can an
interrupt in 8051 and three of them
come from two operations: Timer 0,
Timer 1 and serial port interrupt (Rl
or

Tl).

The

other

two

are

from

external interrupts INTO# and INT1,

through port pins P3.2 and P3.3. The
8051

have

interrupt

three

enable

registers:
(IE)

an

register,

interrupt priority (IP) register, and

timer

control

controlling

(TCON)

the

register

operations

for

of

the

interrupt.
The bit-definition of Interrupt Enable
(IE) register is given below

EA

ET2

ES

ET1

EX1

ET0

EX0

EA: Enable all interrupt. If set, all

the interrupts will be enabled and
if reset, all the interrupts will be
disabled.
ET2: reserved for future use.
ES: Enable serial port interrupt. Set
to one to enable serial port interrupt

and reset to zero to disable serial

port interrupt.
ET1: Enable timer 1 interrupt. If set,
timer 1 interrupt will be enabled and
if reset, timer 1 interrupt will be
disabled.
EX1: External interrupt 1: If set,
external interrupt 1 will be enabled
and if reset, external interrupt 1 will
be disabled.
ET0: Enable timer 0 interrupt. If set,
timer 0 interrupt will be enabled and
if reset, timer 0 interrupt will be
disabled.
EX0: External interrupt 0: If set,
external interrupt 0 will be enabled
and if reset, external interrupt 0 will
be disabled.

The

bit

definition

for

Interrupt

Priority (IP) register is given below.

PT2

PS

PT1

PX1

PT0

PX0

PT2: reserved for future use

PS: Priority of serial port interrupt
PT1: Priority of timer 1 interrupt
PX1: Priority of external interrupt 1
PT0: Priority of timer 0 interrupt
PX0: Priority of external interrupt 0

Interrupt types
Timer interrupt: The timer interrupt
occurs as a result of timer overflow
(from all ones to all zeros). The

corresponding timer flag is set and

the

processor

is

directed

to

the

vector location.
Serial port interrupt: The serial
interrupt occurs when a byte has
been received or transmitted. When
a byte has been received, the Rl flag
will be set and when a byte has been
successfully transmitted, the Tl flag
will be set. But both these events
cause

single

interrupt

and

the

program must check which event had

taken place.
External

interrupt:

external

interrupts

different

interrupts.

The

two

causes

two

The

interrupts

can be programmed to respond to

level or high to low transition by
altering the bits IT0 and IT1.

Reset: This is also an interrupt which

causes

the

CPU

registers

to

be

cleared and the program counter is

loaded with 0000H. The value of the
program

counter

is

not

stored

anywhere.

Interrupt priority
The register IP gives the high or low
priority

to

interrupts

the
occur

interrupts.
at

same

If

instant,

then they will follow the ranking.

1.

IE0

2.

TF0

3.

1E1

4.

TF1

5.

Serial RI or TI

two

Interrupt destinations
If an interrupt occurs the program
sequence will be transferred to a
vector location. The interrupt types
and their jump locations are given
below.
Table 5.1
Interrupt

Address

type

(HEX)

IE0

0003

TF0

000B

SIE1

0013

TF1

001B

SERIAL

0023

8051 system Design

The common 8051 have 4K EPROM
and

128

bytes

of

RAM.

If

the

requirement of the memory exceeds

this limit, the 8051 memory can be
expanded

by

interfacing

external

memory to it. Commercially available

memory chips can be used to expand
the memory. The memory may be
EPROM with size 8K to 64K and RAM
with size 2K to 64K can be used.
The

typical

expansion

of

microcontroller is shown in figure.

The system design uses a 12MHz

crystal

and

the

following

components.

8031

(ROM

microcontroller

which

Jess
is

equivalent to 8051)

64K external EPROM

32K external RAM

8 general purpose I/O lines (port

1 of microcontroller)

general

programmable

purpose
I/O

lines

pins P3.2 to P3.5)

1 full duplex serial port

or
(port

Figure 5.1: 8051 based System Design

The system shown in the figure can

be divided into external memory and
memory-decoding circuit, reset and
clock circuits, and expanded I/O.

External

Memory

and

Memory-Decoding circuit
External memory is interfaced to the
microcontroller via the ports 0 and 2.
The port 0 is an open drain output,

so a pull-up resistor of 33K ohms is

connected to each pin of the port.
The port 0 supplies the multiplexed
address (A0 to A7) and data lines
(address at one part of machine cycle
and data in the rest). The pin 30 of
the microcontroller supplies the ALE
signal to indicate the validity of the
address in the port 0 lines. When
this line is high, it indicates that the
port 0 is supplying the address in its
lines. The latch 74LS373 is provided
to latch the address lines from the
port

and

the

ALE

signal

is

connected to the latch enable pin of

the latch. The rest of the address
lines (A15 to A8) are supplied by the
port 2. If the EPROM of 16K and RAM

of 8K are used, the EPROM occupies

the address from 0000H to 3FFFH and

the RAM occupies 3FFFH to 5FFFH.

The

CE

signal

to

the

EPROM

is

supplied

through
the
OR
gate

decoded by A15 and A14. The OE

pin of the EPROM is connected to the

P3EN pin of the Microcontroller. The

CE signal for the RAM is supplied

through decoding the A 15, A 14 and

A13 (010) lines. The OE and WE

signals are connected to the WR and
RD signals. The figure shows a 8051
system having a variety of EPROM
and RAM combinations, which can be
chosen according to the requirement,
by placing or removing jumpers. The
jumpers and their relative addresses
are shown in the table 5.2.

Table 5.2

Memory Size

EPROM

RAM

8K

None

None

16K

J1

NA

32K

J1, J2

J4, J5

64K

J1, J2, J3

NA

Reset and Clock circuits

The 8085 reset pin is an active high
pin. If a high signal is supplied to
the reset of the microcontroller, the
microcontroller is reset and all the
registers will be loaded zero and the

ports will output zero. The reset pin

must

stay

low

for

atleast

two

machine cycles. At a threshold of

2.5V, the microcontroller begins to
run. The clock is supplied by a 12
MHz crystal is connected to the pin
18 and 19 of the microcontroller.

Expanded I/O
The ports 1 and 3 are used as I/
O ports. Two pins of port 3 (P3.6
and P3.7) are used for supplying

WE and RD signal. The pins P3.0 and

P3.1 supply the RXD and TXD of the
serial port. The rest of the pins of the
port 3 can be used as I/O ports or as
interrupt lines and timer input lines.
The entire port 1 can be used as
bi-directional programmable parallel
port.

The ports 1 and 3 can be used

expanded using programmable port
chips

like

8255

Programmable

Peripheral Interface. The schematic

is given in the figure. The port 1 and
some pins of the port 3 are expanded
to three ports.

5.4 Testing The Design

Once every hardware is assembled,
it must be tested to verify that the
system is working. The system can
be tested by some procedures and
some

programs,

discussed here.

which

will

be

Crystal and RESET Test

This is the first test to be performed,
because if the crystal is not working,
the other peripherals of the system
cannot be tested in any way. The ALE
signal is connected to an oscilloscope
to check the oscillator. Because the
if

the

oscillator

is

working,

the

microcontroller will start executing

the program stored in the EPROM
starting from 0000H. The ALE signal
will be active and its frequency will
be 1/6 of the crystal frequency. The
RESET switch is pressed and the
statuses of the ports are checked.
If they stay high, it means that the
RESET circuit is working.

ROM Test
The ROM must be tested to ensure
that the programs entered into them
will

be

executed

by

the

microcontroller. One of the ways of

testing the memory is by entering
small programs into the memory and
testing the microcontroller. One such
program is given below. This program
will cause the microcontroller to jump
from one location to another in power
of two. At the end of the program the
microcontroller will stay at 8000H.
The address line A15 can now be
checked whether it stays in high or
not.

If

there

interfacing

the

is

any

trouble

microcontroller

in
will

stay at the last memory location. The

EPROM 64K is used for this test.

Address

START:

Mnemonics

Comment

.ORG

start

OOOOH

program

LJMP ADD2

; test A1 and A0

.ORG
0004H

ADD2:

LJMP ADD3

; test A2

.ORG
0008H

ADD3:

LJMP ADD4
.ORG

; test A3

001

OH

ADD4:

LJMP ADD5

; test A4

.ORG
0020H

ADD5:

LJMP ADD6
.ORG
0040H

; test A5

of

the

ADD6:

LJMP ADD7

; test A6

.ORG
0080H

ADD7:

LJMP ADD8

; test A7

.ORG
0100H

ADD8:

LJMP ADD9

; test A8

.ORG
0200H

ADD9:

LJMP

; test A9

ADD10
.ORG
0400H

ADD10:

LJMP
11

.ORG
0800H

ADD

; test A10

ADD11:

LJMP

ADD

; test A11

ADD

; test A12

ADD

;test A13

12
.ORG
1000H

ADD12:

LJMP
13
.ORG
2000H

ADD13:

LJMP
14
.ORG
4000H

ADD14:

LJMP

; test A14

ADD15
.ORG
8000H

ADD15:

LJMP
ADD15
.END

; test A15

5.5 Time Delays

Time

delays

can

be

done

using

software loops, which do nothing but

executes the same operation over
and over. Time delays can also be
generated using one of the timers.
The

timer

can

be

used

either

in

software or using interrupt method.

In

software

method,

the

timer

is

continuously monitored by software

polling (reading and checking) and if
it reaches the expected value, the
delay ends. In interrupt method, the
timer is initialised to deliver interrupt
and the microcontroller waits until
the timer interrupt is generated.

Pure Software Time Delay

The

time

delay

is

generated

by

loading a register with a count value

and decrementing one by one until
it becomes zero. If the number of
machine cycle is known, it is easy to
find the time need to execute that
instruction. The time to execute an
instruction

having

Cnumber

of

machine cycles is given by.

T inst = (C x 12) / crystal frequency
The illustrative program shows how
the register R7 is used for generating
time delay of 0.5ms.

DELAY:
LOOP:

MOV R7, #0FAH

; R7 is loaded with count value FAH
DJNZ R7, LOOP
; decrement and checks R7
RET

; return to the main program

Software Polled Timer

This

method

uses

the

timer

to

generate a precise timer interval. The

timer

is

continuously

polled

and

checked whether it has reached the

count value or zero. If the timer
reaches 00H, the overflow flag will
be set. The program should monitor
this overflow flag and generate the
time delay. The timer is initialised
to generate 250 microseconds at a
crystal frequency of 11.0592 MHz.
.ORG 0000H
LJMP MAIN
.ORG 0030H
MAIN:MOV TCON, #01H
MOV TMOD, #02H
MOV TH0, #19H

; configuring timer control register

; configuring the mode of timer 0
; loading the delay count to timer high byte

WAIT:

MOV TL0, #19H

; loading the delay count to timer low byte

ORL TCON, #10H

; start timer 0 to run

JBC TF0, OVER

; check overflow flag. if set, reset and exit
SJMP WAIT
; if not check again

OVER:

SJMP OVER
END

Hardware time delay

The

method

generate
discussed

the

uses

the

delay.

later

in

timers

This
the

will

to
be

interrupt

programming.

5.6 Lookup Table

When one number is converted to
another, on one to one basis. One
such example is to convert ASCII to
BCD. To convert an ASCII number
to BCD, 30H should be subtracted
from it. This is simple approach and

Double click this page to view clearly

each ASCII number is taken and 30H

is subtracted and stored. Another
method is to create a table, which
has all the corresponding values of
BCD for ASCII values. So it is simple
to read the BCD number from the
table, which is called lookup table.
The ASCII character is used to form
the part of address of the lookup
table. The following table 5.3 shows
a lookup table for ASCII to BCD
conversion
Table 5.3:

Mnemonics

Comments

.ORG

Starting

1030H

table

address

of

lookup

.DB 00H

.DB 01H

.DB 02H

.DB 03H

.DB 04H

.DB 05H

.DB 06H

.DB 07H

Location 1030H contains 00

BCD

Location 1031H contains 01

BCD

Location 1032H contains 02

BCD

Location 1033H contains 03

BCD

Location 1034H contains 04

BCD

Location 1035H contains 05

BCD

Location 1036H contains 06

BCD

Location 1037H contains 07

BCD

.DB 08H

.DB 09H

Location 1038H contains 08

BCD

Location 1039H contains 09

BCD

The low byte of each BCD code is

supplied by the ASCII code itself. If
the DPTR is loaded with 1000H, and
A is loaded with the ASCII number,
then the address will be calculated by
DPTR+A and the instruction is MOV
A, @A+DPTR. This copies the content
of

the

location

specified

by

the

address (A+DPTR) to A. The Program

counter (PC) can be used in the place
of DPTR. But the PC can be used
for only lookup tables located in a
small range from the program. The
DPTR can be used for lookup tables
far from the program.

PC as a base address
Whenever the lookup table is very
nearer to the program within 256
bytes and small, the PC can be used
as a base address for the lookup
table. The offset can be supplied by
the

Accumulator

program

A.

illustrates

the

following

finding

the

square of numbers from 0 to 15.

.ORG 0000H
LJMP
MAIN .ORG
MAIN: 0030H MOV A, #VALUE

; load the value to A

ADD A, #02H
; compensate 2 bytes for last
MOVC A, instruction
@A+PC ; copy from lookup table
OVER:

SJMP OVER
.DB
OOH
01H
04H
09H

.DB
.DB
.DB

; 00^2 = 00
;
01^2
=
01 ; 02^2 =
04 ; 03^2 =
09

Double click this page to view clearly

sjmp

.DB 10H
.DB 19H
.DB 24H
.DB 31H
.DB 40H
.DB 51H
.DB 64H
.DB 79H
.DB 90H
.DB 0A9H
.DB 0C4H
.DB 0E1H
.END

;
;
;
;
;
;
;
;
;
;
;
;

04^2
05^2
06^2
07^2
08^2
09^2
0A^2
0B^2
0C^2
0D^2
0E^2
0F^2

=
=
=
=
=
=
=
=
=
=
=
=

16
25
36
49
64
81
100
121
144
169
196
255

DPTR as a base address

The DPTR can be used wherever the
lookup table is far from the program
location or very large. The DPTR can
be used as a base address and the
value itself (loaded in A) supplies the
offset

address.

illustrates

such

The
method

program
is

listed

below. The program calculates the

square of numbers from 0 to 255.
Each element of the lookup table
occupies two locations.

.ORG 000H
LJMP MAIN
.ORG 0030H
MAIN: MOV A, #21H

; load value to A

MOV R1, A

; load value to R1 for future use

MOV DPTR, #0200H

; load DPTR with low order address

MOVC A, @A+DPTR
MOV R0, A

; get the value from low lookup table

; store result in R0

MOV A,R1

; load value to A

MOV DPTR, #0300H

; load DPTR with high order address

MOV A, @A+DPTR
MOV R1, A

; get the value from high lookup table

; store result in R1

OVER: SJMP OVER

.ORG 0200H
.DB 00H
.DB 01H
.DB 04H
...
...
...
.DB 41H
...
...
.DB 01H
.ORG 0300H
.DB 00H
.DB 00H
.DB 00H
...
...
...

.DB 04H
...
...
.DB OFEH
.END

; lower order result for 21H^2

; lower result for FFH^2

; higher order result for 21H^2

; higher result for FFH^2

Double click this page to view clearly

Serial communication
The

8051

contain

serial

transmission/reception

data

circuitry,

which can be programmed to operate

in one of the four modes 0 to 3. One
of the modes is an UART (Universal
Asynchronous
Transmitter)
asynchronous

Receiver
mode.
mode,

and

In
the

the

data

is

accompanied with a start bit and stop

bit. The 8051 uses the timer 1as a
baud rate generator, which generates
the

baud

required

for

data

transmission and reception. Before

transmitting

character,

the

microprocessor should check whether

the

previous

transmission

is

completed or not. This is done before

every transmission to prevent data
loss. The following program describes
the transmission of data with a baud
rate 2400 using an 11.0592 MHz
crystal.

The

crystal

frequency

11.0592 MHz is used instead of 12

MHz to reduce the amount of error.
The baud rate is calculated using the
formula; baud = crystal frequency /
(32 x 12 x (256 count)).The count
value Is found using the formula and
is loaded in the timer 1. The UART
takes approximately Sms to transmit
one character. The delay program

has an execution time of 0.5ms and

to get 5ms delay it must be executed
ten

times.

The

program

is

listed

below.
; The clock frequency is 11.0592 MHz and the baud rate is 2400
.EQU BAUDNUM, 0F4H
.EQU COUNT, 0AH
.ORG 0000H
ANL PCON, #7FH
; set SMOD bit 0 for baud x 32
ANL TMOD, #30H
;
ORLTMOD, #20H
; set timer mode 2
MOV TH1, #BAUDNUM
; load the baud number to timer
SETB TR1
; start timer 1
TRNS:

XTIM:
DELAY:
LOOP:

MOV SCON, #40H

; select serial mode 1
MOV SBUF, #'A' ; load the data to be transmitted
ACALL XTIM
; call 5ms delay
SJMP TRNS
MOV R6, #COUNT
; execute delay ten times
MOV R7, #0E7H
; R7 is loaded with count value E7H
DJNZ R7, LOOP
; decrement and checks R7
DJNZ R6, DELAY
RET

Serial

;
; return to the main program

Reception

through

Polling
The serial reception is controlled by
polling the specified data bit in the

Double click this page to view clearly

SCON register. When a data has been

received it sets the Rl bit of the SCON
register.

So

the

program

must

monitor this bit regularly to acquire

the data from the serial port. If the
serial port receives a data before the
previous data has been read by the
microcontroller, the new data will be
discarded. It is necessary to reset the
Rl bit before the serial port receives
the last bit of the new data. The
example program shows how it is
done.

The

program

monitors

the

serial port by monitoring the Rl bit

and if Rl is set, it reads the data in
the SBUF and outputs the data in the
port 1. Then it resets the Rl bit and
waits for next data.

; The clock frequency is 11.0592 MHz and the baud rate is 2400
.EQU BAUDNUM, 0F4H
.ORG 0000H
ANL PCON, #7FH
; set SMOD bit 0 for baud x 32
ANL TMOD, #30H

HERE:

RECEIVE:

ORL TMOD, #20H

; set timer mode 2
MOV TH1, #BAUDNUM
; load the baud number to timer
SETB TR1
; start timer 1
MOV SCON, #40H
; select serial mode 1
SETB REN
JBC RI, RECEIVE
NOP
SJMP HERE
CLRRI
MOV P1, SBUF
SJMP HERE
.END

Similarly serial transmission is also

done by polling. If any data is written
to the serial buffer SBUF before the
transmission of the previous data is
completed, the transmission will be
error some. The TI flag in the SCON
register will be set, if the serial port
completes the transmission of a data.

Double click this page to view clearly

So program should check the Tl flag

before transmitting a character. An
example program is listed below.
; The clock frequency is 11.0592 MHz and the baud rate is 2400
.EQU BAUDNUM, 0F4H
.ORG 0000H
ANL PCON, #7FH
ANL TMOD, #30H

XMIT:
HERE:

; set SMOD bit 0 for baud x 32

ORL TMOD, #20H

; set timer mode 2
MOV TH1, #BAUDNUM
; load the baud number to timer
SETB TR1
; start timer 1
MOV SCON, #40H
; select serial mode 1
MOV SBUF, #'A' ; loading SBUF with data
JBC TI, XMIT ; check for transmission complete
SJMP HERE
.END

5.8 Interrupt Programming

The

interrupt

system

follows

the

steps given below.

1.

The interrupts should be enabled

before any interrupt is generated.

Double click this page to view clearly

If

of

any

the interrupts is

generated before it is enabled,

it

will

be

discarded. So

programmer
interrupt

the

should enable the

enable

bits

in

the

interrupt enable register (IE).

2.

Once the interrupt is generated,

the

CPU

finishes

the

current

instruction and pushes the PC in

the stack. Then the content of
the PC is replaced with the vector
address of the interrupt. At the
start

of

interrupts

the

routine,

are

all

the

disabled

to

prevent further interrupts.

3.

The service routine is executed.

At the end of the service routine,
the status of the IE is restored.

4.

Every service routine should be

ended with a RETI instruction,
which

returns

to

the

main

program.
An interrupt service program is
also called as real-time program
because it does not wait for any
software polling action and the
transfer of the program is very
quick.

Subroutines

that

are

written to specifically deal with

the interrupts are called as the
interrupt handlers. The 8051 has
two

registers

to

control

the

interrupts: the Interrupt Enable

(IE) and the Interrupt Priority
(IP).

The

Interrupt

Enable

(IE)

register
The

IE

register

controls

alt

the

interrupts associated with the 8051.

The

interrupts

are

individually

programmable and can be enabled

and disabled through this register.
Additionally, the IE register provides
global interrupt enable bit, which can
enable or disable all the interrupts in
a single instruction.

The

Interrupt

Priority

(IP)

control register
The IP SFR may be used by the
programmer to determine which

interrupts are the most important.

If two interrupts occur at a same
time, the priority should be provided
to any of the interrupts depending on
the necessity or emergency, to avoid
confusion.

The

interrupt

priority

register has been discussed already

in detail. If two interrupts happen at
the same time, and they have same
priority,

the

8051

itself

preference as follows
1.

External interrupt 0 (P3.2)

2.

Timer 0 Overflow

3.

External interrupt 1 (P3.3)

4.

Timer 1 Overflow

5.

Serial Port

give

Interrupt Handler
The interrupts have vector addresses
in the page starting from 0003H. The
interrupts

and

addresses

of

the

interrupt handlers are specified in the

table 5.4.
Table

Interrupt source

Vector address

External interrupt 0

0003H

Timer 0 Overflow

0000BH

External interrupt 1

0013H

Timer 1 Overflow

001 BH

Serial Port

0023H

Timer Interrupt delay

The timer is initialised to deliver an
interrupt to the system, whenever an
overflow occurs. An interrupt service
routine

should

be

written

at

the

vector address. The timer 0 has the

vector at 000BH. So whenever the
timer

interrupt

microprocessor
address

and

is

generated,

goes

the

the

vector

executes

the

instructions written there. Here at

the

vector

address,

the

machine

sequence is shifted to 00D0H, where

the interrupt service routine has been
written. The timer is initialised to

generate

250

microseconds

at

crystal frequency of 11.0592 MHz.

The program counts four interrupts
to get one millisecond delay.
.ORG 0000H
LJMR MAIN
.ORG 000BH
LJMP ISRT
.ORG 0030H
MAIN: ORL IE, #82H
MOV TCON, #01H

; vector address of timer 0

; go to service routine
; enabling timer interrupt
; configuring timer control register

MOV TMOD, #02H

; configuring the mode of
MOV THO, #19H
; loading the delay count
MOV TLO, #19H
; loading the delay count
MOV R7, #04
; get for interrupts from
ORL TCON, #10H
; start timer 0 to run
CJNE R7, #00, LOOP; is 64 data over ? if no
; Timer 0 interrupt service routine

timer 0
to timer high byte
to timer low byte
timer
go to loop

.ORG 00D0H
ISRT;ORL IE, #7FH ; disable all interrupts
DEC R7
; decrement interrupt counter
ORLIE,#80H
; enable all other interrupt
RETI
; return from interrupt
.END

Serial

Reception

and

Transmission using Interrupt

When large volume of data is to be
received,

the

polling

and

delay

methods cannot be done.

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The serial port interrupt is used to

reduce the time delay caused by the
polling and delay
serial

methods.

The

port interrupt has a vector at

the address 0023H.

serial

Whenever

the

port receives or transmits a

data., a serial port interrupt will be

generated

and

sequence

jumps

the
to

program

the

interrupt

vector address. An interrupt service

routine
address.
have

is

written

The

RETI

at

service

instruction

the vector

routine must
at

the end

to return to the main program. The

interrupt

service

routine

reads the

data from the SBUF and outputs the

data in the port 1. The program is
listed below.

; The clock frequency is 11.0592 MHz and the baud rate is 2400
.EQU

BAUDNUM, 0F4H

.ORG 0000H
LJMP MAIN
.ORG 0023H
CLR RI
MOV P1, SBUF
RETI
.ORG 0100H
MAIN:
ANL PCON, #7FH

; set

SMOD bit 0 for baud x 32

ANL TMOD, #30H

ORL TMOD, #20H

; set timer mode 2

MOV TH1, #BAUDNUM

SETB TR1
MOV SCON, #40H
SETB REN

; load the baud number to timer

; start timer 1
; select serial mode 1

ORL IE, #90H ; enable serial interrupts

HERE: SJMP HERE
.END

The same method can be used for

transmission
transmission

also.
is

When

complete,

the
serial

port interrupt will be generated and

the

microprocessor

jumps

to

the

vector address. At the end of the

service routine the RETI instruction is
written. The program is listed below.

Double click this page to view clearly

; The clock frequency is 11.0592 MHz and the baud rate is 2400
.EQU BAUDNUM, 0F4H
.ORG 0000H
LJMP MAIN
.ORG 0023H
CLR TI

; clear Tl

MOV SBUF, # A ; load SBUF with data

RETI
MAIN:

.ORG 0100H
ANL PCON, #7FH

; set SMOD bit 0 for baud x 32

ANL TMOD, #30H

ORL TMOD, #20H
; set timer mode 2
MOV TH1, #BAUDNUM
; load the baud number to timer
SETB TR1
MOV SCON, #40H

; start timer 1
; select serial mode 1

ORL IE, #90H; enable serial interrupts

HERE: SJMP HERE
.END

Data

acquisition

using

External Interrupt
The external interrupts can be used
by slow responding external devices
to

communicate

with

the

microcontroller.

Double click this page to view clearly

The
1

external interrupts
has

and

vector

0013H.

example,

addresses

In

the

this

and

0003H

following

external interrupt 0

is used for monitoring the end

conversion

of

an

ADC0804

is

ADC.

of
The

successive

approximation type ADC and has an

internal RC oscillator. The start of
conversion

to

the

ADC

must

be

applied to the pin 2 (WR#) and is

given through the port 2 (P2.1) and
the

converted

data

is

inputted

through the port 0. The data is then

outputted

via

the

port

1.

The

schematic diagram is shown in the

figure.

Figure 5.2: Interface of ADC0804 to 8051.

The program is listed below.

.ORG 0000H
SJMP MAIN
.ORG 0003H
LJMP EISR
.ORG 0100H
MAIN:
ORL IE, #81H ; enabling external interrupt 0
CLR P2.2
; start of conversion
NOP
NOP
SETB P2.2
; rising edge starts conversion
HERE: SJMP HERE
.ORG 0200H
EISR:ANL IE, #7FH
CLR P2.1
; enable the output latch of ADC
NOP
NOP
MOV A, P0
SETB P2.1
MOV P1, A
ORL IE,#80H
RETl

; read data from port 0

; disable output latch of ADC
;enable all other interrupts

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