68000,68010

and 68020 Primer

Stan Ke ll y-BootIe and Bob Fowler

Howard W . Sams & Co ., Inc .

A Subsidiary of Macmillan, Inc.
4300 West 62nd Sireet, Indianapolis, Indiana 46268 U.S.A.

" 1985 by n.. IMliIe GrouP. Inc.

f1RST EO!TJON
SECOND PRlNTING-I987

AI rIt,jIl$ ~ fib pill" ollhis book 5MII be reprockxed. SIQI\'d in ;, Te!!leval \mI. or mmsmlned by IIOJ me;'ll$.
1kctn:ric:. ll'lI!CMniciIl, photocopying. recording. or CIIIle!I.uise. withoutllllinen pemtlssio. from me publlshal fib pillenI
Iiobllily Is lIS5Umed with respect I() me use of me In!ormalion conIaIned herein. While e\Il'fY prtc.IIulion I>M been taken In
me pref)II~tion ollhls book. me publi5her llSSUme5 no responsibility lor errors or omIsIons. Neltha Ii ;,rt,'lIobitily aswmed
lor dam;,ges resul~ng from me use of me information conUIlned hereon.
The w;'lle Group hM rnbde eue.y ;,nemplto wpply tradmlari< Inlormalion ;,00..1 CQIllpiI", 1'WTOI!5. ~ iIIld seMces
mentioned In IIlIs book. The ~ indicated beICJo,r.o were derived from worious to.,,~es. The w;'''e Gn:Iup Cilnnot ;,nesl
I() the IOCCUIllCll ollh'$ Informlltlon.
808O.8088I8086;,nd Intel III'\! I~rb ol lnlel Corporlltlon.
AM t oo Is;, registered 1I'!lderMri< 01 Alpha Mkrosystems. Inc.
Apple Is II 1rlsde1'Tl!lri< 01 Apple Computer, Inc.
EXORciser. EXORtnbCI. EXOOset. VERSAmodules. ;,nd VMErnOO..oIe$ 11m mg1s10'ed ~rk$ 01 MoIOfda. Inc:.
IBM;,nd IBM PC III'\! tr!>demlln.s oI lnlernalion.lJ Businoess M;ochlne$., Inc:.
l..otus, 1-23. and Sym~ are Ir'a!IerMrks of Lotus ~I ~Iion.
MlIdnlosn Is II trlIdetnD.ri< 1Ic~ 10 Apple Compu~ Inc:.
MBASIC Is a reglsleNd 1l'lIdemari< of MIr:r<.>soft Corporation.
R6dio Sllack Is a reglSlefed 1Ji\demilri< 01 R6dio SIlack.
VobrdSt;,r Is ;, m9siered 1l'lIdemari< ol MiaoPIo lntem/ltiorwll Caporalion.
Z80 Is a ~ trademari< of Zilog. Inc.
Inlernatiorwll Standard Bcd Number 067224a.-4
LJbolIry of Congrew Catalog Card Number: 85-61636
TypogrlIIlhy by W;,I\oer Graphoc:s
Pffrud In the lkIi!ed SfoIes 0/ Ammca

To my childers everywhere:
Edmund Paul, Michele Rose,
Carol Ann, David Russell

and rather late, alas,

Anna Clare
-SIan Kelly-BooOe

To Curuprem Singh Khalsa,

whose encouragement, inspiration,
and vision over the years have helped
to prepare me for this task
- B.F.

Acknowledgments

We v.oere templed for a while to break with tradition , and claim that this book
was entirely our ()VJn v.ork, conceived, written and produced with no outside
help whatsoever! I-bnesty and chivalry, though, combined with threats from
certain quarters, finally convinced us that we should pay oor respects in the
customary manner.

First, we must thank Motorola's MOS Integrated Circuit Group without

whom (as they say) our primer \.IJOUld undoubtedly be devoted to a less inter
esting and rewarding family of chips. In particular, we are grateful to James J.

Farrell III , Technical Communications Manager, and Margaret Dickie at Motorola

Inc., Austin, Texas for their coorteoos help with permissions, pictures and diagrams.
Our debt to writers on the M68000 and 16/32 bit micros in general is
enonnous and must here be condensed to a simple, nonexhaustive enumeration:
Stritter, Treddenick, Scanlon, Starnes, Kane, Hawkins, Leventhal, Alexandridis,
Waite, Morgan.
Editorially, \Ale received encouragement from James Rounds of t-IovJard W.
Sams & Co., helpful advice from DI: Roger C. Gledhill of International Micro
Technologies, Inc., and much-needed cajolery from Mitch Waite and Jerry \-blpe
of The Waite Group.
On the production side, \Ale would like to thank lynella Cordell and her
staff at The Waite Group, who together with Marla Rabinowitz and Walter Lynam
resolved the maT>/ typographical and stylistic problems created by our keystrol<es.
Our program examples were derived from VJOrk on the Alpha Microsystems
Am - lOO/L' ~ using their M68 Assembler. The authors wish to thank Alpha
Microsystems and the San Francisco Chapter of AMUS (Alphamicro Users'
Society) for their technical assistance. We also benefited from many informal
discussions with Dr. Michael Godfrey of ICl, london and Bob Toxen of Stratus
Computer, Inc., Boston. Nevertheless, \Ale accept fuJI resp::msibility for any residual bugs and v.Jelcome your polite corrections.
Sian Kelly-Bootie proclaims his everlasting devotion to his wife IVJOnka and
step-daughter Natasha leof for their love and support throughout the project.
IV

Contents

Inlroduction

VI/I

1 Basic Microprocessor Concepts

Microprocessors
Binary Arithmetic

1
6

10
Binary Coded Decimal
13
14
Boolean Algebra
Microcomputers - the Three Components
Inside the MPU
25

BCD -

Octal and Hexadeci mal

20

29
Memories Are Made of This
Softwa re - General Overview
36

40

2 The M68000 Family

Introduction
40
The M68000 Success Story
Timing
46
W hy 16Bit?
49

44

55

3 M68000 Programmer's Models

55
Leve ls of Programming
M68000 Instru ction Set - Brief Introduction
Memory Model
62

Register Model
68
M68000 Basic Register Model

71

61

vi

Contents
Register Arithmetic
Address Registers
System Byte
84

79
83

4 M68000 Instruction Set -

First Steps

91

Instructions
91
Addressing Modes
106
Absolute Addressing Modes
116
Address Register Indirect Memory Addressing Mode
Address Register Indirect with Post-Increment: (An)+
Address Register Indirect w ith Pre-Dec rement: -(An)

t 24
128

133

5 M68000 Instruction Set - Advanced Topics

Preserving Regi ster Values - W hy and How
135
Stacks
138
Add ress Register Indirect w ith Offset
147
Address Register Indirect wi th Offset and Index
149
Index Mode - Appl ications
1SO
Multiplication
151
Division
153
Relative Modes - Motivation
158
Relative Addressing - Program Counter Addressing with Offset
Relative Addressing - Program Counter with Offset and Index
Addressing Modes - Grand Summa ry
165

6 Miscellaneous M68000 Instructions

Bit Manipulation
172
Logical Operations
173
Shift and Rotate Instructions
187
Rotates
200
Bit Testing and Setting
204
Compare wit h the CMP Family of Instructions
Miscellaneous Math
222
Multi-Precision Math
225
Binary Coded Decimal
229
Miscellaneous Data Handling
233
LinkiUnlk - Preamble
237

135

159
163

1 72

214

Contents

7 The MC66010

252

Virtual Memory
253
Virtual Machine
256
Vector Base Register
258
261
The MOVEC and MOVES Instructions
The SFC and DFC Registers and Address Spaces
Loop Mode
264
The MC6801 2
265

262

6 The MC66020

266

Instruction Cache
266
New Addressing Modes
274
Trace Bits TO and T1
278
Coprocessor Support
280
The Master Bit
285
New Instructions on the MC68020

A M66000 Instructions -

vii

288

Number of Operands

295

B M66000 Addressing Mode Types

297

C M66000 Instructions/Legal Modes

300

D M66000 Instruction Summary

303

68000 Addressing Modes

303
Addressing Mode Orthogonality and legality
307
The 68000 Instruction Summary Table - Preliminaries

310

E M66000 Resources

329

F ASCII Table
Index 349

345

Introduction

This primer is intended for the growing number of programmers and hobbyists,

both novice and experienced, who want to understand the pcMIIiul instruction
set of the Motorola M68000 family of 16/32-bit microprocessors. The instruction

set represents the language built into the chip, and ultimately, all programs
written for the M68000, whether in ADA, BAS IC, C language, assembly language, or whatever, need to be translated "dO\Aln" to this level.
With 8 -bit micros it was tricky but possible to hand code at the machine

level without assemblers. With 16-hit instruction VJOrcls (up to seven of them per
instruction) hand coding is strictly for masochists too tight to buy an assembler.
So the M68000 instruction set will usually be studied in the context of an
assembler.
The authors' attempts to master M68000 assemblers revealed a monstrous,
horrifying gap in the literature. There was no patient elementary introduction
even to those basic instructions and addressing modes that are common to all
M68000 models. More understandably. there were no popular expositions of
the exciting extensions available on the MC68010 virtual machine chip and the
fu ll-32-bit mainframe-micro MC68020. This primer is our selfless attempt to fill
both gaps.
You can view the book as a painless " first pass" for all those who wish to
gain fluency in any of the many fine M68000 assemblers and cross-assemblers
now available (see Appendix E).
Assembly language documentation can be pretty daunting unless you
already understand how the op codes \A.IOrk, a nd many of the manuals are less
than clear on which addressing modes are legal with which instruction. Beyond
that you face the hurdles of directives, macros, conditionals, libraries, linkers,
overlays. monitor calls, and so on - all of which can vary from assembler to
assembler.
Yet the rewards are great. Quite apart from the obvious advantages speed and compactness (notice hovJ often advertisements for software boast,
VIII

Inlroduclion

ix

"Written in tight, fast assembly language!"), we kn()IN of no greater joy in

computing than successfully running one's own first sizeable chunk of assembled
code. There is a feeling of, "1J.Ja.N. we did it - the 68000 and me!"
Our book should also be useful for those wanting to experiment with the
varioos M68000 educational single board kits and systems.
We have purposely avoided a detailed exploration of the M68000 microelectroniCS and IC technology. Our bird's eye view of the M68000 hardware is
a simple " black-box" approach, but sufficient, we hope, to reveal the subtle
interplay of hardware and software as realized by the Motorola design team. If
you want to delve deeper (and in the field of computers there is no bottom layer
beyond possible delving) this book will help you tackle the vast technical literature on M68000 architecture and timing, support chips, VO , coprocessors and
systems integration.
Success breeds success - a maxim which is compounded in the microcomputer industry. All semiconductor prices fall dramatically as fabrication volume and yield increase, so successful chips like the M68000, especially the
economy MC68008 version, are inevitably finding their way into the !OVJ-cost
entry-level personal and home computer market. The basic MC68000, now
available for around $50 each in small quantities, can already be found playing
diverse roles in graphics IJ.Qrkstations and multiuser business systems - not
only on the main CPU (central processing unit) board, but also pov..'ering
intelligent device drivers and VO (input/output) preprocessors. Even the more
expensive MC68010 is found lurking inside peripherals, such as the Apple laser
printer.
The MC68020 chip, currently selling for $500 in small quantities, seems
certain to fall in price to the MC68()(X) level over the next few years. The impact
on personal and office computing will be staggering!
The Apple Macintosh has already given us a glimpse of what can be done
with the pov.!eTof a basic 16132-bit MC68000. The user-friendliness we associate
with crisp, bit-mapped screens, icons, windows, and mouse-controlled pulldo.....m
menus puts heavy demands on CPU and memory.

The MC68020's extra speed (16.67 MHz, with fast RAM to match), lower
consumption (l .5 watts) , built-in coprocessor interface for economical
multiprocessing and number-crunching support, and increased memory addressing space (over 4 billion bytes) - will allOVJ bigger and friendlier operating
systems, more complex color graphics (including animation) , and less unnatural
high-level query languages providing easier access to large databases.
An added bonus will be the ability to offer several operating systems on
the same machine, solving many of the present compatibility qUirks ("what runs
on what?") and ending once and for all those tiresome medieval disputes such
povJeT

as "UNIX versus AMOS" or "CPIM versus PC-DOS." Our book will prepare
you for this revolution!

Introduction

All members of the M68000 family share the same basic instruction set,
with each enhanced model building up from the previous simpler model. This
concept of upwards compatibility at the object code level provides vital insurance for all software developers, both the individual "hacker" and the major
software houses. For as fast as hardware prices shrink, the cost of programming
escalates. The M68000 was designed with ease of programming and debugging
in mind, and further, with the assurance that whatever advances might occur in
IC techniques, programs will run without change on all future models. We will
all undoubtedly have new things to learn as the revolution unrolls apace, but
readers should be happy to know that little in this book will have to be unlearned.

PREREQUISITES
Exactly how much prior knowledge should be assumed is a problem faced by
all computer book authors. We have veered in the direction of assuming less
rather than more exposure to computer basics, and \IJe rely on your own
judgment to skip any familiar material.
Chapter 1, for example, is a quick summary of some essential microprocessor concepts that you are invited to bypass at your own discretion.
Our strategy was conditioned by the fact that a new generation of programmers, the class of '85, is entering the field with little or no prior exposure to the
previous (dying?) generation of 8-bit micros. If you have done any assembly
language programming on the Intel '" 8080 "', Zilog Z80 '" or Motorola M6800,
for instance, many of the M68000 op codes will be old friends (at least functionally), and you will be able to concentrate on the subtleties introduced by the
richer set of addressing modes. But for those new to the v.orld of op codes, \IJe
have tried to explain both the function and the motivation for each instruction,
with lots of simple examples. We have carefully chosen the order in which the
instructions are introduced, grouping together those which share some funda mental property.
There are four appendices (A - D) that list the op codes and addressing
modes in different ways, plus a pullout reference card.

BOOK PLAN
After the optional basic concepts in Chapter 1 (\IJe dismissed the corny notion
of calling this Chapter 0), Chapter 2 gives some historical and design perspectives and lists the features distinguishing the five M68000 models currently
available. Chapter 3 explains the chip from a software perspective (memory
organization and register disposition). The instructions and addressing modes

Inlroduction

XI

are then progressively described with examples, starting with the most common
and useful in Chapter 4 , accelerating gently to more advanced op codes in
Chapter 5 . Chapter 6 deals with the remaining instructions. Chapter 7 explains
the VM concept in relation to the MC68010. Finally, Chapter 8 discusses the
many enhancements found in the new full-32-bit MC68020.

M68000 RESOURCES
If. as \.\Ie hope. you are encouraged to explore the M68000 scene in more depth ,
we have listed some sources for hardware and software in Appendix E. Be
warned that no such list can claim to be complete or entirely accurate by the
time you come to read it. Prices and telephone numbers are especially volatile.
As you can see, the M68000 has been implemented in an incredibly wide
variety of microcomputer systems, ranging from the under-$500 home computers, through the sophisticated $ 1,500-$3,000 personal computer bracket
(highlighted by the ubiquitous Apple Macintosh T" ), on through the professional
$5.000 + UN IX'" VJOrkstations (from over 20 different manufacturers at our last
count) - the IBMe 9000 laboratory system , multiuser business systems from
AlphaMicro, Stride, Cromemco - the list grows daily.
From $200 to $200,000, they all use MOVE.z Om,On! When you reach
Chapter 4. you'll know why.

1
Basic Microprocessor
Concepts
Inasmuch as the completed device will be a general-purpose computing
machine if should cOnlain certain main organs fe/aling 10 arithmetic,
memory storage, conlrol, and connection with the human operator.
- A. W. Burkes, H. H. Goldstine, and
J. von Neuma nn , Prelimmary DIscussion

,In

of !he Logical Des,gn 01 Ekelrome

Compt.III"g Inslfumt"nI (1946)

This chapter presents a number of useful basic ideas that you will need to better
understand the M68000 family. Primers, by definition, cannot assume too much
prior knO\.Vledge, so \.\Ie will warn you, up front, that we plan to cover such
fundamentals as bits, bytes, binary arithmetic, and busses which are essential
for later chapters.

MICROPROCESSORS
On first hearing the \oVOrd microprocessor one immediately senses that we are
talking of something small, and it is indeed a physically small computing com-

ponent on a silicon chip (micro is a common prefix in science standing for a

millionth part, as in microsecond).
The MPU (MicroProcessing Unit) is just one element, or resource, in a
computer system. Figures 1 1 and 12 show typical computer systems. The
MPU chip, when ITnmted on a drcuit board with other essential supporting
chips, is often referred to as a microcomputer or an MPS (MicroProcessing

System) or a CPU (Central Processing Unit).

1

68000,68010, and 68020 Primer

Computer

Printer (output)

Mouse (input)

Disk Drive
(inpuUoutput)
Keyboard (input)

Fig. 1-1 Typical Sma ll Computer System

The MPU is often called the brains of the system, the resource with programmable intelligence that coordinates all the other dumb elements connected
to it. MPUs have logical and. arithmetical abilities, and they make dedsions and
exert control in many ways. Yoo will see, hOVJeVer, that all this occurs in a
predetermined way, set up by program s (sequences of precise instructions).
MPUs are no longer the most expensive component in the system , and
several MPUs may be foond in the one system (which is then labeled a multiprocessor system) . Quite often there is one master MPU with several slave
MPUs assigned to particular duties; sometimes each MPU is an independent
source of intelligence that can be called on to process any job.

PROCESSING WHAT!
But what and why are ~ processing? Cuisinarts process food, and sewage
plants process sewage, but microprocessors process data and (with the help of
rna"" attached gadgels and carefully detailed programs)1hey produce inlonnatioo.

Basic Microprocessor Concep15

Printer 1#1

DO
Printer #2

Terminal #1
Disk Drives 1#3 and #4

Disk Drive #2

Mouse

Fig. 12 Typical Multiuser System

If this sounds abstract and intangible, \.Veil , in a sense, it is. The computer
is a very general purpose, blind manipulator of symbols - it is you, the user,
who gives meaning and purpose to its processes.
Throughout the following discussions, \Ale will use the word data as a
singular, collective noun.

Information and Data

Information, in everyday usage, is a strange something that reduces uncertainty.

In the 1940s Claude E. Shannon of Bell Labs refined this vague idea into a
whole nV.' branch of mathematics, known as information theory. !-Ie shQl.lJed

68000, 680 10, and 68020 Primer

off

/ . on
Power
Two State
Switch

Fig. 1-3

lamp

c)
Two State
Indicator

Light Switch as a Bit

that in many situations the amount of infonnation in a message can be measured

and expressed as a number of binary digits or bits. Milk is traded in pints, but
you order infonnation by the bit

BITS IN ACTI ON
The miracle of computing rests ultimately on this concept - one of the simplest
in the whole of mathematics. A bit is the basic unit of infonnation, capable of
resolving a single yes or no uncertainty. A bit can therefore represent just one
of tv..o values, usually given the symbols "0" and " 1 ", but that can be interpreted
in many ways: on and off, black and white, true and false, yes and no, but note
that the bit is incapable of indicating any shades in between , like gray or maybe
or perhaps.
It turns out that many physical devices, such as the familiar household
electric switch, have this same on-or-off property and can therefore be used to
store one bit of infonnation.
Devices like switches which have a limited number of states are called
discrete devices, as opposed to devices like rotary volume controls which can
vary continuously through an infinite number of states.
In Figure 1-3, the slate of the switch is indicated by the slate of the lamp,
on or off.

Basic M icroprocessor Concepfs

The information you could signal from your window using this simple onebit device might be "Yes, I am here" or "No, I'm out of town." Ah-ha, but
which is which? " Lamp-on" could signal your absence, perhaps. The message
of the lamp requires a prearranged code between you arxi the intended receiver
of the message. There are only tvJo possibilities:

Code A

CodeB

Lamp on = at home

Lamp on = away

Lamp off = away

Lamp off = at home

The main point is that the bit as a bearer of information is meaningless

without some prior coding agreement betvJeen sender (encoder) arxi receiver
(decoder).
Shannon defined the bit as the amount of information that \.VClU.]d make
something twice as definite! T\MJ equally likely outcomes share a probability of
112 (a 50/50 chance of each), so one bit will completely resolve this amount of
uncertainty, but no more. For more useful information storage you need to
increase the number of bits, and at the same time devise methods for rapidly
storing, accessi ng, changing, sending, and decoding the information.
Each bit you add to your store doubles the amount of information. For
example, with tvJo lamps in your window, you can devise a code to represent
foor distinct messages:

Lamp 2

Lamp 1

Message

off
off
on
on

off
on
off
on

Leave
Leave
Leave
Leave

no milk today
one pint
tvJo pints
three pints

Once again you must ensure that the decoder (milkperson, in this case) knows
the code, and espedally, which lamp is which. If the lamps are not marked or
distinguishable in some way, you can see that only three possible messages can
be encoded. So, in order to extract the maximum benefit from our 2 bits, they
must be ordered in a prearranged manner. With this proviso, there is a simple
rule relating the number of bits to the number of possible encoded messages:
1 bit
2 bits
3 bits
N bits

can
can
can
can

encode
encode
encode
encode

2
2x2 = 4
2x2x2 = 8
2 x 2 x .. . x 2

(21)
(2' )
(2J)
(2")

messages
messages
messages
messages

68000,6801 0, and 68020 Primer

For this reason, po.vers of 2 play a fundamental role in information theory and
computing.
The case of N = 10 is also important, since 2 10 = 1,024, which is widely
abbreviated to K (as in kilo). So when you read of a 32K memory, this means
32 x 1,024 = 32,768 rather than 32,000.
The messages you encode can be anything you like - instructions, sym
bois, numbers, names, or perhaps even nothing at all (a perfectly valid message
might be " ignore this message"). Some combinations of bits may be specially
earmarked as errors. Often there are more bit patterns available than messages
to be decoded. This redundancy can be exploited to detect and possibly correct
transmission or storage errors.

BINARY ARITHMETIC
There is a natural way of relating these bits to fami liar decimal numbers - we
call it binary arithmetic because it uses pov.!I"S o f 2 with the tv.o symbols 0
and I , rather than powers of 10 with the ten symbols 0 through 9 . Nearly all
computer calculations are performed internally in binary arithmetic, even if the
final results are needed in decimal form. Our tv.o-Iamp code for ordering milk
has already given a hint of how this VJOrks. Given the following code:
Lamp on = 1
Lamp2 = 2

Lamp off = 0
Lampl = I

these \M)Uld be the results:

Lamp 2

Lamp 1

of pints

o
o

I
1

The decoding rule is:

pints = (2 x Lamp 2)

(1 x Lamp I)

1
2
3

Basic Microprocessor Concepts

With three lamps we can extend our order to 7 pints as follows:

Lamp 3

Lamp 2

Lamp 1

of pints

0
0
0
0

0
0

I
I

I
2

I
I
I
I

0
0

I
I

I
I
I

Lamp 3 nOVJ carries the value 4 = (2 x 2) and

pints

3
4
5
6
7
VJe

decode as follOVJs:

14 x lamp 3) + 12 x lamp 2) + II x lamp I )

You can already recognize the similarities betVJeen our usual decimal notation and this binary system. Treating the lamps as column positions, each
column represents a povJer of 2. When you write, say, 2379 in dedmal, you
are using a shorthand for
2 thousands

3 hundreds

7 tens

9 units

2 x llO x lO x 10) plus 3 x (lO x 10) plus 7 x lO plus 9 x I

2379

where each column represents a power of 10. The units column may not look
like a power of 10, but in fact it represents 1oo which equals 1.
In the same way, the binary number 1101 , is evaluated as:
1 eight

1 four

a twos

1 unit

I x 12 x 2 x 2) plus I x 12 x 2) plus Ox 2 plus I x I

13

VJe can therefore establish a straightforward correspondence betVJeen bit

patterns, binary numbers, and dedmal numbers. This is just one of many
encoding schemes and must be agreed upon in advance as in any scheme for
sending information.
To stress the role of the bit let's look again at our 3-lamp signals to the
milkperson. Initially, the number of pints needed is uncertain to the extent that
it lies anywhere in the range 0 through 7 18 possibilities). Lamp I reduces this
uncertainty as follOVJS:
Lamp 1 on = number of pints must be 1, 3 , 5 or 7
Lamp 1 off = number of pints must be 0 , 2, 4 or 6

68ODO, 68010, and 68020 Primer

The uncertainty is nOVJ down to four possibilies, so it has effectively been halved.

Lamp 2 and Lamp 3 each independently halve the uncertainty:

Lamp 2 on
Lamp 2 off
Lamp 3 on
Lamp 3 off

=
=
=
=

number of pints
number of pints
number of pints
number of pints

must be 2, 3, 6 or 7
must be 0, 1, 4 or 5
must be 4, 5, 6 or 7
must be 0, 1, 2 or 3

All three bits (lamps) in parallel completely remove the uncertainty - just
one of the eight possible messages is indicated.
The modem computer uses exactly these principles in sending and decoding messages and data . The switches and lamps are replaced by large numbers
of high-speed two-state electronic devices such as transistors built into silicon
chips.

SUMMARY OF BITS AND MESSAGES

With an ordered group of N bits ycMJ can encode up to 2Ndistinct messages. A
common encoding system relates these to the 2N binary numbers running from
through 2N - 1. Since binary numbers can be easily stored electronically in
the form of on-off switches (or gates) , computers perionn all their basic arithmetical and logical operations in binary.

Special Groups of Bits

Groups of 4, 8, 16, and 32 bits are so commonly encountered that they have
their QI.IIn names:

A nibble = 4 bits, which can store 16 messages

A byte = 8 bits, which can store 256 messages
A VJOrd = 16 bits, which can store 65,536 messages
A longv..ord = 32 bits, which can store 4,294,967,296 messages!

These names and their associated "ranges", will crop up repeatedly because,
for excellent reasons to be explained, the M68000 is designed to operate on
these groups of bits.
Notice in Figure 1-4 how the bits are numbered from right to left, starting

with bit 0, called the LSB (least significant bit). The highest, leftmost bit is called
the MSB (most significant bit); because of a commonly used method of encoding

negative numbers, the MSB is also called the sign bit (more on this later).

Basic Microprocessor Concepts

Bit

=1

bit

Range:::: 0- 1

o
Nibbl e

=4

bits

Range:::: 0-15

Byte = 8 bits

Sign
Byte

Range:::: 0-255

)] ,,0 ,,0
7

upper
nibble

Word
Sign
Byte

= 16

Longword

= 32

bits

Range'"' 0-65 ,535

11i i'l'j II dil l!"'tit?

1 5 upper byte

S;go
Byte

lower
nibble

lower byte

bits

Range:::: 0 . 4,294,967,295

~rl ~wrrnl I ilimTIll1 I6iIi IlrEJ

31

upper word

MSB

(Most significant byte)

lower word

LSB

(least significant byte)

Fig. 1-4 Groups o f Bits: Nibble, Byte, Wo rd, l ongword

10

68000, 68010, and 68020 Primer

BCD -

BINARY CODED DECIMAL

One important use of the 4-bit nibble is to encode the 10 decimal digits 0
through 9 . Three bits will only encode 0 through 7, so four bits is the minimum.
The resulting code, known as BCD (binary coded decimal), has five unassigned
combinations. They, and the binary codes for decimals 0 through eleven, are
shown here:

BCD

Dedmal

0000
0001
0010
0011
0100
0101
0 110
011 1
1000
1001
1010
1011
1100
1101
1110
1111
(000 1)(0000)
(0001)(0001)

0
1

2
3
4
5
6

7
8
9
unused
unused
unused
unused
unused
unused
10
11

This coding scheme is rather ineffident, space-wise. Compare, for example,

the two ways of expressing the decimal 2379:
2379 decimal
2379 decimal

~
~

100101001011 binary 112 bits)

(0010)(0011 )(011 1)(1001) BCD (16 bits)

The main application of BCD is in financial calculations where some of the

accuracy problems you can get with binary-decimal conversion are unacceptable.
ASCII CHARACTER CODE

The byte's claim to fame is that 256 is a useful number for encoding a set of
characters, such as those on a typewriter keyboard. The upper- and 100000-case

Basic Microprocessor Concepts

Table 1-1

Binary

0111
0110
0101
0100
0011
0010
0001
0000
1111
111 0
1101
1100
1011
1010
1001
1000

11

Decimal Inte rpretation of 4-Bit Binary

1's Complement
Mode

2's Complement
Mode

Unsigned

Mode

7
6

7
6

7
6

5
4

5
4

5
4

2
1
0
-0
- 1
- 2

2
1
0
- 1
-2

2
1
0
15
14

-3

13

- 3

-4
-5

12
11
10

- 4
- 5

-6
- 7

-6
-7
-8

9
8

letters plus the usual crop of punctuation symbols and controls (carriage return,
backspace, etc.) take up only 128 combinations (encodable in 7 bits ) but since
!he 8-bit byte off"" 256. we have lois of spares for graphics, There is a standard
called ASCII (American Standard Code for Infoonation Interchange) which
assigns a symbol for each 8-bit pattern. Apart from a few variants for foreign
scripts, ASCII is pretty constant around the world.
HOME ON THE RANGE

The byte can only store numbers in the unsigned range 0 through 255, so for
most mathematical operations we need more than 8 bits. The situation is even
worse because in order to handle negative numbers, we must steal a bit to
indicate the sign (0 for plus and 1 for minus).
Under what is known as 2's complement notation (see Table 1-1) a nibble
can store a number in the range - 8 through + 7 (still a total of 16 distinct
numbers) and a byte can store a number in the range - 128 through + 127
(note that we are still encoding a total of 256 distinct numbml,

12

68000,68010, and 68020 Primer

The bits in a byte are numbered 0 through 7 from right to left (so remember
the first bit on the right is bit 0). In 2's complement form bit 7 (the leftmost) is
designated the signbit.
The 16-bit word offers a range of 0 through 65,535 unsigned (that is,
positive numbers), but if we use the sign-bit trick for negative values we can
store signed (2's complement) numbers from - 32,768 to + 32,767.
Before the arrival of 32-bit micros, the above 16-bit data range was a
restriction needing extra programming if your sums led to larger numbers. Also
since 16 bits were often used to encode addresses in memory (more on this
later) this resulted in a more tricky restriction on memory capacity to 65,536
different addresses (again, there were tricks in hardware and software to overcome this).
You can now guess why there is so much excitement over the arrival of 32bit microprocessors. A 32-bit longword can store unsigned numbers in the
range 0 through 4,294,967,295, and sig ned numbers in the range
- 2,147,483,648 through +2,147,483,647. And when you are not doing big
sums, the longv..ord can store t\.oo smaller 16-bit numbers, or four ASCII
characters, or eight BCDs.

BINARY SUMS
IAbrking with binary numbers has its good and bad aspects. On the bright side,
the rules are fewer than with decimal numbers:

I - I

=0

10 - 1 = 1
The hard part is that binary numbers are not compact; the human eye and
brain suffer from reading and remembering 100101001011 compared with its
decimal eqUivalent, 2379.
Let's add tVJO binary numbers together manually, so you can see the rules
in action:
10111 = decimal 16+0+4+2+ 1 = 23
+ 11101 = decimal 16+8+4+0+1 = 29
110100 = decimal 32+ 16 +0+ 4 +0+0 = 52 (check)
(We proceed

from the right: I + I = 10, so write 0 and carry I , and so on.)

Basic Microprocessor Concepts

13

OCTAL AND HEXADECIMAL

We should mention here t\.vo other number notations you will encounter, both
of which are easily derived from binary notation but which offer more compactness and ease of use.
The octal system uses the base 8, so that only the numbers through 7
are employed, and each column represents a po.ver of 8. Here are a few
examples:

Binary

Octal

I II
1000
100000
11 1111

7
10
40
77

Dedmal

8
32

63

Conversion from binary to octal is very simple. The trick is to partition the
binary expression into groups of 3 starting from the right. Then evaluate each
group of 3 bits into dedmal.
111111 = (111)(111) = (7)(7) = octal 77
100101001011 = (100)(101)(001)(011) = (4)(5)(1)(3)

= octal 4513

The hexadedmal (short name hex) system uses a base of 16, so we need
16 distinct symbols to express numbers in hex. Our usual symbols through
9 are okay for the first ten , then we borrow the letters A = 10, B = ll . C = 12,
D = 13, E = 14, F = 15. Here are some examples:
Binary

Octal

111
1000
1010
1111
100000
11 11 11

7
10
12
17
40
77

Decimal

Hex

10

IS

F
20
3F

32

63

Once you get used to it, hex is probably the most convenient notation for
t\.vo of them
make a byte, and so on. Binary-to-hex conversion can be done "at sight" using
a similar trick to the binary-octal method just descrtbed. Divide the binary
number into fields of 4, from the right:

16/32-bit computer \A.IOrk. Each hex symbol represents a nibble,

111111

(OOII)( l lll)

(3)(F)

hex3F

14

68000, 68010, and 68020 Primer

An even easier method, if you wnture into serious machine-level programming, is to buy an electronic hand calculator with instant binary, octal, decimal,
and hex conversion.
Bases higher than 16 have been bled, but what you gain in compactness,
you lose in legibility. The mathematician and computer pioneer, Alan M. Turing
(1912-1954), was fond of the base 32. This requires, of COU"", 32 distinct
symbols, namely 0 through 9 and the 22 letter.; A through V, for example.
Whence: 1111111111 = 1777 (base 8) = 1023 (base 10) = 3FF(baseI6)
= W (base 32). TUring's notation was even trickier since he was tied to the
arbitrary 32 characters on his fiw-channel teleprinter (an early printer, operated
from five-track paper tape) .

SUMMARY OF NUMBER SYSTEMS

Numbers can be expressed using bases other than the familiar base of 10
(deCimal system). Binary (base 2 ), octal (base 8), and hexadeelmal (base 16)
arise naturally in computer mathematics.
The neat thing about binary numbers is that Simple a nd fast electronic
circuits can be built that automatically perform the basic arithmetical operations
(add, subtract, multiply and divide) - witness, for example, the aforementioned
pocket calculator. The step from on/off switches to arithmetic requires a brief
detour into logical operators and Boolean algebra.

BOOLEAN ALGEBRA
George Boole (1815-64) was the first to develop mathematical rules for logical
operations, now knolJJn as Boolean algebra.
Logic deals with a particular binary situation since it labels propositions
true or false. Boole therefore assigned the numeric symbols 1 for true and 0 for
false , and then studied the rules for combining these using the logical operators
NOT, AND and OR in place of the familiar arithmetical operators.
As in everyday " logic," if the propositions A and B are both true, VJe say
that the single proposition (A AND B) is true. If either or both A and B are false ,
then we say (A AND B) is false. Similarly, if A is true, we say that (NOT A) is
fa lse. We commonly use the symbols
A

AND
= OR

= NOT

Ba sic Microprocessor COflcepfS

15

Replacing true and false with 1 and 0, the rules tum out to be similar to binary
arithmetic with "A = multiply" and "v = add" but there are some subtle
differences:

Logic
false OR false

Boolean

Binary

false

ov 0 =

true OR false
false OR true

1v0

true
true

false AND false

false

true AND true

true

true AND false

false AND true

=
=

false
false

1A 1 = 1
1A0 = 0
oA l = 0

0+ 0

= 1
v i = 1
A 0 = 0

1 + 0
o+ 1

= 0
= 1
= 1
Ox 0 = 0
1 x 1 = 1
1 x0 = 0
x1= 0

So far, so goocl! But the rules diverge with:

Logic
true OR true

true

NOT(true) = false
NOT(false) = true

Boolean

Binary

1A 1 = 1
- 1 = 0

1+ 1

-0

= 10

1's complement of 1 =
1'5 complement of =

COMPOUND LOGICAL OPERATORS

Various compound logical operators can be defined in terms of AND, OR, and
NOT. For instance NOT and AND can be combined to give NAND. The tables
below (known as truth tables, since they never lie) , show the compounds you'll
meet in computer schematics and programming situations:

NAND (Not AND)

AND

A
0
0
1
1

B
0
1
0
1

OR

A B
0 0
0 1
1 0
1 1

AAB
0
0
0
1

~
~
~

A
0
0
1
1

NOR (Not OR)

~
~
~

AvB
0
1
1
1

A
0
0
1
1

B
0
1
0
1

~
~
~

- (A vB)
1
0
0
0

B
0
1
0
1

-(AAB)
1
1
1

~
~
~

EOR (Exr;/usiue OR)

A
0
0
1
1

B
0
1
0

~
~

(A vB) A- (AAB)
0
1

16

68000. 68010, and 68020 Primer

The exclusive OR gives true when either input (but not both) is true. In
normal speech \.Ve do not always distinguish between these h.vo meanings of
OR. So everyday "Jogic" is not always predse enough for "reasoning" with a
computer.

PROGRAMMER'S LOGIC
The precision of Boolean algebra is a vital part of the programmer's life, since
\Ale are often interested in getting the system to test the outcome of a routine
(true or false) and then perform different programs according to the result. An
example familiar to all those who have ever tackled a tax form might be:

If you are male, married, over 40, earning less than $10,000, or fema le,
single, under 50 earning more than $6,000 complete line 3. Otherwise
skip to line 12.
In Boolean terms this requires evaluating an expression like:
(- F x M x A> 40 x SAL<!O,OOO)

(F x - M x A< 50 x SAL> 6000)

where each individual term, called a Boolean variable or expression, is set to 1

for true and for false. The ans\.Ver obtained by mechanically following the
rules will be 1 for true (so complele line 3) or 0 for false (skip to line 12). Note
that if you are male, then F ("being a female") is false = 0, while- F ("not
being a female" ) is true = 1, and so on.

LOGIC GATES
Electronically, it is possible to build devices called gates that combine signals
according to the rules of Boolean algebra. Figure 1-5 illustrates how these are
shown in circuit diagrams. In modem micros, these gates are transistors embedded in the silicon. The MC68000, some say by coincidence, has about 68,000
such gates. (The earlier M6800 had about 6,800 tranSistors, 50 there may be
some logic to Motorola's numbering scheme.) The " 1" and "0" can represent
any t\VQ distinct electrical states, for example "0" may mean a + 5 volt signal
and " 1" may be volts. The NOT function is called an inverter since it inverts
to 1 and 1 to O. Gates are the basic building blocks of computers. They can
be interconnected in complex patterns to periorm a variety of functions, such
as decoding and binary arithmetic. Ie (integrated circuit) chips are available in
tens of thousands of variations offering every conceivable combination of logic
for the circuit designer. And if your volume is high enough, a special purpose
chip may save you wiring together off-the-shelf chips.

Basic Microprocessor Concepl5

Input

Truth Table

Output

NOT
(Invertor)

AND

~
8

A 81 (
In In I n
0 1 0
1 0 0
1

OR

NAND

~:]

>-C

EOR

Fig. 1-5 logic Gates

A 8
0 0
10 1
1 0

Av 8

-(A"B)

1
1
1

A 8 C
0 0 1
1
1 0 0
1 1 I0

A
0
0
1
1

A'B

A 8 C
0 0 0
0 1 1
1 0 1
1 1

NOR

-A

-(A

v B)

8 C

(Av8)

0
1
0
1

"-(A" B)

0
1
1

17

18

68000, 6801 0, and 68020 Primer

INPUT
A
0
0
1
1

OUTPUT

B
0
1
0
1

S = Sum = (A V B) A -(A A B) = A

S
0
1
1
0

C
0
0
0
1

E9 B (EOR)

C=Carry=A A B

lOR

AvB

I AND

B
-(AilS)

!A r )'"!

/:f.NOT

S
AilS)

AND

A' B

Fig. 1-6

Binary Adder

FROM GATES TO SUMS

Let's see hQIJJ Boolean Algebra helps to design circuits which bridge the gap
between logic and arithmetic. In Rgure 1-6 we shQIJJ a table for a simple binary
A + B adder, where A and B can equal 0 or 1. The ou~uts are S = sum and
C = carry. Sand C also take the values 0 and 1, follOVJi ng our rules for binary
addition. We note that S is the EOR (Exclusive OR) of A,B, while C is AAB.
The circuit in Rgure 1-6 is obtained by replacing the Boolean symbols with
their silicon equivalents - 2 AND-gates, 1 OR-gate and 1 invertet What is even
more remarkable is that with Ie technology many thousands of such circuits
can be integrated into a tiny mass-produced chip.

Basic Microprocessor Concepls

19

Flip

'=== R -----"-:L.-/

input at 0

Flop!
o

IJL R -----'-:L.-/
input at 1

Fig. 1-7

Basic Flip-Flop

The half-adder drcuit in Figure 1-6 just adds tvJo bits together, but it is not
difficult to cascade similar circuits in series to give full binary addition of 8 or
16 bits depending on the chip's architecture. A full -adder needs three inputs,
since it must take in the previous "carry" bit - but the principle is as shown
in Figure 1-6.
FLIP-FLOPS
Before VJe: leave the topic o f basic computer drcuitTy, VJe: want to show yoo a
clever combination of gates which indicates ho..v data can be stored electronically. The flip-flop consists of two NOR-gates wired as sho",,," in Figure 1-7.
Momentartly pulsing the 5 (Set) and R (Reset) inputs in different ways causes

20

68000,68010, and 68020 Primer

the tIM> output lines to flip-flop between 011 and 110 states. These states are
remembered long after the input pulses have disappeared, so we have the basis
for storing 1 bit per flip-flop, and the means of reading or writing its value. As
with the binary adder, flip-flops can be wired together in \AJOndroos ways to
provide fast on-chip storage units knCl\.llTl as registers.
SUMMARY OF GATES AND BINARY SUMS
We have seen, in very general terms, that the basic logical operators, AND, OR,
and NOT, and their compounds NAND, NOR, and EOR, all have silicon analogues called gates. These gates can be interconnected to perfonn more complex
functions, including binary addition and register storage.
To coordinate these netlM>rks of gates, we need another ingredient - time.

CLOCKS

The frozen-frame 1's and O's shovm as inputs A, B, 5, and R in Figures 1-6
and 1-7 actually arrive as a stream of high-speed electrical pulses synchronized
by a system clock. This quartz-controlled clock (which may be part of the MPU
chip or a separate chip) sets the pace for a host of MPU activities. Generally
speaking, the faster the clock, the faster the computet A typical MC68000 clock
VJOUld run at 8 MHz (8 million cycles per second) giving a cycle time of 125
nanoseconds (a nanosecond is a billionth of a second - 1/1,000,000,000 sec.
This is the time it takes light to travel approximately 1 foot).

MICROCOMPUTERS COMPONENTS

THE THREE

We can nOVJ take a look at the overall organization of a typical microcomputer

system, so we can identify the main elements prior to discussing each in detail.
We will find that a microcomputer can be viewed as . 'three black boxes on a
bus".
SYSTEM BUS

figure 1-8 shovJs the system bus, a sort of wiring freeway, throogh which the
major components, labeled MPU, memory, and 110 communicate with each
other.

Basic Microprocessor ConcepfS

21
rJl

'<

II>
( I)

til

c:

II>

kayboard CAT

Fig. 1-8

Microcomputer System Bus

M emory

The box marked memory, subdivided into RAM and ROM, represents the main
immediate storage for data and programs. Each piece of memory is assigned a
unique address allowing fast, random access by the MPU. ROM is read only
memory, whereas RAM (Random Al:.cess Memory) can be read hom or written
to.
1/0 -

InpuUOutput

The single black box marked VO (inpuVoutput) covers a multitude of devices

- disk units, user terminals, printers, modems and so on - each with its own
particular interfacing hardware circuits (known as VO controllers) supported by
dedicated software such as terminal drivers. 110 is the area of most direct visibility
and concern to the average user. In the midst of our microelectronic delving \..\Ie
must not lose sight of the average user, keying in data and printing pie charts.
The system bus carries three kinds of signal traffic: data, address and
control. In some computers these three sets of signals are electrically independent (separate wires). We call these multibus systems, since one can identify a
data bus, an address bus, and a control bus. Cheaper, slQl..lJef systems may have

22

68000, 68010, and 68020 Primer

a single bus that is shared among the three, using a technique known as

multiplexing.
Microcomputer Operation

In a read cycle, (Figure 1-9) the MPU seeks data (numbers or instructions) from
memory or 110 by sending appropriate request signals down the control bus. If

the bus is busy doing something else, the MPU may have to stand by for a few
cycles (we call this a wait state).
If and when the bus is free, the MPU places an address on the address
bus. This address is decoded by circuits in the memory or 110 interface and, if
all goes well, the data found at the requested address is moved from memory
or 110 10 the data bus. The control bus then signals to the MPU that the dala is
available on the data bus. Once the data is transferred to the MPU's data buffer,
the control bus signals that the system bus is free. In a moment you'll see how
the MPU handles the incoming data.
The width of the data bus (measured in bits) dictates how much data can

be fetched during each read cycle - so the wider the better. You'll see that the
size of the data bus plays a vital role in detennining the flexibility, performance,
and the cost of an MPU . The cost element stems from the fact that each bit of
the data bus needs a corresponding pin on the MPU chip and associated
pathways within the chip.
When people talk about 8-, 16-, and 32-bit computers without further
qualification, they should be referring to the width of the MPU's data path. But
note that some salespersons have been knOVJn to lie. Remember Gerswhin's
law : " It ain't necessarily so!"
We really need four sizes to honestly characterize an MPU: data width ,

ALU (Arithrnetic/Logic Unit) width, register width, and address width , but life
is so short. Who wants to buy an 8!16132120-bit micro? (That's the MC68008.
by the way.)
The width of the address bus determines the total number of distinct
memory (including 110) addresses that can be accessed and hence affects the
maximum memory size. As with data width, the wider the better, but also the
more expensive. Here we can make use of our earlier messages-per-bit theory.
Most of the 8-bit MPUs have a 16-bit address bus that, as we've seen, allows
a maximum of 64K memory addresses (each of which normally accesses an

8-bit byte), since 2"

65,536

64K.

Although there are many clever ways of fitting more than 64K of memory
on a 16-bit address bus, they all add overhead in time or cost. The M68000

family has address widths in the range of 20 to 32 bits, giving memory addressing
spaces from I Mbyte to 4 Gbytes.
The write cycle (figure 1-10) allOVJS the MPU to send data to memory or

110. The MPU Signals its intentions (request to write) on the control bus, and

Basic Microprocessor ConceplS

23

Ul

'<

en

10
3

til

c:
en

1: Read Request
2: Send Address

Memory
MPU

RAM

Addr~ss

Bus

Ul

'<

-3

en

Data

Bus

CD

til

Control

Bus

c:
en

Step 3: Receive Data

Step 4: Signal OK

Memory
MPU

RAM

Fig. 1-9

Read Cycle

24

68000, 68010, and 68020 Primer

Address

Bus

(J)

'<

II>

Dala

Bus

<D

'"c:
II>

Step 1: Write Request

Memory
MPU
RAM

(J)

'<

II>

a;

'"

c:

II>

Memory

Step 2: Send Address

Step 3: Send Data
Step 4: Signal OK
MPU

RAM

Fig.1-10 Write Cycle

Basic Microprocessor Concepts

25

when the coast is clear, it places the data on the data bus, and the destination
address on the address bus. The MPU can then carry out its next instruction.
Recall that the data being moved around is represented by fast bursts or
pulses (O's and 1's) synchronized by the system clock. When we talk of read
and write cycles, these are defi nite periods of time related to the speed of the
system clock.

SUMMARY OF SYSTEM BUS

The system bus links the main units of the computer, providing an electrical
path between MPU, memory and Va. It carries three types of signals: data,
address and control.
Now that you have an overall picture of hO\.V the MPU interacts with the
system bus, you can look inside the MPU and see hOVJ it v..orks. Although MPUs
have evolved into myriad designs, there is a useful "generic" architecture that
serves to describe them all.

INSIDE THE MPU

The first thing to notice in Figure 1-11 is that the microprocessor has three main
connections to the "outside VJOrld," namely the paths to the data, address, and
control busses. Note that it also has an internal bus (there can be several of
these) connecting various functional units of the MPU. Within the MPU , in fact,
control and data signals move along the internal bus, synchronized by the system
clock - not unlike the picture we drew of the traffic on the system's bus.
Corresponding to the user programs of the computer system, the internal
operation of the MPU is gUided by microprograms stored in special ROM within
the chip. (This is true of the M68000 and many other MPUs; other MPUs
employ hard-wired control logic. )
Let's run through a typical sequence of events.

1. instruction Fetch: The program counter (PC) is a special register that holds
the memory address of the next instruction . Placing this address on the
address bus and calling a read cycle will fetch this instruction over the data
bus and load it into the instruction register (lR ), via the internal bus. Instructions, briefly, are v.ords (or groups of VJOrds) that represent the steps of the
program stored consecutively in memory. Each instruction is encoded to
perform a particular operation, such as ADD or MO\lE, on one or more
specified operands. For an ADD instruction , for instance, the operands \.VOUld
be the two numbers to be added. A MOVE instruction IOOUld speafy the
operand to be moved (the source) and the place it is to be moved to (the

26

68000,68010, and 68020 Primer

DATA

BUS

AlU
;
Decoder
Timing &
I

ADDRESS

Fig. 1 11

BUS

Microprocessor Schematic

destination ). Once the instruction has been fetched, the program counter is
incremented so that it "points" to the next instruction in memory.
2. Instruction Decoding: The instruction VJOrd passes from the IR to the instrllc
tion decoder, which "decides" from the incoming bitpatterns what operation
is needed. Typically, the instruction also contains addressing information for
the operands, that is, which register or memory location holds the data to
be operated on.

3. Data Fetch: Determining where the operands are often involves some arith
metic to calculate the operand addresses from the infonnation included in
the instruction. For some mu]tiv.ord instructions there may have to be another

Basic Microprocessor Concep15

27

instruction fetch , as in step 1 above. It may now take one or more read
cycles to bring in the operands from memory, or to transfer them from
registers. The operands will be routed along the internal bus(ses) to temporary registers.

4. Execute Cycle: The microprocessor is n()',A.I, hopefully, ready to execute the

instruction. The MPU "knows" what to do, where, and to whom. More often
than not execution will involve the ALU (ArithmetidLogic Unit). The anSVJer
will be n:x.tted via the internal bus to a register, or to the data bus buffer en
route to memory. In the latter case, a write cycle will be initiated using the
destination address spedfied in the instruction. The ALU also sets a flag
register (also kn()',A.In as a condition code register) according to certain
conditions arising from the operations (result negative, result zero, overflow
and so on).
Having completed steps 1 through 4 , the MPU is all set to do the same for
the next instruction - since you saw that the PC (Program Counter) has already
been increased, and therefore has the address for this next instruction. Remem ber that instructions are normally stored in successive memory locations.
Among the many deviations possible from the simple sequence listed above,
a common one involves branching. In branching, some program condition
arises that calls for the execution of an instruction out of normal sequence.
Branching is achieved by setting a new address in the Pc.
Other deviations can arise from errors, exceptions, and interrupts from other
jobs. These will be covered in later chapters, since the M68(X)() has some unique
features for handling errors and exceptions.
A rather amazing fact is the sheer speed with which our four basic steps
take place. MPU speed is rated in MIPS (million instructions per second) - of
course, not all instructions take the same time, so MIPS can be misleading. A
single instruction can take from 4 to over 200 basic machine cycles. The
MC68020, to give you an idea, runs at a sustained rate of 2 to 3 MIPS, with

occasional bu"ts of 8 MIPS.

PREFET(H AND PIPELIN ING
If you look at our four steps -

fetch instruction, decode, fetch data, execute -

you can imagine a tremendous amount of bus activity, both on the main system
bus and on the MPU internal bus. In the never-ending fight to squeeze more
performance from a system, the designers obviously attempt to speed up each
aspect of the cycle, especially by reducing the possibility of delay (wait statesl
arising from bus contention or a sla...v memory access time. But when that has
reached practical limits there still remains the possibility of gaining speed by

28

68000, 68010, and 68020 Primer

overlapping operations - achieving what is known as concurrency. It turns

out that several of the steps 1 through 4 can be overlapped - performed
simultaneously. A typical prefetch strategy involves having three instructions
passing through the MPU at anyone time - one being executed, one being
decoded, and one being fetched. In pipelining a greater number of instructions
may be passing through. These steps often require different system resources,
provided the chip has the necessary buffers and pathways. If, as will happen
from time to time, there is a clash or contention, one of the steps will be held
up. In Chapter 8 you will see hOVJ the instruction cache on the MC68020 further
improves performance by holding a set of instructions at the ready in fast onchip registers. In many programming situations the same loop is iterated many
times; the instruction cache can reduce the fetch time considerably.
Let's review in more detail some of the main boxes in Figure 1-11, and
then see hOVJ memory is organized.
ARtTHMETIC/LOGIC UNIT

An area of the MPU designed spedfically for arithmetic and logical operations
is called an arithmeticllogic unit (ALU ). Advanced MPUs like the M68000 have
several independent ALUs. The width of the ALU, 16 bits for the MC68000,
for example, tells you how many bits can be added together in parallel, at one
time. Larger numbers, of course, can be handled by taking extra clock q,ocles.
You saw earlier hov.r gates could be combined to perform binary addition.
It is not too difficult to extend these to perform the other basic arithmetical
operations.
Subtraction is equivalent to adding a complement (easily obtained with
inverters); multiplication is repeated addition (although it is sometimes performed
from preset tables) ; and division is repeated subtraction and testing for zero.
Hardware division, inddentally, is one of the many mainframe features nOVJ
appearing as standard on the 16132-hit micros. The alternative on most of the
8 -bi! micros, dividing by software, is tedious and much slowet: Similarly, the
M68000 offers hardware BCD (Binary Coded Dedmal) arithmetic as well as a
useful repertoire of shifts, rotates, and extended arithmetic. The latter involves
several clever multi-predsion aids for doing sums across several registers for
increased accuracy.
MATH COPROCESSORS AND THE MC68881

For heavy number crunching using floating-point format, Motorola introduced

the MC68881 math coprocessor, which is fu lly compatible with the M68000

Basic Microprocessor Concepts

29

range (indeed the MC68881 is a chip in the same range of complexity as the
MC68000).
Coprocessing differs from multiprocessing in the way that the work load is
shared. A""} sUitably interfaced MPU in the system, on decoding an instruction
calling for floating point, will pass that instruction over to the MC68881 - so
coprocessors actually share the same instruction stream. Multiprocessors nor
mally do their own thing from independent programs, although they can and
do interact by sharing data and passing signals (known sometimes, rather
pleasantly, as semaphores) via memory.
Simply stated, you can look on the ALU as the calculating center of the
chip, capable of seeking help from a math coprocessor.
Inputs to the ALU are numbers from temporary registers (or buffers) via
the internal data bus together with control signals, (instructions indicating the
calculation or logical operation required). Output from the ALU, the results of
the calculation plus various control and routing signals, flQV.I back to other parts
of the MPU via buffers and the internal bus. An important source for ALU data
input, as !Nell as a destination for ALU data output is a spedal area of on -chip
fast memory, organized into fixed length registers. Unlike the temporary registers
and buffers, these are accessible to the programmer.
REGISTERS

Registers play a major role in giving an MPU its personality and programmability,
and they come in all shapes, sizes, and flavors. The basic MC68000 has 17
general-purpose registers, each 32 bits wide. In Chapter 3 IJ..Ie will cover this
aspect in depth , since the instruction set and the way the registers are organized
are intimately related.

MEMORIES ARE MADE OF THIS

The normal fast immediate memory for modem computers is the RAM (Random
Access Memory) chip. RAM Chips come in various sizes and are plugged into
memory boards to give a total capacity per board from 16 Kbytes up to 2
M-bytes. A system may well have more than one memory board within it. The
physical arrangement of memory is usually of no concern to the programmer,
who is interested only in the logical addressing scheme.
You should remember, in passing, that a grov..nng number of peripherals
will have local RAM and/or ROM, outside the main MPU addressing space.
Typical examples are buffers for printers, keyboards. and CRT displays.

30

68000, 680 10, and 68020 Primer

Addresses

o
1

Contents
01 memory

N-~=,----_

65 ,535 -

Fig. 112

l.2:::"':::=--.J

Addressing 64 K-Byte Memory

ADDRESSING MEMORY

As you saw in the read/write cycles, the main characteristic of RAM is that the
MPU can read and write data from and to RAM. To determine which of the
many byte locations it needs to access, each byte (or group of bytes) is given
an address. A 64K-byte memory can be thought of as 65,536 mailboxes,
numbered 0 thru 65,535. Inside each mailbox is a byte (8 bits) holding data
(256 possible characters, remember) .

WHAT ARE WE READING?

If the computer v.Jere to read from byte address 1 (see Figure 112), it VJQUld
fetc h the byte 10110110. What \.VOUld this mean? \AIeIl, almost anything! Out
of context the byte has no spedfic meaning. If the computer \IJeTe expecting a
number it could be either
10110110 = decimal 182 (unsigned)
or

10110110 = decimal-74 (signed 2's complement)

If the byte were part of a 7-bit ASCII string, the leftmost bil coold be a parity
bit with the remaining 7 bits giving the numeric character " 6". Or it might be a
full 8-bit ASCII graphics character or "private" control code.

Basic Microprocessor Concepts

31

If the MPU lJJeI"e reading a program, the byte 1,.V()Uld be interpreted as part
of an instruction. The v..ords and bytes that make up instructions have their Ql..Vn
peculiar coding schemes built into the MPU. You saw that the instruction decoder
has to interpret this code before the MPU can execute il In Chapter 4 , you will
see hovJ the M68000 instruction set is encoded into groups of 16-bit VJOrds.
Recall that each 16-bit v.ord offers up to 65,536 messages, so I.Ve have the basis
for a very rich and varied set of different operations.
Since the bytes we read from memory can mean so many different things,
you may be VJOndering how the MPU distinguishes all these possible interpretations. The answer lies in the program itself. And the reason that program bugs
can produce such bizarre results is because the MPU will blindly interpret each
byte as requested. So if you inadvertently ask the system to execute rather than
print an ASCII character, it is likely to do strange things.

IMPORTANCE OF MEMORY SIZE AND SPEED

Memory size and speed playa vital role in every aspect of computing. At the
simplest user level the amount of memory can dictate both the types of job you
can run and the speed with which they are performed. A RAM or ROM that is
not matched to the speed of the MPU can, as we've seen, induce wait states in
the MPU. Too little memory can often bring the system to a halt with a sneering
"insufficient memory" message on your screen. Some programs need to be
completely resident in RAM before they can run at all. Other programs are
arranged to run with just portions of the code in RAM and are smart enough
to pull in overlays from a disk. Overlays overwrite sections of code in RAM
once they have served their purpose. \krry large programs can theoretically be
made to run in very small memories, but the overhead caused by constant
swapping can create some ennui for the user.

MEMORY MANAGEMENT
Our simple picture of memory Sitting on an address bus deliberately evades
many complex problems concerning the interactions between the MPU (s), system and user programs, and memory access. These are particularly severe when
the system allQl..Vs multitasking, that is, the "simultaneous" running of several
jobs, or different parts of the same job. Clearly, care must be taken to prevent
one task from intruding on the memory allocated to another task.
In particular, the operating system (OS) which is overseeing all user tasks,
is itself running tasks, (including the task of scheduling tasks) and its system
memory space must be secure from accidental or deliberate intrusion. Users

32

68000,68010, and 68020 Primer

may bithely kill each other's jobs, but if the OS goes, \.I.e all go. What makes
the system memory sacrosanct is not only the programs resident there (OS ,
compilers, utilities) , but a lso vital system data, such as tables for handling
interrupts and exceptions, and an area known as the system stack which holds
transie nt information concerning the status of interrupted jobs.
Even a Single-user, single-MPU system nowadays frequently offers many
levels of concurrency. The speed of the modern MPU, compared with the speed
of most VO devices, allows it to service many requests in sequence, so qUickly
that each job is convinced it has the MPU's undivided attention.
There is considerable diversity in the methods used to partition memory
safely and economically, and much debate on the merits of various approaches.
The initial proble m is that of mapping physical to logical memory. By this \Ale
mean relating the physical memory addresses as "seen" by the address decoders, with the logical addresses presented to the MPU by the programmer.
Some MPUs, like the Intel 808818086, have the solution to this problem
designed into the silicon, while others (like the M68000) leave all the options
open to the system designer.

SEGMENTED MEMORY

The Intel approach is called memory segmentation, as opposed to the Motorola

linear memory philosophy. In a segmented memory, the programmer looks at
several exclusive, fixed memory spaces (or segments), typically 64 K-bytes each.
As shown in Figure 1-13, the logical addresses he or she uses are offsets,
modified by the MPU to obtain the physical addresses. The modification is
achieved by adding values (called segment identifiers) held in segmentation
registers, and this can be done in such a wCty that the user's programs and data
are kept apart, safe from other users. The advantages are the security and speed
that arise from the use of short 16-bit addresses. The disadvantage is the
overhead involved in checking and adding the segment identifiers.

LINEAR MEMORY AND THE MMU (MEMORY

MANAGEMENT UNIT)

In the linear approach the programmer looks on memory as one long continuous
addressing space from zero to the maximum possible address, addressed by
means of a single number. With the 20- to 32-bit address widths available on
the M68000, this represents a generous chunk (from 1 M byte to 4 G bytes) to

play with. Within this maximum, jobs can be allocated the optimum memory
size needed. Security must be "supplied" externally, as it were, but the M68000
is designed to fadlitate this. Several spedalized chips, such as the MC68451

Basic M icroprocessor Concepts

logical Addresses
Prog Offset

33

Segmentation Registers

I Prog SegmentlD , I Data Segmen' ID , ~ 1---=-_-'-__

'

,-_D_a'_a_Of
_f_se_,-"
16.bit

16-bit

Segmented Memory

Prog 3 Segment

phys ical
address

max

Data 2 Segment

logical Address

~~~--~
I
20 32 bits

Linear Memory

physlca
address

(anywhere)

max L _ _ _ _ _- '

M68000 Fe
(Function Control)

Addresses

Linear Memory with MMU

fi g. 1-1 3

max L..._ _ _ _J

Segmented and Linear Memories

34

68000,68010, and 68020 Primer

(available hom Motorola) perform something resembling segmentation. These

chips are called Memory Management Units, or MMUs. In Figure 1-13, VJe
indicate how MMUs accomplish their purpose. The FC (Function Control) pins
on the M68000 automatically signal the processor state, namely whether the
M68000 is in supervisor or usermode, and whether the address is data or
program. from these values and the actual logical addresses, the MMU derives
the physical addresses. The MMU can also provide write-protection to selected
areas of memory, and allocate separate address space for DMA (Direct Memory
Access) operations.
MASS MEMORY

One characteristic of RAM plays a big role in computer design - volatility.

With most RAM, you lose your data when you switch off the p<>VJef. So a more
permanent memory is needed, and this is provided by various types of backing
storage or mass memory, in the form of hard and soft disks, tapes, and

cartridges.
Programs are usually marketed on pennanent media such as floppy disks,
but need to be read into RAM before they can be run. During a typical run
there will be many VO transactions - data being output to disk, and data and
programs read in from disk. Overall performance is much influenced by the
amount of RAM available - the more RAM, the fev.Jer disk accesses.
VIRTUAL MEMORY (VM)

It often happens that the available RAM is far less than the addressing range.
In fact, until memory prices fall much 1()I.Vr, it is highly unlikely that you'll see
many MC68020s with a fu ll complement of 4 G-bytes of RAM! A technique
called virtual memory (VM) pioneered by Ferranti Ltd., Manchester, England,
in the 1950s (and reinl.oented by 16M in the 1970s), allows data to be accessed
from disk as though it were in RAM.
Referring to Figure 1-14, suppose you hal.oe a IM-byte addressing space
(20 bits), a 128 K-byte RAM and an 872 K-byte disk. With VM you could use
your fu ll 20-bit address as though all your data were in RAM. On decoding the
address, the VM system VJoldd calculate (by table lookup perhaps) its equivalent
page number. A page is a conl.oenient chunk of memory, say 1 K-byte. If that
page is currently in RAM (case Y, in Figure 1-14), it will be fetched in the normal
wt!ly. If the page is not in RAM (case X) , VJe say that a page fault has occurred,
and Ihis causes Ihe syslem 10 load !he page from disk 10 RAM , swapping out
an unwanted page if necessary.

Basic Microprocessor Concepls

Ad dr ess Sp ac e

35

RAM

update
table
swap out
old page

TABLE

location

Address

Fig. 1-14

page
lault

RAM

Virtual Memo ry

Chapters 7 and 8 will discuss virtual memory in more detail, as implemented

on the MC68010 and MC68020.

RAM DtSK
The opposite to VM is the RAM disk. If your program is written to access files
from a disk, and you have plenty of RAM to spare, it is possible to increase
performance by loading your fi les into RAM. The RAM disk software then fools
the program into treating RAM like a disk. The starting memory address of each
file record can be calculated - provided, naturally, that the disk formatting
rules are known.

36

68000.68010. and 680Z0 Primer

DIRECT MEMORY ACCESS - DMA

There is a widely used technique called Direct Memory Ac.c
(DMA) which
allows direct data transfer betvJeen RAM and disk with little or 0 involvement
by the MPU. If you look back to Figure 1-8, you can see tha since VO and
memory are both tied to the system bus, there is already apical pathway
available for DMA. The actual mechanics are beyond our immed te scope here,
but DMA is achieved by having spedal hardware (intelligent chip called DMACs
- DMA controU",,) that grab addresses from the MPU and th n set up read!
write cydes with no further reference to the MPU (thus freein the MPU for
more useful tasks).
Let's take time out for some general comments and rec ps on the allimportant topic of software.

SOFTWARE -

GENERAL OVERVIEW

Software is needed to goad the inert hardware into action. So

programs (sometimes referred to simply as code), carefully con
instructions written in one of the ma ny programming \angua
Basic, C. assembly language, and many others - gUiding the
by step to perform specific tasks.
We have already seen that programs need to be loaded into
they can run but there are many potential hurdles before we
happy state.

are consists of
tructed lists of
s available hardware step

rnory before
n reach that

COMPATIBILITY
An essential concept throughout the industry is compatibility
the idea of
hardware and software elements throughout the system IJJOrk ng together in
harmony. We will reserve the VJOrd system for an organized atching set of
devices and programs.
Hardware and software exist today in a dazzling profus on of shapes,
flavors, and sizes, and creating a system from diverse com pone ts, even when
you buy from a single manufacturer, is no trivial matter.
Portability in hardware simply means that the thing ha a handle and
weighs less than 100 pounds; software portability is a less tan Ie concept. A
program written to run on many different systems is clearly~re marketable,
although sometimes you lose efficiency by aiming at portability.
I-known packA group of related programs is often called a package.
ages such as IJ..brdStart and Lotus '" 1-2-3 '" offer one specialized application

Basic Microprocessor Concepls

37

(!J..Ord processing and spreadsheets, respectively) . A more recent fashion is the

integrated software package such as Symphony '" which provides both \oVOrd
processing and spreadsheets. Rnandal data from the spreadsheet can be transferred automatically to the WP program in order to produce neatly typed reports.
If you want your computer to run your payroll, you'll need to load a payroll
package that Specifically and in minute detail tells the computer how and when
to cakulate each element of tax deduction, where to find the various tables, and
so on . The hardvJare has no preconceived notions regarding your wages and is
blissfully unaware of the IRS. When we talk about the computer as a general
purpose machine, we mean that it can do anything - as long as we have the
appropriate compatible software.

APPLICATIONS SOFTWARE
The payroll programs mentioned above belong to what we call applications
software. Applications software is aimed at solving particular user problems.

SYSTEMS SOFTWARE AND THE OS

The computer also needs systems sohware to handle a variety of basic support
functions required by every applications program , such as resource allocation,
controlling peripherals, and so on. These support programs, kn()l..VJ1 as utilities,
are often lumped together under the title OS (Operating System), pronounced
" Oh-ess." Without the as, each applications program VJOUld have to knOVJ the
exact hardware configuration and include all these tiresome details. In the early
days of computing, in fact, there UJere no operating systems, and the programmer
just had to code everything. The OS frees the programmer from many housekeeping chores. Furthermore, each OS provides its standard way of communicating with the computer and isolates the programmer from many machinespedfic features.
The successful operating systems such as CP/M, PC-DOS and UNIX are
available on many different computers, so a program written for a UNIX-based
computer, say, stands a fair chance of running, with little or no tweaking, on
any system which supports UNIX. This success is self-reinfOrcing, in the sense
that a widely used as attracts a plenitude of software, while the computer
buyer's chdice of OS is greatly influenced by the availability of packages.
As ~ might guess, rivalry betvJeen supporters of different OSs reaches
heights of religious fervor. MPUs like the M68000 family are opening up new
vistas in cOfJ1puting which will help dampen these passions by offering economic
multi-OS systems, capable of running programs from all sources.

38

68000,68010, and 68020 Primer

SUMMARY - OPERATING SYSTEMS

The operating system is simply a complex set of programs that must reside in
the system to provide a uniform set of vital controls and functions for the user's
applications software.
Once an OS has been ported from system A to system B, programs written
for system A become portable, and will run on system B (fingers crossed).
So hardware needs software, and applications software needs systems
software. Of course, software without the hardware to run it on is also a pitiful
sight. Computing is but a mental construct until the tvJo get together.
FIRMWARE
We should mention briefly that programs, including the OS itself, are often
supplied fixed in ROM (Read Only Memory). Variants exist called PROMs
(Programmable ROMs) and EPROMs (Erasable PROMs) that allO\A.l factory
changes to the ROM program. These programs. falling as it were betvJeen hard
and soft, constitute the firmware. Unlike the software we have been discussing,
firmware arrives fully loaded and ready to go.
Firmware, of course, is written and checked most carefully before being
permanently attached to the system. A good example of firmware is the BASIC
interpreter provided with the IBM PC '''.

COUNTING THE COSTS

Spectacular advances in mass production continue to reduce hardware costs.

It has been observed that if car makers had achieved the same price reductions
as computer makers over the last 30 years, the price of a new Rolls Royce v..ould
nov'! be $100! Unfortunately, software has turned out to be an unexpectedly
tricky occupation, resisting similar efforts at mass production. Programming is
labor-intensive, demands rare creative talents, and commaoos increasingly higher
salaries.
Software costs have become the dominant factor in computer projects large
and small. On our car-cost analogy, the $100 Rolls Royce v..ould, alas, require
a $100,000 a year chauffeur plus gas at $50 per gallon!
The phrase software engineering is often used to describe the efforts being
made to apply production methods such as project management and quality
control in the mainly cerebral field of programming.
Correcting the imbalance between hardware and software costs is the major
challenge faci ng the computer industry today.

Basic Microprocessor Conceprs

39

The M68000 family was designed " by programmers, for programmers"

and represents a serious attempt to address this challenge.
CONCLUSION

Thus concludes our gallop through some of the basic concepts. Many of them
will be amplified and, we trust, clarified in the chapters that follow.

2
The M68000 family

This chapter offers a little historical background for the Motorola M68000 family
of microprocessors, just to place them in the context of today's restless marketplace. We also delineate the various members of the family, and show you what
they look like (see Rgure 2-1), We suggest that you reread this chapter after

Chapters 3 and 4. Some of the M68000 design features discussed here will
become more meaningful after you have seen the instructions in action.

INTRODUCTION
The first 16132-bit MC68000 (see Figure 2-2), introduced by Motorola in 1979,
represented a quantum leap forward in microprocessor povJer and flexibility.

Since then, Motorola has developed, as promised, a family of compatible MPUs

(MicroProcessor Units) and support chips -

ranging in price and performance

from the "economy" MC68008, via the MC68000, MC68010, and MC680 12
up to the latest 32/32-bit MC68020. The MC68000 had already attracted the
title of "supermicro", leaving us short of suitable superlatives to describe the
MC68020. Adding number-crunching povJeI' to the family is the MC68881

FPCP (floating-point coprocessor).

We hope to reveal some of the design features of the Motorola M68000
microprocessor family and to indicate the main areas where radical dedsions
made to create this breakthrough in perfonnance, programmability, and

VJeTe

future family growth.

The microprocessor chip is mankind's most intricate invention with VLS I

(Ikry Large-Scale Integration) densities now approaching theoretical upper

40

The M68000 Family

41

COtIrtesy of MOfCitOlo, Inc.

Fig. 21

The M68000 Family

limits. There are many VLSI technologies offering different densities and pov..oer
requirements. They are referred to by acronyms including the letters MaS (Metal
Oxide Semiconductors). The MC68020, for example, using the 2micron HCMOS
(High-density Complementary Metal Oxide Semiconductor) process, packs
200,000 transistors on 3/8" square of silicon (see Rgure 2-3),
A detailed study of the vast field of chip design and microelectronic circuitry
is, of course, outside the scope of this primer.
Our aim, therefore, is to give you some feel for the high lights of this
remarkable fam ily, stressing those elements which relate to the central theme of
our book, the M68000 instruction set.
We will follow Motorola's official designations by referring to the family as
M68000, reserving the MC prefix for a particular member of the family. So the
MC68000 is a speCific MPU chip in the M68000 family.
Rgure 2-4 gives a schematic overview of how the family members and
support chips might be interconnected. In practice, you IOOUld seldom meet

42

68000,68010, and 68020 Primer

MC68000

II 000 ""ANSISfIl'lS
UI I l'a1 _llS

Courtesy oJ Motorola. Inc.

Fig. 22

The MC68000 Microprocessing Unit

The M68000 Family

43

Courtesy of MorotoIo. Inc.

Fig. 2-3

MC68020

such a comprehensive all-Motorola configuration. In fact, mainly through Motorola's oVJn efforts , a standard bus knOVJTl as the VME bus has received ISO
and IEEE approval; its growing acceptance means that devices from many
manufacturers can interface with the M68()()() - and conversely Motorola's
VME-based support chips can be found on many non-Motorola systems. Figure
2 -5 shOOJS a typical MC68000 single board computer (from Educational Microcomputer Systems, Irvine, California) complete with 20 K-bytes RAM, 16 K-

bytes EPROM and various

va support chips).

44

68000,68010, and 68020 Primer

M68000
MATH

FAMILY

BUS

PROCESSING ARBITRATION

DISK

STORAGE

CONTROLLERS

MC6881
FPCP
MPU

MC68230

MC68451
MMU

DDMA

PIfT

MEMORY
MANAGEMENT

DMAC

MC68901
MFP

DMA

M6800

MPCC

EPCI
GENERAL
PURPOSE

DUART

1/ 0

DUSCC

510
DATA COMM

Fig. 2-4

M68000 Family and Supporting Chips

THE M68000 SUCCESS STORY

Nowadays, it takes a lot more than excellent price-performance hardware to
gain success in the microcomputer marketplace. Computer manufacturers and
independent software suppliers also need baSic software support upon which to

The M68000 Family

45

Courtesy of EMS (fducotionoI Microcompurer Sysr.ems). Irvine, Colijomlo. See A~ /t7 moils.

Fig. 25

MC68000-Based Single Board Computer

build up complete end-user systems and applications software, To this end

Motorola has provided state-of-the-art software development tools, such as the
EXORmacs ''', EXORset''', and EXORdser ''', as \Alell as modular systems components such as the VMEmodules '" and the VERSAmodules'" ,
These are supported by a host of Motorola-developed operating systems,
like the System V/68 UNIX-derived OS, conversion and debugging aids, assemblers, and compilers,
Motorola was also prompt in establishing cross-licensing agreements with
major chip manufacturers in the USA, Japan, and Europe (see Appendix E) ,
You can nOVJ buy the M68000 from several manufacturers. Without such "second-sourcing" vendors can feel vulnerable, and it can prove difficult, if not
impossible, to penetrate the military and industrial markets, both domestic and
overseas.
TIle fruits of these efforts can be seen in the countless M68000 implementations nOVJ available. Appendix E lists many of the manufacturers who have

46

68000, 68010, and 68020 Primer

adopted these chips. They range from the giants of the industry such as IBM,
Apple, Honeywell, NCR, ICl, and Hewlett-Packard, thru the mass-merchandizers like Sinclair and Commodore, to the smaller, spedalized firms such as Alpha
Micro, Charles Rivers, AJcyon and SSE. It is probably no exaggeration to say
that the M68000 is currently the best knov.m if not the most widely used
microprocessor family VJOridwide.

THE DESIGN PROBLEM

VLS I (Ikry Large Scale Integration) chips like the MC68000 have such a lengthy
and expensive design-to-manufacture cycle that, like the proverbial airplane,
they can easily become obsolete before they take off. There are tVJO ways around
this potential disaster - first, you use the finest possible crystal ball and try to
predict how the market will lock two or three years from now. Second, you try
to reduce the gestation period by automating the design and testing process.
As Oscar Wilde once said, predictions are dangerous things, espedally when
they involve the future.
Nevertheless, a whole subindustry of microelectronic market-watching and
trend-plotting does the best it can in a most volatile Situation, not only to assess
the types of products needed but also the many associated imponderables such
as optimum price/performance, market share, demand patterns, and the like.
The recurrent fluctuations of over-stocking and shortages, layoffs, and recruitments in the semiconductor industry underline the fact that planning in this area
is far from being an exact science.

TIMING
A major ingredient in the success of the MC68000 was undoubtedly timing.
Even by the mid-seventies the Motorola crystal ball predicted that the existing
8-bit micros \.VQUld soon run out of steam - their very success, in fact. was
attracting more sophisticated applications. Both commercial and scientific users
VJere demanding faster processing of larger, more complex databases, formerly
the preserve of the mainframe and minicomputer systems. The advances in lowcost mass-memory (hard- and soft-disk units) and RAM (Random Access Mem ory) added to this pressure in many ways. More elaborate operating systems
and languages were needed to exploit the larger data banks, and these in tum
prompted the call for more poo.verful instruction sets and addressing modes.

The M68000 Family

47

A NEW MARKET
The growing personal computer market was calling for more friendly user interfaces. Although the lively grass-roots hobbyist was happy to hack away with
primitive interfaces, the home and office user was asking " What will it do for
me?" and "Why are these things so difficult to use? "
An inescapable fact of life is that insulating the user from the harsh realities
of bits, bytes, and bugs incurs an enormous software overhead. To offset the
inefficiency of user-mendliness yct.I need more sheer processing povJer and larger
memory-addressing space, just as an automobile's automatic gearbox requires
a more ~ I engine if you want to maintain the comparable performance
of a stick shift.
To support the professional systems software engineers in their search for
amicable user interfaces, more pQVJeIful instruction sets with more flexible addressing modes were called for.

THE MACSS PROJECT

This was the situation facing Motorola when it initiated the MACSS (Motorola's
Advanced Computer System on Silicon) project in the mid 1970s. The design
challenge was a fami liar one in the computer industry - how to reconcile tvJo
fundamentally conflicting goals: pushing ahead into a new generation while
preserving compatibility with current software and peripherals.
Invocations to the Roman god Janus, reputedly blessed with hindsight and
foresight, are no longer in favor:. In the hurly-burly of the real world the MACSS
team settled for gritty compromises between technical and marketing considerations, making literally thousands of trade-off decisions, some backed by hard
facts, others based on fallible intuition.
An existing user base represents a substantial hardware and software
investment that cannot lightly be ignored, yet at the same time it can inhibit the
fu ll exploitation of advances in silicon technology, computer architectures, and
the black arts of programming.
Solid state innovations have continued to beda22le us since the transistor
first emerged from Bell Labs in the late 1940s. At any point in time there are
hundreds of promising IC (integrated Circuit) breakthroughs progressing (hopefu lly) through the follOVJing stages: theoretical predictions from the solid-state
physicists; mathematical models and simulations; small-scale R&D tests; pilot
schemes to establish fabrication and quality control methods; and studies to
determine the economic feasibi lity of large-scale production. Crucial to completing this cycle is predicting market demand and product life. No other industry

48

68000,68010, and 68020 Primer

faces the same delicate equations relating start-up costs, production volumes
and yields, and unit cost.
THE LEGACY

The diwrsity of MPU designs launched betvJeen the pioneering Intel 4004 (1969
through 1971) and the MACSS project (1976 through 1979) reveals the variety

of responses possible. The evolving story has been one of "Ieap-frogging"

betvJeen the major contenders: Intel, Motorola, and Zilog.
By 1979 the Intel 8080/8085, the Zilog 280, and the Motorola MC6800

v....oere the dominant microprocessors, all 8-bit and not dissimilar in overall architecture and performance. In taking advantage of higher-density Ie techniques,
such as the HMOS (high density metal oxide) process, all th ree were moving
toward 16-bit designs. Intel and Zilog favored maintaining object code compatibility with their vast existing 8-bit installed base, repeating their earlier design
philosophy that had seen, for example, the Intel sequence of 8008 to 8080 to
80BOA to 8085, each one a faster sibling of the previous model. When the Intel
8088/8086 16-bit micros emerged, they bore obvious signs of this tradition.
BREAK W ITH T H E PAST

The MACSS team made the big decision to break away from the past and to
create, from scratch as it were, the best possible 16-hit design. The sole concession to the 8-bit MC6800 customer base was the provision of timing circuits to
handle the slower synchronous MC6800 peripherals. Although M68000 soft-

ware VJOUld have to be developed from zero, at least there would be a wide
range of 110 devices a nd support chips already in situ.
This break with the past was a gamble in many ways, but it addressed the
reality that the 8-bit micro had evolved in a rather ad hoc fashion, during a
period when the programmer's needs took second place to the hardware designer's requirements. When the first Intel 4-bit 4004 spawned the 8008 in the
early 1970s, the latter inherited many of the features of a calculator or CRT
control chip. This is not a criticism, of course, of those noble pioneers. Janus
himself coold not have predicted the explosion of microprocessor applications
that occurred during the following decade.
During this period, once a particular instruction set had been established,
and a large body of software had developed around it, subsequent improvements
in MPU design had been dominated by program compatibility considerations

- the understandable desire to provide a machine that could be put to u.ork

immediately.

The M68000 Famil y

Table 2-1

49

The M68000 Family of Microprocessors

Model

MC6BOOB

MC6BDOO

MC6BOI0

MC6B012

MC6B020

Technology

HMOS

HMOS

HMOS

HMOS

HCMOS

Pins

64 DIP

64 DIP

64 DIP/68 QP 84 GA

114 SPG

Clock speeds

4- 12. 5Mhz

4-11.5Mhz

4-12 .5Mhz

4- ll.5Mhz

16.67Mhz

Number of
registers

17

17

20

20

23

Instruction
length (16bit
words)

1 to 5

1 to 5

1 to 5

1 to 5

1 to 7

Regi ster width

32

32

32

32

32

ALU width

16

16

16

16

32

Data bus
width

16

16

16

8116/32
dynamic

Address bus
width

20

24

24

31

32

Addressing
range

1Mb

16Mb

16Mb

2Gb

4Gb

The lesson was clear. The new Motorola 16-bit design had to be expandable
so that future enhancements preserved software compatibility without restricting
the hardware. So far, the MACSS team has been proved correct

WHY /6 -BIT?
As we saw in Chapter 1, the numbers used in describing a micro can be
misleading. As shown in Table 2-1, even within a closely knit family the vital
statistics vary widely.
All the parameters listed are cunningly interrelated, and they have their
particular significance for the overall price/performance of the chip. But, asked
to single one out, the programmer v.ould probably opt for the length of the
instruction mrd. T his dictates the richness and poo.ver of the instruction set -

50

68000, 68010, and 68020 Primer

/11

2 Registers

0= Register A
1 = Register B

2' = 32 op-codes

4 Addressing Modes
00 = Immediate
01 = Direct
10 = Indexed
11 = Extended
Fig. 2-6

8-Bit Instructions

and these have the most farreaching consequences from the programmer's
viewpoint
The data bus width , for example, determines the number of read/write
cycles needed to access data. But if you c.ycle fast enoogh, who cares if the data
bus is 1 or l()(x) bits wide? 'Nell, Engineering cares, and so does Sales (" How
can we market a lbit machine?" ), but the programmer will be happy provided
the registers are reasonably wide and plentiful.
The address bus width , as we've seen, determines the maximum physical
addressing space, and \.Ve certainly want to end the tyranny of 16bit addressing
and 64K bytes. Vctrioos memory management schemes can solve this problem.
The importance of the instruction word size is clear if \.Ve look at a typical
S-bit op code, as shown in Figure 2-6. Altha.Jgh , at first glance, it provides 256
distinct codes, once you assign bits for address mode encoding (telling the op
code which register or memory location to act on) , you are soon d()IJJn to 32
distinct operation codes. The contention here is among the number and type of
registers, the number of addressing modes, and the number of op codes. Eight
bits is just far too restrictive.
Motorola's jump to a 16-bit instruction \.\lOrd changes the picture dramatically, but naturally calls for more complex ciocuitry.

CHIP REAL ESTATE

Designers talk aboot chip real estate, and this is exactly hOVJ feature decisions

must be made. For a given te technology (NMOS, HMOS and

50

on l, offering

The M6BOOO Family

51

a given component density, and a given chip surface area, you establish an
upper limit to the number of logic gates. This, in tum sets a limit to the feature
sizes and functions you can build on the plot, and to those functions that will
have to be performed by separate support chips.

NU MBER OF PINS
The selected functions obviously have to communicate to the outside VK>rld, so
careful thought had to be given to the physical deSign, or packaging of the chip.
J.ust as the 8-bit designs cast a shadov.l over progress, the number of pins on
existing microchips was another hurdle. The standard 4O-pin arrangement had
the merit of low cost in manufacture and testing - and there were lots of 40pin sockets out there pining for a chip - but you could only feed in and out a
limited number of bus lines for data, addressing, and control. Often designers
were forced to multiplex or share signal paths, which is basically self-defeating.

The MACSS approach for the MC68000 was a 64-pin DIP (Duallnline Package) that allOOJed more freedom in choosing bus widths, and avoided multiplexing data and address paths. The pinouts are shown in Figure 2-7.
Coming back to instruction size, sixteen silicon paths have to be established
between buffers and instruction decoders. T he 65,536 different instructions that
can be encoded in 16 bilS have to be allocated - no trivial task compared with
the 8-bit situation where the op codes and register encoding almost write
themselves.

REG ISTER AllOCATION - TYPE AND NUMBER

You nov.r have enough instruction space to implement a symmetrical set of
orders, that is, to have op codes that IJJOrk uniformly with a large number of
general-purpose registers. With 8 bits you can only increase the number of
registers by having them dedicated or special purpose. For example, if ADD
IJJOrks only with register A, there is no need to encode register A in the ADD
instruction. We will see that symmetrical registers are programmer-friendly, in

keeping with M68000 philosophy.

A key decision was made to implement 32-bit registers throughout, even
in devices like the program counter and stack pointer where 24 bilS v.ould have
served the immediate purpose.
Motorola made a reasonable compromise in the number of registers and
register types. By electing 10 have 16 basic programmable registers. 8 for general

52

68000,6801 0, and 68020 Primer

PIN ASSIGNMENT
D4
D3
D2
D1
DO
AS

U5S
i:Ds
RiW
DTACK
8G
8GACK
8R
VCC
Cl K
GND
HALT
RESET

VMA

E
VPA
8ERR
IPl2
IPL1
IPlO
FC2
FC1
FCO
A1
A2
A3
A4

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

Fig.2-7

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

D5
D6
D7
D8
D9
D10
D11
D12
D12
D14
D15
GND
A23
A22
A21
VCC
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
AS

MC68000 Pinouts

data operations and 8 for general addressing operations, 3 bits for register
encoding IJJTe needed in some instructions (where the type was implied by the

op code), and 4 bits for the more general instructions which could VJOrk with
any register. When you consider that the MC6800 had only 2 general registers
plus 1 index register, you can appreciate the good news.

The M68000 Family

53

DATA TYPES
The 160mt instruction word also aUows bits to be assigned to selecting the size

of the operand. Although the registers are 32-bn and the data bus is 16 bns
wide (on the MC68O(X)), Motorola wanted to offer the programmer a simple ,
unifonn way of hand~ng data in units of 8-bit bytes, 16-bit words and 32-bit
long words . T wo bits were assigned for this in most instructions which allow all

three basic data types. At the assembly language level , it needs on ly a

data-size code (8, W, or L) to select the operand data type .

~ngle

ADDRESSING MODES
Likewise, the number and power of the addressing modes could be increased
from just 4 on the MC6800 to 14 or more on the M68000. The importance of
this will emerge in Chapters 4 through 8.
The M68000 also has additional on-chip ALUs and spedaJ instructions to
speed up the addressing mode calculations.

IMPLEMENTATION
The final design decision, having listed all the goodies - number and size of
registers, size of addressing space, instruction op codes, and addressing modes
- is how to implement this in silicon. There are tu..o main choices in arranging
the complex paths and logical steps needed to put the chip on the road.

RANDOM LOGIC
The traditional method, called random logic design required that you mapped
everything in perfect detail , then devised particular netu..orks of discrete logical
elements to achieve your grand design. This leads to a compact economical
chip with no "wasted" real estate. J-iovJever, as VLSI microchips increased in
complexity, it became more and more difficult to implement. Random logic is
simply too inflexible. The alternative, which in fact was invented by Maurice

Wilkes in the early EDSAC days (Cambridge, 1949-57), is called microcoding.

In those pre-micro days the name was not as confusi ng as it is now.

MICROCODING
Motorola adopted microcoding for the bulk of the M68000 implementation. In
microcoding, you really have something like an MPU within the MPU. Each

54

68000, 68010, and 68020 Primer

instruction is broken dovm into subinstructions or microinstructions, just as an

external (or macro) program can be reduced to procedures and subroutines.
For example, if you write dov.m all the internal MPU steps involved in
moving data betvJeen registers, then list all the steps involved in adding two
registers together, you will find that they have many microroutines in common.
These make up the microprogram which is stored in onchip microROM (Read
Only Memory).
For each instruction a microsequencer routes the data and control signals
according to this microprogram. The advantage is enormous flexibility in design,
testing, and fine-tuning, albeit at the expense of silicon real estate. Microcode
can be simulated and tested off-line before embarking on costly chip fabrication.
CONCLUSION

BeIOVJ the microcode level, the M68000 employs nanocode - and so on, ad
infinitum. This threatens to take us into levels beyond this chapter's modest
aims - so having whetted your programmer's appetite with some of the design
dedsions behind the M68000, let's proceed to the final product. In Chapter 3
we describe the features accessible by the programmer.

3
M68000 Programmer's
Models
Thy gift, thy tables are within my brain,
Full charactered with lasting memory . ..
-

Shakespeare, Sonne! eXII

In Chapter 1 we covered some of the basic concepts common to all microcomputers, and in Chapter 21J.1e looked at some of the design dedsions and tradeoffs

fadng Motorola as they moved on from the 8-bit 6800 to create a new range
of 16-bit and 32-bit microprocessors, the M68000 family. You saw that Motorola's prime aim was programmer mendliness - so let's look at the M68000
family from the programmer's point of view.
First, though, we must identify more predsely how programming languages
are classified, the different roles they play and h()I.IJ they call for different levels
of processor knov.r-how from the programmer.

LEVELS OF PROGRAMMING
The term programming covers a wide range of activities requiring many different

skills and perspectives. As you saw in Chapter 1 all programs sooner or later
are reduced to a stream of instructions summoned from the processor's memory
(RAM or ROM) and translated into specific actions, such as the accessing and
manipulation of data from other spedfied areas of memory.

55

56

68000, 68010, and 68020 Primer

Programmers, and the programs they write, come in all shapes and sizes.

They can be programming to earn their daily bread or to save the Free IMlrld
or just for the sheer fun of it. The al11C\.lnt of detail they need to knOVJ about
the inner workings of the processor, such as hOUJ it accesses programs and data
from memory, varies enormously depending on the levels of the programming
languages they use. Figure 3-1 illustrates some of the major categories of
software, to give you an idea of what we mean by programming leuel.

HtG H-LEVEL LANGUAGES

With high-level languages such as BASIC, FORTRAN, or Pascal, the programmer wrttes source code which the machine cannot directly run without some
intermediate transformations. The programmer is essentially isolated from both
the processor and the detailed organization of its supporting memory systems.
The high level programmer can concentrate on solving his or her applications problems in the chosen programming language, leaving a compiler or
interpreter to translate the source code into the m achine la nguage instructions
which the chip itself "understands." These machine language instructions are
highly inscrutable sequences of D's and 1's, whereas a high -level source program
uses readable " English-type" sentences that offer a more natural and general
WCly of expressing your problem.
The output from a compiler is a compiled, "ready-to-run" machine language version of the source program, knov.m as the object, executable. or run
program or module, to indicate that the processor can directly execute or run
the instructions without further translation . As yc>u can see in Figure 3-1, the
object code modules created by the compiler are usually stored on disks or
other mass storage devices, from which they can be loaded into memory when
needed. Interpreters work slightly differently in that the run version is usually
executed immediately as each line of the program source code is translated.
This technical difference is not relevant to our present discussion , so we will use
the IJJOrd compiler to include interpreters as \.Vell.
MtD-LEV EL LA N G U AG ES

A mid-level programming language like FORTH or C still needs compiling, but

it offers the programmer more control over the processor than, say, BASIC or
Pascal.

M68000 Programmer's Mode ls

57

MEMORY

MPU

HIGH

rl-:'-:'c'-.-n-YO-U-I-.'-m-.-:-h-av-.-'--:do-z-.-n-7-"---'

Set all levels to 0

Increase stock by 12
Bill's subroutine comes here

10 STOCK", STOCK + 12
20 GOSUS BILL

main ()
(
Int 5=0
S
S +12

Natural Languages
Design Languages
Informal Programs

HighLevel Languages
BASIC, ADA, APl, Algol ...

Sealevel Languages
CPL,C ...

.. . .

ADD.W '12,5
J SR

Assemblers

Bill

1010011011011101
0111010110110110
1000100011110001

Machine Code

. .. .

....

r-

L-

'D~7'

Microcode
Nanocode

LOW

Fig. 3-1

Programming Language Level

58

68000,68010, and 68020 Prime,.

LOW LEVEL LANGUAGES

An assembly la nguage program offers precise control over the way the pro
cessor will carry out your instructions. At this level 1Ne are really writing the
processor's built-in machine instructions in a simple, oneforone symbolic,
mnemonic version using easily remembered VvOrds such as ADD, MOVE, and
SUB. (Appendix C has an alphabetical reference list of these - hoo! lhey all
work is the subject of our next three chapters). For rlOVJ, all you need to kn()I..V
is that they provide a legible version of the processor's machine code. Instead
of having to write OOl010110011()(X)() or some such binary mix for each
instruction, assemblers allow you to program with more meaningful and readable
symbols. But note that, unlike the higher-level languages, each line of assembly
corresponds to one machine language instruction. When you write a line in
BASIC, for instance, the compiler may well generate fifty or a hundred or even
more machine language instructions. With assembly level programs, instead of
having a fairly complex compiler between yoo and the chip, you use a simpler,
faster assembler to translate the mnemonic symbols into machine code. Assem
biers, then, are rather like simple compilers - they convert from one programming level to the one bel()I..V. They are simpler than compilers because the jump
dov.m in level is much smaller.
At the assembly language level you clearly need to kn()I..V a good deal about
how the processor finds and handles each instruction. But the rewards are great
As we'll soon see, assembly language programs are extremely compact, effident,
and superfast - and not that difficult!
MICROCODE AND NANOCODE LEVEL

Even below the machine-language level there are microcode instructions permanently built into the chip which translate the machine-level code, and belOVJ
that, the M68000 has nanocode instructions to translate the microcode! We
pointed out in Chapter 2 that these esoteric levels are outside the normal
programmer's scope, but insofar as they provide tremendous fleXibility during
the chip design and testing stages, we, the end users, directly benefit. Each
language level has its advantages and disadvantages for the programmer.
COMPARISONS OF LANGUAGE LEVELS

One of the reasons for the success of high and midlevellanguages is that the
same program can be written and run on different configurations of the same

M68000 Programmer 's Models

59

processor, or even on an entirely different processor. All you need in the latter
case is a version of the compiler appropriate to the particular target chip. For
example, a program written in Microso~ MBASIC no can be run on Apple,
Radio Shack no, IBM and hundreds of other systems based on many different
microprocessor chips with endless variations in memory size and structure. Of
course, this happy state of affairs is the result of Microsoft's efforts to pTOlJide
different versions of the MBASIC compiler and interpreter for a wide range of
machines.
Software that can run with little or na change on different systems is said
to be portable, and in view of constantly escalating programming costs this is
a highly desirable property. !-hv.>ever, as someone once neatly put it, there are
na free lunches; there is a price to pay for portability. Similarly, there is a price
to pay for the higher programming productivity that highlevel languages pro
vide. That price is paid in reduced speed and efficiency, and in increased size
of the programs themselves.

Speed, Size and Efficiency

As you move dovm the hierarchy of language levels, tQlJlards assemblers and
machine language, your programs become less portable and more chipspedfic.
On the other hand, the lower levels allow you more direct control of the chip's
resources, and you can take advantage of particular features of the chip in ways
nat available to the highlevel language programrnet In a nutshell, the 10VJer
levels are harder to program in, and are less portable, but they are more compact
and run much faster:. On typical test programs, known as benchmarks, an

assembly language version of a BASIC program might run 10,000 times faster
and take only 1 percent of the system's memory. Many factors, of course, affect
overall computer performance, and it is pointless to speed up just one stage in
the computing sequence unless the other elements in the system can keep pace.
Compilers themselves are, in fact, programs, and the programmers who
write them for specific processors have to know in great detail how the processor
functions at the machinelanguage level. Their constant aim is optimization, to
reduce the Ql.JeThead involved in translating from high to lOIN level, and to
produce the most efficienttorun code. For this reason many compilers are
written in assembly language. Another common method is to write compilers
in C language, translate them down to assembly language format, and then
massage them at that level to obtain the best possible executable version. The
same techniques are applied in many other software development areas, espe
dally for operating systems, utilities, and the whole field of what we call systems
software. Such programs, which are used to support all users and are often
permanently stored in ROM , must clearly be as compact and effident as possible.

60

68000,68010, and 68020 Primer

A sound general rule is that frequently used programs repay the effort
needed to write them at the ICMIeSt convenient level, and this usually means the
assembly language level. Today most high-level languages offer some way for
the programmer to switch or chain to commonly needed rootines written in
assembly language. You might call this the classical " best of both v.orIds"
situation. For this reason, most programmers today are well-advised to seek
fluency in several high-level languages aoo at least one assembly language. Uke
driving a car, it soon becomes easy to switch from a Ford to a GM - the
controls are in different places, but the underlying prindples are the same.
Continuing with this analogy, assembly language is like slipping behind the
wheel. of a Ferrari! There are lots of new techniques to master before you gain
the maximum perfonnance potential, but gradually they all fall into place and
whoosh! - you are driving in style.

PROGRAM LEVEL SECU RITY

It is worth mentioning briefly (because it may help to clarify some aspects of

language level) that software publishers tend to guard their source code with
great intensity against piracy and illegal access. In most cases the public can
buy and use only the run version of a program, and even this, of course, is
protected against unauthorized use and copying in a variety of ways, ranging
from severe written warnings to sophisticated encrypted chips! There are several
well-known packages where the run version is available for $500, but the source
code would cost $5 million. The key to this is that the source code more readily
reveals the strategy of the program and allows the unscrupulous to exploit the
efforts of the programmer.
Source code can be printed, read, modified, and recompiled (or reassembled) , then resold with some degree of impunity, whereas the run version is
useful only for running. Now Homo sapiens, being the cunning spedes it is, will
always seek ways around such situations. Some people patiently and manually
trace throogh all the binary O's and 1's of a run module to uncover Its hidden
secrets; others misuse special programs called decompilers and disassemblers
to automate this conversion from run to source code. We stress the word
" misuse" because decompilers and disassemblers are quite legitimate tools in
the right hands. Even bright programmers occasionally lose their O\.Vn source
code (traditionally, one blames the computer) and decompiling your O\.Vn stuff
is no crime. The big snag is that the full majestic structure of the source code is
seldom recoverable by decompiling, and dedphering a disassembled program
(remember you are still very close to machine language) is a hard Wi!II to make
a dishonest living.

M68000 Programmer's Models

61

LANGUAGE LEVElS SUMMARY

Our language level discussion can be summed up in the following way:
Higher level = Easier to program and update,
more portable, larger, slo.ver
Lower level = Harder to program and update,
less portable, smaller, faster
In order to exploit the speed and povJer of machine language, you must
learn more about the processor's instructions and how the processor finds them
in memory. Then you can look at the many essential devices (called registers)
built into the chip which give the programmer direct control over the processor's
operation.

M68000 INSTRUCTION SET INTRODUCTION

BRlfF

You have seen that the microprocessor, when it is running or executing a

program, fetches from memory, then obeys, a sequence of machine language
instructions represented by strings of binary O's and 1'5. These instructions pack
a great deal of infonnation that the processor must decode in its instruction
decoder before it knows where to get its data, what to do with it, and where to
put the results. After all that, it needs to know where to get the next instruction.
As in sending and receiving Morse Code, for example, certain conventions
must be observed at both ends for sensible communication to occur. An obvious
convention is needed for the processor to know how many O's and 1 's must be
looked at before it starts decoding. In the M68000 these rules are simple:
Instructions are groups of 1&obit words.
A simple instruction may need just one \.\.Qrd.
More complex instructions may require additional extension \.\.Qrds, up
to a maximum of seven in total.
The first \.\,.Ord in the instruction tells the processor whether to look for
extension \.\.Qrds or not.

So the processor fetches and decodes an instruction from memory 16 bits

at a time, until it "knows" what to do. Depending on the particular instruction,

62

68000,68010, and 68020 Primer

Table 3-1

M68000 Fami ly: Bus Sizes

Regisler

Data Bus

Model

Widlh

Width

MC66000
MC66006
MC66010
MC66012
MC66020

32
32
32
32
32

16
6
16
16
6116/32

Address Bus
Width

ALU

24

16
16
16
16
32

20 or 22

24
30
32

Width

the processor will carry out certain tasks. If the instruction says " MOVE data
from one place in memory to another," for example, it will also contain information on what is to be moved and to where.
To understand how these instructions and the data they refer to are located

you must take a closer look at the way the M68000 memory is
organized. You are not concerned here with the nuts and bolts of memory

in memory,

boards or memory chips or whether it is RAM or ROM . What you need is a

conceptual model of memory as seen by the programmer. The M 68000 memory
is a model in simplidty - just a huge set of numbered boxes, each holding
8-bit bytes. The number on the box is called the byte address.

MEMORY MODEL
M68000 memory, from the programmer's standpoint, is a simple succession of
byte addresses ranging from 0 , 1, 2 , 3 up to the maximum address allOVJed. At
each byte address you will find 8 bits of data sitting in memory waiting for
action. This straight sequence of consecutive addresses forms what we call a
linear address space, to contrast it with othel; more complex addressing schemes
in which memory is segmented, such as the Intel 8086/8088 approach (see

Chapler 1.)
The maximum legal address is set by the width of the address bus which
in tum depends on which chip in the M68000 fami ly you are using. Members
of the M68000 family differ in the number of physical address lines wired out

to the address bus (see Table 3-1).

Determining your maximum legal address is a simple exercise in binary

arithmetic. Each bit you add to an address bus line doubles the number of

M68000 Prog rammer's Models

Byte
Address
( Hex)

Word
Address
(Hex)

,o

Bvte 0

2
3
4
5
6
7
8
9
A
B

/
Bvte 0
2
4
6

Bvte ,

0
2
4
6

C
E

D
F

High Address
Low Byte
low Address
H;gh Byte J

N'N

Bvte N

Nd

N+'
N+2
N+3
N+4
N+5

N+2

.A

!lyle
Fig. 3-2a

3
7

'5

""'"
7

Bvte N
N+2
N+4
N+6

N
N+2
N+4
N+6

f\ 1r

FFFF ... FF

63

Bvte N+'
N+3
N+5
N+7

~~
FFFD
FFFF

FFFC
FFFE

.. . FF FC
... FF FE
15

8 7

Y'Lord

M68000 Memory Model (Part One)

memory bytes you can legally address. A one-line address bus coold access
only two addresses, namely address 0 and address 1. A tv..Q-line address bus
\\W)d double this to foor possible byte addresses, namely 0, 1, 2, and 3.
The full 32-bit address bus of the MC68020 allows a linear memory space

of 232 = 4 gigabytes = 4,294,967,296 bytes. So, byte addresses on the

64

68000,68010, and 68020 Primer

longwo rd
Address
(He x)

l
,. /,
Word 0
Byte 0
Byte 1
W rd4
Byte 4
ByteS
Weird 8
WordC
Word 10

0
4
B
C
10

Word 2
Byte 2
Byte 3
WOldS
Byte S : Byte 7 [;'
[;'
Word A
Word E
Word 12
1/

High Address 1
Low Word J

"'\

Low Address

1
High Word J

31

! I.

[;'

/"

Byte N : Byte N+ 1i Byte N+2 : Byte N+3

Word N+4
Word N+6
i
Word N+8
Word N+A
[I

N
N+4
N+B

!..fVV\~~
.f\J\f\;.f\./\J\Y'fV';.f\./\J\

... FFFB
.. . FFFC

FFF8
FFFC

31

FFF9
I FFFD

:,

24 23

:
FFFA
FFFE

16 15

r
[;'

FFFB [I
FFFF
8 7

Max Legal
- Addre
ss

Longword
Fig. 3-2b

MC68020 can run

M68000 Memory Model (Part Two)

from

0 to 4 ,294,967 ,295. This upper limit is"-Qrth remembering. It will crop up many times as the maximum unsigned number you can
store in a 32-bit device. You m~ find it easier to remember in binary:

11111111111111111111111111111111 (count them)

M68000 Programmer's Models

65

or in hexadedmal :
$FFFFFFFF (note that the " $" means hex, not money)

THE IMPORTANCE OF EXTRA-LARGE

ADDRESSING SPACES
Memory prices have been falling dramatically over the years, but it may be some
time before 4 gigabytes of physical FLAM become an affordable feature for the
average user! f-bwever, VM (Virtual Memory) techniques, originally developed
on the Ferranti ATLAS in the late 1950s, are now available on the latest
supermicros. VM allows you to access mass storage data using memory addresses beyond the range of the actual RAM installed, so you don't need lots
of RAM to justify a large addressing space. Systems programmers are constantly
thinking up new ways of making one thing look like another, an art known as
emulation. The RAM-disk, for example, allOVJS you to access RAM as though
it \.VeTe a disk, while VM lets you access disks as though they were RAM! The
ultimate in emulation is the virtual machine, a technique that allOVJS one
microprocessor to look and behave like another (even like one that you haven't
yet built). As we'll see in Chapters 7 and 8, the MC68010 and the MC68020
have many spedal features that encourage the use of virtual machine techniques.
The MC68000 has 24 of the 32 address bits wired oot, giving it an address
space of 2" = 16 megabytes = 16,777,216 = $1000000 bytes.
The " budget-scaled" MC68008 has only 20 of the 32 internal address bits
connected for external use, providing an address space of "only" 2 20 = 1
megabyte = 1,046,576 = $1()()()()() bytes. How quickly times change I It seems
like only yesterday VJ were SIM>OI'1ing over microprocessors that supported 64K
bytes l

THIS SPACE RESERVED -

FOR SYSTEM USE ONLY

Having established our wide open linear address space, let us immediately grab
addresses 0 through 1024 for essential M68000 business known as system
memory and system data. These hold important tables for interrupts, reboots,
etc. and should not be altered by the average user. Some of these sacrosanct
areas have to be in ROM so that they are preserved when you povJer down the
system , but they still take up addressing space just like any other memory
allocation.
There will almost certainly be other areas of memory assigned permanently
to other vital systems functions, and therefore not available for user-only programs or data. As most systems and user programs grow more "friendly", they

66

68000,68010, and 68020 Primer

increase in complexity and size. l-lence the large M68000 address space is a
real blessing. There are, for example, many microprocessors boasting 128 K
bytes of memory, but by the time the essential systems programs are loaded ,
the user may be left with SOK or so.

ACCESSING MEMORY
You still have lots of logical address space remaining and I.Ve assume you have
some boards of RAM to physically relate to some or all of your available
addresses. I-b.v do you get data and instructions from physical memory? You
need to look at the M68000 data bus, the electrical two-way path between
memory and processor.

DATA BUS
Table 3 -1 reminds us of another important and relevant fact about each M68000
family member - the data bus width. This dictates h()I.V much data can be
transferred during each memory read or write cycle. A nalTOVJ data bus will
require more read or write cycles to transfer a given amount of data.
Note first that the data bus lines are completely independent of the other
bus lines. Many MPUs economize on silicon and pinouts by multiplexing or
time-sharing data and address lines, and maybe other lines too. A dedicated
data bus means that on each memory read or write cycle, all the bits on the
data bus can be transferred in parallel withwt waiting for other line activity to
finish.
Nov.> since different members of our happy M68000 family have different
data bus widths (ranging from 8 to 32), you may VJOnder haul the same memory
acceSSing instructions can apply to all of them. l-lere is how. Each instruction,
regardless of data bus width, includes a data size letter code, L, W, or B. The
MPU interprets this, and will transfer a 32-bit longword ILl. a 16-bit word IW),
or a n 8-bit byte IB) to or from memory. Each 68000 takes the appropriate
action for you. The actual number of read/write cycles is transparent to the
programmer - a longword operation will take 4 cycles (4 x 8-bit fetches) on
the MC68008, 2 cy<:les on the MC68000, and just 1 cy<:le on the MC68020.
Clearly the MC68020 is faster, but the point I.Ve are making (yet again) is the
high degree of insiruction-""'" compatibility between the member.; of the M68000

family.
The basic MC68000 reads 16 bits at a time which is quite neat since I.Ve
already kno..v that instructions are encoded into 16-bit v.ords or multiples

M68000 Programmer 's Models

67

thereof. But if you just want a byte from memory this will still take 1 cycle, the
same as reading 2 bytes.
Because of the M68000's data size instructions we can look at its memory
as though it \.VeI'e divided into either bytes at byte addresses, or \OOrds at VJOrd
addresses, or longv.ords at 10ngvJOrd addresses. Figures 3 -221 and 3-2h show
how we do this.
Here are the rules:

1. Byte addresses can be even or odd. Byte addresses increase by 1 as you

go up.
2. IJJord addresses are even. \Abrd addresses increase by 2 as you go up.
3. Longword addresses are also even. Longv.ord addresses increase by 4 as
you go up.
4. When you access a VJOrd at address N (where N is any even number) , it will
contain the byte of address N in its upper byte and the byte of address (N
+ 1) in its lower byte. Read this rule again. It says that when you look at a
VJOrd in memory, its most Significant byte is at the 10VJer byte address and its
least significant byte is at the higher boyle address. Nov" embroider the
follOVJing on a sampler and hang it over yt:llIr bed:

low addresslhigh byte, high address/low byte

5. When you access a longv..ord at address N (where N is any even number) ,
it will contain the lNOrd of address N in its upper u.ord and the VJOrd of
address N + 2 in its lower lNOrd. As in rule 4 , we have an inversion to watch
out for. Of the tv.o VJOrds found in any 10ngvJOrd the most significant VJOrd is
at the loo.ver VJOrd address and the least significant word is at the higher IJJOrd
address. So reate the following mantra:

low address/high word, high address/low word

6 . If you try to access memory by longword or VJOrd using an odd-numbered
address, you will get a bus error message. (The MC68020 is more forgiving,
but this is still a wise rule to follow.)
If the M68000 is the first microprocessor you have ever studied this closely,

you may not be pUZ2led by Motorola's boylelVJOrdllongv..ord addressing com.oentions. Others will immediately notice that Rules 4 and 5 are exactly opposite to
most other chips. It's like driving on the wrong side of the road in Europe - it's
not a deep ethical question of right or wrong, but you do have to knOVJ the
rules. When we come to registers in the next sections, you will see that the
M68000 addressing rules are consistent and sensible.

68

68000,68010, and 68020 Primer

Let's sum up what VJe have learned so far on M68000 memory addressing
and organization.

MEMORY MODEL SUMMARY

A large linear addressing space. No restrictions on program size (up to

maximum space).

MC68008 can address 1 Mbyte. MC68000/68010/68012 address 16

Mbytes. MC68020 can address 4 Gbytes.

Byte (S-bit), word (16-bit) , or longword (32-bit) addressing is controlled

by data size code in instruction.

\A.brd and 10ngvJOrd addresses are even.

Program instructions are stored as IJJOrds. Data can be stored as bytes,
words, or longv..urds.

\A.brd at address N has its most Significant byte at address N and its
least significant byte at address N + 1.

Longword at address N has its most significant word at address N and

its least significant word at address N + 2.

LongvJOrd at address N contains the 4 bytes at addresses N, N

N + 2, and N + 3.

+ 1,

REGISTER MO DEL
Now that you have a general picture of hOVJ the M68000 addresses external
RAM and ROM, you can venture into the chip itself and look at the internal
devices, called registers, which allOVJ the programmer to directly or indirectly
control every facet of the M68000's operation.
The programming " beef" of the M68000 is its powerful yet simple instruc
tion set. Each of the 60 or so basic instructions in the set, such as ADD or
MOVE, performs a speCific program step by manipulating or interacting with
the contents of onchip registers and off.chip memory, so our programmer's
model must include the registers and the memory addressing modes available
to the programmer before you can make sense of the instruction set.
To some extent you face a "double-egg-and-chicken" situation since the
registers, the addressing modes, and the instructions are all closely intertwined
and mutually dependent Some of the M68000 register features can appear
rather arbitrary until you reach a related instruction in Chapters 4 through 6 that
suddenly reveals the full beauty and symmetry of the M68000. We urge you to

M68000 Programmer's Models

hang in there while

VJe

&9

build up a picture of what registers are, and the many

roles they play.

WHAT IS A REG ISTER!

As a first approximation, you can look at a register as a small piece of very fast
RAM built into the chip - fast because the data held in a register can be
accessed and updated directly by the processor without any time-consuming
memory-fetch cycles. Registers even have numerical addresses like RAM, but
these are for internal reference within the machine language instruction; the
assembly language programmer always uses symboliC addresses such as 01 ,
PC, or A6. The big difference between RAM and registers is that registers have
various built-in functions and are connected directly to control units on the chip
in order to provide these functions. From the programmer's stance, registers are
bits of "smart" ultrafast RAM.

REGISTER TY PES AND FUNCTIONS

As you saw in Chapter 2, a major chip-design question is hOVJ many on-chip
registers to supply, and hov.r many different functions they should each provide.
The follCMling essential register functions are always needed in some form or
other:

Passive work areas for holding intermediate results

The simplest, but

nonetheless important function of registers is to hold intermediate results during
a program. The key fact here is that the data held in on-chip registers can be
accessed and processed very quickly using short economical instructions. And
the more registers you have, and the wider they are, the more data (both numbers
and addresses) you can hold at the ready, without wasting time switching data
to and from external memory.
J---b..vever fast your RAM is, machine cycles are used in calculating addresses, then accessing, retrieving, and storing the data in memory. To attain
the highest possible throughput we always try to keep the engine stoked with
fuel-data from the registers. A simple analogy exists with desk adding machines
_ if you have only one register, you often have to write down and reenter
intermediate subtotals, whereas judicious rolling of subtotals with a multiple
register machine avoids this chore.

Arithmetic and logical operations

Registers, traditionally known as accumulators, are linked to the ALU (ArithmeticILogic Unit) to receive the results

70

68000, 680 10, and 68020 Primer

of an ALU operation. The early microprocessors usually offered only one such
accumulating register, forcing the programmer to shuffle data about before and
after performing an arithmetical operation.
With general purpose data registers, as provided on the M68O(X), arithmetic can be performed directly without this coding overhead.

Addressing operations Address registers supply the processor with memory

addresses for fetching and saving data. Before an instruction can access or save
data in memory it must obviously determine the target memory address; in the
most common case this address is obtained from an address register, but there
are other more complex modes where the address is calculated from t\.vo or
more registers.
Different microchips use widely different memory addreSSing schemes, and
this is reflected in the diversity of spedal purpose registers used for the funda mental task of providing the effective address for the data needed by an
instruction. With the Intel 8086/8088, for example, as IAI explained in Chapter
1, spedai registers exist for the sole purpose of providing base, segment, and
index values from which the effective address is formed. We' ll see that the
M68000's non segmented addressing structure simplifies the situation considerably; there is just one type of general-purpose address register (although you
get seven of them) and any register (including the data registers) can be used
as an index register.
Program sequencing The PC (Program Counter) is a spedai addressing
register dedicated to keeping track of the memory address of the current instruction, so that the processor knOVJS where to go next during a program run.
Stack pointers Theoretically, a stack pointer is simply an address register used
to access a dedicated area of memory known as a stack. Stacks, as you'll see
in Chapter 5, play an important role as places for saving clata while the MPU
breaks off to do something else. Most MPUs have one or more registers dedicated
to the job of keeping track of stack addresses.
Processor status Registers known variously as the SR (Status Register) , the
PSW (Processor State Word), or the CCR (Condition Code Register) are needed
to report on various important states or conditions that can arise after each
program step.
Typically the processor will flag events, such as whether the result of a sum
is zero or negative, by setting l 's or O's in certain bit positions of the SR.
Instructions allow the programmer to test these bits in the SR, and alter the
course of the program accordingly.

M68000 Programm er 's Models

71

Other bits in the SR indicate interrupt priority levels. These are used to
control the types of jobs which will

be allowed to temporartly suspend the

currently active program. Such suspensions are naturally called interrupts. When
an interrupt is requested by, say, an VO unit, the MPU must decide the relative
urgency of what it is doing, compared with what the 110 unit wants to do. Such
dedsions are made on the basis of numeric priority levels stored in the SR
After this quick review of register types and functions, we are ready to
examine the M68000 basic register model.

M68000 BASIC REGISTER MODEL

Agure 3 -3 shooJs the basic register model that applies to all members of the
M68000 range. As "'" I11(M! up-market from the MC68008 thlOOgh the MC68000
to the MC68010 and MC68020, you'll find enhancements to this model, but

there is nothing to unlearn. For the programmer, the M68000 models are upward
compatible - which is probably the most friendly thing you can ever find in a
range of microprocessors.
Although the Ie technology, pinouts, shapes and sizes, speeds, and memory addressing ranges of the chips in the family may be different, the M68000
fami ly is object code upward compatible. Programs written for a vintage 1979
MC68000 will run without change on the latest 1985 MC68020.
V.Je'1l quickly run through the five types of register in our basic model, and

then explain each type in detail.

L 32-bit data registers: There are eight of these, named DO-D7.
2. 32-bit address registers: There are seven of these, named AO-A6.
3. 32-bit stack pointers: There are two of these, the USP (User Stack Phinter)

and the SSP (Supervisor Stack Pointer). Since only one of these registers
can be active at any point in time, they are both referred to as A7 - but
remember that there are two distinct stack pointers maintaining tv..o distinct
stacks (naturally called the user stack and the supervisor stack) , and they
retain their QIJJI1 pointer values in spite of sharing the same register designation.
4. 32-bit program counter: There is just one program cou nter, called the Pc. It
is rather like an address register, but it specializes in keeping track of the
address of the instruction being obeyed. The number of active bits in the
PC will depend on the
MC68020.

model, that is, 24 for the MC68000, 32 for the

72

68000,68010, and 68020 Primer

DO
Dl
D2
D3
D4

Data
registers
32-bit

D5

DS
D7

31

16 15

Address
registers
32-bit

31

A7 Stack pointer
32-bit

Program counter
32- blt

Status register
IS-bit

Fig. 3-3

Basic Register Model

M68000 Programmer's Models

73

5. 16-bit status register: There is just one, called the SR The lower byte (bits
0-7) is called the CCR (condition code register); the upper byte (bits 8- 15)
is called the system byte. The CCR has 5 flags which are set to 1 or cleared
to 0 to signal various conditions arising from each operation:
C
V

Carry flag

Overflow flag

Z ~ Zero flag

N = Negative flag
X = Extend flag
The system byte has a flag or flags to indicate which of two states the
processor is in (either the privileged supervisor state or the unprivileged
user state); it is this flag that determines which of the two stack pointers, SSP
or USp, is active. The system byte also contains a 3-bit interrupt mask (jO-i2)
to signal the interrupt priority level (0-7), and a flag (T) to indicate that the
processor is in trace mode (a mode allOVJing the MPU to single-step through
the program).
DATA AND ADDRESS REGISTERS

The data and address registers are the work horses of the M68000, and most
instructions involve them in one way or another: As the names imply, the data
registers, 00-D7, are used for general data manipulation, while the address
registers, AO-A7. hold the addresses needed to access or update items in
memory.
Typically. an instruction would use an address register to fetch a number
from memory and place it in a data register; you then do your sums by referendng
the data register, and finally, use the address register to direct the answer back
to memory.
The different functions of data and address registers are reflected in the
way they are wired, and in the rules governing which instructions you can use.
The only arithmetic you ever want to do on addresses is adding and
subtracting in order to index or point to a given location - it is very seldom
necessary to multiply or divide addresses. Also, addresses are always 16- or
32-bit numbers, so it makes no sense to design address registers to handle bit
or byte operations.
The instruction set reflects this by having instructions that v.ork only with
data registers or only with address registers, or that perhaps work slightly differently with each. These apparent exceptions soon become quite natural and
sensible throughout the M68000.

74

68000, 68010, and 68020 Primer

The data registers are designed to handle all the usual arithmetic and logical

operations, and since they are 32 bits wide, they can hold addresses and act as
index registers too.
REGISTER SYMMETRY

All the data registers behave the same, and all the address registers behave the
same, so compared with many other microprocessors, there are fewer personality
quirks to remember.
If you compare the M68000 with its closest rivals, you'll see that Motorola
offers a very clean, symmetrical set of registers and a uniform 32-bits for data
and addresses. An instruction set that has this kind of uniformity is said to be
orthogonal, and although it may increase the complexity of the MPU, it makes
programming much easier.
Let's look at the data registers in greater detail. We will look at the basic
subdivisions of the 32 bits and hOVl they are handled by the MPU.
DATA REGISTERS

The eight 32-bit data registers, 00-D7. all look like the sample shovJO in Figure
3-4. The bits are numbered from 0 on the right, the LSB (least significant bit)
position, up to 31 , the MSB (most significant bit). You need to remember that
VJe start numbering with bit number 0 on the right up to bit number 31 at the
extreme left You'll get most peculiar results if you ever get this wrong. Bit
number 1 is the second bit from the right.
The 32 bits can be used in almost any combination (you could access just
bits 5, 19, and 28, say, if you felt so inclined); hOVJeVer, the instruction set is
spedally geared for fast manipulation of the three most common subdivisions,
namely:
The 32-bit 10ngv..Qrd - one per data register
The 16-bit \.IJOrd - tvx> per data register
The 8-bit byte - four per data register
Less frequently, VJe may be involved in the further subdivision of eight 4bit nibbles but VJe' 1I defer this aspect until UJe meet BCD (Binary Coded Decimal)
operations in Chapter 6.
Figure 3-4 shows the names applied to these subdivisions. We talk about
the upper and 10\.Vef \.IJOrds in a longv.ord, and the upper and lo.ver bytes in a
""",d.

M6BDDD Programmer 's Models

S~,"

75

Longword = 32 bits

11
)1 I i 111161111 'nn 11'11116111111 O~B

MSB

31

24 23

16 15

8 7

(Most significant bit)

Sign

Upper Word

B;,

(least significant bit)

Sign

= 16 bIts

B;,

crliliti ITi Ii ili'~

31
MSB

16

=8

= 16 bits

Ymni!ifUl'lili~
o

15

MSB

l SB

Lower Byte

Lower Word

bits

l SB

Upper Byte

=8

bits

n!lOll 0
15
!ASB

Upper Byte

= 8 bits

Lower Byte
Sign

dj jO'fjO
31

MSB

8
l SB

=8

bits

Byto~' rl'n'iY~

24

7
MSB

l SB

Fig. 3-4

Data Register

0
lSB

76

68000,68010, and 68020 Primer

Source

01

4 E F 1 5 A 8 F
o

6 15

Before
Dest ination
~~::::

/
0000 1011

0010 0011 1100 0111 0011 1100

/
02

0 B 2 3 C 7 3 C l/
Before Longword MOVE from 0 1 to 0 2

01

4 E F
Alter

~W:.:~

/41

E /F/1

15 IAI 8

02

Afte r Longword MOVE from 01 to 02

Fig. 3-5

Longword Operation: MOVE.L

In the section on memory you met the idea of byte, I,.I)()rd, and \ongvx>rd
addressing. Not surprisingly, you have the same choices when you do operations
with a data register.

REGISTER SIZECODES
Most instructions operate in three modes, namely iongvx>rd, I,.I)()rd, and byte

mode, indicated by the letters L, W, or B in the instruction. These dictate which

part of the register is affected: the whole longword, the lower word, or the lower

by1e.

M68000 Programmer's Models

77

Source

01

Before
Destination

02
Before Word MOVE from 01 to 02

01
After

02
After Word MOVE from 01 to 02
Fig.3-6

Word Operation: MOVE.W

Let's see how this works, using the MCNE instruction to move data from
one data register to another. We always describe moves as follows: from the
source data register to the destination data register.
The fonnat of the MOVE instruction is:

MOVE . <s ize-code> <source>,<destination>

Our examples will use:
MOVE. L 01 , 02

MOVE. W Dl , D2
MOVE . B 01 , 02

78

68000,680/0, and 68020 Primer

16 15

31

o
Before

Desti nation

r-"""'!"".-,..._

02

Before Byte MOVE from 01 10 02

Alter

...
o

02

B
After Byte MOVE from 01 10 02
Fig. 3-7

Byte Operation: MOVE.B

Let's assume that before the moves, 01 contains the decimal number
1,324,440,20 = $4EF!5A8F ($=hex) and D2 contains 186,894, 140 =
$OB23C73C.
In Figure 3-5 the instruction MOVE.L 01,D2 moves the longvx:>rd in D1
to 02. Not unexpectedly. D2 ends up with $4EF15A8F. All 32 bits have been
transferred. The source register is unchanged.
In Figure 3-6 we have changed the sizecode to MOVE.W. This time only
the 100000r word of D2 is affected; it picks up the 10UJer v..oord of D1. The upper
word of D2 is unchanged.
Finally, in Figure 3-7, we look at a move from D1 to D2 in byte mode.
Only the lower byte (bits 0 - 7) of 01 is transferred to the lower byte of D2.
The three upper bytes of D2 are unchanged.

M68000 Programmer's Models

79

Being able to operate on parts of a register without altering its other parts
proves to be useful in many programming situations. On some computers, the
byte move shown in Figure 3-7 might require three or more steps, possibly using
a third register as you shuffle the data arrund.

REGISTER ARITHMETIC
Since data registers are mainly used for doing sums, you need to look at the
arithmetic of 32-bit registers. You will see that, as with MOVEs, you can perfonn
8, 16, or 32-bit calculations. A1so, just like MOVEs, byte and 'M>rd sums do not
disturb the upper parts of the register. The choice of data size will determine the
numeric range of the numbers you can handle.

DATA SIZE-CO DE AND NUMERIC RANGE

As \oI.Ie explained in Chapter 1, each bit the designer can add to a register doubles
its range and , therefore, its numerical accuraq,l. So, wider registers mean more
accuraq,l - hence the exdtement when 8-bit registers replaced 4-bitters, and
when 16-bit registers replaced the 8-bitters. The endless search for accuracy is
reflected in the SO-bit registers available on the Motorola MC68881 and Similar
number-crunching coprocessors. As you will see, there are many programming
hicks available for combining registers to get what we call multi-predsion results,
but the ideal is to have the hardvJare do this for you.
As we saw in Chapter I, the unsigned range of a 32-bit register is 0 through
+ 4 ,294,967,295 while the 2's complement mode allows signed numbers in

!he range 01-2, 147,483,648!hrough +2, 147,483,647.

SEEKING A SIGN
In the 2's complement notation (see Table I -I in Chapter 1), \oI.Ie find that the
above negative numbers have a 1 in bit position 31 (the leftmost bit), while the
positive numbers, including zero itseH, have a 0 in bit position 31. This bit is
therefore called the sign-bit.
Similarly, with 16- and 8-bit operations on 2's complement numbers, the
sign-bit in positions 15 and 7, respectively, indicates the sign of the number in
a 'M>rd or a byte.
The important rule for signed numbers is:
Sign-bit = 0 for positive numbers (including zero)
Sign-bit = 1 for negative numbers

68000, 680 /0, and 68020 Primer

80

Reg i s t er

3'
101

J.ongword

~~iiiiiiiiiiiiiiii~u

,.)' 1

,.

'5

Sign bit

0 10 +2,'47,483,647 posilive
-2,' 47,483,64810 _, negative

o to +32 ,767 pos itive

W 0 rd

~iiiiiiiiiiiiiiiiii~
...

32,768 to 1 negative

/)110'1-'-1-----,7
: -..." 0
~
IL--'"

Sign bit

Byte

Sign bil---"'"

...

..

0 to +127 positive
128 to 1 negative

Si gned numbers

)~:'(" ~J-LSB

0 10 4,294,967,295

MSB
01065,535
010255
Unsigned numbers
Fig. 3-8

Range of Signed a nd Unsigned Numbers

For unsigned numbers, of course, this bit represents a normal binary value
(2 31 , 2 15, or 27). Unsigned numbers have no signbit; they use all the available
bits to give us the maximum positive rcmge. In Figure 3 -8 we shov.l the ra nges
available for each data-size, L, W, and B.
Now, if you peep into any data register you will see a Tov.I of 32 bits - O's
and 1's in profusion . The M68O(X) attaches no intrinsic meaning to these bits;
they cwld be signed or unsigned numbers or nonnumertcal characters. What
ever legal operation you program on this register will be obeyed without question.
If you use an instruction such as ADD, to add 1, say, to the register, then the
MPU will treal the bits in the register as numbers. Bul does the MPU know

M68000 Programmer's Models

81

whether the register represents a signed or unsigned number? The answer is

no' ADD happens to be an operation that works equally well on signed and
unsigned numbers, provided that the answer stays within the ranges VJe have
listed in Agure 38.
Since the ranges are different for signed and unsigned numbers, the M68(X)()
gives us two distinct warning signals via the CCR (condition code register) flags.
The V (overflow) flag = 1 warns if the signed range is exceeded. The C (carry)
flag = 1 warns if the unsigned range is exceeded. You'll see shortly how this is
done. The important thing to note here is that the MPU does not know or care
whether you, the programmer, are using signed or unsigned numbers. The V
and C flags simply report a condition arising from your instructions. It is entirely
up to the programmer to heed or ignore these warnings.
If you are using signed numbers, the C flag warning is irrelevant, but the
V flag warning is cruea!. If you are using unsigned numbers, the V flag warning
is irrelevant, but the C flag warning is cruea!. (An exception to this can arise
during unsigned division. We will cover this in Chapter 5.)
Both the V and C flag warnings are based on the ranges appropriate to
the datasize of your instruction. Adding in the byte mode, for example, \A.OJld
flag unsigned numbers exceeding 255, or signed numbers outside the range-

128 to + 127.
Let's probe this situation. Arst, a closer look at the carry flag.

CARRY
Unsigned registers are rather like automobile odometers; after a certain mileage

they flip back to 0, you lose the vitalI (meaning 100,000 miles) and you are
suddenly the proud owner of a low mileage car (or register) . With a 32bit
register you can get this result by adding 1 to 4,294,967,295. The correct
ansv.rer to this sum is:

4,294,967,296

2"

10000000000000000000000000000000

Alas, this needs 33 bilS, so our register, doing the best it can, reports only
the loo..ver 32 a 's. The register gives a a result, which is on the low side. by

4,294,967,2961
Unlike the automobile's odometer, happily, the most significant I at the left
is not lost. Rather, it is carried to a bit position in the CCR - yes, the C for
carry flag.
You can test this bit. If it is 0, you know there was no carry; if it is 1, you
can take action to correct your result. In our example we \A.OJld need to make
sure that 2 32 rather than a is returned as the anSVJef. (We shall see in Chapter
6 that there are spedal extended arithmetic instructions for achieving this).

82

68000, 68010, and 68020 Primer

In many ways the carry bit acts as an extension to your data register when
doing unsigned sums, giving you, effectively, 33-bit arithmetic.
I-Ic>.vever, there is only one CCR, and therefore the one carry bit serves all
eight data registers. If you fail to check for carry immediately after the crudal
addition there is a danger that the next operation could change the carry bit,
resulting in another 4,294,967,296 mistake. The mysterious X (extend) flag is
provided to help you handle this situation. The X flag is normally set the same
as the C flag, but many instructions that dear the C flag leave the X flag
undisturbed. For the moment, you can consider the X flag as a sort of C flag
memory. Upon detecting a carry, you may have to move stuff around prior to
correcting the situation. If the C flag gets lost, you still have the X flag available.
If you are VJOrking with v.Qrd instructions, you'll get a carry when the 10VJeT
v.ord flips past its maximum unsigned limit of 65,535; likewise byte instructions
set the carry flag when the 10VJer byte exceeds 255. This, again, is all very
uniform and programmer-friendly. The data-size code does a lot for you.
The carry flag also indicates another kind of danger in unsigned arithmetic.
If you subtract tv.-o unsigned numbers and the anSVJeT is negative (for example
1 - 2 = -1), the result cannot be held correctly in an unsigned register. In this
case the carry bit indicates that a borrow has occurred at the top end of the
difference operation. So the programmer can test the carry flag after subtractions
and take evasive action.
The standard unsigned multiplication on the M68()()() does not require
tests on the carry flag. In this case, multiplying 1\00 16-bit unsigned values gives
you a perfect 32-bit result and always dears the carry flag. You cannot exceed
the limit.
CARRY AND EXTEND - SUMMARY

Summing up, there is a C (carry) flag or bit in the CCR byte of the status
register which warns us that our unsigned sums have gone over the 32-, 16-,
or 8-bit unsigned limit. Both the C and X (extend) flags are set to 1 whenever
a carry or boTTO\.lJ occurs. The X flag is preserved for later use, even if the C
flag is cleared. The programmer can test the carry flag and take corrective
measures.
OVERFLOW

The V (overflow) nag or bit warns you of errors in signed arithmetic. Let's look
at a simple example of signed arithmetic to help us understand overfiOVJ. We'll

M68000 Programmer's Models

83

use just 4 bits, but the prindple extends readily to 8 , 16, and 32. If \.Ve add 1
and -1 , like this:

Binary

Dedmaf

=
=
=

- 1
+1
SUM

1111 12'5 complement)

0001
10000

'We have a good-looking answer in bits 0-3, so we ignore the carry in bit 4. This
explains our rule that the C flag is irrelevant in signed arithmetic. In 2 's complement addition you simply discard the carry.
Now try adding 6 + 7:
+6
+7
SUM

+ 13

0110
0111
1101 '>??

= - 3 12'5 complement)

Here \.Ve get the wrong answer, and yet there was no carry. Why is the 2 's
complement sum wrong? The reason is that + 13 is outside the signed range of
4 bits 1-8 through + 7).
Similarly, when \.Ve add tvJo 32-bit signed integers the carry flag does not
warn us if the limits have been exceeded. To guard against results violating the
signed range of -2, 147,483,648 through +2, 147,483,647. the M68000 has
to be a lot more devious. It has to watch the sign-bits of the tvJo integers as \.Veil
as the carries from bit 30 to bit 31. The details of this are not important, provided
you understand the end result: if the V flag is set to 1 by your signed arithmetic,
then the answer is wrong - you have exceeded the legal limits for 2's complement mode.
Our diversion into register ranges, sign-bits, carry, and overflow has set the
scene not only for the CCR, but also for our next type of register - the address
register

ADDRESS REGISTERS
The seven 32-bit address registers, referred to as AO-A6. can each physically
store the same range of data as a data register. So what's the difference? The
difference lies in the permissible subdivisions of the 32 bits.

Byte mode is never allowed in address register operations.

84

68000,68010, and 68020 Primer

Address regist"" are designed to handle either 32-bit long addresses or

16-bit short addresses, so you are restricted to longv.ord and VJOrd modes when
you operate on AO through A6 (and A7 too).
Ahhough M68000 addressing ~ based on 32 bits, the short 16-bit fonnat,
which allows you to address the top and bottom 32K bytes of physical memory,
~ used whenever feasible to save bus cycles. The M68000 has a neat feature for
handling short addresses, called sign-bit extension. Let's see how tt works.
The lon9'M'l'd mode on address registers VJOrks exactly the same as for
data registers; all 32 bits are involved just as IJ..Ie saw in Figure 3-4. Look at the
first move in Figure 3-9. We have 01 set up as before, but this time YJe are
moving in Lon9'M'l'd mode to AD rather than 02. The end result is the same
- AO picks up all 32 bits from Dl.
Vvbrd-moves to address registers VJOrk differently, and the difference is
important. In the second part of Figure 3.9 VJe shOVJ the effect of a v.Qrd move
from 0 1 to AD. This time the whole of the destination register (AD) is affected,
not just the 10VJer v.Qrd. The 10VJer VJOrd of AD picks up the 10VJer 'M)rd of 01
in the usual way, but the upper v.Qrd of AD undergoes sign-bit extension.
The sign bit involved is the sign bit (bit 15) of the 10VJer IJ.,Qfd of 01 , which
happens to be D. This Dis replicated in bits 16 through 31 of AD. The net result
is that AD, taken as a whole, reflects the value and sign of the source v.Qrd,
namely the 10VJer v.ord of 01 . The iOVJeT v.ord of 01 happened to be positive
(sign bit 0), so AO was forced to be positive by setting bit 31 to O.
Figure 3- lD shows what happens if 0 1's 10VJer \UOTd is negative, with the
sign bit (bit 15) equal to L A longword move from 01 to AD v.orks as usual,
but the \AJOrd move sets l 's into the upper \UOTd of AD. The sign-bit extension
has preserved the sign of the register AD.
ADDRESS REGISTERS SUMMARY

The address registers are for fu ll 32-bit addresses, but the short 16-bit form
saves space and time in many situations. The sign-bit extensions preserve
arithmetical integrity without bothering the programmer.
You nOVJ come to the all important SR (status register) which you saw has
tv.Q bytes of important data, one for the system and one for the user.

SYSTEM BYTE
The upper byte of the SR is the system byte. The name of this byte derives
from the fact that it is a protected area holding global data about the entire

M68000 Programmer's Models

"

01

..... ............ .........

4 E F 1 5 A 8
31

16 15

85

aefo[l:

Longword

Oest

MOVE
01 ..... AO

AO

01

AIm
Longword

MOVE

AD

01 ..... AO

4EF15A8

A!!.tl
Word

MOVE
01"" AO

Fig. 3-9 Sign Bit Extension in Word Address:

Sign Bit = 0

86

68000, 680/0, and 68020 Primer

, S~ln-t)n

of lower word

Source

01

3
31

A 1

8
16 15

Ii! !i::fg rt
longword
MOVE
01" AO

Dest

AO

9 F E

M68000 Programmer's Models

System Byte

87

User Byte
Condition Code Reg ister

c
o
Interrupt Mask
(levels 07)

Mod e

Fig. 3-11

MC68020 onl y
M _ Master/Interrupt State
10,. Trace enable

Status Register: System/User Byte

system. It can be read by all users, but can only be written (changed) when the
machine is in a privileged supervisor state.
As shown in Figure 3-11 , five bits of the system byte are allocated as follOVJS

(bits 12 and 14 are used only on Ihe MC68020; !hey are explained in Chapter
8):
Bits 8 -10 = lnterrupl mask (10, 11 , 12)
Bil 15 = T (trace mode flag)
Bit 13 = SS (supervisor stale flag)

INTERRUPT MAS K
These Ihree bits allow the syslem to sel up 8 priorily levels (0 Ihroogh 7) Ihal
determine which interrupts will be accepted or setviced by the M68000. The
name mask gives a useful insight into this concept, since certain level interrupts

are masked or disallowed by these 3 bits.

External devices can request an interrupt of priority level 1 through 7 (7
being the highest priority) by sending a 3-bit signal to the MPU. When the MPU
has completed its current operation, it will compare the requested level against
the current mask level. Only if the incoming request level is higher than the
mask setting will the interrupt request be serviced. Otherwise the request is
ignored. If the mask is set to level 0, then obviously all interrupt requests are
serviced. A mask set at 7 means, "Oon't interrupt!"

88

68000, 68010, and 68020 Primer

TRACE MODE
Setting a 1 in the T (trace mode) flag will switch the M68000 to a special singlestep state, called the trace mode. In this mode the MPU will complete just one
program step and then switch to a user-supplied debugging routine. An excellent

example is the RX program available on the MC68000-based AlphaMicro AM100 .... Using AX 'y'ClU can display your program, execute it step-by-step, set
breakpoints, and examine the contents of each register at any time.

SS FLAG -

USER AND SUPERVISOR MODES

The M68000 operates in one of two exclusive modes (or states): user mode or
supervisor mode. It is easy to tell which mode is in force - you just test the
SS (supervisor state) flag in the status register. If SS = 1 you are operating in
supervisor mode. If SS = 0 you are operating in user mode.
A program running in supeIVisor mode has access to all resources in the
system, including special areas of memory, the supervisor stack and the system
byte, by means of privileged instructions. A program in user mode will generate
error conditions if it encroaches on these systems resources.
In a typical IoVOrI<ing system, the mode will be regularly switched betvJeen
supervisor and user states. Roughly speaking, normal applications software is
run in user mode, while the OS and other systems software will run in the
privileged supervisor mode.
You will see in Chapter 6 that many different events bigger these state
changes. These events can be deliberately programmed or they may arise from
unexpected exceptions known as traps.
This tv.o-state approach is Motorola's solution to the problem of system
integrity which we discussed in Chapter 1. Or, rather, it offers the systems
designer methods of increasing systems security. In particular, it helps protect
the OS memory areas from aCcidental or deliberate incursion by user programs.
The state is not only indicated in the SS flag of the system byte, it is also
broadcast to all external devices via the 3 FC (Function Control) pins to the
control bus. Referring back to Figure 1-13, you saw how a memory management
unit could use these signals to segment memory into system and user areas.

SUPERVISOR MODE SUMMARY

The supeIVisor mode has access to all the user mode resoorces but additionally
enjoys some extra privileges and resources needed by the operating system for
added efficiency and security. Normal user programs run in user mode, but
interrupts, traps, and exceptions are processed in supervisor mode.

M6BOOO Programmer's Models

89

STACK POiNTERS
A stack is simply a portion of memory with a pointer address, allowing you to
push data in, and pull data out, on a LIFO (Last in R"t Out) basis. in Chapter
5 IJ..'e will sho..v in detail how stacks are easily handled on the M68000 using
M<JVE instructions with builtin stack pointer increments and decrements.
Stacks are commonly used to save all kinds of parameters and status words
while you jump off to do other things, such as subroutines, which in tum jump
off, and so on, in what is called nesting. Even if you have plenty of registers for
saving and recalling data during the nesting, the stack is more convenient for
the programmer, since the sequence of pulling (recalling) automatically reverses
the sequence of pushing (saving).
Some care is needed to avoid confusion in the 68000 terminology for stack
pointers. You are free to set up your ovm private stacks using any convenient
address register as a stack pointer. l-\ovJever, such private stacks are entirely your
responsibility.
The M68000, on the other hand, maintains tvJo systems stacks, the user
systems stack (active only in user mode) and the supervisor system stack (active
only in supervisor mode). Some M68000 instructions make implicit use of the
systems stacks, others allow the programmer to reference them with the mnemonic Sp, or systems pointer. SP is, in fact, another name for A7. Because the
two systems stacks are never active Simultaneously, they can both be referenced
with SP ( ~ A7). Remember, though, that the meaning of SP is determined by
the M68000 mode at execution time.

CONDITtON CODE REGISTER

The single 8-hit CCR (condition code register) forms the l~ user byte (hits
0-7) of the SR (status register).
The 10VJeT 5 hits of the CCR, as lJ..'e've seen, are used to signal various
conditions following arithmetical or logical operations. The top 3 hits of the CCR
are not currently used.
The five condition flags (sometimes called status flags) are designated as:
Bit

CCR nag
Where:

X = eXtend
N = Negative
= Zero
= oVerflow
C = Carry

Z
V

1
V

0
C

90

68000,68010, and 68020 Primer

We discussed the X, V, and C flags in depth in the data register section

above. The remaining flags are extremely simple. The Z flag is set to 1 if the
result of the last instruction was zero, otherwise the Z flag is cleared to O. A
nonzero anSVJer gives Z =O. A zero answer gives Z =1. The N flag is set with
the value of the MSB (most significant bit), also knov,m as the sign bit. So, for
signed arithmetic we have: N = 1 for negative answers; N = 0 for positiveizero
answers.
CONCLUSION

In this chapter we have set the scene for a more detailed look at the M68000
instructions. In Chapter 4, you will look at the most commonly used op codes
and see, with program examples, just hO\.l.l they work and when to use them .

4
M68000 Instruction SetFirst Steps
Bloody instructions, which being taught, return
-

10

plague the invenfor.

Shakespeare, Macbeth I, vii

Chapter 4 will explain what an instruction is, and introduce you to some of the
Simpler, more commonly used M68000 instructions. The program examples VJe
offer as illustrations are not meant to be complete, practical programs, all ready
to be entered and run, although VJe have tried to make them interesting and

rooted in the real v.orld.

INS TRUCTIONS
As far as the M68000 is concerned an instruction is a set of 16-bit \.\.Qrcls sitting
in memory and a progr am is a sequence of such instructions which will hopefully

guide the system through some useful VJOrk.

To the untrained human eye machine-level instructions form a bewildering

sequence of O's and 1 '5, but as they are read in and decoded by the chip, these
instructions are obeyed according to very precise rules - and this is what is
called running a program.
In this chapter I.Ve will be dissecting each M68000 instruction to see how
it works and why it is used. The functional side of the instructions will be
illustrated with beforeand-after diagrams. Where and when to J,lse them is the
creative art I.Ve call machine-language programming, and I.Ve can only hint at
the infinite number of possibilities by showing you isolated program examples.
91

92

68000, 68010, and 68020 Primer

There is no substitute for practical hands-on experience - Appendix E (M68000

Resources) is designed to help you acquire the hardware, software, and further
documentation needed for this.
If VJe VJere purely binary creatures VJe could refer to machine instructions
as "Ol11001000(XXXX)1" (which actually tells the M68000 to move the number I to data register I) or "0101111010010010" (which """Id add 7 to a
number in memory) and so on. Alas, life is too short and humans are just not
built to communicate like this. Dropping a 1 or mispladng a 0 can have a
disastrous impact on the meaning of the instruction. 'Abrse still, some instructions
have one or more extension words and may take up to 80 bits to spell out.
Imagine learning Morse with over 150 million different codes!
The obvious way out is to have recognizable English symbols for each
instruction - and, in fact, this is exactly hOVJ an assembly language programmer
thinks, writes, and talks about each instruction. The symbols you use are called
mnemonics since they help you to remember the function of each instruction.
In the two examples just mentioned, 0111001000000001 is written
MOVEQ

#1 . 01

and 0101111010010010 is written

ADDQ . L 17 . (A2 1

The English versions may still look bizarre to you but you have to admit that
they are better than all those O's and 1'sf As you proceed, the full beauty and
predsion of the instructions will become clear - what they can achieve and
hov.r they are combined to produce working programs is, after all, the reason
for learning their secrets.
Keep in mind, though , that the M68000 itself never "sees" these mnemonic
symbols. They are simply an aid to human learning and programming. As VJe
saw in Chapter 3, our symbolic instructions have to be translated or assembled
into binary machine code before they can run. The actual binary patterns of
each instruction are shOVJn in Appendix D. Feel free to memorize them if you
wish, but VJe still think that a good assembler is the ansv..oer.
INSTRUCTI ON FO RMATS

Each symbolic instruction is rather like a sentence in English. As v..oell as getting

to knOVJ the meaning of each word, you also have to knOVJ the correct grammar
or syntax so thai you avoid illegal or nonsensical combinations. For example,
"bites dog man" contains three perfectly understandable words, but the overall

M68000 Instruction Set -

First Steps

93

meaning is somewhat obscure to say the least. And just as English usage varies

as you travel around, you will find different M68000 implementations using
slightly different names and formats for the same instruction. Luckily there is a
natural standard, and not surprisingly, it was invented and promoted by Motorola
- so VJe will use it throughout. If you spot any deviations on your own machine
you knOVJ who to blame.
Since our object is to teach the basic workings of the M68000 instruction
set, we will avoid most of the technicalities of assembly by adopting the following
plain "vanilla" version of the Motorola syntax.

tNSTRUCTtON SYNTAX
There are three different instruction layouts in the M6800G:

1. No operand: op code stands alone

2. One operand: op code foll()l..l.led by operand
3 . T1,1,.0 operands: op code followed by source operand and destination operand
The op code is a mnemonic such as JMp, MOVE, ADD, SUB which tells
you what the instruction will do. The M68000 has about 60 basic op codes,
and many of these can have up to 500 variations! Even experienced 68000
programmers do not carry all these combinations around in their heads. Rather,
they understand the governing principles and consult the reference sheets when
in dcxJbt on a particular instruction. For this reason we have constructed some
useful appendices crossreferendng the op codes in various ways to help you.
The operands are registers or memory locations which tell you what the
op code acts on. Continuing our analogy with English, you can consider the op
code as the verb, and the operands as the direct or indirect objects in a sentence.
To get a feel for these three instruction formats let's look at some examples,
without delving too deeply into hOVJ they I,I,.Ork.

No Operand

RTS

The op code is ReTurn from Subroutine. No operand is

needed for the RTS instruction .

One Operond

ASL.W (AO)

The op code is Arithmetic Shift Left. Word. The single

operand (AO) tells the M68000 where to find the data to

be shifted, namely the IM)rd at the memory address

stored in address register AG.

94

68000,68010, and 68020 Primer

Two Operands
MOIIE.B D3,D4

The op code is MOVE.Byte, which needs two operands,

namely the source operand, data register 3, and the
destination operand, data register 4. Our example says
move the lower byte of D3 to the lower byte of D4, that
is, from source, to destination.

Since most of the instructions are of the t\.vQoperand type, let's examine
this layout in more detail (see Rgure 4 1). l-b..vever simple or complex our tVJO
operands may be, you will always find a comma separating them. The source
operand always comes first; this is where the instruction gets its initial data from.
The destination comes after the comma, and indicates where the result of the
operation is to be found.
Source operands are not changed by an instruction.
Destination operands are changed.
So, MOVE.S 03,04 leaves the contents of 03 undisturbed and replaces the 04
byte with the D3 byte. Later on we'll show you particular examples of MOllE
and its many variations.
l-lere is another example of a very popular tvJooperand instruction called
ADD.

ADD.L 06, D7

ADD. Longv..ord says: add the 32 bits of source, 06, to

the 32 bits of destination, 07, and place the sum in the

destination, 07. Here again we see the destination
operand receiving the result of the instruction's op code.

DATA SIZE CODES - l , W, AND B

In the above examples you will see that some op codes have a letter attached
to them. We call this the data size code because it dictates how many bits of
the source and destination operand are involved in the instruction. The rules
are very simple and apply whether the operands are values in registers or in
memory:
L means Longv...ord - operate on all 32 bits.
W means lAbrd - operate on loo.ver 16 bits.
S means Byte - operate on loo.ver 8 bits.
Most instructions VJOrk with any of the three data sizes, so we will often use a
shorthand notation, for example, ADD.z, where the z can represent L, W, or B.

M68000 InSlruction Set -

First Steps

95

I
-1---"r--~~~dataDestination
What to do~~~~~~ ~
register 4
MOVE.B

03

04

Size code!bte

Source
' - - - data register 3

16 15

31

From
03
source

8 7

Belore

t--- not involved -~.". Lower .

~1.

MOVE

To
04
destination

.4t--

not involved -~...

03
unchanged

Alter
}

MOVE

04
lower byt e
only changed
not

Fig. 4-1

involved -~."

Two Operand Instruction: MOVE.B 0 3,04

You already knQ\.V enough to write a real program, so we've created a

hypothetical Situation to test your mettle.

PRACTICAL APPLICATION
frubIom, \bu ... running a poyroIJ program at the end of _ . and need to
update the - ' hours \IQIoed yearl<HIate iYJD) to include the hours to._.
Use ADD and MOlE, and put the updated - ' in data ~_D3
_
. _ __

96

68000,68010, and 68020 Primer

GiYell:
I. T.,.,I hours worhed VTD. January through Februoll< _ I n ...... 01.

2. Hours worhed in Mon:h _

in ~

02.

SompIoC...:

Hours VTD - 320 In 0 1

Hours Mon:h : 138 In 02
New Hours VTD : 458 place In D3
Solution: ,."",om 4-,
JlVE L
ADD_L

01, D3
02,03

D3 """ coolOins !he sum 102

01) : 458. 01 and 02 ... unchanged

DATA SIZE AND TH E RANG E OF THE RESULTS

The ADD instruction gives a straightforward binary addition , and it is up to you

to dedde whether you interpret the results as signed or unsigned. In this tiny
program \.Ve are dealing with small positive numbers \.Veil within the range of a
32-bit register, so the question is academic.
It is worth noting here that the M68000 usually has more work to do when
per!onning a 32-bil I.L) operation compared wilh a 16-bil (.W) operation.
Similarly, W instructions usually require more internal processor steps than their
S-bit (.B) variants. If someone asks, "J-iovJ fast is the M68000 ADD instruction?"
- all we can give is a range of values (worst and best cases) for L, W, and B
variants. Even these will depend on the chip model and its clock speed (typically
ranging from S MHz to 16.7 MHz - giving a basic clock cycle ranging from
125 nsec to 60 nsec). f'.k>, we are not evading the question! ADD effectively
takes from 0 (yes, zero) to 30 clock cycles depending on "where, when, and
what" is being added. The effective zero miracle is, briefly, due to the way the
MC68020 OI..'eTlaps instructions.
In any case, there is no simple formu la to relate the timing of L, W, a nd B
operations. For example, W instructions seldom take twice as long as their B
versions - however, common sense dictates that when there is a choice of data
size, you pick the smallest which will handle the data range for the job at hand.
Indeed, in !he above example yw could have saved a few clock cycles by
using MOVE. W and ADD. W since you kncm your numbers are all within the
range of a 16-bil operation Isigned or unsigned). MOVE.B and ADD.B, however,

M68000 fnSlrucfion Set -

First Steps

97

IJ..OUld not \.UOrk since our data values exceed 255 (1 1111111 ), the unsigned
limit for a byte. The most common situation in practice is to \.VOrk in signed (2's
complement) numbers - so the above program, for example, VJOUld allow a
negative value in D2 to adjust the hours YTD (ADD a negative to SUBtract).
As you develop your payroll program you will be watching out for the range
and sign of various data values, so you can use the appropriate data size letter:.
You will also see hovJ to use the CCR (condition code register) to check the
accuracy of your arithmetic.
COMMENTS
A useful convention offered in all levels of programming is the ability to add
titles, dates, revision numbers, comments, remarks, notes, and reminders in a
program text intended for human consumption only. Such comments are ignored
by assemblers and compilers but can prove remarkably useful when you (or
your colleagues) come to read your program listing months later and \.UOnder
. "What's going on here?" or "Why did I do that?"
Adding sucdnct comments is a good habit, espedally in low-level languages
where the actual intent behind each line may not be immediately obvious.
Motorola commenting conventions are simple. They allow both separate comment lines and "in-line" comments as foUOI.AIS:
anywhere signals a whole line of comment

so that the assembler ignores all characters following the (asterisk) until the
next line of source code is read. Alternatively, you can comment anywhere to
the right of a program line:
<OP CODE> <operand (s

In-line comments here

provided you have at least one space (or tab) between operands and comment.
Let's develop good habits by adding a few comments to our first program
example.

* Program 4-1 with comments

* Update YTD 4 rev I SKB
MOVE . L

ADD. L

* D3

01 ,03
02 , 03

now has updated hour s VTD

Old YTD now in D3 (32 bits)

Add March hours to old VTD

98

68000, 68010, and 68020 Primer

CCR - CO NDITION CODE REGISTER

In Chapter 3 you saw how the flags in the CCR monitored various processor
conditions, warning you of possible errors. It is important to knOOJ hOOJ each op
code affects the five CCR flags , so we'll use the following notation:

CCR flag
MOVE

X
~C

ADD
Where:

C
0

means unchanged
means always cleared to 0
means always set to 1
means either cleared or set depending on the
result of the instruction
means undefined, that is, the flag will not tell you
anything useful
means set or cleared the same as the C flag

0
1

U
~C

Rgure 4-2 shows how Ihe regislers and CCR change during Program 4-1.
Let's embellish rur program by testing the CCR. This will require several new
instructions for branching and a construct knOOJn as label to mark the place in
the program where you want to branch to.

, Program 4-2: Testing the OCR

Updat e YTD 4 rev 2 SKB
MOVE . L

ADD . L

D1 , D3
D2 , D3

Old YTD now in D3 (32 bits )

Add March hours to old TV

D3 now has updated hours YTD

BVS
ERROR. 1 Branch if oVerflow Set to label ERROR. l
SEQ
IDLE
Branch if EQual zero t o label IDLE
<rest of program>
ERROR . 1

BRA
OVER
BRanch Always to OVER
<take action: D3 overfl ow>
We have detected overfl ow

M68000 Ins/ruction Set Source

MOVE.L

++

01

Size code

,hongword

99

31

Oeslinalion

01 . 03

First Steps

320 _ _J
L-_""::"::":"

I}

before

03

r'lu....don.,-c.,......,

01

L-----'3:..:2:..:0_---'. } after

CCR before

II
II

L:. ~,

CCR after

Source

CD

AOO.L

320

Desl inalion

t02. 03t

31

02

138

Size code

!.ongword

03

320

02

138

.}

before

CCR before

I xl~I~I:I~'
CCR after

03

BRA
IDLE

OVER

Update Hrs YTO

BRaneh Always to OVER

OVER

<t ake aelion: hours YTD : 0>

after

1
....._4-'5'-'8_----'

~ -D2+D3

Fig. 42

'}I

<w ind up program>

03:0 Possible error?

100

68000, 680/0, and 68020 Primer

BRANC HES AND LA BELS

As promised, our revised program introduces two ne\.V, closely related concepts,
branching and labels. Unless otherv.rise informed the processor will advance
sequentially from one instruction to the next, something like this:

I. Look al Ihe address in the PC (program counler).

2. Fetch the first IJJOl'd of this instruction from memory address

= PC.

3 . Decode this instrucoon-v..ord and, if necessary, fetch any additional (or extension) v..ords to decode the complete instruction.
4. Carry out the steps needed to complete the current instruction.
5 . Increment the value of PC so it points to the next instruction.
6. Repeat cycle from step 1 above.
This steady linear sequence of instruction-fetch -obey (see Figure 4-3) can
be varied either unconditionally or conditionally by the use of branching instructions and labels.

UNCONDITIONAL BRANCHING - BRA LAB EL

The BRA (BRanch Always) instruction is an unconditional branch - and it has
the dramatic effect of changing step 5 in the normal sequence listed above.
What happens is that the PC, rather than increment to the next instruction
memory address, receives a brand new address depending on the label used,
and program control is switched to the line in the program with that label. So
BRA OVER in our example causes the program to skip to the line labeled
OVER - and from there you are back into your nannal sequence of steps 1
through 5, at least until you hit another branch.
Let's see how the normal sequence is changed when the BRA instruction
is encountered:

I. Look al the address in the PC (program counter),

2. Fetch the first IJJOl'd of this instruction from memory address = Pc.
3. Decode this instruction v..ord and, if necessary, fetch any additional (or
extension) \.VOrds to decode the complete instruction.
4. If instruction is BRA OVER, step 3 will have obtained a signed number, called
the branch displacement, which depends on the location of the label OVER
in the program.
5. ADD this branch displacement to the value of PC and place the SUM back
in PC. PC now points to the instruction labeled OVER.
6. Processor is now ready to proceed with step 1 above, where it will fetch,
decode, and obey the instruction labeled OIlER.

M68000 Inslruelion Sel -

First Sleps

Program counter
f.lch (N)

N' _

Address. N

p~2 Bl
PC+2

N+4

Oecode
fetch
fetch

N+2 }

N
Ext word 11

N+6

N+4

"~-"~~

]1
.-

N"' _

I WO<d
instruction

N+8 }

N+IO

'" ~,
.5

Oecode (N+6)

Ext word 3-1

~2

101

N+12

r....~~I~~f.~lch~(N~+~8~)J

p~2 1,-__N_+I_O...J~

Oeoode N+8
letch N+10

Fig. 4-3

PC and Instruction Seq uence

Notice that steps 1 through 3 are always the same, but that IF a BRA
instruction is decoded at step 3, the PC, rather than incrementing to the next
line of your program, will be adjusted to pick up the line labeled OVER (see
Figure 4-4). You need not, at this stage, worry too much about precisely hovJ
the branch displacement is calculated in order to achieve the correct PC value
for OVER The main points to appredate are:

Branching involves a break in the normal "get the next instruction"

sequence by an adjustment to the address in Pc.

102

68000, 680/0, and 68020 Primer

fetch

PC

N
Decode

PC

PC

N+d

Fig. 44

PC and Branch Instruction Sequence

Labels are essentially instruction addresses translated by the system

so that the new PC address equals (PC + branch displacement) takes
you to the instruction at the labeled line.

Since the branch displacement is a signed value (plus or minus). note

that you can branch forward or backward in a program. If the label is
located later in our program , beyond the BRA line, then the displace
ment will be positive, increasing PC so that you branch forward. If the
label comes before the BRA line, the displacement is negative, you
decrease PC and branch backwards.

Readers with a knO\.Vledge of BASIC will recognize the similarities bet\.veen

BRA and GOTD. A big difference is the use of alphabetic mnemonic labels
rather than the line numbers used in most BASICs. Behi nd the scenes, as we
have hinted, the label OVER acts very much like a line number. When the above
program is assembled, loaded, and executed, the label OVER is translated into
the memory address of that particular instruction, and it is this address which is
eventually placed in the PC when the BRA OVER instruction is decoded. l-L::::lvJ
this is achieved will be covered in greater detail when \IJ discuss absolute and
relative addressing.

M6BDOD Instruction Set -

First Steps

103

The programmer is free to use any reasonable set of characters as a label,

but naturally one must avoid duplication of label names within the same pro
gram. Also, the correct syntax must be follOVJed - labels must be placed on
the extreme left of the line, and spaces or tabs are needed between label and
op code.
Branching unconditionally is not much fun. Let's see hOVJ and why v..oe
branch conditionally, so we can fully understand Program 42.
CONDITIONAL BRANCHING
A set of 14 branch instructions of the general form

Bee

<label >

allOVJs you to branch only if the condition code (ccl is met. The h.vo letters, cc,
are mnemonics for the particular CCR flag conditions that the M68000 can test
before deciding whether to branch or not. If the condition is not met the next
instruction is fetched and decoded. If the condition is satisfied, the M68000
branches to the labeled line using the mechanism \.V outlined for BRA
So, Bec < label> can be read as:

If cc true, do a BRA < label>.

If cc false, do the next instruction.

Understanding Bee is roughly 150% of the way to

M68000 fluency.
What sort of cc conditions can we test using Bec? Program 4 2 shovJs h.vo
simple cc cases in which the test is made on single flags in the CCR BVS has
cc = VS so look at the V flag. Is it Set = 1 or not? SEQ has cc = EQ so look at
the Z flag. Is result EQual to zero or not? That is, is Z = 1 or not? BVS ERROR 1
says: Branch (to line labeled ERROR 1) only if oVerflOVJ flag is Set = 1. If adding
02 to 03 results in overflOVJ the answer in 03 is wrong, and you must do
something about it. So, you test the V flag with BV5. If V = 0, all is well (so far)
and you ignore the branch. If V = 1, you have overflow, and you have had the
courage and foresight to guard against this with a BVS.

The program section begin ning with the line labeled ERROR.IlM:lUld have
to deal with the fact that overflOVJ had occurred and the result in 03 is arith
metically wrong for signed numbers. In our example it v.ould mean that the

104

68000,68010, and 68020 Primer

hours YTD had exceeded the range-2 ,147,483,648 through +2,147,483,647

and this UJOUld seem to indicate either errors in the initial data or a bug in the
program. BVS tests can therefore be useful error traps when developing and
debugging a program, but when handling large or potentially large (near the
limit) numbers, BVS provides an essential check against error
BEQ IDLE says: Branch (to line labeled IDLE) only if ",suit is EQual to
ZERO, that is, only if the Z nag is set (~ 1). The cc ~ EQ mnemonic here is a
little unobvious (why didn't they call it BZS for Branch Zero Set?), but v,.oe'll use
it anyway. What this program is testing for is whether 03 = hours YTD is zero
or not. If D3 is nonzero, you carry on with the rest of the program. If D3 is zero
you want to do something different, so you branch to the line labeled IDLE. You
choose a suggestive mnemonic, as always, to increase the legibility of your
program . The BEQ is commonly used to bypass unnecessary parts of a program. A very common example v.ould be "Never print an invoice for $O.OO!"
In our example, the branch to IDLE if hours YTO is zero does not necessarily
indicate an error (although it may require special scrutiny) but in a complete
payroll program it may simply mean that yoo can safely bypass further wagel
tax calculations if the employee has not worked.
Hcc AND TH E CCR
Bec tests the CCR but does not change the CCR flags - so you can make
successive Bec tests, such as BVS follOVJed by BEQ, as shown in Program 4-3.
If BVS does not branch , you immediately test for zero with BEQ.
This point highlights the importance of knowing how each instruction affects
the CCR. Let's see a common piece of careless coding which can spell hours
of frustration. Suppose that after Program 4-2 has been up and running successfully for some years, we decide to add an innocent line (such amendments
are known as one-line patches) as in Program 4-2A:

Program 4-2A: Incorrect change to Program 4-2

Update YTO--4 rev 3--Save 03 in 04 for later use
MOVE . L
AOO . L

MOVE.L

01 , 03
02 , 03
D3 , D4

old YTD now in 03 (32 bits )

Add March hours to old YTD

++ one-line patch

03 and 04 both have updated hours TO

M68000 Ins/ruClion Set -

BVS

Firsl Sleps

105

RROR. l Branch to ERROR.l if OVerflow???

<Tes t of program as in 4-2>

ERROR . 1 <take action: 03 overflow>

We have detected overflow???

We have inserted a MOllE.L between the ADD and the BVS, as indicated
by the + + comment. Can you spot the mistake? Yes, the V flag is cleared by
the MOVE and the BVS test is now meaningless. We will never branch to

ERROR. I ewn if ADD sets the V flag.

Bee - THE FULL STORY
You have now seen tv..o of the 14 Bec branches. The other 12 Bec instructions
test a variety of CCR flag conditions, both single flags and combinations of
flags. We postpone discussion of the multiple flag tests until IAI cover CMP
(CoMPare) in Chapter 6. Here are the single flag Bec's which all \o\.Ork like BVS

and BEQ.
BVC - Branch if olkrflow flag Clear IV = 0).
BVe and BVS are therefore complementary tests; if one is true, the other must

be false.
BNE -

Branch if Not Equal to zero, that is, if Z = O.

BNE and SEQ are also complementary tests - again, if one is true, the other
must be false.

BCC - Branch if Carry flag Clear IC = 0)

BCS - Branch if Carry flag Set IC = I)
Here once more, Bee and BeS are complementary tests. By the wCI.J, be careful
not to confuse ee (Carry Clear) with cc (any condition code).

BPL - Branch if PLus lpositiwl, that is, if N = 0

BMI- Branch if Minus Inegatiw), that is, if N = I
You guessed it. SPL and BMI are complementary tests.
This chOice of cc's (and remember, there are more complex ones to follow)
allows considerable flexibility in testing results and taking the appropriate action
by branching to a labeled program line. They come, as you can see, in pairs of
opposites, which may seem wasteful at first sight For example:
BPL ANS_PLUS

<program M>

Do

program P if answer +ve

00 program M if answer -ve

106

68000,68010, and 68020 Primer

ANS]LUS

<program P>

can also be written as:

BM!

ANS_MIN
P>

<program

Do

program

if ansllo'er -ve

Do program P if ans ....er +ve

Both programs achieve the same result, so you could survive with just BPL or
with just BM!. In practice, however, it turns out that the choice is useful - you
can often produce more legible programs by picking the natural Bec for each
situation, for example, by branching if the abnormal condition prevails,

BRANCHING SUMMARY

BRA LABEL causes unconditional branch to label.

Bee LABEL branches to label only if cc condition is true. If cc is false ,
obeys next instruction.

Na..u that you have seen a few simple instructions \VOrking with data register
operands, ya.t can look at other types of operands that are spedfied by various
combinations of registers and/cr memory addresses, known as addressing modes.

ADDRESSING MODES
You can imagine an instruction saying "OK, I know I'm supposed to ADD or
MOVE or whatever, but you have to tell me where to get the source and
destination operands." This is done by expressing each operand in a certain
format , laced, as it UJere, with suffident information to direct the instruction to
the correct operand data, These operand formats are called addressing modes
- a nd they fall into tv..o main groups, register direct modes and memory
modes, As you'll see, each of these groups can be broken down further into
smaller groups of addressing modes. Also, you'll fi nd that most instructions allow

a choice of m:xles for both soorce and destination operand, in many combinations.

M6BOOO inslIuc tion Set -

First Steps

107

Having stated earlier that understanding Bee is 150% of M68000 fluency,

we can now add that the remaining 150% of M68000 fluency comes with
mastering the addressing modes!

REGtSTER DIRECT MODES

In our programs, so far, the initial data was available from data registers, 01
and 02, and the result of the program, D1 + D2, was then stored back in a
data register, D3. All our operands, therefore, both source and destination, were
expressed directly in a simple fonnat called register direct addressing mode.
This mode has two variants:

Address Mode

Symbol

What Is the Operand?

Data Register Direct

Address Register Direct

On
An

The value in Dn
The value in An

where On is any data register (DO through D7) and An is any address register
(AD through A7). To reduce verbiage we will often refer to these direct modes
as the On mode or the An mode.
Yoo saw in Chapter 3 how the address registers are used to hold 16- or
32-bit addresses, and for this reason the An mode has some spedal rules
prohibiting Byte operations and certain purely "data" operations. Apart from
these differences, which will be detailed later, the On and An modes are broadly
similar.
So, the two direct modes are used when the source operands are values
(data or addresses) actually available in registers. When the direct mode is the
destination, you are telling the processor which register is to receive the result
of the instruction.
The next section deals with operands in memory.

MEMORY ADDRESSING MODES

In most practical situations the initial data input for a program is loaded into
user memory (RAM) via some external device such as a disk or keyboard. The
results of the programs' various calculations are then stored in user RAM, and
thence back to some output device such as a disk, printer, or CRT. To achieve
this you need memory addressing modes, which " tell" the op code where to
locate its source and destination operands in memory. The MC68000 has 10

108

68000,68010, and 68020 Primer

and the MC68020 has 16 distinct memory addressing modes as listed in

Appendix B.

MEMO RY ADDRESSI NG AND THE EFFECTIVE

ADDRESS
The memory addressing mode formats range from extremely simple ("Here is
the memory address of the operand") to very complex ("To get the memory
address of the operand you will need to add tv..o numbers to form an address,
go to that address in memory where yc.u will find another address, add a number
to it, and that's the address of yc.ur operand!" ) Luckily, the beginner can gently
build up from the simple modes. The complex example was intended to stress
the fundamental fact about memory addressing modes:
A memory addressing mode a llows the instruction to
calcula te the < ea> or effective address of a n opera nd.
A~ operand sitting in memory is uniquely identified and located by its
< ea>, effective address. For each addressing mode, the processor has a spedfic
< ea> calculation to perform before it can fetch the source operand from
memory address < ea >, and Similarly, before a destination operand can be
written to memory, its < ea > must be ca1culated. These calculations (and
associated fetches, if any) can take from 0 to 24 clock c;des. The importance
attached to these < ea > calculations is typified by Motorola's inclusion of tv..o
additional ALUs that can perform the < ea> arithmetic while the main ALU is
handling the normal data arithmetic.
t-bN does the M68(x)() kno.v which < ea > calculation to perform? Without
digressing too far, I.Ve can simply say that each instruction VJOrd, at the machine
code level, has bits assigned that uniquely encode each possible addressing
mode for the source and destination operands. When the instruction VJOrd is
decoded, the M68000 knows both the operation required and how to derive
the operand < ea > s.
We saw in C hapter 2 that one advantage in moving from 8-bit to 16-bit
processors was that a 16-bit instruction VJOrd a llows a richer instruction set, and
with this comes the possibility of more complex addressing modes.

WHY SO MANY ADDRESSING MODES?

This abundance in addressing modes, formerly available only on mainframes
and minis, is a major key to the success of the M68000. The novice may

M68000 Instruction Set -

First Steps

109

consider it paradoxical, but the apparent complexity of the addressing modes

actually Simplifies the programming of the M68000's huge addressable memory
for today's wide and growing range of sophisticated multiuser operating systems,
language compilers, relational databases, and bit-mapped graphics applications.
All of these require the rapid manipulation of complex data structures in memory,
such as linked lists, " trees" that grow in all directions, multidimensional arrays
and tables, stacks, and queues. Much of this manipulation, espedally In commercial as opposed to scientific applications, involves address rather than data
calculations.
To locate complex memory operands on the earlier 8-bit micros with few
addressing modes, the programmer had to write spedfic, often tedious, code to
compute the < ea >. The more advanced addressing modes available on the
M68000 dramatically reduce this effort. In effect the programmer can pass the
onus of < ea > arithmetic to the chip's fast internal ALUs.
In essence the M68000 addresSing modes (and the modern assemblers
that exploit them) provide a sort of high-level language for accessing complex
data structures in large amounts of RAM.
As you'll see, each addressing mode is designed to solve a particular
memory-access and data-manipulation problem. Our first example is probably
the simplest addreSSing mode, called immediate, which is used only for source
operands.

IMMEDIATE ADDRESSING MODE

In many situations we want to use fixed numeric constants - that is to say,
numbers that are predetermined and not the result of some calculation. Suppose, for example, that in Program 4-2 we want to keep a count of the number
of idle emplQljees - all those with zero hours YTD. Let us assign data register
D4 to keep this count. Each time you branch to the label. IDLE you will increment
(add 1 to) 04. At the end of the payroll you can print out the number in 04.
Program 4-3 shows the new program (with the additions highlighted).
Program 4-3 : Count Idle Employees
Update YTD 4 rev 3 SKB

MOVE. L
ADD . L
CLR . W

01 , 03
02, D3
D4

D3 now has updated hours YTD

Old YTD now in D3 (32 bits)

Add March hours t o old YTD
Set lower 16 bits 1M to 0

110

68000, 68010, and 68020 Primer

BVS

ERROR. ]

BEQ

!DlE

Branch if overflow Set

Branch if EQual Zero

<rest of program>

BRA
OVER
BRanch Always to OVER
ERROR . l <take action: 03 overflow>
We have detected overflow

BRA
!DlE

ADOQ.W

OVER

#1 , 04

BRanch Always to OVER

Incre_ent 04 = idle count

OVER<wind up program>
<print value in 04>

NOTES ON PROGRAM 4-3

There are two new op codes in the revised program, CLR (CLeaR) and ADDQ
(ADD Quick). CLR is a simple but useful one-operand instruction with the
following syntax:
CLR . z <operand.>

which clears some or all of the operand to 0, depending on the data size letter

z. CLR. L will clear all 32 bits. CLR. W will clear just the lower 16 bits. The
upper 16 bits are unchanged. CLR.B will clear just the 10VJeT 8 bits. The upper
24 bits are unchanged.
In this example, we have chosen to use just the lower 16 bits of D4 as the
"counter of the idle", leaving you free, if ycu wish, to use the upper 16 bits for
something else. For a small payroll (less than 255 employees) you might consider
using only a byte of D4 (unsigned ) - the data size code z gives great flexibility
in register utilization. You CLR W D4 to make sure that your 16-bit counter is
"zeroed" before you start counting. Remember that CLRW does not affect the
upper 16-bit IJJOrd of 04. It is a surprisingly common oversight to forget to CLR
counters.
CLR changes the CCR in a reasonably predictable way:

CCR flag
CLR

v
o

since the operand is now 0 (2 = I), non-negative (N =O), and there is no overflow
or carry (V = 0, C = 0). The X flag is unchanged, as we saw in the MOVE
instruction earlier.

M68000 Instruction Set -

111

Firs! Steps

Uke ADD, ADDQ is a two-operand instruction. The general fonnat is:

ADDQ . z

#<data> ,<des tinati on operand>

where < data > is a number between 1 and 8. This means ADD the number in
< data> to the destination (L, W, or S , depending on the size code) and place
the sum in the destination. The Q in
stands for the Quick fonn of the
ADD op code. The immediate source data, written always with the # (pound
sign ) symbol, is simply added to the destination. In our case,

ADoo

ADDQ . W

#1, 04

increases the iOVJef VvOrd of D4 by 1.

The reason it is quick is that the processor does not have far to look for the
source data. In fact , the sance data is stored as 3 unsigned bits in the ADDQ
instruction \.\lOrd itself - and this explains why ADDQ can only add small
unsigned constants in the range # 1 to #8.
Here is a quick check to see if you are paying attention. f-bw can you store
the numbers 1 to 8 in 3 bits? Surely 3 bits can only store the numbers to 7?
\Nell, the M68000 perionns a trick! It will be instructive to explore this trick
because it gives us a chance to peep "inside" a simple instruction y.,ord and
see its bit pattern. The ADDQ instruction word looks like this:

Bit 15 14 13
0
1 0

12
1

Where: ddd

zz
mmm
m

11
d

\0 9
d

Biis 9 -11
Bits 6-7
Bits 3 -5
Bits 0 -2

8
0

6
z

specify the
specify the
specify the
specify the

2
r

1
r

0
r

# < data >

data size code

destination mode
destination register

Bits 8 and 12-15 identify the instruction as ADDQ

The mode and register codes (mmm and rrr) are the bits VJe mentioned
earlier that tell the M68()()() which < ea > calculations are needed - in this case
mmm and ITT are encoded for the destination operand < ea> . Their lonnat is
not of immediate concern, apart from noting that 6 of the 16 bits in an instruction
word are commonly assigned for this Puf]X>5e. Complete instruction bit patterns
are listed in Appendix D.

112

68000, 68010, and 68020 Primer

The data size code is simple: 00 = Byte, 01 = I!.brd, 10 = Loo9"<'rd

(leaving data size 11 unused, a useful spare for the future) . Now for the trick
- hOYJ to code #1 to #8 in 3 bits:
#1
#2
#3

Sets ddd

=
=

#4
#5
#6
#7
#8

=
=

=
=
=

So, the instruction decoder translates ddd

00 1
010
011
100
101
110
111
000
= 000 not as #0 (which VJOUld

be a waste of time and effort) but as #8. This small digression will prove helpful
in giving you an early feel for what \.Ve mean by decoding an instruction. In the
more complex multiVJOrd instructions you shall meet, it will become necessary
to knQV.I how different forms of data (including addresses) are stored in instruction \AJOrds and their extensions.
We hope, also, that this inside view of an instruction gains your respect for
the people who wrote your assembler! Remember that the assembler program
has to convert
ADDQ

I<data> ,<destination>

from your source code into the bit patterns shown above (as \.Veil as performing
many other chores).

ADDQ AND THE CCR

ADDQ changes the CCR just like a normal ADD:
CCR flag
ADDQ

=C

so you get all the usual warnings about the result of your arithmetic. But what
if you need to add larger constants than 0 through 8? Read on.

M68000 Instruction Set -

ADDI -

11 3

First Steps

ADD IMMEDIATE

If you need to ADD larger constants than #8, there is the ADDI instruction,
which we introduce nON because it is very similar to ADDQ. It looks like this:
ADDI. z

I<data>,<destinati on operand>

ADDI al"""" you 10 add up 10 32 bits of immediate data 10 a 10nQlMOrd, up to

16 bits of immediate data to a \NOrd, or up to 8 bits of immediate data to a
byte destination. For example:

ADDI . L

l$fFFFF ,OO

would increase DO by $FFFFF ~ 111 11 111111111111111, but

ADOI . W

#$FFFFF ,OO

would increase the lower ""rd of DO by only $FFFF ~ 1111111111111111

and

AOOI. B

ISFFFFF. DO

would increase the lower byte of DO by only $FF ~ 11111111.

ADDQ is about twice as fast as ADDI because ADDI needs one or two
extension \M)rds to store its larger-sized immediate # < data>. ADDQ's 3 -bit
# < data > can be squeezed into the ADDQ instruction \NOrd, but ADDl .W and
ADDI.B need one extension IJJOTd, while ADDI.L needs two extension \NOrds.
Let's see hovJ.

ADDIINSTRUCTION CODING
3

IJ..brdlOO 0 0 0 1 1 0 z z m m m
IJ..brd 2 W # < data> 16 bits or B # < data > 8 bits
IJ..brd 3 L # < data > has extra 16 bits here == total 32 bits

Bit

15 14 13 12 II 10

These extension mrds, \NOrds 2 and 3, remember, are in memory and need to
be fetched just like any other memory operand. l-b.vever, they do have an
advantage - their address in memory follows immediately after the instruction
1,.V()rd. Now you knOVJ that the PC (program counter) contains the address of
the instruction \M)rd, and that the PC increases by two byte addresses after
decoding. So, as soon as the ADDI is decoded the PC automatically holds the

114

68000, 68010, and 68020 Primer

address of the longv..ord, VJOrd or byte of immediate # < data>. With the
immediate addressing mode there are no extra processor cycles or calculations
needed to obtain the effective address of the memory operand. The source data
is immediately available as part of the normal instruction fetch, decode sequence.
We haw used immediate mode so far only with ADDQ and ADDI. but it
is available as the source operand for many other op codes.
IMMEDtATE MODE -

GENERAL APPLICATIONS

A simple example is:

MOVE.

#<data>,<destination operand>

This simply MOVEs the im mediate data (L, W, or B) to the destination. The
# < data > is stored in extension VJOrds just like the ADDI instruction. There is
no MOVEI instruction , as such; you just use MOVE with the immediate source
format.
Note that the follOVJing instructions are functionally equivalent:
CLR.

MOVE.z

01

10.01

since they both move O's to the L, W, or B parts of 01. Can you guess which
is faster? Clue: CLRz needs no extension words.
Another popular use of immediate mode is:
MOVEQ, L

I<data>.On

which is a quick data move restricted to longword and data registers only.
MOVEQ allows us to move 8 bits of signed immediate data, so VJe will often
use the notation:
MOVEQ . L

#<d8>. On

to remind you. Notice that in order to do a correct L move with only 8 bits of
source, the M68000 must first signextend the # < d8 > to 32 bits.
The # < d8> bits are stored in the instruction VJOrd itself, so MOVEQ is a
superfast way of moving signed numbers in the range 128 to + 127 to all 32
bits of On .

Here is a typical application:

, Program 44 : Counting Cycles

M68000 Instruction Set -

LOOP

MOVEQ . L '52,00
<program>

SUIlQ . L
BNE

11 , 00
LOOP

First Steps

Set counter 00
something

115

+52

Do

Decrement counter by I
Is counter 01 If NO
repeat loop. If YES
exi t loop .

<rest of program>
Suppose you want to perform the same program sequence a fixed number of
times, in our case 52 times. Since 52 is Jess than 127 you can use MCNEQ to
set up your counter in 00. Each time you perform the < program> within the
loop you SUBtract 1 from DO and test the CCR using the BNE (Branch Not
Equal to zero). If DO is nonzero you branch back to the label LOOP and repeat
< program >. After exactly 52 loops DO will reach 0 , and the BNE will not
branch. You therefore exit the loop and carry on with < rest of program > . The
SUBQ.L is a new but obvious instruction:
SUBQ . z

I<data>,<destination operand>

which \AJOrks just like ADOQ, except that you subtract the immediate source
data (unsigned values 1 - 8) from the destination, then place the difference in
the destination. The z data size code has the usual effect on the operation SUBQ.L will subtract from all 32 bits, SUBQ.W from the I"""" IMOfd only, and
SUBQ.B from the I"""" byte only of the destination operand. There are more
general forms of SUB corresponding to ADD and ADDI:

SUB. z
SUBI. z

<source operand>,<destination operand>

I<data>.<destination operand>

All the SUB variants alter the CCR as for the ADD variants:
CCR flag
SUB

~C

so you can check for zero, negative, and overflOVJ in the usual W;:Jy. The C
(Carry) flag really indicates boJTOll...V rather than carry, but the function of the
flag is the same. Has the unsigned arithmetic gone wrong? For example:
MOVEQ . L

10, 06

SUBQ . L

11,06

116

68000, 68010, and 68020 Primer

\!.WId leave the CCR as follows:

CCR flag

X
1

since D6 now holds $FFFFFFFF

z
o

N
1
~

C
1

-1 (signed) which is correct (no overflow)

but incorrect for unsigned arithmetic (C

= X = 1).

IMMEDIATE ADDRESSING MODE - SUMMARY

Immediate mode is neat and fast for fixed soorce values. There are op code
variants for QUick # < data> small enough to fit inside the instruction ; and there
are Immediate versions for larger values of # < data > which need one or tv.u
extension v.urds following the instruction (at memory addresses PC + 2 and

PC+4).
VJe next look at addressing modes that allow you to access data anywhere
in memory, not just in the instruction v.urd or extension.

ABSOLUTE ADDRESSING MODES

Of course, immediate addressing mode is limited to those situations where the
source operand values are fixed and known at the time you write the instruction.
In most cases, hovJever, operands are variables located in memory (via a
keyboard input or a disk file access). The simplest situation arises when you
happen to know the actual physical memory address, also referred to as the
absolute address, of the data you want to manipulate. l et us reu.ork Program
4-1 assuming that your initial values are in memory, rather than in data registers.
As in Chapter 3 , you use $ for hexadedmal numbers.

PRACTICAL APPliCATION

_Ie """""'"

1'robIfm,
ustng
$6008.

Calculalethe new toIaI haun - - . . YTD (Januory Ihrough MaJeh)

operands. Put the updoIed toIaIln the longwanIat_

Gw.n:

1. Total haun YTD (JanuaJy through February) -.d In the

$6000.

1ongwanI., _

M68000 Instruction Set -

2. Houn_In _ _ InIhe~at

First Steps

117

$6004.

SOmpIrC-:
I-bn VTD .. 320 at adI'. $6000
Houn - . - 138 01 addJ_ $6004
New hours YTD - 458 at addJ_ $6008
_ : , . " . , _ 4-S
IDYE.L

$6000,03

03

ADDL

$&004,03

D3

MOVE_L

03.$8008

=hrs Ym
= bra YTD + Hrs

March

Save D3 in -.ory at address

$&008
.Address $6008 now bolds Ute m. 1$80001 + 1$60041 ~ 458

Note the use of brackets to indicate the value stored at a given address.
Thus at address $6000 we have the value ($6000) ~ 320. In the next section
\.\Ie will elaborate on this notation and explain in detail hClV.l addresses can access
longv..ords, VJOrds, or bytes in memory.
Absolute addressing mode simply means using the actual address as source
or destination - it must not be confused with immediate mode. Compare the
fOllowing:
MOVE .L

1$6000, 03

MOVE . L

$6000, 03

and

The little symbol # for immediate data makes a dramatic difference. The first
line says: replace the contents of D3 with the number $6000. The second line
says: replace the contents of D3 with the number found in memory at address

$6000.
ABSOLUTE ADDRESS - SHORT AND LONG
VERSIONS
The absolute address you supply in your source or destination operand can be
stored in one or tv..o extension \.VOrds following the instruction VJOrd, knClV.ln as
the short and long versions of the absolute addressing mode, In the long version
your absolute address is a full 32-bit number stored in tv..o 16-bit extension

118

68000, 68010, and 68020 Primer

IJJOrds, and therefore allows access to the entire address space of the M68()(Xl
The price paid for this is that the processor needs to fetch tv.o extension v..ords
from memory and then combine them into one 32-bit address before it can
access yoor operand. To save time when yoo do not want to access the full
address space, the short 16-bit mode can be used. In this mode the processor
sign bit extends the single extension IJJOrd to form a 32-bit address - and this
is much faster than fetching a second v..ord from memory. The short mode gives
!Pl access to addresses in the ranges $000000 through $OO7FFF (the lower
32K of memory) and $FF8000 through $FFFFFF (the top 32K of memory) ,
depending on whether the sign bit is or 1. (When we talk about the sign bit
of an address, of course, we are not implying that we can have negative
addresses - all absolute addresses are positive numbers. The sign bit here
means bit number 15 in the v..ord address, which happens to be 1 for addresses
gteater than $7FFF)
Assemblers differ widely in the way they handle the short and long versions.
Some will automatically create the optimum mode for yoo (our $6000, for
example, \.VOUld be assembled as short), while others require a letter code L
(long) or W (short - that is, one extension IJJOrd) after the address.

LABELS AS ABSOLUTE ADDR ESSES

So far we have used labels with branching instructions, and we explained briefly
that when your program has been assembled and loaded each label symbol is
effectively translated into the unique address of the instruction yoo want to
branch to. From a novice programmer's point of view it is suffident to think of
labels simply as addresses, and. as such they can be used as mnemonics not
only for branching but as absolute address operands. The obvious advantage
is legibility and ease of programming. To see this, let's dress up Program 4-5
as follows:

Program 4-5A: Use of Labels as Absolute Addresses

Data as in program 4-5 with following labels
HRSYTD = address $6000 holding 320 hours
HRSMAR : address $6004 holding 138 hours
NEWHRS : address $6008 : destinati on for sum
ADD. L

HRSYTD.03
HRSMAR , 03

MOVE . L

03 , ~U1ffiS

MOVE . L

03 : {HRSYID)
03 = {HRSYTD) t (HRSMAR)

Save 03 in memory at address

NEIOiRS

M68000 Instruction Sel -

F;rsl Steps

119

Address ~~ = $6008 , now holds the sum ($6000) + ($6004 ) = 458.

Note, agai n, t he use of brackets t o indi cat e the contents of an
address . HRSYTO:$6000 but (HRSYTD) =320.
There is no doubt that version 4--5A is more immediately understandable
than version 4--5 (dare I.Ve say, a liille nearer to BAS IC) , and this helps the
writing, modifying, and debugging of code. It is no exaggeration to say that you

will hardly ever see lines like:

MOVE .L

$6000, 03

other than in classroom exercises. Of course you have to tell the system what

the labels HRSYTD, HRSMAR, and NEWHRS mean, and for this you need
some help from the assembler. Once you have " assigned" addresses to these
labels, you can program in terms of HRSYTD and so on, rather than taxing
your human memory with meaningless hexadecimal numbers. The allocation
of addresses to data fields is almost as simple as labeling instruction lines for a
branch.

ASSEMBLER DIRECTIVES
To tell the assembler what you have in mind, you need a few assembler
directives, sometimes known as pseudo-op codes because, at first sight, they
look like M68CKXl instructions. Directives, ho.vever, merely direct and control the
assembly process, and unlike " real" instructions they do not generate machinelanguage code. Modern assemblers have hundreds of different directives with
many nonstandard variations, most of which are outside the scope of this primer.
Fortunately, you need only three or four directives to make sense of the
addressing modes, and we'll present them briefly using standard Motorola
"vanilla" syntax. Once we have covered these, we will be able to fill out Program
4--SA so that HRSYTD actually represents the address we have in mind.

ORG - THE ABSOLUTE ORIGIN DIRECTIVE

The follOVJing line
ORG

<address>

Load program at <address>

simply tells the assemblerlloader that you want the next program lines to be
assembled and eventually loaded starting at the Specified absolute address. For

120

68000, 680 10, and 68020 Primer

your immediate purposes you will need just one ORG directive at the very start
of a program:
Prograll starts at address $6000

ORG $6000

Thereafter, each line of S<X1JCe will be translated into machine instructions, some
taking one VvOrd, some five, with each being allocated appropriate v..ord addresses as the assembler increments its location counter - a simple counter
that "starts" at $6000 and increments one or five or whatever the instruction
takes. When it meets a label, presto, UJe krlO'l.V (or rather the assembler knows)
the label address. You saw earlier hO\.V branch labels INOI'k, nOVJ you can look at
data labels, and the tv.o directives used to define them.
DATA AREAS IN MEMORY USING OS AND DC

There are tv.o basic directives, DS and DC, that allOVJ you to allocate labels to
data areas in memory:
LABEL

os. z

<number> Def ine Storage

LABEL

DC.z

<dat a>

Define Constant

os

just reserves the < number> of memory locations (z =- L, W, or B) at

address = label, whereas DC will allocate whatever memory is needed (starting
from address = label) and store the < data > yoo list in the right-hand column.
DATA STORAGE - EXAMPLES
DS.L

Def i ne st orage: 1 longword at NEWHRS

simply reserves 1 "empty" longword for data storage at memory location

NEWHRS, which is exactly what we need for program 4.SA. The following
lines would achieve exactly the same result:
NEWHRS

os. W

Def i ne st orage: 2 words at NEWHRS

NEWHRS

OS. B

Def ine st orage: 4 bytes at NEWHRS

M68000 Instruction Sel- Firsl Steps

121

The \.VOTds buffer or data buffer are often used to describe areas of memory
assigned with a DS for future holding of information. YCXl will often find. for
example, the line:
DSKBUF

512

OS . S

Allocate disk buffer 512 bytes

or a similar line, to define a general area into which a whole disk block can be
loaded and then scrutinized.
You can, in fact, use OS to reserve any number of lonQ\OOrds, IMJrds, or
bytes, provided you are careful to avoid odd-numbered addresses for longwords
or words. For example:

LABEll
LABEL2

DS.B
DS.L

5
2

Allocate 5 bytes starting at labell

Whoops! If labell is even then label2 is Odd
address! Cannot reserve 2 lonQ\OOrds starting at
odd address.

The lesson here is that as the assembler reserves the memory space requested, its location counter is incremented past the assigned area, so the address
it assigns to a subsequent label is incremented accordingly. Hence it \o\rOUld try
to give label2 the value {Iabell + 5 bytes} which may or may not be legal. A
DS.B at labe12 """Id be fine (byte addresses can be odd or evenl. but a DS.L
or OS.W could invoke an address error:.
Assuming you have not broken the odd/even rules, the absolute address
assigned to a DS label will naturally depend on two factors: ORG - the starting
address of the program, and the location of the label within the program.
Before we illustrate this with a program, let's look at the other data labeling
directive, DC, in more detail.

DATA CONSTANT -

EXAMPLES

Data Constant (DC) syntax is slightly different, but the difference is of galactic
importance:

HRSYTD

DC. L

320

Define constant

320 at HRSYTD

does not allocate 320 lonQ\OOrds of memory.

The 320 represents a single field of < data > and you will end up with one
\on9lMJrd (because of the DC. L) containing the binary equivalent of decimal
320 at whatever address the assembler assigns to HRSYTD. You can use DC
to store any amount of data. Lists of related data items stored consecutively are

122

68000,68010, and 68020 Primer

often called tables, just like the log and trig tables at the end of old-fashioned

textbooks.
TABLE

,
,
,
,

Byte
Byte
Byte
Byte

SlO.S2A,$F4,$09 set up 4 byte constant s at TABLE

DC . S

address
address
address
address

TABLE
TABLE+1
TABLE+2
TABLE+3

now contains
now contains
now contains
now contains

$10
$2A
$F4
$09

The general fonnat is:

<data> ,<data>, ....

LABL

oC.z allocates sufficient area to hold the < data >, < data > '''. you have listed,
thereby overwriting any previous data at labeL The < data > can be expressed
in many useful ways - binary, decimal, hex, or ASCII.
It is \.IJOrth stressing again, at this point, that ORG, OS, and DC are pseodoops, not M68000 instructions. They are not translated into machine-level. instruction \.IJOrds like MOVE or ADD. They do, hOVJeVer, affect the location of the
program , the way you write your program, and the values you IM:IUld find if you
looked inside the instruction extension words after assembly and loading.
Moreover, pseudo-ops and directives have been an essential ingredient of
assemblers for many years, and this exerts considerable influence on all microprocessor designers when they come to decide the type and fonnat of the chip 's
instruction set.

DATA LABELS IN ACTION

We nOVJ update Program 4-5 once more to shOVJ our directives at IJJ()rk:
, Program 4-5B: Data Labels with OS , DC
, Program 4-5A revi sed
,
HRSYTD = address $6000 holding 320 hours
HRSMAR = address $6004 holding 138 hours
,
,
NEWHRS = address $6008 = destinati on for sum

ORG
,
,
,

$6000

Star t at absolute $6000

Set up data areas

First label HRSYTD will be = address 56000
After st oring 32 bits there , next label, HRSMAR, will be ::
56004, and so on.

M6BOOO Instruction Set -

DC.L
DC.L
OS . L

320
138

First Steps

123

St ore 320 at HRSYTD

Store 138 at HRSMAR
Reserve 1 long\l'ord at
NEWlIRS

Rest of program as in 4-5A

MOVE. L

ADD. L
MOVE . L

HRSYTD,03
HRSMAR,03
03,NEWHRS

03 = (HRSYTD) : (S6000)
03 :::: (HRSYTD) + (HRSMAR)
Save 03 in memory at address
NEWHRS :::: $6008

Address NEWHRS : : $6008 . now holds t he sum ($6000 ) + ($6004 ) :::: 458.

In the above example we have used ORG to grab an area of memory,

starting at absolute address $6000, which holds not only our data but our

program too. The first MOVE.L instruction would be located at address {$600B
+ 4 bytes) ~ $6006 just after NEWHRS.
It is perfectly possible, and often preferable, to separate your data and
program in memory. The simplest way to achieve this is to use a second ORG
< address> directive to define the start of the program. Here is Program 4-5C
with one line added to show this.
Program 4-5C: Separate Data and Program Areas
Program 4-5B revi sed. Data as in 4-58
HRSYTD:::: address $6000 holding 320 hours

HRSMAR :::: address 56004 holding 138 hours

NE~~ z address $6008 = destination for sum
ORG

56000

DATA starts at absolute $6000

Set up data areas

First label HRSYTD will be = address $6000
After storing 32 bits there , next label , HRSMAR , will be
$6004, and so on.

HRSY11l

HRSMAR
NEWlIRS

DC.L
DC.L
DS . L

320

138
I

Store 320 at HRSYTD

Store 138 at HRSMAR
Reserve 1 10ng'o1o'ord at
NElIllRS

ORG

18000

PROGRAM starts at
absolute $8000

124

68000, 68010, and 68020 Primer

First instruction will be at $8000

Program and results same as 4-5B
MOVE . L
ADD. L

MOVE . L

Address

NKllrllRS =

HRSYTD, 03
HRSW.R, 03
03 , NE.1IliRS

03 = (HRSYTD) :: ($6000 )
03 = (HRSYTD) t (HRSMAR )
Save 03 in memory at address
NEWHRS = $6008

$6008, now holds the sum ($6000) + ($6004) = 458 .

The program still IJJOrks in its new location because when it references
HRSYTD and the other labels, it still picks up the data from the memory
addresses defined by ORG $6000 and our DC and OS data labels. HRSYTD
is defined as $6000 wherever VJ locate our program.
One immediate advantage of separate data and program areas is the
possibility of several users with different programs sharing a common data table
in a mutually agreed-upon portion of memory. In real installations you will find
endless variations on this theme of data and program location. The point here
is that you have considerable flexibility regarding where you put things.

ABSOLUTE ADDRESS - SUMMARY

Data in memory can be accessed (read) or stored (written) using absolute
addresses as source or destination operands. The absolute address can be
written explidtly as $6000 or $FFFFFF, or by means of a SUitably defined
symbolic label.
Absolute addressing, even with labe1s, is not flexible enough for most
applications. A more versatile way to access operands in memory is via the
address registers, as shovJn in the next section.

ADDRESS REGISTER INDIRECT MEMORY

ADDRESSING MODE
The main function of address registers, as you might guess from their name, is
to provide addresses for operands in memory. A useful concept in this connection
is the idea of a pointer. If address register A3, for example, contains the value
$3000, we say that A3 points to memory location $3000.
To distinguish the pointer A3 from the operand in memory being pointed
to, VJ use the following standard Motorola syntax: A3 is the pointer and (A3)
is the operand at address A3. The brackets in (A3) represent what VJe call
indirection . A3 is address register direct but (A3) is address register indirect

M68000 Instruction Set -

First Steps

125

In the " Memory Model" section of Chapter 3 you saw that the M68000
uses byte, word, and long\OOrd addresses - so what does A3 really point at?
If A3 contains an odd-numbered address such as $3001 , there is no ambiguity
- A3 must point at the byte at $3001 , but if A3 is even, like $3000, it is
pointing at three possible memory values. If 1.A.Ie 90 and look at this location \.\.Ie
might conceivably find the foiJo.ving values:
The byte at byte address A3 = $3000 is (A3) = $E2
The word at word address A3 = $3000 is (A3) = $E278
The longword at long\OOrd address A3 = $3000 is (A3) = $E278BOIC
The actual values shown are less important than how they are related. So before
'we can answer the question , "What is (A3)?" \.Ale have to kn()I..V the data size
involved - is it L, W, or B. For example:

MOVE . L (A3) ,07 moves $278BOIC to 07

MOVE . W (A3) ,07 moves $278 to lower word of 07
MOVE . B (A3) , 07 moves $2 to lower byte of 07
You can see that the source operand (A3) behaves very much like a data register
- the L, W, or B size code selects which parts of the operand are involved. The
important differences are: Land W operations on memory need even addresses.
B operations on memory can use odd or even addresses. Remember the L()I..V
Address-High Byte, High Address-low Byte rule (see Chapter 3).
Let us revamp Program 4-5 using address register indirect mode in place
of absolute address mode.

PRACTICAL APPlICATION
_."
U!ing _

Cola ..... tho .... toto1 hours...ned YlD (Jonuary through Man:h)
ml"DY _nels. Put tho updalOd toto1 In tho Iongword at address

$6008.

eMIt'

_In

I. ToIIII hours YlD (Jonuary through February) _

tn tho Iongword at address
$6000
2. IbIIS
Man:h _
In tho Iongword at address $6004

126

68000,68010, and 68020 Primer

Set addresses in address reciata'll

lIMA. L
lIMA. L
lIMA. L

_,AI
1S_,A2

IS600B,AS

ll .... _
AS .... _
AS .... _

of Y1Il

of bra IIIrcb
.. far ... Y1Il

Do calculation

IIJVE.L

IAII.03

AIlO. L

(A2), DS
DS, (AS)

IIJVE.L

os bre 'lTD
D3 bra Y'ft) + bre IIIrcb

Put OS in -.ory at address

AS MOOa

(All now contains the SIll fAa)

tAl) and fAa) are UDCbaaaed.

+ (Al) .e8.

MOVEA - MOVE ADDRESS

Program 4-6 introduces a new op code, MOJEA (lv1OVE Address) , which is a
version of MOVE used when the destination is an address register. The general
format is:
MOVEA . L

<SOUIce>,An

MOVA.W

<SOUIce>, An

or

M68000 addresses are essentially 32bit values (even if your MC6800X

uses only 20 bits or 24 bits for addressing) , so MOVEA.B is not allowed. Even
MOVEA.W tums out to be a 32bit move, because 16-bit addresses are always
sign-bit extended to 32 bits, as explained in Chapter 3. Also MCVEA, like all
operations on address registers does not affect the eCR, because you are not
concerned with O\.'et"flOVJ, carry, negatives, zeroes, or positives when you manipulate addresses.
You use MOVEA here with immediate source data to set up your three
address registers. Once you have the proper addresses in AI , A2, and A3, the
program uses (Al) and (A2) as source operands and (A3) as a destination

operand.

M68DOO Instruction Set -

First Steps

1 27

RESTRICTIONS ON ADD
You may wonder why \Ale used 03 in the above program. Why not save a line
(and a regisler) by having
MOVE . L (AI ), (A3 )
ADD. L (A2 ), (A3 1

OK

ILLEGAL

The first line is legal: it \.IJOUld move the contents of address $6CK)() to memory
address $6008. The second line, hovJever, is illegal because: ADD must have
at least one data register and SUB must have at least one data register: The
M68000 does nol allow ADD or SUB on Iloo memory operands. So you can
OK

ADD. Z Dn,Dm
SUB . z Dn,Dm

OK

ADD.Z An,Om
SUB . Z An , Om

OK for Z ; L, Wonly
OK f or Z = L. Wonly

ADO. ,

On , (All )
On , (Am )

OK

SUB . z

OK

ADO. ,

(All )

,on

OK

SUB . Z

(All ) , On

OK

ADO . '
SUB.,

("'), (An)

ADO . '

On , Am
On , Am

But yoo. cannot

SUB . z

(All ) , fAn)

is
is

The above rules forbid ADD and SUB with An as a destination - so how
can you increase or decrease an address in an address register? There is a way;
iI's called ADDA (ADD Address). Let's tackle Program 4-6 in a different way, to
show how ADDA works:
Program 46A : Alternative Solution to 4-6 Using ADDA

Set addresses in address registers

MOVEA . W 'S600a,AO

AO has address of YTD

MaVEA . W

Al also has address of YTD

AO , Al

128

68000,68010, and 68020 Primer

ADDA . W
MaYEA. W
ADDA . W
MOVEA . W

AO = $6000 + 4 = $6004
A2 has address of hrs Mar
AO = 56004 + 4 = $6008
A3 has address for new YTD

#4 ,AO
AO , A2
#4,AO
AO,A3

Do calculation--same as 4-6

MOVE.L

(A I I, 03

ADD. L

(Al ) , 03

MOVE . L

03, (A3 )

03 = Hrs YTD
03 = Hrs YTD + Hrs Mar
Put D3 in ~e~ory at address
$6008 = A3

So, to ADD something to an address register, we use ADDA (ADD Address),

just as \.\Ie use MOJEA to move something to an address register. The general
format is:
ADDA . L
ADDA . W

<source>,An
<source>, An

To subtract something from An

SUBA. L
SUBA. W

\.\Ie

have:

<source>, An
<source>, An

Note again the fundamental fact of M68<X>O life - no byte operations

allo.ved on An. Also, as with MCVEA, there are no CCR changes when we
manipulate addresses in An.
The key to Program 4-6A is the w;:J.j ADDA is used on the pointer AD. By
adding 4 to an even-valued address register ycJU make it point to the next
longv...ord in memory. Similarly, adding 2 or 1 to a pointer "moves" it to point
to the next v.ord or byte. Frequently ycJU find that the data ycJU are manipulating
are stored in memory in sequences or tables - so ADDA and SUBA are useful
in "setting" address register pointers to scan tables of data in either direction.
This type of operation is so common that the M68000 provides two spedal
variants of the (An) addressing mode to simplify the scanning of consecutive
addresses. The new modes a utomatically increase or decrease the pointer An .
We look first at the address register indirect with post-increment mode.

ADDRESS REGISTER INDIRECT WITH

POSTINCREMENT: (An) +
The address register indirect with post-increment mode, written (An) +, is best
explained with an example.

M68000 Instruction Set -

First Sleps

129

, Program 4-68: Alternative Solution to 4-6 using (An)t

Set address of first value in t able
MOVEA. W 1$6000, Al
Do

Al has address of hrs YTD

i . e. Al points to hrs YTD

calculation
MOVE . L

(AI )t, 03

ADO . L

(Al )t, 03

NOVE . L

03 , (AI )

set 03 = ($6000 ) = hrs YTD

then add 4 t o Al
Add ($6004 ) to 03
then add 4 t o Al
Put 03 in lIIemory at address
Al = $6008

Rather than using three address registers for the operands, this solution
uses just Al - and the post-increment advances Al to the next longword after
each operation. The a utomatic increment of Al saves using ADDA #4,AI , but
better still, it saves INOrry about the size of the increment.
(AI) + will increment Al by either 4 , 2, or 1, depending on the data size
code used in the op code. for example:
MOVE . II'

(A2 )+, D5

Se t word 05 = word (A2 )

then ADD 2 to A2

will conclude with A2 pointing to the next IOOfd (A2 + 2), and
MOVE. B

(A2 )t , 05

Set byte 05 D byte (A2 )

then ADD 1 to A2

ends up with A2 pointing to the next byte (A2 + I).

TEMPUS FUGIT - A TIME-OUT TO lOOK AT TIMINGS
Since v.oe've nOlN shOlNn you so many different ways to perfonn the same simple
hours YTD addition, it might prove useful to compare them briefly from a timing
standpoint. In our simple context we are not going to quibble over a few
microseconds here and there, but from the broader, practical perspective it Is
important to gain an insight as to what \IJe are asking the MC68000 to do.
(Note that in the following table, the S-bit data bus of the MC68008 would need
more cycles while the 32-bit data bus of the MC68020 would need fewer.)

Progrom 4.1

Register Direct:
Get data from registers-very fast-no memory access

needed. Store answer in register-very fast But how did

130

68000,68010, and 68020 Primer

the data get into the registers? And hOlN will we print the
anSVJef? Sooner or later we will need memory accesses.
Program 4.5
(+ variants)

Program 4 .6

Absolute Addressing:
Get address of data from extension VJOfd(s)-takes 1 or 2
memory reads. Then get data-takes 1 or 2 memory reads.
Get address to store answer-takes 1 or 2 memory reads.
Store longu.ord answer-takes 2 memory writes.

Indirect Addressing:
Set up 3 address registers with immediate data-takes 3 to
6 memory reads. Get addresses from An-very fast. Then
get data-takes 1 or 2 memory reads. Store answer-takes
2 memory writes.

Program 4.6A

Indirect Addressing Using ADDA:

Set up 1 address register with immediate data-takes 1 to
2 memory reads. ADDA immediate data twice-takes 2
memory reads. Get addresses from An-very fast. Then get
data-takes 1 or 2 memory reads. Store answer-takes 2
memory writes.

Progrom 4.68

Indirect Addressing with Post-Increment:

Set up 1 address register with immediate data-takes 1 to
2 memory reads. Get addresses from (An) + -fast. Then
get data-takes 1 or 2 memory reads. Store anSVJef-takes
2 memory writes.

So far, then, indirect with post-increment seems to offer the best overall
method - providing you can arrange your data in suitable sequential memory
locations. A typical situation where data naturally occupies successive addresses
is in v.ord processing where you have to handle long strings or sequences of
ASCII characters, each needing a byte of memory. The M68000 is often criticized for lacking explicit string handling instructions. Our next program refutes
this criticism.
STRING MANIPULATION USING (An) +
Here is a po.veriul example of (An) + in action. The problem will be familiar to
all readers who have ever moved or copied a block of text while INOrd processing.

M68000 Ins!rue!ion Sel -

Firsl Steps

131

program 4-7 : Copy a String of Characters from One Memory

Location to Another
Al points to first ASCII character of a block of text in
mellory .
Assume that the last character in a string is ASCII NULL (0).
We want to copy the block of text excluding the final NULL to
another part of memory starting at address A2 . Any old data at
A2 can be overwritten.
A2 is larger than <AI + length of string>!
If the string at Al is empty (that is , starts with NULL) don ' t
bother to move it !

LOOP

PINt

TST . B

(AI)

BeQ
MOVE . B

PINI
(AlI+, (A2 ) +

BRA

LOOP

Have we reached a NULL~

Test byte at address Al = O~
If yes exit to PINI
Move byte at Al to byte at A2
Then increase Al and A2 by 1 to
point to next byte in memory
Back to LOOP to test next
byte.

<rest of program>

WARNING_remember that Al and A2 have changed unless first (AI )

was NUlJ...
You can see how (AI) + as byte source and (A2) + as byte destination
neatly advance each pointer (the "sending" pointer Al and the "receiving"
pointer A2) through each character of the string. Without a test for the end of
the string, MOIIE.B (AI) + ,(A2) + """Id continue right through all available
memory, with strange results! So the simple little TST. B introduced above has
saved wiping out all the data in RAM.

TST.z

operand

tests the z = L, W, or B of the operand and sets the Nand Z flags in the CCR
depending on whether the operand is negative or zero. The N flag happens to
be irrelevant in this particular example. So,
TST . B

(AI )

"asks" the question: Is the Byte in memory at address Al = O? If yes the Z

flag is set - 1; if no the Z flag is cleared to O. The M68000 has no knOVJ\edge

132

68000, 68010, and 68020 Primer

or interest in ASCII codes as such - it is entirely our problem hOVJ I.I.Ie interpret
the 8 bits in each byte of our string.
Our TST.B IM)rks on the assumption that the string ends with an ASCII
NULL character which equals binary (X)()(X)()(X) (sometimes called blank and
not to be confused with ASCII "space" which equals OOl()()(x)() or with ASCII
"zero" which equals 001100(0). All of which is to remind the beginner that
NULL is an ASCII character like the rest and takes up a byte of your predous
memory. It just happens to look like a 0 to the TST. B instruction.
The BEQ after TST.B checks the CCR and branches to FIN I only il the Z
flag is I, that is, only il the byte (A I ) is NULL.
Notice that VJe TSTB right at the beginning of the loop. If the first (A I )
byte of our string VJeTe NULL we \A.IOUld branch to FINI right away without
moving anything. Zen programmers enjooy pondering the question whether an
empty string, that is, one which starts (and therefore also ends) with a NULL is
VJOrth copying. You should certainly distinguish between an empty string and
no stri ng at all. Program 4 -7 will just ignore an empty string - since \IJe branch
out be/ore copying NULL. It is not difficult to rewrite 4-7 so that the NULL in
(AI ) """Id copy to (AZ). In many walks of life such nitpicking """Id be
condemned as outlandishly metaphysical, but in computer programming, alas,
such details can be vital. A good reason for not copying NULL to (A2) might
be that you want to append more text at the end of the copy string or, for the
sake of a longer, more impressive !J.()I'd, to concatenate it with something. If
you inSist on an exact copy of a non-empty string including the final NULL,
here is Progra m 4-8:

Program 4-8: Copy a String of Characters from One Memory

Locati on t o Another

Al points t o first ASCII character of a block of text in

memory.
Assume that the last character in a string is ASCI I NULL JO I.
W
e want to copy the block of text includi ng the final NULL t o
another part of memory starting at address A2 . Any old data at
A2 can be overwritten .
A2 is greater than <AI + length of string>.
If the string at Al is empty (that i s starts with NULL) don't
bother to move it !

LOOP

TST . 8

(AI )

BEQ

~INI

MOVE . B

(AI )+, (A2)+

Is first byte NULL?

If yes exit t o ~INI
because string is empty.
Move byte at Al to byte at A2
then increase Al and A2 by 1 to
point to next byte in me~ory

M68000 Instruction Sel - FirSI Steps

BNE

fINI

LOOP

133

If byte moved is not NULL (:O)

there 's more to copy.

<rest of program>

Remember that Al and A2 may change.

(An)+ MODE SUMMARY

The (An ) + mode as either source or destination or both, is the most effident
way of manipulating successive low-to-high memory locations. You set An to
point at the starting location, and having chosen the data size of the operation
(L , W, or B) you can trust the M68000 to increment the pointer correctly.
We promised you t'Ml ways of scanning consecutive addresses, so having
seen (An) + going forward through memory, IJJe present the converse mode,
-(An) , for accessing memory backwards.

ADDRESS REGISTER INDIRECT WITH

PRE-DECREMENT: -(An)
Closely related to the (An) + mode is the Address Register Indirect Pre-Decrement Mode, written -(An). The pointer An is reduced or decremented by 4 , 2 ,
or 1 before the operation takes place. As with (An) + the change in pointer
value is determined by the data size code used in the instruction. A simple
example:

AS contains $8008 when we star t

CLR. L
- (AS ) would reduce AS by 4. then clear longword ($8004)
but

CUR. W

- (AS)

would reduce AS by 2, then clear word (S8006)

CUR.S

- (AS ) would reduce AS by 1, then clear byte ($8007 )

and

Using -(An) you can scan data tables from end to beginning (which is
sometimes quicker), providing you remember to set the address register pointer
pointing just beyond the end of the table to allO\.V for the pre-decrement (An) +
and -(An) work nicely together, when you think about it! (An) + leaves your
pointer in the correct position, after a fOtward scan , one place bey:>nd the end

134

68000,68010, and 68020 Primer

- ready for a reverse scan using -(An). This idea is used in IM:lrd processors,
such as INordStar, that allow a forward or backward search of your document
for a matching string.
-{An) MODE -

SUMMARY

The -(An) mode as either source or destination or both, is the most effident
w~ of manipulating successive high-to-IQI.\I memory locations. You set An to
point just beyond the higher location, and after you have chosen the data size
of the operation (l , W, or B), the M68000 will decrement the Pointer correctly
before each operation.

CONCLUSION

We conclude this chapter with a brief overview of the addressing modes we

have covered. In Chapter 5, we will discuss more advanced uses of these modes,
and introduce fresh modes and instructions.

Mode Description:
On
An
(An)
(An) +
-(An)
Im med
AbsW

Abs.L

Data register direct

}
Address register direct Jointly called register dlrecl
Address register indirect
Address register indirect with post-increment
Address register indirect with pre-decrement
Immediate data operaTXI-also written as #(data)
Absolute short address (16-bit, sign-extended)-also written
xxx{W) or label
Absolute long address (32-bit}-also written xxx{ .L} or label

5
M68000 Instruction SetAdvanced Topics

In this chapter IJJe build upon the basic instructions and modes covered in
Chapter 4. OUf fi"t topic deals with what is generally described as housekeeping
- a word used to describe a wide variety of situations faced by the programmer:

keeping track of where things are in memory, saving and restoring register values,
and so on. This subject provides a real and practical reason for many of the

M68000 instructions and features.

PRESERVING REGISTER VALUES WHY AND HOW

With the (An), (An) + and -(An) modes you face a problem that crops up in
many disguises, especially as your programs get longer a nd you start "using
up" your registers. Although the M68000 is more generous than most in providing 16 versatile registers, you can easily reach a position in a program when
they are all " assigned". In other IAoQrds, you may be holding 8 important
intermediate results in 00 through 07. and each of the normal address registers
AO through A6 may hold pointers you don't want to lose.
Suppose you now embark on a string copy using
MOVE. B (1.3 ) + , (1.0)+

135

136

68000, 68010, and 68020 Primer

for example. Obviously, as you saw in Chapter 4, you "lose" the initial values
of A3 and AO, since they end up pointing at an address that depends on the
length of the string - which is often unpredictable. Obviously you can " save"
A3 and AO by writing their values to memory before the string copy, then
"restoring" them afterwards, as in:
Program 5-1

We want to copy string (A3 ) -> (AD) without losing pointer

values in A3 and AD .
Save A3

MOVE . L
MOVE . L

A3, $4004
AO , $4000

MOVEA . L
MOVEA . L

$4000 , '\0

Restore AO

$4004 , A3

Restore A3

Save AD
<Copy string

(A3 )

->

(AO) >

The same "trick" can be used to save and restore On values. It certainly
achieves the desired goal, but there are obvious snags. First, it can become
messy and error prone in a complex program (where did I put A3 and 07 ... ?).
Second, there is a risk that a saved value might be inadvertently overwritten
during some convoluted branching. Third, if you are sometimes saving bytes.
sometimes saving words, and sometimes saving longwords, you have to pay
attention to the odd/even address restrictions.
The M68000 provides _ methods to simplify the saving and restoring of
register values: the MCNEM instruction and the user stack.

MOVEM - MOVE MULTIPLE REGISTERS

MOJEM is a special version of MCNE offertng a fast and economical way of

saving any number of register values into consecutive memory locations, and
then restoring them later as needed.
To save registers in memory the format is:

MOVEM . Z

<register list>,<destination>

To restore registers from memory the format is:

MDVEM. Z

<source>, <register list>

Note that Z can equal L or W only, so MOVEM. B is illegal.

M6BOOO Instruction Sel -

Advanced Topics

137

The < register list> can specify up to 16 different registers IDO through 07,
AO through A7 ) for saving or restoring, while the destination and source specify
the starting memory location. M<NEM.L transfers a1132 bits, while M<NEM.W
transfers only the Io.ver word with some judicious sign-bit extensions when you
restore. Program 5-1 could be written:
, Prograa 5-1A MOVE: Saving/ Restoring Multiple Registers
, at Absolute Addresses
We want to move a string without losing pointer values AO , A3 .
MDVEM . L

AO / A3 , S4000

MDVEM . L

$4000,AO / A3

Save AO and A3 at $4000

and $4004
<Copy string (A3 ) -> (AO
Restore AO and A3 from
$4000 and $4004

Note ho\.v the < register list> is set up with a slash (I) between each register. To

save consecutive registers you can list them as:

MDVEU.L

OO-D5 /A4-AS ,$SOOO

which I.I.OUld save 9 registers, the 6 data registers DO through 05 and the 3
address registers A4 through A6. The 9 register values I.I.OUld be stored in 9
lon9'A<JTds at memory locations $6000 through $6020. You I.I.OUId restore them
all with:
MOVEM . L

$SOOO , DO-D5/ A4-AS

You have been saving your registers at absolute memory locations, but you
can also save them by specifying a pointer (always providing you have a spare
An) using the -IAn) pre-decrement mode, in which case you must restore by
using the (An) + post-increment mode in the source operand. Again , you will
notice hovJ these two modes complement each other. Program 5-18 shows this
variant:

Program 5-18 MOVEM--Saving/Restoring Multiple Registers

Using Address Indirects - (An) and (An )+

We want to DOve a stri ng without losing pointer values AO , A3 .

AS points to the last used address in our saving area in
lIIemory.
Assume AS = $4008.

138

68000, 680 /0, and 68020 Primer

MOVEM. L , AO. /A3,-(A5)

Reduce AS by 4. Save A3 first at $4004. Reduce AS again by 4.
Then save AO at $4000. AS now = $4000.
Note that WOVEM conveniently reverses the saving order for you!
<copy string (A31 -> (AO
MOVEM. L

{AS)+, AO/A3

Restore AO first from $4000. Increment AS by 4 then restore A3

from $4004 . Increment AS by 4. AS i s again : $4008 .
The MOJEM with -(An) and (An) + is very flexible. As you will see in the
next section, it is very similar to the stack concept.

STACKS
The stack solution to saving and restoring registers requires a brief preamble on
stack jargon and mystique.
As shown in Figures 5-1 and 5-2, the address register A7 is deSignated as
the USP (User Stack Pointer) and its job is to point to a special area of memory
called the user stack. This stack "grov.rs" downwards from a stack base address,
from high to low memory as you save data, and "shrinks" upwards, back
towards the stack base, from low to high memory as you restore.
It helps to stand on your head during this paragraph. Which recalls the
famous box that arrived from Dublin, Ireland, with the following inscription:
"This box must always be kept upside-down. To avoid any confusion the bottom
has been marked 'Top.'"
The preferred term for saving is pushing data on the stack; you restore by
pulling or popping data from the stack. Stacks are LIFO (Last In Fi"t Out)
devices because when you pull off a stack you restore the most recently saved
data. In contrast, a queue is a FIFO (First In First Out) device.
There is never any doubt about where you are saving stuff on the user
stack. A7 always points to the last item saved, which is also the first candidate
to be restored.
The sequence for pushing 01 , say, on the stack is:

MOVE . L

Dl , - (A1 )

Save Dian stack

Pre-decrement of A7 (by 4 because of the L) means movi ng the

stack poi nter down in memory. (Down is the direction of stack
, growt h.)

M6BOOO Instruction Set- Advanced Topics

Stick

USP
01

A924
31

FB a1
1615

~
a

Befpre
Push D1 word on user stack
MOVE.W D1 ,-(SP)
Decrement SP by 2 before MDVE.W

Base o f - - 4 ; - - - - - - - - f .
stack

USPA7~~
I~F80' P

01

31

1615

Base of
slack

Push D1 word

Fig. 51

User Stack Operation: Pushing

Then save 01 at the new address in A7.

points at item just saved.

Stack pointer therefore

Pulling D1 from the stack involves:

MOVE . L

(A7 )t,01

Restore 01 from stack

Previous 01 value is stored at A7 , so move (A7 ) to 01 , then

, post increment A7 by 4 to shrink the stack. A7 now points at
the data (if any ) that was pushed before 01 .

139

140

68000, 68010, and 68020 Primer

St a c k

""!!'!!!'_.. po inter

USP
D1

A7~iiii~:;~~~~~-,~==~~~~~~
I;
F
5F23

31

OA24

1615

Before
Pu ll 01 word from STACK

MOVE.w (SP)+. D1
increment SP by 2 after MOVE. W
Base of

slack

Sta c k

usp

D1

A7~iiii~~ii~~
~
i
F
5F23

31

F801

1615

Base

Pull 01word

stack

Fig. 5-2

o,.-4t:--------r.

User Stack Operation: Pulling

Standard syntax aUows you to use the mnemonic SP (Stack Pointer) in place
ofA7:
MDVE . L
MOVE . L

Dl , - (SP)
(SP)+, Dl

Save 01 on

MO VEM AND THE STACK

You can use MCNEM to save multiple registers on a stack:

MOVEM. L

stack

Restore 01 from stack

DO -D3 / AO -A6 , - (SPj

M68000 Instruction Set -

Advanced Topics

141

will push 11 register values and

MOVEM. L

(SP) t, DO-03 /AO-A6

will pop them all back.

MOIIEM, however, saves only registers (L or W) , whereas with MOllE you
can also push memory data on the stack, including bytes.
PUSHING BYTES ON THE STACK

When you push a byte on the stack with, for example:

MOVE . B

02 , - (SP )

Save lower byte of 02 on

stack

the M68000 has a nice built-in trick to spare you the embarrassment of hitting
odd-numbered memory boundaries if you subsequently wanted to push a \.IK)d
or longword. Rgure 5-3 shO\AlS how this trick 1ArOrks.
Normally, the MOVE.B pre-decrements and post-increments An by 1, but
with SP ( = A7) the processor adjusts the pointer by 2 to preserve evennumbered addresses. All stack data, then , is aligned on v.ad boondaries. When
you push a byte, in fact, it goes into the upper half of the stack 1ArOrd, and the
\QtI..I.IeT half is "wasted."
Having seen the stack invoked explidtly by MOVEs and SPs in the program,
you will next see a situation where the M68()(X) makes use of the stack under
its own steam, as it were, without a spedfic MOVE being required. Rrst you
need to understand the general concept of a subroutine.
SUBROUTINE -

BRIEF DEFINITION

A subroutine is a specially constructed piece of program which can be called

into operation from anyv.'here in the main program, and having performed its
duty, will return control back to the place in the program that called it. Subroutines have identifying labels and calling a subroutine is rather like branching.
Unlike the Bec, which just branches you eJsewhere, calling a subroutine requires
a mechanism for remembering the line that called it, so that when the subroutine
has concluded, the system knows where to resume.
Subroutines are vital in reducing the amount of code you need to write
and debug. Almost any sequence of instructions that you find used several times
in a program can be usefully made into one subroutine, and then called as
often as you like from any line in your program. Let's see how subroutines are

142

68000, 680 10, and 68020 Primer

SP A7
02

~~~~20~0~2J.; ~'~'~~~~~~
i

~ F01A
31

5A23

1615

Before Push

Base of
stack

MOVE. B D2,-(SP)

High part of
word gets byte

m2 ~

SP A7
02

F 01A

31

5A 23

",.$2000

A2

93

1615

Buem.-tr-------t------lr.

Alter Push

stack

Fig. 53 Byte Operations on Stack

called, and how the stack is invoked automatically by the M68000 to ensure
that the return address is saved.

BSR - BRANCH SUBROU TINE

Subroutines are called with a BSR instruction. The format for BSR is the same
as Bee:

BSR

<label >

Branch to SubRout ine at

<label >

M6BOOO Instruction Set -

Advanced Topics

143

At the line < label > VJe would find our subroutine, coded just like any other
piece of program, but always concluded with an RTS, ReTurn from Subroutine.
Here, step by step, is the sequence of operations BSH biggers:
1. Calculates the address of the next instruction and pushes this address on the
user stack.
2. Branches (unconditionally like BRA) to the instruction labeled < label > by
setting the PC to the < label> address.
3. The subroutine instructions at < label > are then obeyed sequentially until
the HTS is encountered.
4. The PC is then loaded by puUing from the stack the address we saved there
in step 1 above. In effect the processor internally perfonns a MOVE. L
(A7)+ ,PC.
5. The processor takes its next instruction from the address in PC, SO control
passes back to the instruction follCl'oNing the BSR Instruction.

The BSR, < label > , and RTS trio have combined to perform the neat trick
referred to, namely calling a subroutine. The chosen label should be, as
usual, mnemonic, since VJe will usually talk about calling the "label" subroutine.
A subroutine saves programming effort and reduces the length of a program,
thereby conse1Ving memory.
Neither BSR nor RTS affect the CCR condition flags directly, although the
instructions in the subroutine itself will almost certainly change and make use
of the eCR. Let's see BSH in action:
\oV

Program 5-2 Calling a Subroutine called ACCUN

Program to add some numbers that are in memory
01 wil l be used as an accumulator.
Subroutine ACCUM adds DO to 01 .
START

MAIN

CLR . L

01

clear accumulator 01
-Do other things

Set DO from memory address Al

Call ACCUM subroutine
Set DO from address A2
MOVE . L
Call ACCUM again
OSO
<print grand total in 01>
<conclude>
MOVE . L

(Al) , OO

OSO

ACCUlI
(A2 ) ,DO
ACCUlI

, Subrouti ne section starts here .

ACCUlI

ADD.L
RTS

OO,Dl

This is a one line subroutine

called ACClIM

144

68000, 68010, and 68020 Primer

ACCUM input
output

= l ongword DO which is unchanged

= longword Dl = Dl + DO

<possibl y more subrout i nes follow here>

Usually, of course, subroutines are 10nger and more useful than this ex
ample. ~, it does illustrate the basic principles of subroutine calling.
Subroutines -

Input and Output Parameters

You usually set up particular values using MOVE just prior to the BSR. Each
subroutine will have its QI.VTl set of required inputs or parameters. ACCUM has
just one input, the value of DO, and one output, the total in 01. To maximize
the usefulness of subroutines, these parameters and how they are affected should
be well commented and documented. Subroutines are often designed as general
purpose programs or utilities. Once they are thoroughly tested they can be
added to a library of subroutines accessible to everyone using the system. Many
assemblers allow such library files to be scanned during assembly; any subrou
tines referenced in the main program can be automatically copied into your
program. TIle motivation is " never reinvent a perfectly good wheel." Once you
understand the function of a particular subroutine you learn to treat it almost
like a single instruction without being bogged down by the inner details.
Subroutine Side Effects on Registers
A I.YE!lI-designed subroutine for general use must guard against unwanted side
effects. A complex subroutine may make use of many registers and, unless steps
are taken, their orignal values could be lost to the calling program. The user
stack turns out to be an excellent place to save and restore such values, in spite
of the fact that BSR and RTS both use the stack to save and restore the
subroutine return address (steps 1 and 4 above). The stack UFO philosophy
handles any number of pushes and pulls - provided your pulls and pushes are
sequenced correctly. Here's a program using the user stack during a subroutine:

Program 5-3 Subroutine CLRMEM

AO points t o an area of memory whi ch we want t o CLeaR.
DO contains the number of words to be cleared.
Subroutine CLRMEM must not alter AO and DO .
llAIN

<do things>
BS.

CLRIIE!I

return address
then ca l l CLRMEM

Push

M68000 Insuuction Set -

Advanced Topics

145

<back here after subroutine> AD and DO unchanged

Stack back to original

state
Subroutines start here
CLRMEN
MOVE . L
DO , - (SP)
Push DO to save
Push AO to save
MOVE . L
AO , - (SP)
Clear (AO ), inc AO by 2
MLOOP
CUR.W
(AO)+
Decrement counter
SUBQ. L
",00
If counter 0 exit MLOOP
BNE
MLOOP
(SP)+,AO
Pull
AO to restore
MOVE . L
(SP)+, DO
Pull DO to restore
MOVE . L
Pull return address
RTS
<more subrouti nes here possibly>

The pulls from the stack (implidt and explidt) reverse the sequence of the
pushes, leaving the stack in the state it was in before the BSR.
Subroutine Side Effects on the CCR

It is almost certain that the flags in the CCR will change during a subroutine
and this could be a nuisance to the mainstream program. Quite often you will
test a result and call one of three different subroutines depending on a result of
zero, positive, or negative. When you return you may want to test again using
the original CCR flags.

CONTEXT
Also, as you've seen, you may want to call the same subroutine under many
different conditions, and a subroutine that changes the context of the main
calling program reduces our flexibi lity and leads to errors that can prove difficult
to diagnose.
Many other user and systems events can temporarily interrupt your program
to do other things - so the general concept of " preserving the context" is
fundamental to all modem computer operations.
Context simply means a list of all those registers and processor states
(including the current PC) which \Ale need to save somewhere so that when the
time comes to resume our program (after a subroutine or interrupt or whatever)
the entire status quo of our job can be restored. A very high proportion of all
software bugs can be traced to the side effects of poor context handling. The
M68000 instruction set, therefore, has many instructions (tvtOJEM is one good
example) to simplify this problem. Depending on the situation, the saving of the

146

68000, 680/0, and 68020 Primer

context may either be the programmer's responsibility or it may be a task

assigned to the operating system or the hardware.
Later \AJe will see how the M68000 maintains an independent supervisor
stack using the SSP (Supervisor Stack Pointer) accessible only in supervisor
mode. The latter is a privileged mode intended to protect vital systems contexts
held in the supervisor stack.

SAVIN G THE CCR

For user-supplied subroutines you can use the user stack to save the CCR flags
rather as you did to preserve normal register values. Pushing the CCR on the
user slack, however, differs between the MC68000 and the MC68010/68020
(for reasons \Ne'll discuss in Chapter 7). The MC68000 has to use:
MOVE . W SR, - (SP)

Push SR on stack

So, although you need to save only the CCR, you are forced to save both bytes
of lhe Status Register (the upper system byte as well as the CCR).
The MC68010120 allows the simpler:
MOVE . W CCR, - {SP)

Push OCR on stack

which just saves the CCR byte on the stack (the other byte moved is all zeroes).
You can restore the CCR on all models with

MOVE . W (SP}+. OCR

Pull OCR from stack

In all Chapler 5 examples we'll use the MC68000 version (MOVE hom SRI.

RTR -

RETURN AND RESTORE CCR

A simpler way to restore the CCR is to use a special version of RTS called RTR
(ReTurn from subroutine and Restore condition codes) . RTR at the end of your
subroutine will first pull the CCR hom the stack, then perform an RTS. Using
RTR when you have not earlier pushed the CCR is a dreadful mistake - your
stack will be "out of synch" with \Neird results all round.

NESTING SUBROUTINES
Once you grasp the basic LIFO mechanism of the user stack, you will readily
see that subroutines can themselves ca1l subsubroutines and so on - a concept

M68000 Ins/ru c/ion Se/ -

Advanced Topics

147

knolJJn as nesting. You just trust the stack to pull what was last pushed! The
maximum depth of nesting allowed will depend on \KlUr particular

as and

memory disposition - many systems do not allocate a fixed amount of memory

for the stack; rather, the stack is allOVJd to "gro..v down" in free user memory
until it " hits" occupied tertitory.
It is now time to introduce some more addressing modes. Excluding special
modes on the MC68020 only, VJe have four more addressing modes to reveal
in this chapter. They are all variants of the address register indirect.

ADDRESS REGISTER INDIRECT WITH OFFSET

This mode is written d16(An) where d16 represents the 16bit offset (sometimes
called the displacement) in bytes, which is added to the pointer value of An
before the operand is fetched from memory. Unlike the -(An) and (An) + modes,
however, the value of An is unchanged by d16(An) .
The offset can be any signed 16-bit number in the range 32,768 through
+32,767 and VJe use the notation d16 to remind yt:lU of this limitation.
So d16(An) allows \KlU to access memory within 32K bytes (above or

below) of the pointer address, An. Its main use is to operate on data in a table
where An points to the starting address (or base) of the table.
It is helpful to express the d16(An ) mode in terms of an < ea> (effective
address) calculation. namely: < ea> := d16 + An. This formula tells yt:lU how
the processor determines the actual operand address. The d 16 offset is, in fact,
stored as one extension VJOrd. just as yt:lU saw earlier in the case of immediate
data. The <ea > calculation time can range from 0 in the simple direct modes
to as many as 17 clock cycles for a complex indirect mode. Let's look at the
d16(An)

mode in action.

Offset Mode - Applications

In Figure 5-4, A2

$6000 points to a table of data consisting of 20 longv..urds,

($6000), ($6004), ($6008) , ($600C), etc. To load D3 from the 4th table entry,
VJe

need
MOVE. L

12(A2),D3

since the source effective address

A2 + (310ngv..ordsl

:=

$3000 + 12 bytes

= $31lOC. After the move A2 still = $3000. If we wanted to reverse the second

and third entries in our table, one wirY VJOUld be as follows:

Program 54 Swap Table En tr ies

148

68000, 68010, and 68020 Primer

3

'0

CCR

- - - - -

lEla15 16 IF ~03
IIII III r

121915

31

2423

1615

87

Bef ore

MOVE.l

12(A2), 03

CCR
no

~4:..!3~2,,'

0
N Z V rI:.

---t:.,
' r'~c;::,:O,..

eo

chaoge n

"
non-"cleared
zero

aala'j~r~t 10 10 _

31

2423

1615

A2

wordN

WOld N+1

T
$6000

03

1
31

I I I i I I I _PC
2423

1615

87

$600C I--ii+~f--,O+"""Y
$600E

A1lH

MOVE.l

12(A2), 03
Fig. 54

MOVE.L 12(A2),D3

M68000 Insuuction Set -

Advanced Topics

149

Illustrate use of dI6 (An ) mode in source and destinati on.

A2 points to base of table of longword entries .
Switch the 2nd and 3rd entries.
MDVE . L
MDVE . L

MOVE.L

4 (A2),DO
8(A2), 4{A2)
DO,8 (Al I

Save 2nd table entry

Move 3rd to 2nd
Move 2nd to 3rd

Three points to note when using this mode are:

1. For L and W operations the sum (d16 + An) must be even.
the sum can be odd or even.
2. -I (An) should not be confused with -{Ani. For example,
MOVE.B -1(A2),D3 and MOVE.B -(A2),D3 both move
lower byte of D3, but the -1(A2) move leaves A2 still
pre-decrement -(A2) reduces A2 to $2000.

For B operations
if A2 = $2001 ,
byte ($2000) to
= $2001. The

3. This mode often appears as TAG(An), for example, in real-life programs,

where TAG is a symbolic (preferably mnemonic) offset which, as you saw
with labels, gets equaled to a numerical offset during assembly.
There are many situations where VJe need the flexibility of a variable offset
to supplement the fixed offset of the d16(An) mode. Our next addressing mode
supplies the solution.

ADDRESS REGISTER INDIRECT WITH OFFSET

AND INDEX

all~n

This extension of the dI6(An) mode

extra variable offset, known as
an index, to be added from a register. For brevity VJe will call it the index mode.
It is written as d8(An,XLZ) where d8 is a fixed offset in bytes (8-bit signed
number) giving a range of -128 through + 127; An holds the base address as
in the dI6(An) mode; Xi is any register (DO - D7, AO - A7) , known here as
the index register, and Z is a size code, L or W.
The effective address, < ea > is built up from three separate elements:
< ea> = An + d8 + Xi.Z. In other VJOrds, the processor adds the offset d8
bytes, then gets the number from Xi.Z and adds that number of bytes as an
additional offset to An. The conbibution to this total from the index register, Xi,
is either the full 32 bils for Xi. L, or just the I"""" 16 bils for XiW. The speed
of the < ea > cakulation is the same for Land W indexing.
As with the dI6(An) mode, the actual value of An is unchanged. Also, we
must watch that the < ea> we obtain is even for Land W operations.

150

68000, 680/0, and 68020 Primer

We often abbreviate the index mode to d(An,Xi). If the fixed d offset is 0,

this mode gives us a simple indexing mode as found in many 8- and 16-bit
processors.

INDEX MODE - APPLICATIONS

The main application of the d(An,)G) mode is accessing complex multidimensional arrays and tables of data in memory. With tvJo offsets, for example, you
can set An pointing to the base of a spreadsheet. If you set the offset d to the
line number and move the column number to the index register Xi, d(An,Xi) is
the effective address of the data-cell in the target box, the intersection of row d
and column Xi.
Although the fixed offset d8 offers only -128 to

+ 127 displacements, the

addition of an index register is ample compensation. XLL can give you a range
of 2 gigabytes on either side of the An pointer.
Using the data in Program 5-4, let's see the index mode in action, first with
d8 = to shO\.V simple indexing.

Program 5-5 Swap Table Entries Usi ng Index Mode

Initial data as for Program 5-4

Illus trate use of d8(An.Xi . Zl mode in source and destinati on.
A2 points to base of table of longv..ord entries.
s"'itch the 2nd and 3rd entries.
MOVEQ. L
MOVE . L

14,01

O(A2,OLW),OO
MOVEA . W ,8 , AO
O(A2,AO.W),O(A2,OI.W)
MOVE . L
DO.O (A2.AO . W)
MOVE. L

Set Index Reg 01 : 4

Save 2nd table entry
Set index reg AO : 8
Move 3rd to 2nd
Move 2nd to 3rd

Note that A2 is unchanged .

In Program 5-5 we have used both 01 and AO as index registers just to
remind you that any register can be used to index. The data registers are, in
fact, more popular than address registers for indexing, simply because you can
do more arithmetic on them. When you are scanning or searching a table using
the d(An,Xj) mode, you often want to add, subtract, multiply, and even divide
the offset sitting in Xi.
In Program 55, the table consisted of longwords, so we had 10 remember
to adjust the index offsel by multiples of 4 bytes. For tables of words the offsets

M6800D Instruction Sel -

Advanced Topics

151

""",Id have to be multiples of 2 bytes. Naturally you can ask the M68000 to
do these cakulations for you. To obtain multiples, let us go forth and multiply!

MULTIPLICATION
There are

t\.I.Q

I4ULS
II\JW

basic multiply instructions which use the same format

<source>, On
<source>. On

MULtiply Signed
MULtiply Unsigned

They both multiply two 16-bit I'.brds to give a 32-bit result. No data size code
is needed since W is always implied. The source can be any addreSSing mode
except An (Address Register Direct). What happens is this:
(IA.Ord from source) times (lower IA.Ord of destination On)
in Dn)

(32-bit result

Just like ADD and SUB, the source is unchanged but the destination factor is
C>veIWritten by the answet Unlike ADD and SUB, however, multiply needs
separate versions: MULS for signed and MULU for unsigned operations. With
ADD and SUB, you will recall, the V (o\krflow) and C (Cany) nags were set
to warn )oOJ of erroneous signed or unsigned results. Multiply is different.
The inviolate laws of binary arithmetic teU us that whether you multiply 2
signed or 2 unsigned 16-bit numbers, the anSVJer always fits in 32 bits without
overflow or carry! Multiplying a signed number by an unsigned number is not
a fruitful exercise and the M68OCX) assumes you knOVJ in advance the type of
numbers you intend to multiply. You must therefore choose betvJeen MULS and
MULU to get a sensible answer. Both MULS and MULU set the CCR thus:
Rag
MULSIMULU

(To remind you of our notation: X unchanged; N set to sign-bit 31; Z set to 1
if result 0; V and C flags always cleared to 0.) MULS , of course, will correctly

handle the sign of the result, for example, (-6) x (-2) ~ + 12 and (-6) x (+2)
= - 12 so the N flag literally means "positive or negative." MULU is multiplying
without regard to sign, so the N flag is simply telling you if there is a 0 or 1 in
the most significant bit (position 31) of Dn after the multiplication.
We illustrate MULS with a simple (but essential) payroll example.
Program 5-6 Payroll : Hours x Rate = Pay

152

68000,68010, and 68020 Primer

As in Program 4-1 02 word contains hours worked in March = 138.

04 word holds the hourly rate in cents = 699 .
Calculate March gross salary and if positive save it in memory
at longword absolute address $A200. Preserve the values in 02
and 04 .
Save D4 lIord on stack
04 now = 02 x 04
= Hrs x Rate : Gross
(02 unchanged, 04 changed )
If result negative branch
DEBIT
8M1
to label DEBIT
(Branch if MInus )
NOPAY
If result zero branch to
BEQ
label NOPAY
D4,SA200
Save Gross in memory
MOVE. L
(SP)+,04
Restore 04 from stack
MOVE.W
<carry on--normal payroll>

MOVE . W
MULS

DEBIT

BRA
MOVE . W

04 , - ISP)

02 , 04

OVER

(SP)+,04
<check negative gross>

BRA

OVER

(SP)+, 04
<check zero gross>

NOPAY

MOVE . W

OVER

<conclude program>

Skip to end
Restore 04 from stack
(see note 2 below )
Skip to end
Restore 04 from stack
(see note 2 below)

Gross pay for March = 96462 cents is stored at SA200.

02 unchanged and 04 restored.

1. We used MULS rather than MULU because in most finandal applications

would be allowing for negative amounts (refunds, adjustments, etc).
MULS permits us to use BMI (Branch Minus) meaningfully, since 8MI tests

I.I.Ie

the N flag.
2 . We must remember to keep the stack "tidy." Since I.I.Ie pushed D4, we must
pull it sooner or later; We could not pull it before our tests 8 MI and BEQ,
since MOJE alters the N and Z flags.
3. We have a typical use of BRA (Unconditional Branch) to bypass irrelevant
sections of a program. Without the first BRA OVER, for example, the main
program v.ould "run on" into the DEBIT section - a common source of
program misfortune.

M68000 Instruction Set -

Advanced Topics

153

DIVISION
Just like multiply, there are t\oo divide instructions:
DIVS

<source>, On
<source>, On

DlVU

DIVide Signed
DIVide Unsigned

Both divide the 32bit destination On (dividend) by the 16--bit VJOrd source

(divisor), to give a 16--bit quotient in the 10VJef On IM>rd and a 16bit remainder
in the upper On IM>rcl. The source can be any addressing mode except An , so
VJe can divide a data register by another data register or by a IM>rd in memory.
As we have found in other arithmetic operations, the source (divisor) is un
changed but the destination (dividend) is "lost" - ovetWtitten by the results.
Divide, then, perionns as follOVJS:
(Destination On
divisor)

gives (upper On IM>rd

quick example:

32bit dividend) divided by (] 6bit IM>rd source

=

remainder) ,(IOVJeT On IM>rd

quotient). Here is a

Program 57 Payroll : Average Daily Earnings Us ing DIVS

Using the data in Program 56: 04 holds March gross pay :
96462 cents . Cal culate the average daily earnings and st ore in
2nd word of a table with base pointer A2 . Save the relllainder in
the 6th word of this table . Preserve value in 04 .
MOVE . L

OI VS
MOVE . W

SWAP

MOVE. W
MOVE . L

04 ,07

Save 04 in 07
Divide 04 by 31 (i mmediate)
Lo\\'er 04 : quotient
Upper 04 = remainder
04 , 2 (A2 ) Save quotient in table
Reverse words in 04
0'
Remainder now lower word of 04
Quotient now upper word of 04
04 , 10 (A2 ) Save remainder in table
Restore 04 from 07
07 , 04

131 , D4

2{A2 ) now holds 3111 and 10 (A2 ) holds 21 .

96462 /31 = 3111 and 21 over.

SWAP Dn is a simple but useful instruction which reverses the upper and
lower half words of a data register only. Notice that in the Program 5-7, you
cannot immediately use MOVE to save the remainder, since MOVE.W moves
the lower word and MCNE. L moves the whole word. Later, you'll see more

154

68000. 68010. and 68020 Primer

exotic ways of manipulating portions of a register, using shifts and rotates - but
here !IOJ see the motivation for such operations: the need to "isolate" and
access part of a register.
We used DIVS for the same reason we used MULS in Program 5-6. DIVS
gives the correct signed answer, for example, (-24) /(-2) ~ + 12 and (24)1(-2)
= -12, and so on. The Nand Z flags in the CCR reflect the state of the quotient,
because the remainder takes the same sign as the dividend (unless the remainder
is 0). for example,
~

(-12) with remainder + 1

(-25)/( + 2) ~ (-12) with remainder-1
(-25)/( + 25) ~ (-1) with remainder +0
(25)/(-2)

Unlike MULS, though, DIVS and DIVU can run into t\.vo snags. The first
snag is "Divide by 0". If your program doesn't test and take avoiding action ,
then the M68000 will TRAP this error (to avoid the horrors of an infinitely long
calculation). TRAPs belong to a class of exceptions (some of which you can
control, others of which are controlled ~ the system) that put the M68000 into
the supervisor mode (which VJe mentioned in Chapter 3). In this privileged
mode the operating system can take appropriate action.
Briefly, TRAPs, such as the "TRAP on zero divide", guide the processor
to a table in system memory (addresses $000 - $3FF) called the exception
vector table, where it finds the address of a routine for handling the exception.
The M68000 therefore has tremendous flexibility in coping with conditions that
on less thoughtful chips IJXX.Ild result in crashes, chaos, or both.
The second snag is this: DIVS and DIVU can give rise to overflow, when
the dividend is so large in relation to the divisor that the quotient exceeds the
16-bit capacity (signed ~ -32,767 to + 32,768 or unsigned 65,536). To protect
you, then, DIVS and DIVU both set the V flag in the CCR if overflow occurs.
If your numbers are likely to stray into these ranges you can use BVS
(Branch if oVerflow Set) immediately after the diviSion, just as VJe did earlier to
test an ADD.
Alternatively, there is a special TRAP instruction called TRAPV (TRAP on
oVerflow) which, like the trap on zero divide (except that TRAPV is voluntary),
takes the system into the exception vector table to select the chosen remedy.
DIVS and DIVU change the CCR thus,
Flag
DIVSIDIVU

which is the same as MULSIMULU except for the V flag.

M68000 Instruclion Sel - Advanced Topics

155

In Program 5-7 we used immediate mode source, #31 . as our divisor the number of days in March. A more practical program \UOUld allOVJ for other
months in the year! For example, we could set up a small table holding the days
in each month. Such a table v.uu1d be useful in many financial applications calculating elapsed days between dates for interest charges, and so on. The
index mode is tailor-made for accessing such tables. Our next example also
shovJs how you can do arithmetic on the index register to simplify the location
of a table entry.

Program 5-8 Average Daily

for Any Month

Month number M (Jan=l , Feb=2 , etc ) is in lower word DO .

04 holds gross pay i n cents for that month .
AO points to base of table MDAYS in memory holding 12 words .
(AO ) = 31 ; 2(AO I = 28; 4(AO) = 31; 6(AO) = 30
S(AO I = 31 ; 10 (AO) = 30; .
.. . .. ;12(AO ) = 31
Hence number of days in month M is in word 12 x <M-l >I(AO ).
We ignore leap years for the moment.
Calculate average daily earnings to 1 deci mal place and put
result in word 06.
Save regi ster values of 00 , 04 .
We use <> as brackets to avoid confusion with indirect address
brackets ().

MOVE . W

00 /04 , - (SP)
11 ,00
12 ,00
1100, 04
O(AO , DO . W) ,04
04 ,06

MOVEM . L

(SP)t , 00 /D4

MOVE.Id . L

SUBQ. W
MIJW
MULS

OIVS

~arnings

Slack ' em
WordOO:M-l
00 = 2 x <M - I>
Multiply gross by 100
Divide 04 by days in month M
Ignore upper word 04 ::: remainder
lower word 06 ::: average x 100
Unstack ' em

For the familiar month of March , M::: 3, so DO index register

contains 2 x <3-1> = 4. Source operand divisor for Drvs is
therefore word at address 0 + AO + 4 = 4(AO j, that is, 3rd
entry in MQAYS table which ::: 31. 06 now contains our average x
100. We can round this off to 1 pl ace later.

An alternative method of multiplication is to use shifts, which we discuss

next.

156

68000, 68010, and 68020 Primer

10

... 2? ASR by 1 gives

1 1

01

=6

I0 0 1 1 I = 3 divides by 2 OK
1

x 2? ASL by 1 gives 11 1 0 0
1
x 4? ASL by 2 gives 11 0 0 0

11 0 1
... 2? LSR by 1 gives 10 1

I = 12 multiply by 2 OK

I = 8 wrong - overflow error

(j = -6

(2's complement)

o 1 I = 5 wrong (no warning)

... 2? ASR by 1 gives 11 1 o 1

= -3 divides by 2 OK
1
x 2? ASL by 2 gives 10 1 001 = +4 wrong - overflow error
( 12 is beyond range of4-bit signed numbers)

Fig. 5-5

Shifting to Multiply and Divide

ASL - ARITHMETIC SHIFT LEFT

We used MULU in the first multiplication because we are dealing with small
knovm positive integers (and it is slightly faster than MULS). In fact, there is a
much quicker way to multiply by 2, 4, 8, or any small pov.oer of 2. We can use
ASL . z

N<d3>,Dn

which does an arithmetic shift left on On. The number of places shifted is
detennined by the 3-bit number in < d3 >, giving a shift count in the range of
1 to 8. The z detennines which portion of On is shifted, L, W, or B. Rgure 5-5
shOVJS hOVJ ASL can be used to multiply by 2.
Each shift left of the bit pattern in the L, W, or B of On is equivalent to
doubling the value of that part of On. So, an ASL of 1 can double just the lovver
byte or word of On without affecting the rest of On. Zeroes are " pushed" into
On from the right as the shift takes place, and bits get "pushed" out at the other
end.

M68000 Instruction Set -

Advanced Topics

157

In Program 5 8 we can replace:

12 , 00

Longword DO "" Iword 00 x 2}

11,DO

Longword DO = /longword 00 x 2}

11 , 00
11 , DO

\\'ord DO = {'olt'ord DO x 2}
Byte DO = {byte DO x 2}

with any of these:

ASL. L
ASL. W
ASL. B

All the ASLs above work the same as MULU in our example since the
maximum value in 00 is 22, well within the signed capacity of DO's 10000r byte.
For larger numbers, of course, you v.Qllld need to decide the safest size code to
use. Unlike MULSIMULU, ASL can cause overflOVJ - and the CCR should be
tested if there is any danger of exceeding the L, W, or B range of Dn.
ASL is about three to five times faster than the equivalent MULS or MULU.
If you need to shift more than 8 positions or shift a variable number of
positions, you can use the format
ASL . z

Do,On

Shift On Left , Om times (max 63 )

where the 10VJer 6 bits of the source data register Dm contains the shift count.
Finally, you can ASL a memory operand, but the shift count is restricted
to 1:
ASL . z

<memory operand>

Single left shift me.ory operand.

In Chapter 6 we will expand on the whole subject of shifts and rotates, so

for nOVJ we briefly mention an obvioos variant on ASL - ASH, which lets you
shift Right.

ASR -

ARITHMETIC SHIFT RIGHT

As shOVJn in Figure 5 5, shifting a register to the right is the same as dividing

by a pov;er of 2, To pre"""" the sign of the number yw are shifting, ASR
" pushes" the sign-bit into the left-hand side as the register is shifted to the right.
ASH formats are the same as ASL formats:
ASR . z
ASR . z
ASR . z

I<d3>,Dn
Shift on Right , <d3> times
Dm, On
Shift on Right , On times (max 63 )
<memory operand> Single right shift memory oper and

158

68000,68010, and 68020 Primer

INDEX MODE SUMMARY

The index mode allows us to set pointers to structured data in memory. Positive
or negative offsets to a base address held in An can be calculated in many ways
using arithmetical operations on any register, designated as the index register,
Xi, in the d(An ,Xi) mode.
We now conclude our examination of the baSic M68000 addressing modes
by looking at the "'" relative modes.

RELATIVE MODES - MOTIVATION

In previous examples we have often made use of data located at absolute
memory addresses, for example, "hours YTD is stored at address $6000 or
HRSYTD". In real-\A.Qrld applications programming we seldom know in advance
the absolute address of anything - programs or data. In fact, we often take
spedal pains to ensure that our programs will \A.Qrk wherever they are loaded
in memory.
Such programs are said to be relocatable or position Independent. Indeed,
some operating systems (such as the Alpha Micro AMOS running on its MC68000based AMIOOL) require that all programs be relocatable. Other operating systems may place restrictions or require spedalloading software for nonrelocatable
code.
In a relocatable program most memory references must be made relative
to addresses within the program itseJL which are not known in advance. Obvious
exceptions to this rule are memory references to fixed locations such as memorymapped 110 locations and systems areas like the exception vector tables.
When a program is loaded in memory and running, of course. the instructions must have enough information to enable the processor to calculate the
effective address of each operand, so it can locate, fe tch, and update correctly.

THE ROLE OF THE PROGRAM COUNTER

The key to all this is PC, the Program Counter, which we have already seen as
a rather special address register holding the absolute address of the current
instruction. Wherever our program ends up in memory, we can regard the
succession of addresses in the PC rather like the arrows you see on public signs
that say, "You are Here!"
So, if we have a way of referring to memory operands, not in absolute
address tenns, but relatively as, say, "420 bytes beyond (or behind) the current

M68000 Instruction Sel -

Advanced Topics

159

PC, grab the YTD hours for March," \.\.Ie can boldly relocate such instructions
without restriction.
The 1\00 relative addressing modes. PC Offset and PC Index, give us this
ability. They make use of PC in the same WCJ!y as the dI6(An) Offset and
d8(An ,Xi.Z) index modes make use of An.

RELATIVE ADDRESSING-PROGRAM
COUNTER ADDRESSING WITH OFFSET
This mode is written symbolically as d16(PC) , which looks just like the d16(An)
mode with PC playing the role of An. You'll recall that dI6 is a signed I6-bit
offset or displacement, held in an extension IM)rd, and offering a range of plusl
minus 32K bytes.
The effective address is calculated by adding dI6 to the address held in
PC: < ea > = d I 6 + PC, allOVJing access to source memory addresses within
32K bytes on either side of the current PC value. The offset is stored as a single
extension IM)rd follOVJing the instruction and, strictly speaking, it is the address
of this extension IM)rd which represents the value of PC when the < ea > is
calculated. This is hardly surprising if you remember that the processor has to
fetch the dI6 \.IJOfd from memory, so PC has advanced beyond the instruction
itself.
Although the d16(PC) mode, so far, looks like the d16(An) mode, there is
one fundamental exception.
Relative modes can only be used as source operands.

Am; combination of op code/operand in whieh dI6(PC) is an alterable destination operand is illegal. The reason is simply to discoorage you from modifying
or writing over your o..vn program. We will elaborate on this later.
Relative mode operands cannot be altered.

The dI 6(An) mode can be used as source or destination , but the dI6(PC)
mode is source only.
It may seem at this point that the dI6{PC) mode could prove irksome in
practice - how on earth can \.\.Ie supply values for dI 6? How many bytes
beyond or behind my current instruction is my target operand's <ea>? The
anSVJer is that by using label operands we can delegate the chore of displacement
calculation to the assembler. This trick is somewhat similar to the one we saw
in action with Bee < label > in Chapter 4.

160

68000,68010, and 68020 Primer

LABELS AS RELATIVE OPERANDS

We saw in Chapter 4 that the ORG directive forces the assembler to assign
absolute addresses to label operands.
There is another assembler directive called RORG (relative origin) . In a
RORG section of a program, the assembler automatically translates the label
operand into dI6(PC) addressing mode. It then calculates the relative offset
(plus or minus) in bytes betvJeen the current instruction and the label address
and sets this value into the d 16 extension v.ord.
At this stage the assembler does not know what value the PC will hold
when the instruction is eventually decoded during a run. All the assembler needs
to determine is the relative offset, the "distance" in bytes betvJeen a ny instruction
using a label and the label itself.
Most assemblers are m ultipass, that is, they scan the source code several
times, allOVJing the m to establish the relative poSitions of all labels, and then
compute a nd store the correct d16 offsets.
Let's look at a typical situation. We introduce the JMP (JuMP) instruction,
which is simply a more versatile version of the unconditional branch instruction
BRA. There is also a JSR (Jump SubRoutine) corresponding to BSR (Branch
SubRoutine). In normal computer jargon jumping and branching are identical
concepts. In M68000 parlance, hOVJever, there is a technical distinction. JMP
and JSR can accept a wider class of destination operands than BRA and BSR,
as we'll see when we cover < control. effective addresses> at the end of this
section.

RORG

JMP

LOOP

Following program is Relative

<do more>

LOOP

Do something
JUMP to LOOP
600 bytes worth of ins tructi ons

The tVJO v.ords of the assembled JMP instruction I,.\.()IJld look like this:

Bit

15 14 13 12 II !O 9 8 7 6 5 4 3 2

I 0

mmmrrr

JMP

0100 111011111010

dl6

0 0 0 0 0 0 I

0 0

I 0

I 0 I

I 0 = + 598

M68000 Ins/ruc/ion Set -

Advanced Topics

161

Bits 6 through IS encode the JMP instruction, while bits 0 through 5 encode
the dI6(PC) addressing mode. The extension IOOI'd holds the calculated offset
to the instruction labeled LOOP This offset is positive because UJe are jumping
forward.
When this instruction is decoded during execution, the processor, following
the rigid rules of d16(PC) mode, fetches the extension \VOI'd and calculates the
effective address of the operand as follows: < ea> ~ PC + 598 bytes. The PC
currently holds the address of the extension v.ord, so, < ea> = address of JMP
+ 600 bytes, which is the address of the LOOP line. The JMP instruction then
places the calculated <ea> into the PC. The processor therefore takes Its next
instruction from the memory address of LOOP. In other v.ords, we have jumped
to LOOP.
The assembler automatically calculates: offset d16 = " < label> - PC"
bytes, while the processor calculates: < ea> = PC + offset d16, with a real,
known address in PC to obtain the effective address of < label>.
Labels in an ORG section equal absolute address mode. Labels in a RORG
section equal PC relative with offset address mode.
You will seldom code dI6(PC) directly, but each time you use a label in a
RORG section of a program, you now know that you are invoking PC relative
addressing with offset.
In addition to the use of labels with branch and jump, labels can be used
as soorce operands in many ways. RORG allOVJS the DC (Define Constant) and.
OS (Define Storage) directives with PC relative labels. The data areas are
relocatable because of the PC relative mode. For example:
RORG
TABLE

DC.'

$34 A2 , $0087

sets up 2 \.VOrds of data at an address TABLE that can be accessed as a soorce

operand no matter where the program is in memory.
MOVE . W

TABLE , 01

will move $34A2 to the 10VJer \.VOrd of Dl. To achieve this the assembler sets
up a d16 offset in an extension \.VOrd to the MOVE instruction and the soorce
operand is encoded as d16(PC) mode. When the instruction is decoded and
executed the offset + PC gives the correct effective address for the data stored
at TABLE.
We can now look at yet another method of accessing memory using the
important LEA (Load Effective Address) and PEA (Push Effective Address)
instructions.

162

68000, 68010, and 68020 Primer

LEA is a tv.Jo-operand instruction with the folJOVJing format:

LEA <source>, An
LEA calculates the effective address of the source operand and places this
address in the register An. All 32 bits of An are affected, even if thE! chip uses
fewer address bits.
PEA is a one-operand instruction: PEA < source> perfonns the LEA calculation and pushes the effective address on to the user or supervisor stack
(whichever is active). PEA is equivalent in effect to:
LEA <source>, An

MOVE . L

An , - (SP )

(although no intennediate An is involved).

We can illustrate one use for LEA with labeled data areas:

Program 5-9 Use of LEA

Calculate the average (arithmet ic mean) of

t~~

numbers in TABLE

RORG
TABLE

DC. W

$34A2, $00B6

Define 2-word data area at

address TABLE

CLR.L

01

LEA
MOVE . w

TABLE , A3
(A3)+, 01
(A3) , 01
11 , 01

Clear accumulator regist er

Load <ea> of TABLE in A3
01 :: 1st word . Inc A3 by 2
Add 2nd word to 01
Divide sum by 2

ADD .W
ASR .W

Answer is in 01 lower word

= <$34A2

+ $00B6>/2

= $lAAC

Using LEA can often save time. If a complex operand needs to be accessed
several times during a program , it pays to use LEA first to get the operand's
< ea> into an address register. For example, suppose \Ve have done some heavy
calculations to establish values for An and Xi prior to using d8(An,Xi) mode to
access a complex array. Each time \.\J use d8(An ,Xi) as an operand we force
the processor to calculate the < ea> (taking from 8 to 14 clock cycles). But if
we use

LEA d8 (An,Xi ), Am
\Ale

Load Am wi th <ea>

have Am as a pointer for all subsequent processing.

= d8t An+xi

M6BOOO Instruction Set -

Advanced Topics

163

Alternatively, if we were about to call a subroutine which needed our

d8(An ,XiI operand, we coold

PEA d8 (An , Xi)

Push d8+An+xi on stack

before the BSR or JSR. The stack would then hold

at address SP
at address SP+4

Return address for subroutine (2 words )

<ea> from the PEA (2 words )

During the subroutine we can " recover" this <ea> using

MOVEA,L 4 (SP), Am

Load Am from SP+4

Conceptually, LEA is the converse of the () indirection brackets.

An points to data (Ani.
The < ea > of (Ani is An.
LEA (Anl, Am sets Am equal to An.
Next we look briefly at the remaining relative mode, PC relative with offset
and index.

RELATIVE ADDRESSING-PROGRAM
COUNTER WITH OFFSET AND INDEX
We will call this PC index mode for short. This mode is written as d8(PC,XLZ)
from which you can correctly deduce that it follOVJs the format and rules for the
normal index d8(An,XLZ) mode, replacing An with Pc. The operand effective
address is calculated as
<ea>

= d8

+ PC + xi.z

where dB is a signed 8 -bit offset (-128 to + 127 bytes) , and XLZ is any register
selected as the index register. The data size code Z can be L or W, and this
dictates whether 32 or 16 bits (Sign -extended to 32) of Xi (signed) are used as
the additional indexing offset to Pc. The dB offset and codes specifying the
register Xi and size Z are all located in a single extension VJOI'd.
To simplify oor formats we sometimes write this mode as d(PC,Xi). We
repeat the warning we gave for PC offset d16(PC):
Relative modes can only be used as source operands.

164

68000,68010, and 68020 Primer

Any combination of op code/operand in which d(PC,XO is an alterable destination operand is illegal.

From our discussion of relocatable code, it will be dear that PC index mode
allows us to set up and access labeled tables and arrays. Let's revamp Program
5-9 to shovJ a very simple use of PC index with our TABLE data.
, Program 5-10 Version of 5-9 usi ng PC Index Mode
, Calculate the average (arithmetic mean) of tv.o numbers in TABLE
RORG
01
#0 ,00

CLR.L
MOVEQ.L
MOVE. W

TABLE(PC,OO.W) ,01

ADDQ. W

#2 , 00

AOO.W
TABLE (PC , OO.W) .01
ASR. W
#1 , Dl
<conclude program>

Clear accumulator register

Set index reg DO t o 0
01 = 1st word in TABLE
Inc index DO by 2 bytes
Add 2nd word to 01
Oi vide sum by 2

, Define a data area at relative address TABLE

OC. W
$34A2,$OOB6,S56F9.$I ICC
<continue table ad lib>

TABLE

, Answer is in 01 io\\'er \\'ord = <S34A2 + $00B6>/2 :: $IMe

As with our earlier RORGllabel examples, the assembler establishes the
offset value from PC to TABLE. This offset, thoogh, is limited to a d8 signed
value, so Program 5-9 works only if TABLE starts within - 128 or + 127 bytes
of oor MOVE and ADD instructions. The TABLE, thoogh , can be as long as IJJe
need - so with this in mind IJJe have repositioned the TABLE data compared
with Program 5-9. We use DO as an index register, allowing us to pull out any
entry in

TABLE.

Before the instruction

ADD . WTABLE (PC, DO.W) ,01

DO has been set to 2, so the <ea > calculation for the source operand is

PC +

< ea>

+ < TABLE
TABLE + 2

= PC
=

dB

+ DO

PC> +

M68000 Instruction Sef -

Advanced Topics

165

What we add therefore is the second I.I.Q,d in the TABLE.

RELATtVE MODE -

SOU RCE O NLY RESTRtCTtON

As we have stated twice, relative mode is illegal as a destination operand. This

was a deliberate design decision by Motorola to reduce the risk of a program

(especially a relocatable one) inadvertently writing over itself. For example,

NOVE.W

DO ,8(PC)

(i llegal )

if aUoo.ed, I.IoOUld replace the instruction (or a part of it) that lies 4 I.I.Q,ds (8
bytes) ahead, with whatever is held in DO's 10VJeT word. There is a high probability
of chaos when the instruction decoder reaches this word and blindly attempts
to obey it. Of course, you could be extremely clever and deliberately set DO's
bit-pattern to correspond with a valid instruction! Self-modifyi ng programs do
have a role to play, but the M68000 forces you to take special action, as it VJere,
to make sure you knOUl what you are doing.
One side effect of this restriction is that great care is needed when using
labels:
MOVE . W
MOVE. W

DO , TABLE
DO , TABLE

Legal for ORG sections

Illegal for RORG sec ti ons

A1though these tv..Q instructions look the same, their addressing modes differ
TABLE in ORG is an absolute address, and therefore valid as a destination.
TABLE in RORG is a relative mode - dI6(PC) and invalid as a destination.
One of the ways to beat the RORG restriction is:
LEA
MDVE.W

TABLE ,Al
DO, (AI )

ADDRESSING MODES -

<ea> of TABLE to

Al

Move DO word to TABLE

GRAND SUMMARY

We have now visited all 12 of the basic M68000 addressing modes (the MC68020
has 6 more which we cover in Chapter 8). \Ale have, of necessity, glossed over
many of the subtleties in order to give you a general picture.
In describing some of the instructions, we have occasionally indicated that
the source and/or destination operands are restricted to certain addressing
modes. These various limitations can appear quite arbitrary and confusing, even
to experienced programmers. Much of the existing M68000 technical literature

166

68000, 68010, and 68020 Primer

compounds this feeling by using inconsistent and conflicting terms for classes of
addressing modes.
In Appendix B, part of which \.Ve reproduce belOVJ, \.Ve have attempted a
logical classification of the addressing modes that will, hopefully, clarify when
and why certain modes are valid. Appendix C lists all the op codes with their
permissible source and destination modes.
M68000 ADDRESSING MODE TYPES
Each addressing mode can belong to some or all of the following nine overlapping groups.
< ea >
< rea >
< dea >
< mea >
< cea >
< aea >
< adea >
< amea>
< acea >

Any effective address

Register effective address
Data effective address
Memory effective address
Control effective address
Alterable effective address (data or memory)
Alterable data effective address
Alterable memory effective address
Alterable control effective address

An in the table belOVJ indicates the groups for each mode (and the modes
for each groop).

Mode

eo

rea

dea

Dn
An
IAn)
IAn) +
-IAn)
diAn)
dIAn,Xi)
Abs.w
Abs.l
dIPC)
dIPC,Xi)
Imrned
bdIAn,Xi)
bdIPC,Xi)

mea

ceo

aea adea amea acea

68020
68020

M6BOOO inslruc!ion Se! - Advanced Topics

rea

dea mea ceo

Mode

eo

[bd,AnJ,Xi,od
[bd,An ,Xil,od
[bd,PCI,Xi,od
[bd,PC,Xil,od

*
*

*
*

*
*
*

167

aea adea amea acea

*
*

68020
* 68020
68020
68020

The MC68020 modes are a sneak preview of Chapter 8.

Mode Description:
Dn
An

Data reg1ster direct

} .
..
. t d' t JOintly called regi ster direct
Add ress regIs er lrec

IAn)

Address reg1ster indirect

IAn)+
-IAn)

Address reg1ster indirect with post-increment

Address register indirect with pre-decrement

dl6lAn)

Address register indirect with offset-also written as d(An)

d8IAn ,Xi.Z)

Address register indirect with offset and index-also written

as dIAn,Xi)
Abs.W
Abs.L
d161PC)

Absolute short address-also written as xxx. W or label

Absolute long address-also written as xxx.L or label
Program counter with offset (relative mode)-also written as

dlPC) or label
d8IPC,Xi.Z)

Program counter with offset and index (relative model-also

writlen as dIPC,Xi) or labellPC,Xi)

Immed

Immediate data operand-also written as # < data>

MC68020 Only (see Chapter 8 for detailed explanation);

bd(An,XLZ*s)

Address register indirect with base displacement and

index (similar to d(An,Xi) but bd can be d16 or d32)

bd(PC,Xi.Z*s)

Program counter with base displacement and index

Isimilar to d(pC,XiJ but bd can be d16 or d32)

[bd,AnI,Xi.Z*s,od

Memory indirect post-indexed

[bd,An,Xi.Z*sl,od

Memory indirect pre-indexed

[bd,PCJ,Xi.Z*s,od

PC memory indirect post-indexed

[bd,PC,Xi,Z*sJ,od

PC Memory indirect pre-indexed

168

68000, 68010, and 68020 Primer

Abbreviations:
On
An

Xi
z
Z

s
PC
SR
SP
CCR
d
bd
od
xxx

Arry data registet; DO - 07

Arry address register, AO - A7
Any On or An used as an index register
Data size code (L, W, or B)
Data size code (L or W)
Scale factor (1 , 2, 4 or 8)
Program Counter (20, 24, or 32 bits)
Status Register
Stack Pointer
Condition Code Register
A 2's complement or sign-extended offset (displacement); d16, dB,
d3, etc. indicates the number of bits
A 2's complement base displacement (16 or 32 bits)
A 2's complement cuter displacement (16 or 32 bits)
Any valid absolute address

MODE GROUPS -

DEFtNITIONS

Let's pick cut a few modesIgroups to indicate why they are associated as shown.
< dea> data effective address: Includes all modes except An. As VJe saw,
An allOVJS only restricted arithmetic; it is not classified as a true data
operand.
< mea > memory effective address: Excludes just the tvJo direct register
modes in < rea >, On and An, that are nonmemory operands.
< adea > alterable data-effective addresses: AJI those < dea > s which can
be valid destinations, subject to change by an instruction. Clearly immediate data cannot be an alterable destination, so immediate mode is
a < dea > but not an < adea > . Similarly, VJe have seen that the tvJo
relative modes are not alterable. Rnally. An is not < adea > because it is
not < dea >.
< amea > alterable memory effective addresses: All those < mea > s which
can be destinations subject to change.
< aea> alterable effective addresses: Simply a combination of < adea >
and < amea > together with An.
<cea> control effective address: A subset of < mea > representing just
those memory addresses to which control can be passed, for example
by JMP (JuMP) or JSR (Jump SubRoutine).

M68000 Instruction Set -

Adva nced Topics

169

INSTRUCTION FORMATS USING MODE GROUPS

These mode groupings allow yoo to specify the permissible op code/operand

combinations concisely and precisely. Here are some examples using instructions
that 1Ne have already seen (see Appendix C for a complete listing):
MOVE.z

500fte
Destination

<ea>,<adea>
< ea>
< adea >

All addressing modes are legal.

Only alterable data effective address modes
legal. Excludes An, all relative and immediate
modes.

MOVEA.Z
Source

Destination

ADD . z
ADD.z

<ea> , An
< ea >
An

All addressing modes are legal.

Only address register direct legal.

<ea> , Dn
Dn , < amea >

Either

All modes
Dn only.

500fte
Destination
Or

500fte
Destination

ADDI. z
Source

Destination

ADDQ.z
5oon:e
Destination

< arnea >

On.
Only alterable memory effective address
modes legal. Excludes On, An, all relative
and immediate modes.

# <da t a> , <ade a>

# < data >
< adea >

Immediate mode only.

Only alterable data effective address modes
legal. Excludes An, all relative and immediate
modes.

# <da t a> . <aea>

" < data>

< aea>

Immediate mode only.

Only alterable effective address modes legal.
z = L,W only for An. Excludes all relative
and immediate modes.

170

68000, 68010, and 68020 Primer

< dea> , Dn

MULS

Source

<dea>

Destination

Dn

BRA

LABEL

Source
Destination
JMP

Data effective address modes legal; all modes

except An.
Only data register direct legal.

none

lABEL

Relative modes d(PC) and d(PC,Xi) only.

< cea>

Source
Destination

None
< cea >

Control effective address modes legal.

Excludes Dn,An, (An) + ,-(An) and
immediate mode.

The above schema can be extended to cover all but a handful of instructions, like MOIIEM, that have unusual operands.
IMPLICIT OPERANDS
To complete the picture we note that some instructions make use of miscellaneous systems registers without specific mention in the operand field. Examples
we have already seen are:
implidt Operand!s)

Instruction

BRA
JMP

Branch always
Jump always

PC
PC

&c
BSR

Branch conditionally
Branch subroutine

PC
PC,SP

JSR

Jump subroutine

PC,SP

RTS
RTR

Return from subroutine

Return sub/restore

PC,SP
PC,Sp,CCR

MOllE toCCR
MOllE from SR

CCR
SR

M68000 Instruclion Set -

Advanced Top ics

171

CONCLUSION

There you have it, and \.lie trust your basic understanding of the M68000
instruction set has been enriched. In the next chapter, \.lie will cover several
miscellaneous groups of instructions before \.lie proceed to discuss the MC6801
and MC68020.

6
A4~ce"aneousA468000

Instructions

In this chapter IJ..Ie look at some miscellaneous M68000 instructions grouped by

function. We will use the mode groups listed in Chapter 5 and Appendix B to

simplify our discussion of legal operand addressing modes.

NOP -

NO OPERATION

The NOP is a one-VJOrd instruction which advances the PC to the next instruction. No CCR flags are changed and there are no complicated rules for the
source and destination operands, because there are no such operands. I-Jou.rever,
it is definitely a useful instruction to know about if you are developing assembly
language programs, especially if your editing/debugging facilities are primitive.
It is often useful to reserve space in your program (each NOP = 1 \.VOrd) for

subsequent insertions; similarly .you can delete instructions by replacing them

with NOPs. The machine-level (object) code for NOP is $4E71, and on some
systems you can delete by slotting $4E71 directly into your object code without

reassembling.

BIT MANIPULATION
Our first major groop of miscellanews instructions allOVJS you to handle bits
and groups of bits within registers, special registers, and memory.
172

Misce llaneous M68000 Instructions

Table 6-1

173

Summary of Logical Instructions

Opcode

Operand

CCR Changes

AND.LJW/B
OR.LJW/B
NOT.LJW/B
EOR .LJW/B
ANDI {. B}
ORI{. B}
EORI{. B}
ANDI{.w}
ORI{. W}
EOR I{.W}

< dea>,Dn or Dn ,<amea>

X_ N' Z' VOCO

< adea >

Dn , < adea> (NO MEM SRC)

X_ N' Z' VO CO

#xxx ,CCR

X' N' Z' V' C'

#xxx,SR (PR IVILEGED)

X' N' Z' V' C'

X_ N'Z'VOCO

< dea>
data addressing modes - ALL except An
< amea > - memo ry alterable addressing modes = (An ), (An)+ ,- (An)
d IAn ), d (An ,Xi), Abs.W, Abs.l
< ad ea> - data alte rable addressing modes = < amea > + Dn
(zl means data size IMPLI ED
CCR symbols; _ means un changed, means ch,mged according to CCR rules, 0 means always set
to 0

As we have already seen, most instructions have L, W, and B variants for

manipulating selected parts of the operands. 1nere are many occasions when
we need to isolate other portions of the operand; perhaps we need to access
the top or middle bytes of a Long I.I.QI"d. Also, it is often useful to set up our
ov.m private status or condition registers - for example, in a payroll program
you might find an " employee status byte" with the 8 bits representing: sex (1
bit), marital status (2 bits), and so on. The operating system , too, often communicates to the programmer by setting or clearing flags in designated locations.
Many of the M68000 bit-handling instructions are therefore aimed at simplifying the task of testing, setting, and clearing bits that have a logical rather
than an arithmetical significance. So, first let us review the basic logical operators.

LOGICAL OPERATIONS

The M68000 provides four basic logical instructions: NOT, AND, OR, and EOR
which we summarize in Table 6-1. They are used in many situations, such as
setting and changing flag bits, and for masking or extracting data fields in

174

68000, 68010, and 68020 Primer

registers or memory. We shall first recap what each basic instruction

UJe shall show them in action.
NOT

does, then

Logical NOT means reversing each bit, from to 1 and from 1 to 0, throughout
the designated operand. Mathematically, this is the same as forming the 1 's
complement of the operand, so "NOT 01011010" - > 10100101. NOT requi res just one operand, which serves as source and destination. The format is:
NOT . z

<adea>

where < adea > stands for any alterable data-effective address, that is, any
address mode except An, d(PC) , d (PC,Xi) , and Immediate. As usual, the z data
size code dictates whether 32, 16, or 8 bits of the operand are NOTted.
For example,
NOT. B

Dl

in Figure 6 -1 reverses the 10VJer byte of Dl without affecting the upper 3 bytes.
The CCR changes just like a MOVE as shown in Table 6-1 .

AND
AND requires a source and a destination operand. The basis for a logical AND
is the following truth table.
Source
Destination

AND

o
o
o

o
1

1
1
1

-+

New destination

In other words, AND operates bit by bit, checking the bit values in the
source and destination, and forming a new bit in the destination according to
the rules above. Unless both source and destination have 1's in the same position ,
the AND sets a 0 in that position. There are two legal formats:
AND . z

AND . z

<dea> . On
On , <amea>

Miscellaneous M68000 Instructions

BEFORE

NOT.B 01
4 3 2 1 0

~ ~n-bilin

W sign- b ~

.)

~si9n-bit

1000 0101

A 2 3

B 5 7

8 5

01

1615

31

IIIIIIII

AFTER

NOT.B 01

CCR

01111010

A
31

7 A

16 15

01
0

IIIIIIII
f ig. 61

NOl.B Dl

1 75

176

68000, 68010, and 68020 Primer

where < dea> means any data effective address, that is, any addressing mode

except An, and <amea> means any alterable memory effective address (that
is, any < adea > except On).
Note that either the SOllIte or destination must be a data register. Both
source and destination can also be data registers.
Figures 6-2 and 6-3 shows rn.o examples of AND. AND changes the CCR
just like a MOJE, as shown in Table 6-1.

OR
Logical OR is the inclusive OR. Apart from using the OR truth table soovJn
below, OR vx:>rks just like AND, using t\M) operands and the same addressing
modes and data sizes, and it sets the CCR exactly like AND or MOVE.

Soorce

o
o

Destination
OR

o
1
1

o
1

1
1
1 __ New destination

Here you notice that OR sets a 1 if either or both source and destination bits
are 1 - hence the term inclusive OR.
The legal OR formats, just like AND, are:
OR . z
OR . z

<dea>, Dn
On , <amea>

Figures 6-4 and 6-5 show OR in action with different operands.

EOR

EOR is the exclusive OR, as shown in the EOR truth table:

Soorce

Destination
EOR

o
o

o
1
1

o -- New destination

The key difference between OR and EOR is the 0 in the last column. EOR looks
for either but not both when it sets the destination bits. Its claim to fame, as

we'll see, is that it can be used to reverse selected bits in a field with",t disturbing

Miscellaneous M68000 Instructions

BEFORE

ANO.W (A3) , 05
4 3 2 1 0

CCRfIT5!1~
L;

000
1615

AfTER

ANO.W (A3), 05

4 3 2 1 0

cc~1mP

unchanged

non
zero

neg

always
cleared

FI1~'IA3

I~I~r~htng;;:-:td

RI'

31

1615

Fig.62 ANO.W (A3l,OS

177

178

68000, 68010, and 68020 Primer

BEFORE

AND.L D6,(A2)+

4 3 2 1 0

L sign-bit

~""I"SiiiO~UiiRiiiC"lE_W
.,.;ign-bit
2

31

B sign-bit

,.-.:;..,.....

1 5 A

1615

06
0

r'

DE STINATION

0 0

0 1

0 0 0

A2

AFTER

AND .L D6,(A2)+

4 3 2 1 0

L-------'CCR X N
V
- 00
unChanged
non-neg

c-.

nonzero cleared

$1

Fig.63 AND.l D6,(A2)+

Miscellaneous M68000 Instructions

BEFORE

OR .B 4(PC), 03

4 3 2 1

cCRrnr~g1~
L sign-bit
WJign-M
DESTINATION

B sign-bit

~~"I'~ o

31

I
31

1Y,,,d

0111

1615

IIIIIII

I
o

23

AFTER

L...------C...JCR
OR.B 4(PC) , 03

3 2

XN

1 0

vi!

- 1

word N

cleared

i IlololoI2Iol.~31

23

PC increased by normal
a
instruction action, not by 4(PC)

Fig. 64 OR.B 4(PC), D3

179

180

68000, 68010, and 68020 Primer

BEFORE

OR .W 02, -(AS)

word N

4 3 2 1 0

CCRrEr~gjj
139

1
..

~ $6000 ~~~~~iuy

t"....,-'!'-I"....,-'!'-I"o"'lI~2... A'fJ $6002

1010101016101

AFTER

OR .W 02, -(AS)

4 3 2 ,

CCR -x,N v'1

unchange

neg

nonzero cleared

Fig. 6-5

OR.W 02, - (A6)

Miscellaneous M6BOOO InSlruction s

181

the other bits - unlike NOT, which rewrses every bit. Unlike AND and OR,
EOR allows only one legal fonnat:
EOR . z

Dn ,<adea>

You cannot have a memory address mode for EOR source.

EOR changes the CCR exactly like AND, OR, and MOVE, as shown in
Figure 6-6.
LOGICAL INSTRUCTIONS VARIATIONS

IMMEDIATE MODE

With the exception of NOT, the logical instructions have Immediate source mode

formats, ANDI, ORI, and EORI that all follow the same lonnat:
AND!. z
ORI.z
EORI. z

I<data> , <adea>

The size of # < data > should be d32, d16, or d8 depending on the size
code z used (l, W, or B). The instruction takes on one or two extension v.ords
to store the immediate data.
The use of immediate source mode with AND is very common. To mask
or isolate a destination operand, you create a # < mask> with 1's in the "selected" bit poSitions, and D's in the "discarded" bit positions. Since #3 =
00000011 , the AND.B in Figure 6-7 clears all but the 10VJeT 2 bits in 02.
With EORI.W, the # < mask > is chosen so that 1's select the bit positions
for reversal, while D's leave the corresponding destination positions unchanged.
In Figure 6-8 the bits in the lower byte of memory at (A 1) are all reversed by
the "FP' while the upper byte is unchanged.

CHANGING THE CCR

A special format for the immediate logical instructions allOVJs you to change any

or all 01 Ihe flags in the CCR byte:

ANDI. B

OR!. 8

EORI . B

I<d8>, CCR

182

68000,680 10, and 68020 Primer

BEF ORE

IEOR.W DO, 4(A2, D5.L)

I
"""dN

4 3 2 1 0

cCRgr~rr51

L sign-b~
/ . SOURCE

W sig n-b ~

word N+2

B s ign -b~

.-:::;

).

0011 010 1 1111 111 1

9 8

7 6

31

5 F F

DO

16 15

~004
+4

BA SE ADDRESS

0 0

0 0

O~

000

0 0

0 0 OJ"05

INDE X

'(

10 10 10 0

31

AFTER

EOR .W DO, 4(A2, D5. L)

4 3 2 1 0

c~Z~iI

"""d N
~
wordN+1
unchang
...........
non-neg nonzero cleared

17

in:hht51
1615

I dO~
0

I0 i~hr~id0 I 0 10'1
I0 10 11 1 0 I 0 10 105

A2

10 10
31

unchanged

23

$4004

Fig.66 EOR.W DO,4(A2, D5.L)

Miscellaneous M68000 Instructions

BEFORE

ANOtB #3,02

4 3 2 1

cCRfIT5n1~

l sign-bit

DESTINATION Wsign-bit

I~~~~)
3 9

B sign-bit

~~~

tOOl 1111

9 F

IIIIIII

31

02

1615

31

I
o

2l

AFTER

ANOtB #3, 02

CC

4 3 2 1 0

V
R f'X~N~.::t'!<;j"
""

unchange
non-neg

3 9
31

unctanjed
2

1615

nonzero

cleared

i---o 0000 0011

6 0 3

02

Fig.67 ANOI.B #3,02

183

184

68000,68010, and 68020 Primer

BEFORE

EORI.W #$OOFF,(A1)
4 3 2 1 0

CCR

fEIffn1~

000

0 0

Al

31

I
I
31

IIIIIII

I 0 I 0 I Flo I 0 I 0 Ipc

23

AFTER

EORI.W #$OOFF,(A 1)
4 3 2 1 0

CCR X N

unchang~/
non-neg non.
zero

I
I

31

IIIIIII
23

V~
o OJ

cleared

I Flo I 0 I 41pc
o
Fig. 66

EORI.W #$OOFF,(Al)

Miscellaneous M68000 Instru ctions

185

f'.k>te that the destination is simply written as CCR, and that only z = Byte

operations are allowed. The B is optional, but we'll use it to remind yoo what's
going on. To use this fonnat you need to recall that:
Bit 0 ~
Bit 1 ~
Bit 2 ~
Bit 3 ~
Bit 4 ~
Bits 5-7

C flag
V flag
Z flag
N flag
X flag
not used

A common application is to clear the X flag without disturbing the other

CCR flags. Vk use:

ANDI. B

#$EF' , CCR

since $EF = 11101111. This is mandatory before embarking on calculations

involving extended arithmetic, for reasons we'll explain later in this chapter in
the section on multi-predsion mathematics. It is instructive to compare the ANDIto-CCR method of changing the CCR with the MOIIE-to-CCR method.
I$EF ,CCR

MOVE. II'

Only a byte is moved in spite

of the II' data size

I,.I,!(XJld certainly clear the X flag, but the other flags would be set to 1.

CHANGING THE SR (STATUS REGISTER)

In the supetVisor mode only, you can change both bytes of the SR, the upper

system byte, and the CCR

ANDl. II'
OR!. II'
EORI . II'

(~

lower user byte). For this we use the fonnats:

I<d16>, SR

Privileged instructions
(Supervi sor mode only)

The system byte contains the ST (State and Trace) flags as ..veil as the 3-bit
interrupt mask - hence the need for privilege protection! (MOVE-to-SR is
Similarly privileged.) We cover this subject in detail later, in the section "More
on Privilege."

186

68000, 68010, and 68020 Primer

LOG ICAL O PERATIONS -

SUMMARY

By proper choice of the source mask operand, selected bits or flags in the
destination can be altered. The rules are:
NOT

Every bit reversed (NOTted) in destination

AND

o in source-Clears (to 0) selected bit in destination

1 in source-Selected bit unchanged in destination

OR

oin source-Selected bit unchanged in destination

EOR

1 in source-Sets (to 1) selected bit in destination

oin source-Selected bit unchanged in destination
1 in source-Selected bit reversed (NOTted) in destination

PRACTICAL APPLICATION

Prob/om: Clear !he 8th bit (bit posilion 7) of each byte In a strtng of ASCII
characters in memory.

8",_

: In some systems !he 7-bit ASCII character set (see Appendlx F)

I, extended by using !he eighth bit (bit position 7) fo< nonstandard control func lion, On other occasklns !he .,;ghth bit may be used as a parity bit (see Progrom

6-2 for exampie). This eighth bills scmetimes a nuisance and must be SUppi essed.

GWen: A non-empty ASCII string starting at the memory address stored In M ,

that i, to say. !he first byte of !he string ~ byte (A6). The end 01 !he strtng b
slgnaled by a nuU byte $00.

Solution: I'rotltam
LOOP

6-'
AND! B

I$7F , IA6 ) +

l..ediate source is
"01111111 "

is post-increnented
to ~ next byte
Is nex t byte null ?

A6

TST. B

(A6 )

BNE .S

LOOP

<rest of progrBa>

No - - so loop
Yes -- we've reached
end of string .
~-~-

Miscellaneous M68000 Instructions

187

,."",. . Noles: We aR! using S7F as a #<mask> - it has 1', In all the bit
posIlIoo~ 10 tluoogh 6) we do not wish to disturb. and a 0 In the bit _
.....
wont to SUJlllA!SS. The underpinning logic is,

1 AND x = x
0

o AND x =

Ix unchanged)
Ix dean!d)

Notice the power of the 1M) + addressing mode when used In conJundion
with the nuU byte string termlnatoc The latter is a widely used techn~ when
deaUng with variable length objects such as strings. The single ANOI.B Une dears
the 8th bit in the byte at address A6 and then increments A6 by 1 for the next
byte address. TST.B stmply tests thls next byte (without incrementing) - and
BNE says Branch Not Equal to zero. We
keep looping through the SIItng
until the final null byte is reached.

_OR!

SHIFT AND ROTATE INSTRUCTIONS

There are eight shift and rotate instructions that let you move the bit patterns in
data registers or memory to the left or right. By setting the shift count, which
determines the number of shifts, you can effectively relocate bits within bytes,
bytes within VK>rds, and VK>rds within longv..ords. Shifts also have an arithmetical
function.
We saw in Chapter 4 that in simple binary arithmetic, shifting a bit pattern
once to the left is equivalent to multiplying by 2 , while shifting once to the right
is the same as dividing by 2. So one obvious use of shifting instructions is as
an easy and fast w~ of multiplying and dividing by powers of 2.
HovJever, before \I.r'e rush around shifting bit patterns left and right, \I.r'e must
know if they represent signed or unsigned numbers. Recall that in signed 2's
complement numbers the most significant bit is a sign bit. If v..oe lose this while
shifting our anSVJet' may be wrong. Because of this problem the M68000 offers
tv,.Q types of shift: logical shift and arithmetic shift. These differ in the way they
handle the sign bit. Let's look at logical shifts first , since these are the easiest to
grasp.

LOGICAL SHIFT INSTRUCTIONS

A logical shift is mainly used on unsigned numbers. It moves the bit patterns in
a data register or memory a certain number of poSitions to the left (LSL ) or

right (LSR) by pushing in O's from one end or the other. As you push in a 0 ,
you can imagine the other bits in the register being displaced, nudging each

188

68000, 680/0, and 68020 Primer

other along, with one poor bit falling out at the other end! Rgures 6-9 and 610 show two typical word logical shifts.
The number of shifts performed, known as the shift count, is specified
here by an immediate soorce operand, indicated as always with the # symbol.
So in our examples, the contents of the 10VJer I.VOI'd of Dl get 3 left shifts and 2
right shifts. Immediate shift counts are aU()I..I.Ied in the range #1 to #8. This
obviously means that the immediate shift count maximum is #8.
To shift roore than 8 times, you need the fonnat
LSL. z

Om , On

LSR . z

Dm , Dn

where the source data register Dm holds the shift count. With this format you
can shift from 1 to 64 times, left or right. Only the bottom 6 bits (bits 0 through
5) of Dm are used to determine the shift count (which explains the limit of 64
for shift counts using this format). The correct technical term for this, which will
save us much verbiage later, is: data register source shift count = Dm modulo
64 (often abbreviated to Om mod 64). For example, if
Om

3 or 67 or 131 , then shift count

Om

63 or 127 or 191 , then shift count

Om mod 64

Om mod 64

or if
~

63

The rule is: keep dividing Dm by 64 until the remainder is less than 64. Most
clocks run on an (hours mod 12) basis, so the concept is everpresent.
Using Om as the shift count allows greater flexibility than using the immediate data shift count - for example, the shift count can be varied dynamically during a program. Immediate data shifts are for small fixed shifts. If the
shift count ever happens to be 0, by acddent or design , note that no shift occurs,
but the CCR is affected (see list beIOVJ).
The data size code z speCifies hOVJ many bits of the destination register will
be affected by the shift. In our LSL.W example, the lower 16 bits (word) of 01
VJet'e shifted. Had we used L or B the shifting VJol.L\d have included all 32 bits
or \.VOUld have been confined to the lOOJer 8 bits of D1.

LOGICAL SHIFTS AND THE CCR

What happens to the bits that get pushed out of the register as we shift? As
Figures 69 and 6 10 showed, they move after each shift into both the C (Carry)

Miscellaneous M6800D Instructions

LSL.W #3, 01

~~~

III!j

IN
4 3 2 1 0

cCRmffg1~

l sign-bit

I!.i
I!.i

"""d

~ Sign-b~8 sign-bit

DE STINATION

i';;;;;-;;;';;';';;~~IOIO 0010 0001010 1

,.

III!j
III!j

I!.i
I!.i

1615

31

., .,

"",="-I" 0

BEFORE

II!j
II!j

IIIIIIII

189

~.I....-;!;-.l...-.l...-.l...-.l...-~Ipc
31

23

AFTER

LSL.W #3, 01

CC

R XN

last bit
0"

non

1 00

V~
o1

e,0

5 2

9 8

"",dN

0,"

0001 OO()( 1010 1000

1 0

1615

31

-+

01

A 8
o

IIIIIIII

~..I...--..L-..L---,-~--,--~Ipc
31

23

.,

~~~~

:n~9 non-clearedlast bitword N+2

Z

~UfChingei

.,

4 3 2 1 0

Fig. 6-9 lSl.W #3, 0 1

II!j
II!j
II!j
II!j
II!j

I!.:
II!j
II!j
II!j

190

68000, 680/0, and 68020 Primer

., .,

0-+1 operand rc[Q] v.o

lSR
IRI

BEFORE

LSR .W #2 , 01

!3

2 1

~~~

..... .

J!j
J!j
J!j
J!j
J!j
J!j

word

21

CCRR
Ltgn-bit
DESTINATION

.JJ Sign-b~B sign-bit

O's In_ 1010 0010 0001 0101

A 2

5 2 1918

01

1615

31

1 5

I!.i
I!.i

IIIIIII

II'Jj

\::-'--;!!;---Jl...-Jl...-J----'.----'.---!Ip C
31
23
a

AFTER

LSR.W #2, 01

N
CC R X

last bit
out_C
non

~UfChingei

5 2

.L

o0

V~

~~~

.1.

00

cleared . ~

9 non-

word

lasl bit

zero

0",

0010 1000 1000 0101

2 8

8 5

01

1615

31

., .,

4 3 2 1 0

IIIIIII

\::-'--;!!;---Jl...-J----'.----'.----L---!Ip C
31

23

Fig. 610

lSR.W #2,01

'!l
'!l
'!l
'!l
'!l
'!l
'!l

I!.i
I!.i

Miscellaneous M68000 instruclions

191

and X (eXtend) nags of the CCR (Condition Code Register) . If you look at the
e or X flag after the shift instruction is completed, it tells you the value, 0 or 1,
of the last bit that was pushed 001. The N (Negative) and Z (Zero) nags tell you
whether the bits left in 01 after the shift represent a negative or zero value.
Remember that if IN'e are dealing with unsigned operands, the N flag is simply
reporting the state of the most significant bit. rather than the sign of the operand.
The V (oVerflow) flag is always cleared to O. The following list sums up the
CCR changes.
X flag: Set to the value of the last bit shifted oot of destination word.
Unaffected if the shift coont is 0, that is, if no actual shift is perfonned.
N flag: Set to 1 if On is negative after shift, otherwise cleared to O.
Z flag: Set to 1 if On is zero after shift.
V flag: Always cleared to O.
C flag: Set same as X fla g, but cleared to 0 if the shift coont is O. that
is, no actual shift performed.

LOGICAL SH tFT FOR MEMORY OPERANDS

logical shifts of bit patterns in memory are restricted in two ways. Only words
in memory can be shifted, and the shift coont must be 1.
The format for memory operand shifting is:
LSL . Vi
LSR . Vi

<8IIea>
<amea>

where < amea> is any alterable memory effective address mode.

The shift count is always 1, so it is not explidtly listed as a source operand.
The CCR changes just like a register logical shift:
X flag: Set to the value of the last bit shifted oot of destination word.
N flag: Set to 1 if memory word is negative after shift, that is, if bit
position 15 is 1 - otherwise cleared to O.
Z flag: Set to 1 if memory word is zero after shift.

V flag: Always cleared to O.

C flag: Set same as X flag (because shift count is never 0) .
In Rgure 6-1 1 we shift the word at (A6) one to the left. Note the changes
in the CCR.

192

68000,68010, and 68020 Primer

operand

lSl

IIIIIII

4 3 2 1 0

vi!

CCR X N
last bit
out

neg

1 0 00
cleared

non-

zero

last bit
out

4 'I A6
o

IIIIIII
Fig. 6-11

I
LSl.W (A6)

Miscellaneous M68000 Ins/ru ctions

193

PIIACTICAl APPlICATION
_ , Check !he podIy 01 an S-bII ASCO """""'" c..... !he I', In !he
ASCD code and set D3 IIyIe - 0 H..... J*II!r. sol D3 b!III - I Hodd podIy
(error condtIIon).
. . . . . - : The _
7-bit (bUs Q.6) ASCD set ....... In Appe"dlx F
IISIignscharocters to_ 01 !he 128 7-bitoomblnollonoSOOduu $7F. A.. cIIock
on the
of traMlidlllc:lrl. an 8th parity bit (bit 7) II 1CIIT_1h*_ added 10

accurac.v

code. The rule Is:

If !he number 01 1'. In !he 7bIt code Is odd, sol bit 7 - I

If !he number 01 1'. In !he 7-bIt code Is 01IIII1, clear bit 7 - 0

Hence aD valid 8-bIt ASCD codos IAo1II h... an ..... number 011', - and we caD
this an ..... parity chedc. As _ characIer Is '"""""'" we con cIIock to ... K
bit has been chopped ((I' added) during lhetran.--' 'en ThIn In mcnelabcnta
cheddng methods ....doble. but !he .....-odd podIy cIIock Is"""" lor ~
situations. Its chief aduarago Is 1hoI..", odd number 01 bit carupIIont wi change
a vabd ASCn code Into an Inua)d and lhaefore datecblble code.. The want kind
01 erron ON !hose that _
no ""-Ie trace. For ......... !he 7-bit ASCD
code lor nu....-oJ 5 Is $35. If !he lin bit 0 gels "loot" we 1MB . - . . $34. which
is the numeral 4. This type 01 error may not be de' :ted unaI yc1l corne 10 balance
your cIIockbook. The S-bII ..... polity ASCD code would ~1.1_1IIy J*:k up
this erooc
0110101 - $35 ~ ''5''
Dooppiny bit 0 from ''5'' gIwo
00110101 ; $35 = ''5''
Dooppiny bit 0 from "5" gIwo

en-:

An 8-bl. ASCD

0110100 - $34 - "4"

0110100 - $34 - "4"
10110100 - $84 - "4"
00110100 - $34 - INIIWO

_In

7-1>1 ASCO
S-bII ASCD

leMa B!IIe 01 01.

C...s:

Oillyle ; $A2 - 10100010 IAo1II glue D3 - I (31'sln 01 - odd)

01 IIyIe = $47 - 010001111Ao111 glue D3 - 0 (4 I'sln 01 - ..... ,
SGIuIJon: ,.,.",.... 6-2
SIIIn-

a.R. B

D3

m .B
.S

Dl

set D3 byte 0

Is Dl b.Jte all O's!

If,.. .. _

194

68000,68010, and 68020 Primer

LSL..

II,D!

If De we do

ODe

10lical

lIIitt left of tile bJte iD 01

BCC.S

aam

did 1 ' " paobod out!

to
_to_

U DO !boa ......,. I, dear

........_
U ,.. .. _

Dll.B

.,M

to8IIDT
alter III
.. __ .it 0 in II

l e l t _ oat"'1
It ...1 ..t _

BRA. 8

TST.B
IN:

811ft'
III _
_

_ _ _ toaam

11U ..

<rest of pracna. ....Ity III>

Ial'jGI
Go to oilier WIlp
<take _late lCtiaD for ....It, em>r>

BRA

,.,.",MII _ : Some altho _ _ ...... qIIIonII.S .......

which selects tho 1hart8-bll ..... _
Wbm 8 ....1II1hart ... _ (12810
+ 127 bytes) this option _ _ en __ iIiIIILwI. wmd
.1I..... 1nIINdIon.

In"

ARITHMETIC SHIFT INSTRUCTIONS

Figure 612 illustrates the arithmetic shift. As you can see arithmetic shifts are
very similar to the logical shifts of the previoos section. In fact, they use the
same source and destination formats and they shift destination bit patterns to
le'ft or right according to the given data size and shift coon1. (ASL equals
Arithmetic Shift Left and ASR equals Arithmetic Shift Right.) The difference is
that when signed numbers are shifted arithmetically, the processor protects you
against changes in the sign bit that might lead to erroneous results. For example,
if you want to divide - 4 by 2 using a right shift, the logical shift right is wrong!

Here's why:
In 2's complemenl- 4 = 11111100 (in byte formal)
Logical shift right-4 = 0111111 0 = + 126
Correct arithmetic shift right should be -2 = 1111111 0

The situation gets worse if you try to divide - 4 by 4 using a logical shift right
with a shift count of 2.
The problem is that when LSR pushes a 0 in at the left (most significant)
poSition of any negative number, it not only alters the sign bit (from 1 10 0), il
also moves the previous sign bit cIovm to bit position 6 - and the resulting

Miscellaneous M68000 Instructions

operand

BEFORE

ASL

ASL.L #3,01
3 2 1

CCR

fITfffl1~

~~~

wo<d N

III!,I

word N+2

I!.I
I!.I
III!,I
III!,I
III!,I

in

I!.I
I!.I
I!.I

IIIIIIII

195

~L....,:!:-L-L-L-L-~lpC

31

23

AFTER

ASL.L #3 , 01

4 3 2 1 0

C CR X N
o1

last bit
out

31

"",d N

10

neg~~~vei110W
non

1001 OHl( 11 00 0101 0001 000

9 4 C 5

~~r..

v~

word N+2
last bit
o u,

zero

1010 100c

0 A 8

01

1615

IIIIIIII

~L....,:!:-L-L-L-L-~lpC
31

23

Fig. 612

ASl.L #3,01

III!,I
III!,I
I!j

I!.I
I!.I
I!.I
III!,I
J!j
J!j

196

68000,68010, and 68020 Primer

answer doesn 't make sense, as far as signed arithmetic is concerned. LSR \AJOrks
fine with positive signed numbers, but clearly it would be nice to have a shift
right (divide by 21 that woo correctly with all signed numbers.
The ASR achieves this by pushing either a 0 or a 1 depending on the sign
of the number to be shifted. let's take our "-4 divided by 2" example again:
In 2'5 complement - 4 ~ 11111100 (in byte format)
Arithmetic shift right - 4 = 11111110 = - 2 which is correct
Because - 4 has a sign bit of 1, ASR pushes in a 1 from the left, presetVing the
sign of the dividend.
Similarly, multiplication by 2 using a left shift can sometimes go wrong with
signed numbers:
In 2'5 complement + 72 ~ 01001000 (in byte formatl
Shift left + 72 = 10010000 = -112 signed or + 144 unsigned
Here the answer is correct in unsigned arithmetic but wrong in signed arithmetic.
The problem is not with the shift itsel( but with the fact that + 144 exceeds the
signed capadty of an 8-bit byte (-126 to + 127). We have to live with this facl.
As we saw in the ADD instruction, the best we can do is to watch the V
(oVerflOVJ) flag in the CCR - this is our warning against signed arithmetic
errors. Yoo may recall that LSl always clears the V flag in the CCR. So LSL is
dangerous if you want to shift signed numbers. The solution is to use ASL when
shifting signed numbers - because ASL sets the V flag. ASL pushes in D's
from the right, just like LSL, but if a sign bit change is detected at any stage in
the shift, the V flag is set to 1. If no sign bit change occurs, the V flag is cleared
to O. Note that in a multiple left shift the sign bit may change several times, and
may actually end up with the same value it had initially. Nevertheless, V will be
set to 1 and will remain at 1 throughout the shift. As with all signed arithmetic
the obligation falls to the programmer to check the V flag - a V = 1 spells
danget:
let's summarize the differences between arithmetic and logical shifts:
ARI THMETIC AND LOGICAL SHIFTS - DtFFER ENCES

LSR shifts right by pushing in O's from the left.

ASR shifts right by replicating the sign bit from the left.
LSL and ASL both shift left by pushing in 0'5 from the right but LSL
clears the V (olkrflowl flag in the CCR.
ASl sets the V flag to 1 if any change of sign occurs during the shift.

Now let's summarize the similarities between arithmetic and logical shifts.

Miscellaneous M68000 Instructions

197

ARITHMETIC AND LOGICAL SHIFTS - SIMILARITI ES

Arithmetic and logical shifts share the same operand addressing modes:

ASL . z I<d3>, Dn
ASL . z om,on
ASL .W <ailea>

Immediate shift count from 1-8

Shift count 0. mod 64
Memory shift count = 1

ASR . z I<d3>, Dn
ASR . Z om,on
ASR . W <amea>
Logical and arithmetic shifts both push out bits at either end into the C and X

flags, and they both set the Nand Z flags in the same way. Rgure 6-12, a few
pages back, and Rgure 6-13 show two typical arithmetic shifts.
ARITHMETIC SHIFTS AND THE CCR
Summing up the CCR changes:

Xflag: Set to the value of the last hit shifted out of destination . Unaffected
if the shift count is 0, that is, if no actual shift performed.
N flag : Set to 1 if destination is negative after shift - othen.vise cleared
to

O.

Z flag: Set to 1 if destination is zero after shift.

V flag: Set to 1 if any change occurs to the sign bit at any stage of the
shift.
C flag: Set same as X flag, but deared to
is, no actual shift performed.

if the shift count is 0, that

PRACTICAL APPLICATION
I'NIIlMI: Cab 'U the arlthmetk: mean of two signed numbers, DO and 01,
10 tho . -...... """"'- and place the answer In 10wer word of 03. Signal
an fIIQI' If IIgnId IIIft9I is exceeded.

a.m.-,

The _
mean. !I<lrI1OIImes kn<>Nn as the .....90. is found
by adcIng tho ..., -'>ars IDgether and dMdtng by 2. The mean is exactly
haIIMy ~ the .... nurnbcs. A wry oommoo application ~ found in binary
.....a.. of lOlled ftIL We locate _ ..cord by spUtting the file into two
equol ports.
our _
wIIh the middle n!Cord t.IIs us which half of

198

68000,68010, and 68020 Primer

d iperand

BEFORE

rei!

00

sign-bit ASH

ASR.L #2,01

4 3 2 1

eeRfEI%r!!~
in

31

IIIIIIII

!;-;-~!;----'---'---'---'--L~I p e

31

23

AFTER

ASR.L #2, 01

4 3 2 1 0

L-_ _ _ _---'

eeR XNZV~
01000

last bit
001 .

neg
111 1

"'-"

F 4
31

1010 011

Ii
' ' ~ .~
'

nonlast bit
zero no out
overflow

0010 1000 1000 0101

6 2 8

8 5

01

1615

IIIIIIII

~31~L-~~~-L--L--L--L--L__~lpe
Fig. 613 ASR.L #2,01

J!,j
J!,j
JI!j
JI!j
JI!j
JI!j

II!.i
II!.i
II!.i

Miscellaneous M68000 loslrucflOos

199

the file contains the target. Ilk then split that half of the file In two, and so on
until we " home" In on the desim! recooi AI each stage of the binary sean:h we
need to calculate the mean of t\I.o recad numbers in order 10 locate the mktway
n!Ca'd.

eMIl: Two 16-bit signed numbers In DO and 01

C.sfS:

DO = 2979 = SOBA3 01 = 4261 = SlOAS

DO + 01 = 7240 = $IC48 (no owrflowl
03 = 1'2 x 7240 = 3620 = S0E24
DO - -3 = SFFFD 01 = -5 = SFFFB
DO + 01 = -8 = SFFFB (no owrflowl
03 = 112 x -8 = -4 = SFFFC
DO = 43981 = SABCO 01 = 26341 = $66E5
DO + 01 = 70322 = S112B2 (owrflow """,I

Solution: Prot/,.", 63
)I)VE.

DO . D3

ADO. W

01 ,03

BVS
ASIl.'

E!IIlOR
'I,D3

DO word now in D3 word

03 word : DO + 01
Branch to ERROR if V flag set
Divide 03 word by 2
Ignore any reuinder
03 now has .ean of DO , OI
(nearest whole nuaber )

with correct sign.

<rest of prograa>

NEXT_JOB Go on to other thIngs

<signal an error>
<take appropriate action>
BRA

Eli)

Prot/,.,. No,.,: If DO + Oils 1!IIeIl, the mean formed In D3 Is exoct but If DO

+ Oils odd, the mean In D3 will be 0.5 too low. Our IImp1if1ed problem called
for the neamt whole number, so we have ignon!d a~ mnainder when dividing
by 2. There Is an easy VRI1 to distinguish these I\A.o cases. When ~ ASR an
even number the bit pushed oot Is a 0, but when ~ ASR an odd number the
bit pushed out Is a \. Since the bit Is pushed out Into the C and X Hags of the
CCR, we can easily test the C flag with a BCS or sec and lilke approprtate
action.

200

68000,68010, and 68020 Primer

Table 62

Summary o f Shift Instructions

Opcode

Operand

ASl.lJW/B
ASR.lJW/B
ASlW
ASRW

Om ,On or # < d3>,On

lSl.lJW/ B
l SR.lJW/B

Om,On or # < d3 >, On

l Sl.W
l SR.W

< amea >

CCR Changes

< amea >

X N" Z VO C"

< amea> - alterable memory addressing modes '" (An), (An) +, (A n)

d iAn), d IAn,XU, Abs.W, Abs.l
l <d3 > - 3 bits immediate data - Shift Count range 1 - 8
CCR symbols : _means unchanged , means changed according to CCR rules, 0 meanS always set
'00

Table 6-2 gives a condse summary of all the shift instructions and hovJ the

CCR is affected.

ROTATES
Rotating the bits in a register is very much like logical shifting as described
above, except that the displaced bits that get pushed oot at either end are
entered back into the register at the other end. As the IJJOrd "rotate" suggests,
you can imagine the register bit patterns moving clockwise (rotate left) or
counterclockwise (rotate right). As with shifts you can spedfy the number of
times the bits are rotated, using either immediate data or a data register to set
the shift count. The rotate instruction formats for source/destination are identical
to those for shifting. The big difference is what happens to the displaced bits as
they rotate. Table 6-3 summarizes the four Rotate variants.

ROR - ROtate Right

ROl - ROtate l eft

Miscellaneous M68000 Instructions

201

Table 6-3 Summary of Rotate Instructions

Opcode

Operand

ROL.LJW/B
ROR .LJW/B

Om ,On or # < d3> ,On

ROL.W
ROR.w

< a mea>

RO XL.LJW/B
ROXR.LJW/B

Om ,On or # < d3>,On

ROXL.W
ROXR.w

< a mea>

CCR Changes

X N-

z va C

< amea> .. me mory al te rable addressing modes - (An) , (An) + , (An)

dIAn), d{An,Xi), Abs.W, Abs.l
# < d3> .. 3 bits immediate date .. Shift Count range 1 - 8
CCR symbols: _ means unchanged, 'means changed according to CCR ru les, 0 means always set
100

ROXR - ROtate with eXtend Right

ROXL - ROtate with eXtend Left
They all accept the three formats we gave for shifts, which are:
RDR . z
ROR. z
RDR. z

Om ,On
Rotate On t . z} Right (Om mod 64 ) times
I<d3>,On Rotate Dn{. z} Right d3 times (1 - 8)
<amea>
Rotate memory{.z} Right once only

Figure 6-14 illustrates ho.v the displaced bits always pass into the C flag
of the CCR In the RORIROl variants, the displaced bits also move directly into
the other end of the register, and the X flag is unchanged.

In the ROXRlROXL variants, the displaced bit moves into both the C and
X flags. The previous X flag bit gets pushed back into the register. The X flag
is, as usual, playing the role of an additional register bit, so:

ROXRlROXL.L rotates 33 bits (lon!j\OOfd plus XI

ROXRlROXL. W rotates 17 bits (IM?rd plus Xl
ROXRlROXL.B rotates 9 bits (byte plus XI
All rotates, like logical shifts, clear the V flag - so you get no warning of
signed arithmetical errors.

202

68000,68010, and 68020 Primer

~I,

Operand

.4

ROL
ROtate LeU

V- Q

Operand

[[b,

Operand

I.(]

;J

ROR
ROtate Right

V.Q
ROXL
ROtate Left
with EXtend

V.Q

Operand

ROXR
ROtate Rig ht
with EXtend

v-a

Fig. 6.14

Rotates: General Diagrams

Here is an application to further illuminate the nature of rotates.

Program 6-4

Add the 4 Signed Bytes in a Longword

DO contains 4 bytes each representing signed numbers :

Byte 1 '" bits 0-7 (lower-lower byte)
Byte 2 .. bits 8-15 (upper-lower byte)

Byte 3 '" bits 16-23 (lower-upper byte)

Byte 4 '" bits 24-31 (upper-upper byte)

Place the sum of these 4 numbers in 01.

Use 03 as temp (scratch) register .
, Preserve value of DO and 03.

Save scratch register 03

MOVE. L
CLR. L

03 , -(SP)
03

eLlt L
WOVE. B

01
00 , 01

Clear longword 01

ROR .L

'8,00

Byte 2 to lo\\'er-lower byte position

(Byte 3 to upper-lo.,,'er byte of DO)

Clear longword 03
Byte 1 to D1

Miscellaneous M68000 InSlruc!ions

MOVE . B
ADO.'
ROR. L

MOVE . B

ADD.W
KOR. L

MOVE.B
ADO .W
ROR . L

MOVE . L

203

(Byte 4 to lower -upper byte of 00 )

(Byte 1 to upper-upper byte of 00 )
00 ,03
Byte 2 to 03
03 , 01
Add byte 2 to byte 1 : 01
#8, 00
Byte 3 to lower-lower byte position
(Byte 4 to upper-Iov.er byte of 00)
(Byte 1 to lower-upper byte of DO )
(Byte 2 to upper-upper byte of 00 )
00 ,03
Byte 3 to 03
D3,01
Add byte 3 to 01
Byte 4 to lo\\'er-lower byte position
' 8,00
(Byte 1 to upper-lo\\'er byte of DO )
(Byte 2 to lower-upper byte of DO )
(Byte 3 to upper-upper byte of DO )
Byte 4 to 03
00.03
03,01
Add byte 4 to word 01
Byt e 1 to lower-lower byte position
' 8, 00
(Byt e 2 to upper -lower byte of DO )
(Byte 3 to lower -upper byte of DO )
(Byte 4 to upper-upper byte of DO )
(SP)+,03 Restore 03 from stack

00 , after a total of 32 rotates , has original value restored .

01 contains sum of bytes 1-4.

We used D3 and ADD. W to avoid the dangers of overfIOVJ. S umming foo r

signed bytes cannot exceed the 16-bit signed range but can exceed the 8-bit
signed range - so \Ale cannot use
ADD . B

00,01

immediately after the ROR unless \Ale check for overfiOVJ.

There are, of coorse, many differe nt ways of " isolating" the bytes or \IJOrds
in a longword. SWAP, for example, is often used in conjunction with a rotate.
(We'll see more o f SWAP later in this chapter:) Let's revamp Program 6-4 using

SWAP to add just bytes 1, 3, and 4.

Program 6-5

Add Bytes 1, 3, and 4 of a Longword

bytes each representing signed numbers .

0-7 (lov.er - lov.er byte) .
8-15 (upper-Iov.'er byte).
16-23 (lower-upper byte ).
24 -31 (upper -upper byte).

DO contains 4
Byte 1: bits
Byte 2 : bits
Byte 3 = bi ts
Byte 4 = bits

204

68000,68010, and 68020 Primer

Place the sum of bytes 1, 3, and 4 numbers in 01.

Use 03 as temp (scratch I register .
Preserve value of DO and 03.
IoK>VDI. L

CLR. L
CLR. L
MOVE . B
SWAP

MOVE.B
ADD. I'.'

ROR.L

MOVE. B
ADD. W

MDVEM . L

DO/03, - (SP) Stack 'em

Clear long word 03
Clear long lIt'ord 01
Byt e 1 to 01
00.01
Reverse words of DO
DO
Byte 3 is now lower-lov.'er byte 00
Byte 4 is upper-lower byte DO
(Byte 2 is upper-upper byte DO )
(Byte 1 is lower-upper byte DO )
00,03
Byte 3 to 03
03,01
Add Byte 3 to Byte 1 = 01
#8 , 00
Byte 4 to lower-lower byte position
(Byte 1 to upper-lower byte of 001
(Byte 2 to lower-upper byte of 00 )
(Byte 3 to upper-upper byte of 00)
00,03
Byte 4 to 03
Add Byte 4 to 01
03 , 01
(SP)+,00/D3 Restore 00,03 from stack

03
01

, Dl contains sum of bytes 1, 3, and 4.

BIT TESTING AND SETTING

In Chapter 4 we met the TST.z instruction, which tested the whole operand (L,
W, or B) for zero and set the CCR flags accordingly. In the next group of
instructions we refine this idea to include testing of individual bits in a variety of
situations.
BTST - TEST A BIT

8TST allOVJs you to test any bit in a data register, or any bit in a byte of memory.
The result of the test, just as with TST, is reflected in the Z flag of the CCR:
Tested bit
Tested bit

0 sets Z flag to 1
1 clears Z flag to 0

The other flags in the CCR are unchanged.

Miscellaneous M6BOOO InSfructions

205

TST, as we saw in Chapter 4 , tests a whole byte, word, or 10ng'M)Td for

zero, whereas BTST tests only a single bit. BTST has the following formats,
BTST. L
BTST. L

BTST. B
BTST. B

"", On

I<d5>. Dn
DII . <lIIea>
I<d3>,<mea>

Test
Test
Test
Test

the (Om mod 32)th bit of On

the (d5 )th bit of On
the {Om mod 81th bit of <mea> byte
the (d3 )th bit of ~ea> byte

< d5> represents a 5-bit number, 0-31. < d3 > is a 3-bit number, 0-7.
Note that < mea > here excludes immediate mode as a valid destination.
Since the destination is not altered by BTST, relative mode destinations are

allowed.
The source operand, indicating the position of the bit to be tested, can
either be a number in a data register or an immediate constant. Remember that
bit position 0 is the first , least significant bit in all cases.
The actual range limits for bit position are obviously (0-31) for registers
and (0-7) for memory bytes, and this is reflected in the formats. If you try 10
test a bit position outside these ranges, the processor will simply reduce modulo
32 or modulo 8 as we have indicated above.
Since only memory bytes can be tested with BTST, it may sometimes be
necessary to move from memory to a Dn for more elaborate tests.
The data size codes are implied by the format, and therefore optional for
most assemblers. \Ne prefer to use them in order to clarify our intent.
Here are two simple examples of using BTST.

Program 6-6

Testing for Odd or Even Using BTST

03 contains an unsigned number . If it is even , leave it alone .

If it is odd, add 1 to make it even.
BTST.L

#0 ,03

BEQ

EVEN

ADDQ. L

#1 , 03
ERROR

Bes

Is bit 0 of 03 = O?
If Yes 03 is even - so branch
If No 03 is odd - so add 1
03 too big for 32-bit
unsigned. Carry detected .

EVEN

<rest of program>

ERROR

<deal with range error>

Program 6-6 relies on the elementary fact that the least significant bit of an
even binary number is O. Making odd numbers even is a useful trick for adjusting

M68000 addresses to the nearest word boundary.

206

68000,68010, and 68020 Primer

Program 6-7

Tes t Employee Status Using BTST

AO points to employee record in memory . word 1 of record has

employee rD . LoII'er byte of word 2 is employee status byte:
Bit 0 : 0 for male; 1 for female
Bit 1 ::: 0 for FT (full time ); 1 for PT (part tille )
Bit 2 : 0 for HO (head office) staff ; I for branch staff
Increase 06 counter by 1 if emp loyee is female / FT/ HO
"'hen we enter this program segment, 06 contai ns subtotal of
such employees.
BTST.8

#O , 2(AO ) Test sex bi t

IGNORE
Bypass male i . e. if bit 0 : 0
8TST. B #1 , 2(AO ) Tes t FT/ PT
IGNORE
Bypass PT i.e. if bit 1 : 1
BNE
BTST.8
#2 , 2(AO ) Test HO/ Branch
Bypass Branch i. e. if bit 2 : 1
BNE
IGNORE
Add 1 for target employee
ADDQ. L
#1 ,06
IGNORE
<rest of program>
Thi s would form part of a general program for counting the
number of employees in each category.
BEQ

Here v.oe are testing the byte in memory at address AO+2, hence the
destination operand is 2(AO). For repeated tests of 2(AO), we """,Id probably
find it quicker to move 2(AO) to a data register since \.\.Ie u.ould save on <ea>
calculations and memory fetches.
TEST AND CHANGE A BIT

Three variants of 6TST are:

6CLR - Test a bit and clear
BSET - Test a bit and set
BCHG - Test a bit and change
They not only test the specified bit and set the Z flag just like BT5T, but they
then proceed to unconditionally modify the tested bit as indicated by the mnemonic.
The formats differ slightly from 8TST insofar as only alterable memory
operands are allQl..Ved - which is natural when you consider that BCLRlBSETI
BCHG actually alter the destination:
BCLR .L
BCLR. L

Do,On

I<d6>, On

Test the (Om mod 32)th bit of On

Test the (d6 mod 32) th bit of On

Miscellaneous M68000 Instructions

BCLR. B
BeLR. B

Om.,<amea>
I<d3>, <amea>

207

Test the {Om. mod 8)th bit of <amea> byte

Test the {d3)th bit of <amea> byte

Having adjusted the Z flag, BCLR clears the spedfied destination bit to O.
BSET. L
BSE!. L
BSE!. B
BSE:T. B

Om, on
I<d6>,on

Dm,<amea>
I<d3>, <amea>

Test
Test
Test
Test

the
the
the
the

(Om mod 32)th bit of On

(d6 mod 32)th bit of On
(Om mod 81th bit of <amea> byte
(d3)th bit of <amea> byte

Having adjusted the Z flag , BSET sets the spedfied destination bit to 1.

SCHG . L
SCHG.L
BCHG. B
BCHG. B

Om , On

I<d6>,On
Om, <amea>
I<d3>. <amea>

Test
Test
Test
Test

the (Om mod 32 )th bit of On

the (d6 mod 32 )th bit of On
the (Om mod 8)th bit of <amea> byte
the (d3) th bit of <amea> byte

Having adjusted the Z flag , BCHG reverses the specified destination bit, l--.?O
or O-Jo 1.
The three bit test and set instructions are commonly used simply to reset
selected bits, ignoring the test aspect altogether.
Using the data for Program 6~ 7, let us transfer someone to head office by
changing the employee status byte.

Program 6-8

Change Employee Status Using BCLR

AO points to employee record in memory. Word 1 of record has

employee 10. Lower byte of word 2 is employee status byte :
Bit 0 = 0 for male ; 1 for female
Bit 1 '" 0 for FT (full time); 1 for PT (part time)
Bit 2 = 0 for HO staff; 1 for branch staff
Demote employee to head office by clearing bit 2
#2 , 2(AO ) Bit 2 of byte 2(AO) ->0
WHOOPS
Employee was HO already
<rest of program>
BCLR. B

seQ

WHOOPS

<check our records>

BCLR tests bit 2 before clearing it. SEQ will branch if bit 2
was already 0 -- revealing a possible error in our employee
selection or records .

208

68000,68010, and 68020 Primer

BCHG is useful for controlling activity during loops, acting as a flip-flop or

switch. For example:
Program 6-SA
LOOP

Alternating Jobs Using SSE! and BCHG

BSE'J'. L
BCHG. L

10 , 02
10, 02

BEQ

JOBO

<do jobl>
BRA

JOSO

Sec -

LOOP

<do jobO>
BRA

Start with bit 0 of 02 = 1

Flip 0->1 or 1->0
Do jobO on even numbered loops
Do jobl on odd numbered loops

LOOP

~ach

time we reach LOOP we test bit 0 of 02 and set or clear

the Z flag. We next flip bit 0 from 0 t o 1, or 1 to O. Then we test
the Z flag and do ei ther jobO or jobl . The jobs therefore
alternate as we loop . To avoid endless looping we assume that
one or another job contains some test for loop exit.
SET ON CONDITION

Sec is a set of single--operand, byte-only instructions, all using the fonnat

Scc l. B} <adea>
The byte at < adea > is set to $FF (all 1's) if condition cc is true, and set to $00
(all D's) if condition cc is false. Since the destination is altered by $cc, only
< adea> modes are permitted.
Sec has 16 variations corresponding to the condition mnemonics given by
the letters cc. Each condition is based on the state of the CCR flags at the time
the test is made. We have already seen some of these in Chapter 4 under the
section on Bec (Branch on Condition). Table 6-4 sho\.vs the complete list of the
cc codes as used with Sec, Bec and OBec (which VJe will learn more about

laterl.
The essential function of Scc is to store the result of a CCR test, so you
can use the result later in the program after the original CCR has been subject
to change. We have seen that most instructions alter the CCR in some way or
other: This can be a nuisance if you want to delay a conditional action.
HOW THE cc's WORK

The various cc conditions range from simple one-flag CCR conditions to complex

Boolean expressions based on several flags.

Miscellaneous M68ODO Instructions

Table 64

Conditon Codes for Bce, OBee and Sec

cc
Mnemonic Condition

CC
CS
EQ
F

GE
GT
HI

LE
LS
LT
MI

NE
PL
T
VC
VS

Boolean Formula

Carry Clear
-C
Carry Set
C
Equal to
Z
False
0
(N AV) + (- N A-V)
Greater or equal
Greater than
(N AVA-Z) + (- N A- VA-Z)
Higher than
- CA-Z
Z + (NA-V) + (- N AV)
less or equal
lower or same
C+Z
less than
INA-V) + I-NAV)
Minus
N
Not equal
-Z
Plu s
-N
True
1
Overflow Clear - V
Overflow Set
V

legend : - - logical NOT, +

T nOI used wilh Bcc

209

Relevant
N umber Mode

unsigned
unSigned

all
all
signed
signed
unSigned
signed
unSigned
signed
signed
,II
signed
all
signed
signed

logical OR , " - logical AND, F and

The single flag conditions have already been explained under Bec. These
8 basic conditions rely on the state of just one of the N, Z, V, or C flags. These
flags can be considered to be Boolean variables taking the value 1 for true and
for false. They can be combined as shCMIn to represent more complex conditions. Table 6-4 sh()I..Vs the logical calculations performed by the M68000 to
determine true or false to the typical questions VJe pose regarding the relations
bet\.veen numbers - greater, less, equal, and SO on.

A TYPICAL MUlTIflAG cc DISSECTED

Take, for example, the condition HI (Higher [than]) , listed in our table as an
unsigned mode condition. If yc>U want to compare tv.o unsigned numbers in
DO and D1 , ),Kll1 can write
SUB . L

00,01

210

68000, 68010, and 68020 Primer

ThiS subtracts DO from Dl, sets the CCR flags, and replaces D1 by the difference
beru.een Dl and DO. Or, as we'll detail later, you can write
CMP. L

00 , 01

which performs the subtraction and sets the CCR flags, but does not alter 01.
To answer the question "Is unsigned 01 higher than unsigned DO?" we
need to look at the C and Z flags after a SUB or CMF' If Z ~ 1 then we have
a zero difference, so 01 = DO, hence HI is false. Likewise, if C = 1 we must
have had a bol"J'O',.V, meaning that 01 is lov;er than DO, so HI is again false.
l-ience the HI condition is true only if (C = 0 and Z = 0) and this explains our
Boolean formula: HI = - CI\-Z which we read as NOT-C and NOT-Z.
The effect of
SHI

05

Set 05 i f HIgher

for example, is:

If (C ~ 0 AND Z ~ 0) place $FF in lower byte of D5.
Otherwise place $00 in lower byte of D5.

D51Q\.1.1er byte therefore remembers the result of the HI test, and can be consulted
later. Similarly,
BHI

<l abe l >

Branch i f HIghe r

says branch to < label> onty if (C ~ O AND Z ~ O) .

The processor performs such tests blindly regardless of what your previous
program steps have done. It is up to ~ , in fact, to provide meaning to the
condition HI by a previous SUB or CMP step using the two unsigned numbers
you wish to compare.
Each of the other compound conditions can be analyzed in the same way,
looking at the various flags follOVJing a SUB or CMP operation on the two
numbers being compared.
SIGNED AND UNSIGNED cc's

II should be clear that questions like "greater than?" or "less than?" can only
be resolved when you knOVJ which number mode is involved: signed or unsigned. Is " 1()(x)()()()()" greater than "(x)()()()1l1 "? The anS\VeT is yes for unsigned, but no for signed numbers.

Miscellaneous M68000 inSlruclions

211

On the other hand the questions "equal?" and "zero?" can be answered
regardless of number mode. The final column of Table 6-4 indicates which
conditions apply to which mode. Note that Motorola has chosen " higher~owerl
same" for unsigned comparisons, and "greaterlless" for signed comparisons.
You can try out the Boolean formulas by subtracting various signed and
unsigned numbers and noting the CCR flags, (C = 0, N = 1, etc.). Then substitute the flag values, or 1, in each Boolean formula, by applying the following
rules:

0+0=0
1+0 = 1

oA 0 =

- (A

- (A

False OR false = false

True OR false = true
False AND false = false

1A 0 = 0

True AND false

1A 1 = 1
- 0= 1
- 1 =0

NOT false = true

NOT true = false

B) = (- A

B) = (- A

- B)

+ - B)

= false
True AND true = true

NOT (A OR B) = (NOT - A AND

NOT-B)
NOT (A AND B) = (NOT - A OR
NOT - B)

Each cc condition will reduce to 0 (false) or 1 (true), and Sec will record this
fact in any chosen register or memory location.
The rules expressed so concisely in Boolean algebra merit close study.
They are worth whole chapters on the meaning of carry and overfiOUJ. Once
you have convinced yourself that all of the rules work, you can relax and leave
the M68000 to do the Boolean evaluations for you. It's rather good at this.
51 AND 5F
Two of the ee's, T and F, are actually unconditional.

ST
SF

<adea>
<adea>

Always sets <adea> to $FF (t rue )

Always sets <adea> to $00 (false )

Note that VJe do not use T or F with Bec. BRA is used for BT (Branch Always),
while BF (Never Branch) is a structured programmer's slogan rather than an
instruction.

212

68000, 680/0, and 68020 Primer

TAS -INDIVISIBLE TEST AND SET OPERAND

Our final instruction in the bit manipulation group is TAS (Test And Set operand)
which hides a subtle trick beneath its simple exterior.

TAS(, BI

<adea>

This line first tests the byte at < adea> and then sets the Z and N flags in the
CCR (Z = 1 if byte is zero, N = 1 if sign bit 7 is 1). Finally, lAS unconditionally
sets the destination sign bit 7 to 1 - fordng the byte to be negative.
The unusual trick built into this instruction is that the lAS operation is
indivisible - meaning that a spedal read-modify-write memory cycle is employed , which can not be interrupted, and no other program, processor, or device
in the system can access the operand until TAS is finished. Even the normal bus
error routines are modified to keep TAS indivisible. Why all this trickery just to
test and set a byte?
The reason is the need to provide control and synchronization in various
delicate situations that can occur in today's complex M68000-based multitasking and multiprocessing systems. The general idea is that a resource, which can
be almost anything - from a disk file or bank of memory to an I/O device, or
~ n an entire microprocessor - can be shared by different user jobs. Both
hardware and software methods are used to regulate this sharing. \krious flags,
semaphores, and priority and queuing algorithms are employed to control who
gels what and when and for hcAAllong. Typically, the program grabbing a resource
flags it as "in use" by setting an agreed value in an assigned status bit or byte.
The resource is eventually relinquished by clearing the status flag so that other
jobs are free to access it.
Suppose, for example, that we have assigned a byte at address $1 ()(X),
which signals to all user programs as follows:
($1000) = $00 means employee file free to be updated
($1000) nonzero means employee fi le in use - keep off
Such a byte might be given a fancy name such as employee file access status
byte. We have suggested an absolute address so that there is a fixed place where
any user program can test the file status.
Without TAS, our program might proceed as foJlOOJs .

Program 6-9 File Locking without TAS

WAIT

TST .B
BNE .S

$1000
WAIT

IS file free?
No -- keep trying

Miscellaneous M68000 InSfructio ns

ST

$1 000

213

-Grab - file by putting $FF

in byte (SlOOOl

Thi s \\'arns others that

file is busy

ST i s equivalent t o MOVE . B #SFF , $1 000

<process fil e>

CLR. 8

SlOOO

Rel inqui sh fil e by

c learing (S lOOO) t o sao

<rest of program>

ThiS seems fine, but what if an interrupt occurs just before the 5T $1000
instruction? The interrupting program or process may well do a TST.B $1000
and , finding the file free , set ($1000) to busy, then proceed to update the fi le.
When our program resumes at ST $1000, we also attempt to modify the file,
unaware of the file status change - with possibly dire consequences.
Let's see how TAS helps .
Program 6-1 0 File Locking with TAS

WAIT

TAS

$1000

BNE

WAIT

<process fil e>

CLR . B

$1000

Test (S1000) and adj ust

the OCR. Then se t (S1 000)
negative = $80
File is busy el sewhere so
try again
Fi Ie was f ree . but we have
grabbed it. It is flagged
busy t o others .
Re li nquish file

by setting st atus by t e : $00

<res t of program>

The CLRB is vital. Without it, jobs can cycle endlessly waiting to access the file
- and the sooner you can CLRB, the better. The TAS solution , unlike the
TST/ST approach , ensures that the sequence of testing and setting the status
flag cannot be interrupted. It is important to note that the BNE WAIT line is
effectively testing the status byte as it was before TAS set it to $80. Any interrupts
or exceptions occurring after lAS but before the BNE v.ould not affect the BNE
test, since the CCR is always saved and restored (as part of the interrupted
program's context).
In real-VJOrld time-sharing applications, the simple file-locking procedure
outlined above v.Q.Ild naturally be more sophisticated, including such concepts
as read-only files, public-restricted files, file-locking by record, and so on. Since

214

68000, 68010, and 68020 Primer

TAS sets just bit 7 (the sign-bit) of the operand (status byte) to signal "busy",
the other six bits of the byte can be used to signal other properties of the shared
resource. If so, the BNE (Branch Not Equal zero) after TAS can be replaced by
BMI (Branch MInus), which tests the N flag.

COMPARE WITH THE CMP fAMILY Of

INSTRUCTIONS
The next group of instructions allows you to compare the source and destination
operands.
The key notion in the CMP instructions is that the processor goes through
the motions of SUB (that is, subtract source from destination) but does not alter
the destination. Recall that SUB replaces the destination with the calculated

difference. All that CMP does, in fact, is to change the CCR flags (N, Z, V, and
C) as though it had perfonned a SUB. After CMp, or its variants, you can use
any of the conditional instructions which depend on the cc conditions shown in

Table 6-4.
There are tVJO points to remember concerning cc and CMP First, we are
always testing "destination <condition> source", where < condition> says, for
example, higher than, less than, etc. It is not uncommon for programmers to
get this the wrong Wi!J} round, because instructions are written: source,destination.
There are four CMP formats, used according to the type of operands being
compared:

CMP .z <ea> . On
CMPA . Z <ea>, An
CMPI.z I<data>,<adea>
CMPM .z (Am)+, (An)+

Compare
COlllpare
Compare
Compare

anything with value in z of On

any L or Wsource wi th An
immediate data with destinati on
successive memory addresses

CCR changes as does SUB, except CMP does not change the X flag.
Here are some examples:
Program

6- 11

Compare Unsigned Longwords

CMP.L

03 , 04

BEQ

SAME

SHI

04HI

Compare 03 and 04 longwords

Branch to SAME if 03 : 04
Prom here on we know 03,04
are unequal
Branch to 04HI if 04 uns igned
is higher than 03 unsigned
From here on we know 04 is not
higher

Miscellaneous M68000 InSlruelions

SAME

Branch to 03HI if 04 lUlsigned

is lower than 03
<we should never reach here! >
<see comments below>
<03=04 case processed here>

D4HI

<D4

D3HI

<03 higher case processed here>

D3HI

BCS

higher case processed here>

The BLS branch would test "lower/ same"; BNE would test
"lUlequal " -- so there are plenty of overlapping choices after a
eM? on lUlsigned numbers. In the above sequence of conditional
branches, we actually cover all possi ble relations between 03
and 04 . Often you can avoid a condit ional branch because
previous branches have excluded all but one remaining
possibility . In the above, BeS could be replaced with BRA.
Recall that the C flag after eM? or SUB means "borrow" rather
than carry -- so BeS tests source higher than destination .

Program 6-12 Compare Immediate: Signed Bytes

Is signed byte at address $4000
greater / less/equal to -I?
BLE
FROZEN
Branch if less or equal
<process here if ($4000 ) byte greater than -1>

CMP J. B

FROZEN

#- 1, $4 000

<process here if (S4000) byte less than or equal t o -1>

Signed comparisons use B8Q/ BGE/ BGT/ BLE. See Table 6-4
CMPI source N<data> will be stored in one or two extension
words depending on size data code.
Program 6-13 Compare Two ASCII Strings in Memory

ASCII string 1 has pointer AI; ASCII String 2 has pointer A2 .

Both strings terminate with an ASCII NUL (SOO )
Byte 06 is set to $00 if mismatch. $FF if strings identical
Word 07 COlUlts number of matched characters

ST

06

CLR.w

01

Set SfF in indicator byte 06

Clear matched character count

215

216

68000, 68010, and 68020 Primer

LOOP

CMPM.B
BNE
TST .B

(Al) +, (A2)+
IIlISJlAT

SEQ

ENIlOK

ADDQ .

11 , 07

- HAl)

BRA

LOOP

MI5.\lAT

CLR . B

os

ENIlOK

<rest of program>

Compare bytes / inc pointer

Bytes diff er
NUL reached?
Yes -- both bytes NUL
Increase mat ch count
On to next characters
Set $00 in indi cator byte D6

The bytes we are comparing are simpl y tested for NE (Not

Equal ), so we are not concerned with signed/ unsigned
interpretat ions. If we were interested in lexicographic
sequenci ng, e. g. Is string 1 ahead of string 2 in the dictionary? ,
we could test with BHI or BLS (unsigned) and set some
indication in 06 when a mismatch occurs .
Note t he TST. B -1 (AI ) which tests the byte just compared.
Since (AI )+ has incremented the poi nter Al by I (byte), we use
an off set of -1 with a d(AI ) operand. -l(AI ) is not to be
confused with - (AI ). The l atter would move our pointer back
with bi zarre results .

CMPA - COMPARE ADDRESS

The CMPA variant of CMp, like the SUBA variant of SUB, is used only when
the destination is an address register. I-iowever, there is a subtle but important
difference between CMPA and SUBA. SUBA, as with all purely artthmetic
operations on An's, does not affect the CCR - but CMPA IMlUld not make any

sense unless the CCR reflected the various N, 2, V, and C changes. Without
these \Ne IM)Uld be unable to test the cc conditions, such as, are these tu..Q
addresses greater/equallless? So CMPA breaks the rules and sets up the CCR
for us.
CMPA does not allow a byte data size code, and when you do a CMPA.W
comparison, the \.VOrd source is sign-bit extended to 32 bits before the subtraction
is performed. In spite of this, remember that addresses are essentially positive
unsigned values and, as we will see in the next example, \Ne normally use the
unsigned cc tests after CMPA.
CMPA is most useful when we need to check if an address pointer is within
bounds. We have seen several examples of An being incremented/decremented
in various ways, using (An) +, -(An), ADDA, SUBA, and stack operations. In
many cases \Ne must guard against An pointing over or below certain memory
limits. A simple example follQI.VS.

Miscellaneous M68000 Instructions

217

Program 6-14 CMPA: Private User Stack Limit Check

We have established a small private stack with stack pointer
1.2 . 1.0 points to the base of this stack. Al points to the
limit of the stack. The stack grows do~n in memory from 1.0 to
Al as ~'e push on it. Provide simple checks that A2 does not
exceed the stack limits. Normally 1.0 >= 1.2 >= AI .
MOVE . W

CMPA. L

01 , - (1.2)
1.1 ,1.2

FULL

BEQ
BCS

ERROR_2
<stack OK -- continue>
MOVE.L
(1.2 )+, 07
eMPA . L

BeS

typical PULL
Reached stack base?
" Below" stack base error

fULL

<stack OK -- continue>
<warning stack full>

ERROR_l

<recover last save and adjust stack>

ERROR_2

<check last restore and adjust stack>

typical PUSH
Is stack full !
Yes. just -- so branch
"Below" stack base error

The first CMPA does {A2 - AI } so Z is set (SEQ) only if A2=Al ,

meaning that the stack is exactly full . C is set (=borrow) only
if Al is higher than 1.2 , meaning that stack pointer is beyond
limit. BEQ test alone is inadequate since pushing can
decrement 1.2 by 2 or 4.
The second CMPA does {AO - A2 l , so BCS means that A2 i s
higher than AO , hence we have somehow managed to pull !lore than
we pushed! Getting "below" the stack base indicates a
programming error , whereas getting "above" the stack limit
simply means over-usage .

Closely associated with CMP and conditional branching is a composite

instruction called oSec, which gives the M68000 yet another edge over the
competition. Let's see why.

DBee - TEST cc, DECREMENT, AND BRANCH

The format is:
OBee

On , <label >

Test cc , decrement
branch to <loop>

On .

conditionally

218

68000, 680/0, and 68020 Primer

There are three elements to define in DSec. The first is the cc condition
code. The cc part is the familiar condition code, as used in Sec, and. listed in
Table 6-4. Thus UJe find DBEQ, DBHI, etc. The second is the On loop counter:
Dn here represents the lower 16-bit word of Dn, and we call this the loop
execution counter, or just loop coonter, for short. The third element is the
< label> . This defines the start of the loop we want to execute. As in the long
version of the Bec, < label > ends up as a 16-bit PC-relative displacement stored
in an extension w:xd. ~ DBcc displacements allow only baclru.ord branches
from DBcc to < label> , a maximum of $7FFE (32,766) bytes. The < label >
must come before the oSec.
DBee SEQUENCE OF EVENTS

The sequence of events is as follows:

If condition cc is true, do not branch but carry on with the next instruction.
If condition cc is false, decrement v.ord On by 1; that is, On ---1' On - 1.
Now test On. If On == - 1 go on to next instruction. If On not == - 1
branch to < label> .
As the implications start firming up and making sense, oSec becomes an
extremely useful composite instruction. A large percentage o f assembly language
programming effort is the tedious job of establishing loop controls, either by
counting or by condition testing or both. OSee reduces the tedium by combining
all the normal looping requirements into one poo..verfuJ instruction.
DBee IN ACTION

Let's see the simplest count only version of oSec using OBF (that is to say,
where cc = F or always false.
, Program 6-15

OBF:

Simple Count Only Loop

, Perform jobA exactly 24,765 times then rest!

MORE

MDVE . W #24764,00
<jobA program here . . . >

Set DO to l loop count - 1)

OBf'

Branch to MORE until DO

DO , MORE

= -1

<rest>
, The first tillle we meet OBF , condition is false (by definition)
so ""e decrement DO to 24,763 and loop (because DO does not yet

Miscellaneous M6BDOO Ins/rue/ions

219

equal -1 ). If you keep count of this process, you'll discover that

the jobA is performed exactly 24,765 times before DO hits -1.
At this point we stop looping and "drop through " to the next
line marked <rest>,
since jobA is performed once ""hen ""e first enter the loop, and
since 'i'e count until DO i s -1 'i'e must remember to set loop
counter : one less than number of loops needed ,

Using OBF effectively removes the condition testing aspect of oSec, leaving
us with the counting element. Even so, if you compare this example to the
normal non-OSec counting loop, you will see considerable saving of programming effort,
OBT (with cc = always true) actually exists, but if you follow the sequence
given above, you will see that

OBT

On ,<label>

immediately drops through to the next instruction. So, DBT in effect does
nothing. It is mentioned only to check your grasp of the logic behind oSec. If
you are in any doubt, reread the DSec sequence of events.
When we have a "proper" cc condition, like PL (Plus) or CC (Carry Clear),
the DSec becomes the eqUivalent of the DO - UNTIL < condition cc is true>
construct, much prized in structured programming languages, Within this 00UNTIL-condition-loop we have a further test: DO - UNTIL < On loop counter
= -1 >, which allows us to set a limit to the number o f loop iterations. The
next t\o\rO programs should clarify this.

Program 6-16 OBMI: Find First Negative Entry in Table

A2 points to the base of a table of 100 signed words ,

Scan the table and place the first negative nonzero entry in
lower word of 04, Record its table position (l - 100 ) in os ,
If no negatives found set 05 to -1 and 04 word: O.

SCAN

CLR.W
MOVE . W
TST. W

0'

08."'1

#99,05
(A2)+
DS ,SCAN

TST '"

05

R"

NOFIND

Clear 04 word
Set DB counter to {tOO-II
Is (A2 ) word negative?
SCAN until IA2 1
or until 100 entries
tested
Is 05 negative (: -II?
If yes -- all entries +ve
so branch to NOFJND with
D5 = -I.

-v.

220

68000, 680/0, and 68020 Primer

NOrIND

MOVE . w

-2 (A2 ) , 04

SUBQ. W
NEG.W

1100, 05
DS

Save fir st -ve entry

in 04
05 ::: 05 - 100
05 ::: -05 ::: {IOO - counter I
05 now ::: table position

<rest of program>

TST . Wsets Z and N flags according to value of ""ord (A2 ).

CMPI . W10. (A2 )+ would do the same. but takes a few cycles ~ore .
Each non-negative number we read (WI ::: false l will decrement
05 and test for 05 ::: -1 which signals end of table and NOPIND.
The first negative number 1M! = true) (if any) takes us out of
the loop to TST .w 05 . 05 will only be -ve (-1 ) if whole table
was scanned unsuccessfully. If 05 is in the range 0 - 99 , we
can calculate the table position of the find from {lOa - 05 1.
NEG . Wi s a common trick to get {a - Dn l by negating {On - a l.
Note the -2 (A2 ) to get at the previous word , since (A2 )+ has
already advanced A2 to the next word .

You can use this type of D&c loop to pick out all kinds of numbers from
a table. For example:

SCAN

CMPJ. W

63000, (A2)+

DBLE

05 , SCAN

LOOp ends if (A2 )<=3000

""",ld locate the first (if any) entry less than or equal to 3000.
\k.riable length tables or strings can be looped in many ways. You have
already met the idea of having a unique terminator such as NUL at the end, so
you test for this within the loop. Another common idea is to have the length
recorded in a header field at the start of the table or field. As entries or deletions
are made, ycx.J update the header. Let's revamp Program 6 16 to i1lustrate this
and a few other triCks.

Program 6-17 OBEQ; Pind Last Zero Entry in variable Length Table

,
,

A2 points to the base of a table . The fir st word in the table

holds the number of signed words which follow.
Scan the table and locate the last zero entry.
Record its table pos iti on in 05 .
If no zeroes found set 05 to -1 .
If the table i s empty. set 05 ::: a and DO byte ::: $PF
If table not e~pty set DO byte = 0

Miscellaneous M68000 Instructions

MOVE . W

(,1.2 ) +.05

SoQ

DO

IIDl

OO'TY

MOVE . W

05 , 04
11 , 04
04 , ,1.2

ASL. W
ADOA . W

SUBQ . w
SCAN

NeF'IND
EMPTY

TST. W
OBEQ

#1 , 05
- (,1.2 )
05,SCAN

TST . W

05

8MI

NOF'IND

ADDQ . W

11 ,05

221

05 : number of entries
A2 now -+ first entry
DO byte set to "remember if table empty or not
Table is bare! 05 : O!
04 :: number entries also
D4 x 2 = bytes in table
,1.2 now -+ beyond last
entry
Set DB counter = {OS I I
Is (,1.2 ) word zero?
SCAN until (,1.2 ) :: 0
or until 100 entries
tested
Is 05 negative (z -I )?
If yes - NO entries = 0
so branch to NOF'IND with
05 = -1.
05 = 05+1
05 now = table position

<rest of program>

<bypass - no entries in table>

SEQ DO tests the OCR after MOVE to 05 . If 05 = 0 (EQ is TRUE)

\I'e set 00 byte to l ' s ($IT) , If 05 -0 0, SEQ clears DO , Later
in the program , long after ,1.2 . 05 and OCR may have changed, we
can refer to DO \Inich "remembers the SEQ result ,
Note the use of - (,1.2 ) to scan a table from the end, We
were careful to advance the pointer ,1.2 to 1 \I'ord beyond the
last entry before entering the SCAN loop, We had to double the
number of words in the table to get the correct byte offset to
,1.2 . AS in Program 6-16 we set the loop counter 05 to one less
than the maximum number of iterations needed.

OHcc -

GENERAL COMMENTS

We can only give you a brief glimpse at the rich possibilities of the oSec fa mily
of instructions, so we conclude with a few general comments.

The value remaining in the loop counter On when we exit the oSec
loop is useful, as shOVJn in the last two programs. It tells us when and
why the loop terminated.

22 2

68000, 68010, and 68020 Primer

You can often use the loop counter On within the loop as an index
register that is automatically decrementing for you.

Sometimes you may want to branch directly to the oSec line, rather
than enter the loop from the top as we have done in our two examples.
For example:

WOVE. W

BRA

#<eounter>. On Set loop counter

Branch t o OSee line

TEST

LOOP

<loop program>

TEST

OBee Dn , LOQP

This is perfectly valid, provided you watch the initial value for # < counter>.
It is easy to get the wrong number of iterations. In fact, in the above example
# < counter> needs to be set to the exact number of loops needed, rather

than {loops - I}.

With care, you can modify Dn durtng a loop, thereby curtailing (decrease On) or prolonging (increase On) the loop.

The MC68010 has a special loop mode for DBcc that alter.; the sequence of testing/decrementing without affecting the overall function.
J-iorwoever, the execution speed of small loops is increased by holding
the OBcc instruction and its displacement in a twoword pre fetch
queue, thus redudng the number of memory accesses.

MISCELLANEOUS MATH
We have seen the four basic M68000 mathematical operators, ADD, SUB,
MULUIMULS, and DIVUIDIVS, and sonne of their simple vartants (like ADDQ,
ADOI, ADDA, etc.). We now look at the remaining instructions which perform
various arithmetical functions,

NEG - NEGATE

We used NEG in an earlier example without too much explanation. In fact,

NEG.z

<adea>

Negate destination operand

Miscellaneous M68000 Instructions

223

simply replaces the destination < adea> with its 2's complement negative,
namely {O - < adea> }, using z ~ L, W, or B to stipulate which part of the
operand is involved. The destination must be < alterable data effective address>,
which , as you nOVJ must realize, excludes An, d(PC), d{PC,Xi) and Immediate.
If DO contains $12345678, then

NEG.L DO gives DO ~ $EDCBA988 (32 bils negated)

NEGW DO gives DO ~ $1234A988 (lower 16 bils negated, rest
unchanged)
NEG.B DO gives DO ~ $12345688 (kM.er 8 bits negated, rest unchanged)
An excellent reason for keeping NEG in mind is that you cannot write
SUB I. z

On , l<data>

ILLEGAL

to calculate {#< data> - Dn}. But

SUB I . z

I<data> , On

NEG . z

on

On ""
On '"'

On - N<data>
-On

achieves the same end legally.

Note also, that you sometimes want {Om - On} without altering the value
of Dm. SUB.z Dn,Dm gets you {Dm - Dn} but you lose Dm. So why not do
SUB.z Dm,Dn followed by NEG.z Dn?
Another use for NEG is after a Sec to convert TRUE = $FF to TRUE =
1, which is sometimes more convenient:

Sec

<adea>

NEG.B

<adea>

Set byte <adea> to SFF if true

Set byte <adea> to SOO if false
Set byte to 1 if true
Byte remains 0 if false

NEG changes the CCR, predictably, just like SUB - although the nags
are less informative:
X Set equal to C
N Set if result is negative
Z Set if result is zero
V Set if ""","ow
C Set if a borrow generated (always the case unless operand is zero)

224

68000, 68010, and 68020 Primer

EXT - SIGN EXTEND

On many occasions we have observed that the M680CXJ automatically signbit
extends a register or displacement from 16 to 32 bits, for example. The EXT
instruction allows the programmer to perform this trick on a data register in t\VO
different wa'YS:
EXT.'

On

Si gn-bit extend from byte t o word of On

Le . copy bit 7 of On into bits 8 through 15

EXT.L

On

Si gn-bi t extend from word t o lonpord of On

i.e . copy bit 15 of On into bits 16 through 31

If DO ~ $12348765, then after

EXT.'
EXT. L

DO
DO

DO = $12340065
DO = $FFFF8765

since bit 7 = 0 and bit 15 = 1.

EXT is useful in preserving signs when you change data sizes during a
program. It is sometimes easy to forget that if you have a negative number in,
say, DO byte, and then wrile:
MOVE . B

DO , Dl

only the I"""" byte of D1 is " negative." Laler in the program you might have
one of the following:
ADD. W
ADD. L

01 , 03
01 ,03

which I,.I.()IJld give incorrect results. The use of EXT solves this:
MOVE . B

00 , 01

EXT. W

01

AIlIl . W

01 , 03

MOVE . S

DO , OI
Dl

01 word now signed correctly

or

EXT.'

01 lII'ord si gned li ke 01 byte

Miscellaneous M68000 Instructions

EXT . L
ADD . L

225

01 longword signed correctl y

01

01 ,03

EXT changes the CCR like a MalE:

X
N
Z
V
C

Unchanged
Set if result negative
Set if result zero
Always cleared to 0
Always cleared to 0

MULTI-PRECISION MATH
In this section VJe will be using the word extend in an entirely different sense not as in sign-extend - but as a way of gaining an extra significant 9th, 17th,
or 33rd bit to extend the accuracy of our sums.

TH E ROLE OF THE X FLAG

So far, VJe have only hinted at what the X flag in the CCR is meant to do, and
why it sometimes changes like the C flag, and sometimes remains unaltered.
We have seen the X flag acting as an "extra" bit beyond the usual MSB (Most
Significant Bitl of a register. In the ROXl (ROtate Left with eXtend I. for example.
VJe saw bytes rotating in a 9-bit field via the X flag, words rotating in a 17-bit
field. and Iongwords rotating in a 33-bit field. We need some new instructions
to explain the mysterious X flag.

EXTENDED ARtTHMETlC tNSTRUCTIONS

We now introduce three extended instructions, ADDX, SUBX, and NEGX,
which use the X flag numerically, allowing carries and borrows from previous
calculations to be incorporated in multiregister arithmetic.
ADDX . z Dm , Dn
ADOX . z - (Am) ,- (An)

Add jDm + On + X flag }. PUt SUM in On

Add l source + destination + X flag }
Put SUM in destination

226

68000, 680 /0, and 68020 Primer

{On - Om - X flag } replaces

SUBX. Z Om , On
SUBX . z - (AD) , - (An)

NEGX

<adea>

On

{destination - source - X flag }

replaces destination
{O - <adea> - X flag } replaces <adea>

In the examples that follow it should be remembered that in all cases when

we get carry or borrow during arithmetical operations, the X and C flags both
get set to 1. The M68000 rules for CCR changes are carefully arranged so that
certain instructions, such as MOVE, clear the C flag but keep the X flag unchanged. The X flag, as it were, "remembers" a carry or borrow until we are
ready to use ADDX or S UBX, which may be several lines later. Let's add two
64-bit unsigned numbers together to illustrate these points. When we deal with
numbers ouer 32 bits on the M68000, we are talking multi-predsion math .

Program 6-18 ADDX:

Adding 64 -bit unsigned numbers

Each 64-bit unsigned number takes 2 data registers .

Number A = {DO}{Dl } and Number B = {D' }{ D3 }
DO is most significant 32 bits of A, and so on.
The sum A + B to be placed in {04} {05 }
OCR to reflect value of the 64-bit result e. g. C=X=1 if 64-bit
carry; Z=1 if 64-bi t resul t is 0 etc.
MOVE.L
01 ,05
MOVE . L
DO ,04
ADD. L
03 ,05
05 : 01 + 03; carry : X
<any moves here: X unchanged , C cleared>
ADDX.L
D2 ,D4
04 = DO + 02 + X
where X is previous carry from 05
ADDX will create a new X
A + B now in {04 }{D5 }. OCR will reflect any carry fro~ 04 .
But what will the Z flag represent? What if 04=0 but D5<>O!
The next section will answer this question.

EXTENDED ARITHMETIC AND THE CCR

In the follOVJing discussion, when we refer to ADDX we include SUBX and
NEGX too - the CCR quirks are identical.
In the last program example, the final ADDX behaves very much like a
nonnal ADD with the previous X {l or 0) thrown in. An X carry of 1 actually
represents 2 32 (bit 33). The resulting sum in D4 happens to represent the "top"
half of a 64-bit result, because we planned it that wllY. The processor is, of

Miscellaneous M68000 Instructions

227

course, unaware of our interpretation and ADDKL will change the CCR on the

+ D2 + Xl. If there is carry from this we will

find it in both the C and X flags (the previous X is lost but we have no further
use for it). The new X may be useful- its value is 264 - and maybe we want

basis of the 32-bit addition {DO

to create an SO-bit, 96-bit, or even 128-bit sum from this and other 64-bit
results. If so, we are free to engage in a variety of MOVEs and SWAPs knowing
that X is safe. Again, this underlines the importance of knowing how the CCR
flags change with each instruction.
So ADDX sets X = C like ADD. To cope with multi-precision signed

numbers, ADDX also sets N and V like ADD.

THE Z FLAG QUIRK

But for the Z (Zero) nag we need a subtle twist. A nonzero result from ADDX
will CLEAR Z, as normal, but a zero result from ADDX leaves Z unchanged,
which is abnormal. Since there is always a reason for a Motorola quirk, let's look
for it

Going back to the last program example, suppose that the final ADDX.L
D2 ,04 gave a zero result - which is quite possible. (DO and D2 can both be
zero, and D1 + 03 need not produce a carry.) Under normal ADD conditions,
D4 = 0 would set Z = 1, leading us to believe that our 64-bit sum, A + B,
was zero. Clearly, we cannot decide whether A + B is zero simply by looking

at the top 32 bits of our 64-bit answer. So, ADDX is designed to clear Z if the
sum is nonzero, and leave Z alone if the sum is zero. In our example, then, if
04 were zero, the Z flag \M)Uld reflect the sum fanned in 05, the 10VJeI" 32 bits.
Z = 1 \M)Uld correctly imply that the entire 64-bit result was zero. Z = O \M)Uld
mean that either D4 or 05 or both were nonzero.
Now you know why. One important consequence of this quirk is that you
should make sure that Z = 1 (bit 2 of CCR) and X = 0 (bit 4 of CCR) before
embarking on a multi-predsion calculation involving successive AOOX's. Since
4 = 00000100, a neat w~ to do this is

MOVE . W 14 ,CCR

We now show SUBX in action, subtracting 64-bit numbers.

Program 6-19

SUBX: Subtracting 64-bit Unsigned Numbers

Initial data as in Program 6-1 8

Each 54-bi t unsigned number takes 2 data registers .
Number A = (00)(01 ) and Number B = (02 )( 03 ).
DO i s most- s ignificant 32 bits of A, and so on .

226

68000, 68010, and 68020 Primer

The difference A - B to be placed in \04 }{05 }.

OCR to reflect value of the 64-bit result e. g. C=X=l if 64-bit
borrow; Z=l if 64-bit result is 0 etc.
MOVE. L
01,05
MOVE. L
DO, 04
SUB. L
03 , 05
05; 01 - 03; borrow : X
<any moves here leave X unchanged>
SUBX.L
02,04
04 = DO - 02 - X
where X i s previous borrow from 05
A - B now in {04 }{ OS }. OCR will reflect any borrow from 04 .
Z flag reflects value of {D4 }{05 } not just {04 }.
Note t hat the borrowed X is subtracted.

MULTI-PRECIS ION MULTIPLICATION

Our normal MC68000 MULUIMULS allow us 10 multiply t\oo 16-bil values 10
give a 32-bit answer. The MC68020 offers l versions, which provide 32-bit x
32-bit = 64-bit products with one instruction. (DiviSion, too, has been extended.) The MC68881 math coprocessor takes us way beyond this with 80bit floating-point operations. On the " lesser" M68000 models you have to
program these extensions, but with ADDX and SUBX it is not too difficult. We
will briefly outline the steps needed to multiply tv..o long\oVOfds, A and B, to get
a 64-bil product. Suppose A ~ (v.ord l )(word21 and B ~ (v.ord3)(word41. We
first need four 16 x 16 ~ 32-bit products using MULU or MULS.

1.
2.
3.
4.

(v.ord21
(v.ordll
(v.ord21
(v.ord l l

x
x
x
x

(v.ord41 ~ 32-bit (prodlll (prod121

(pr0d211 (pr0d221
(word41 ~
(v.ord31 ~
(prod31 1 (pr0d321
(v.ord31 ~
(prod411 (prod421

where each (prod) is 16-bit So far, we have no carries to IM)rTy about!

As in second grade, you can imagine these (prods) set out ready to be
added column by column from right to left:
(prodlll (prod121
(pr0d211 (pr0d221
(pr0d311 (prod321
(prod411 (prod421
(sum 4) (sum 31 (sum 21 (sum I I

+
+
+

Miscellaneous M6BOOO Instructions

229

where each sum is 16 bits:

sum
sum
sum
sum

1
2
3
4

= prod12
= prod 11
= pr0d21
= prod41

+ pr0d22 + prod32 with CARRY Xl

+ prod3l + prod42 + Xl with CARRY X2
+ X2 with CARRY X3

With judicious use of ADDX, SWAP, and ASL, you finally get the product in
two lon9'MO'ds.

EXTENDED MATH WITH MEMORY OPERANDS

So far, v.re have not used the
ADDX . Z - (Am ) , - (An )

fonnat, and you may have VJOndered why this strange option is offered. A glance
at our multi-precision multiplication example above may offer a clue. If the
various 16-bit or 32-bit components are stored sUitably in memory, it turns out
that a great deal of register shuffling can be avoided by ADDXing directly in
memory while the pre-decrement automatically steps the address pointer throogh
your list of operands.

BINARY CODED DECIMAL

The M68000 supports a data type known as BCD (Binary Coded Decimal).
For certain jobs, especially fina ncial cakulations with large numbers, the vagaries
of binary-decimal conversion inherent in the nonnal binary data types can be
a problem, even with high-precision floating-point facilities. The BCD solution
is at the expense of memory and speed, but it keeps and manipulates all
numbers in exact decimal fannat, using a whole nibble (4 bits) to encode one
decimal digit. Since 4 bits can encode unsigned numbers 0 through 15, and
v.re need to encode only 0 through 9, you can already see the inherent inefficiency
in BCD (see Chapter 11.
VJe handle BCDs with instructions rather similar in fonnat to the ADDX,
SUBX, and NEGX of the previous section.
A8CD . B

011 , On

ABCD . B - (Am) ,- (An)

Add {Om byte + On byte + X flag l. Put SUM in On

Add Isource byte + des tination byte + X f lagl
Put SUM in dest ination

230

68000, 68010, and 68020 Primer

SBCD. B

DID . on

{Dn byte - Om byte - X flag} replaces On

SBCD. B - lAm ) , - IAn)

{destination - source - X flag l

replaces destination

NBCD. B

/0 - <adea> - X flag } replaces <adea>

<adea>

The first point to note is that all BCD operations are on bytes, which means
we can add, subtract, or negate tv..o dedmal numbers with a single Instruction.
Most assemblers will default to a data size code B, but we will use it as a
reminder. The BCD numbers we want to handle are usually packed 4 per 1.VOrd
or 8 per longv.ord. Longer sequences are best considered as strings of bytes,
and this explains the -(Am),-(An) operand option, already seen with ADDXI
SUBX. Suppose we want to store the dedmal number 564728 in memory with
pointer AO. This 3byte (6nibble) BCD siring would look like this:
BCD String A

564728

Byte Address

Byte Stored

Dedmal Equiualent

AO
AO + 1
AO +2

(0101) (0110)
(0100) (0111)
(0010) (1000)

(4) (7)

(5) (6)
(2) (8)

Most significant
Least significant

Note the sequence of nibble within byte and byte within string. The lesser
significant digits are higher in memory, 50 if we set our pointer just beyond. the

end of this siring (at AO +3), the pre-decrement format of ABCD will automat
ically sum with dedmal carry in the correct arithmetical sequence, adding 28,

then 47, then 56 to another designated destination BCD siring.

BCD OPERATIONS AND THE CCR
Since the X carry is added as with ADDX, our previous discussion and caveats
regarding the CCR apply - in particular the Z flag quirk (clear Z if result
nonzero but leave Z unchanged if result is zero) is in forte. The X carry is 1 or
0, but remember the 1 is a dedmal carry representing 100 being carried over

from the lower BCD byte (the range of which is 00 throogh 99). It is especially
important to dear X and set Z = 1 before any BCD work.

Some differences in CCR handling be"""en ADDX and ABCD arise from
the fact that BCD bytes are essentially unsigned, at least they are not 2's
complement format, so the N and V flags are of no value and remain undefined

during all BCD operations.

Miscellaneous M68000 Instructions

231

BCD CC R SUMMARY

x
N
Z
V
C

Set equal to C
Undefined
Cleared if result is nonzero else unchanged
Undefined
Set if a dedmal carrylborro.v

ADDING BCD STRINGS IN MEMORY

Let's set up another BCD string called String B, and then write a program to
add our earlier String A to B:
BCD String B ~ 390112

Byte Address

Byte Stored

Dedmal Equivalent

Al

(0011 ) (1001)
(0000) (0001)
(0001) (0010)

(3) (9)
(0) (I )
(I ) (2)

AI+I

Al +2

Most significant
Least significant

, Program 6-20 A8C0 : Adding BCD Strings in Memory

AO and Al point to top (MSD) of 3-byte BCD strings A and B
Add A t o B, place BCD sum in string B. Signal any carry
-error . - i . e. if sum exceeds 999999 .
MOVE . w
MOVEQ . w

#4,CCR
12 , 00

ADDQ . '
ADDQ . '

13, AO
13 , Al

LOOP ABCD.B

-(AO) , -(A1)

DO , LOOP
ERROR
<rest of program>

DBF
BCS

Set X:{) and Z:l before all BCD ops

Set DBcc counter for 3 iterations
Set A pointer beyond end of string
Set B pointer beyond end of string
Add {A byte + Xl to B byte
Loop three times
Branch if carry

<take appropriate action>

String B would now contain 954840 :

~RROR

Al

Al+l
Al+2

(l001) (0101)
(0100) (1000)

(4) (8)

(DIDO) (DODO)

(4) (0 )

(9 ) (5 )

Most significant
Least significant

232

68000, 68010, and 68020 Primer

The CCR would have X = C "" O. Z = O.
to their original values .

AO and Al would be restored

NEGATIVE BCD NUM BERS

The NBCD instruction simplifies the handling of negative BCD values, but since
have no N flag, the X and C flags must be watched with care to get your
sums right. NBCD no rmally forms the 10's complement of the byte operand {O
- < adea > }, but if there is an X= 1 from the previous operation, that X= 1 is
also subtracted, {O - < adea> - I } to give the 9's complement.
This allO\.Vs a BCD string to be negated (sign-rewrsed) correctly, as the
next example shows.
I.W

Program 6-21 NBCD :

Negate a BCD string in Memory

With the same data as Program 6-20. replace string A with its
negative (lO's complement ).
BCD string A = 564728:
(5 ) (6) Most significant
(0101 ) (0110)
AO
(4) (7)
AO+l
!O lOO) (0111 )
(2) (8) Least significant
AO+2
(0010 ) ( 1000)
MOVE. V
MOVEQ. W

ADOQ. '
LOOP NBCO. B
DBF

#4 ,CCR

12 .00
13, AO
- (AO)
DO , LOOP

Set x=o and Z:l before all BCD ops

Set DScc counter for 3 iterations
Set A pointer beyond end of string
{O - BCD byte - xl to - tAO )
Loop three times

String A now contains 435272 the 10's complement of 564728

(0100) (0011 )
(4 ) (3) Most significant
AO
(5 ) (2 )
AOtl
(0101 ) (0010 )
AO+2
(0111 ) (0010)
(7 ) (2) Least significant
The eCR would have X = e = 1, Z = O.
to its original value .

AO would be restored

x ~ 0 before the lowest byte is negated, so """ get (O - 28) ~ 72 with

borrow, then X is set to 1. Therefore the next negate gives {O - 47 - I } ~ 52
with X = 1, and so on. l~ later in the program, you look a t string A, all you see
is 435272. Is this plus or minus? Unless you have taken precautions, 435272
looks just as positive as the 564728 which I.W negated. \.Veil, there are many
solutions, but they have to be programmed - they are not built-in for you. One

Miscellaneous M68000 Instructions

233

method is to append a sign byte to each BCD string, possibly using the ASCII
plus and minus symbols, and always store the absolute value in the BCD string.
As a final example to underline the mechanics of BCD, lets subtract 2 BCD
bytes that are assumed to be positive and are held in data registers.
Program 6-22

SBCD: Subtracting BCD Numbers

Given two tve BCD bytes in DO and 01 , calculate DO - 01 .

If positive set 01 = DO - 01 with (AI ) byte = ASCII "t"
, If negative set 01 = 01 - DO with (AI ) byte = ASCII "-"

NEG

MOVE . W
SBCD.B
BeS
MOVE . B

#4 , CCR
01 , DO

BRA

REST

ANDI. 8
NBCD . B

lIEF , CCR

NEG

#$28, (AI)

DO
1$20, (Al)
MOVE . 8
REST <rest of program>

Set Z=l, X::O

Put BCD {DO - 01 ) in DO
If C=l branch to NEG
Set ASCII "t" in (AI)
Set X=O (rest of CCR unchanged)
Negate BCD in DO byte
Set ASCII "- " in (AI )

To get the absolute value of a negative BCD byte DO, \.Ve must clear X
before the NBCD. For example, suppose DI ~ 1()()()())(OOIO) and DO ~

1()()()())(OOOI), that is, Dl ~ 2, DO ~ I, and DO - DI ~ - I. Then BCD {DO DI} ~ 11(01)(1001) with X~ I. NBCD with X~ 1 would give DO ~ {O - 99
- I} ~ 0 wrong. NBCD with X ~ 0 would give DO ~ {O - 99) ~ 1 correct.
MISCELLANEOUS DATA HANDLING
There are five instructions under this heading, ranging from very simple to rather
abstruse:
SWAPI wi

On

Swap register halves

<XG I. L)

Rm ,Rn

Exchange registers

MOVEP. Z
MOVE? Z

Om, d (An)

dIAn) , Om

Move peripheral data -- output

Move peripheral data -- input

LINK

An,#< -block_size>

UNIJ(

An

In these instructions, Z

L or W.

Link & allocate stack

Unlink & deallocate

234

68000, 680/0, and 68020 Primer

SWAP REGISTER HALVES

SWAP On simply reverses the upper and IovJer VJOrds of any data register -

so

Ihat bils 0 through 15 move 10 bils 16 through 31 and vice versa.

Example of SWAP

Suppose we have DO = $ABCDEFI2 and we need to MOVE just the upper

"""d $ABCD to 06. We """,Id first use:
SWAP

giving us DO

DO

DO upper = $EF12 . DO lower = $ABCO

$EFI2ABCD. Now we ca n use:

MOVE . W

06

06 word = $ABCO

Rnally, we may wish to restore DO VJith another SWAP:

SWAP

DO

DO upper = $ABCO. DO l ower :: $EFI2

In effect SWAP acls like a 16bit rotate (left or right) - but SWAP is much
faste< Also, SWAP and rotate (RORlROL) have slightly diff",,"nt CCR rules. The
CCR changes for SWAP are exactly the same as for MOVE:
X Unchanged (hence useful during multi-precision jobs)
N Set to 1 if new bit 31 == 1, cleared to 0 otherwise
Z Set to 1 if new long \AOI'd is zero, cleared otherwise (So, in
truth, Z doesn't change. But you may still want to test for
zero.)
V Always cleared to

C Always cleared 10 0
ROR/ROl differ in setting the C flag as the bits are rotated.

EXG -

EXCHANGE REGISTERS

EXG{.L} Rm ,Rn works with any mix of data and address regislers (any of the
following, for example):
EXG (. L) OII.Dn
EXG {. L} Do , An
EXG{. L} Am , An

Contents of Om moved to on and vice versa

Same as EXG An , Om

Miscellaneous M68000 Instruclions

2aS

The l is optional, since EXG implies 1ong\M?rd. (All 32 bits are always exchanged. J
All forms are useful, insofar as they are equivalent to the following three
MOVEs:
MOVE . L RID , Rx
MOVE . L Rn , RID
MOVE . L Rx . Rn

without your having to use a third register Rx as a go-betvJeen.

MOVEP - MOVE PERIPHERAL DATA

MOVEP is a spedalized version of MOVE introduced to simplify interfadng with

the previous generation of 8-hit devices (which are still, of course, being used).
Although Motorola blazed many new trails with the M68000 family, tHey

COf-

made the sensible decision to incorporate features that WCXJld maintain

patibility with peripherals and 110 support chips designed for 8-bit processors,

espedally their own M6800 family.

We have already mentioned the fact that the M68000 can interface with
both high-speed 16-hit asynchronous devices as \.Veil as s\QV.Il', usually 8-Qit,
synchronous peripherals.
The MOJEP instruction is aimed at easing the programming effort in
transferring 8 -bit bytes in " bursts" between data registers and VO devices. The
M68000 uses memory-mapped VO which , for our present purposes, simply
means that you can address peripheral ports as if they were memory addresses..
In place of the special VO instructions you find with some systems, the M68000
can perform VO with MOVE and the appropriate memory operands (with. of
course, a little help from the many friendly device controllers that interface disks,
printers, terminals, and so on).
Because 8-bit peripherals are best attached either to the high eight lines or
to the IOVJ eight lines of the M68000 16-bit system data bus, their control
registers " occupy" alternate byte addresses in the M68000 memory address
space, consecutive odd byte addresses or consecutive even byte addresses.
In sending data and control to such peripheral registers, therefore, the
normal MOVE VJOUld require rather peculiar address cha nges. The (An) + and
-(An) modes, for instance, work fine for contiguous memory transfers, but a
typica l 110 transfer may req u ire the following: DO contains

(byte4J1byte3J1byte2J1byte I J. To output DO to 8-bit port address AO would

need:

MOVE byte4 to address AO

MOVE byte3 to address AO + 2

236

68000,68010, and 68020 Primer

MOVE byte2 to address AD + 4

MOVE byte 1 to address AD + 6
(Note the sequence - high bytes in low addresses.) Without MOVEp, this
could be achieved in many ways, all quite tedious. for example:
00,6(1.0)

MOVE . B
ROR . L

18 , 00

MOVE . B
ROR.L

00 , 4(1.0)
18 , 00

MOVE . B
ROR . L

00,2 (1.0)
18 ,00

MOVE . B

DO , (AO )

Rotate byte2 to l ower byte

position
Rotate byte3 to lower byte
pos ition
Rotate byte4 to lower byte
position

The MOVEP gives a one-line solution:

MOVEP. L

00,0(1.0)

Output 00 to (1.0) ... (1.0+6)

MOVEP achieves this by applying its 0010 built-in rules for post-incrementing addresses. MOVEP moves bytes starting from the top of DO, then postincrementing by 2.
If we look at the MOVEP formats for oolput,
/lK)VEP . L

DIll , d (An)

Move 4 bytes from Om to alternating I /O byte

addresses starting at d IAn)

MOVEP . W

DIII,d (An)

As above but move 2 bytes

we see that L or W dictates the number of bytes, and that the destination must
be address register indirect with offset, which is used to spedfy the starting
address for the transfer,
Motorola had an excellent reason for choosing d(An) as the operand.
Typically, an area of memory will be designated for 110 addressing, An address
register VJOUld be set to point to the base of this area , and symbolic (mnemonic)
offsets VJOUld be assigned in the assembly source to distinguish the peripheral
register addresses within the 1/0 memory map. For example, ~ may find:
MOVEP. W DJ.PIAD (A5}

Miscellaneous M68000 Instructions

237

where AS is pointing to the I/O memory base, and PIAD is the offset from AS
for the address assigned to a Motorola 6821 PIA (Per;pherallnterface Adapter).
In large systems, such mnemonic tags are indispensable.
Figure 6-15 shows the various possible sequences of data-byte to byteaddresses. The predse details are not as important as the general understanding
that by choice of L or W with odd or even starting address d(An). the one
MOVEP can quickly transfer bytes to load the correct upper or lower 8 bits of
the data bus.
The reverse procedure provides input from peripherals to any data register.
MOW . Z

dlAnl, Dm

Load Om with 2 or 4 bytes from

alternating I/O byte addresses st arting dIAn)

Input with MO\IEP v..orks exactly like output but in the opposite direction from alternating liD byte addresses to the chosen data register. This symmetry
in the coding formats for input and output is yet another M68000 programmerbefriending feature.
Finally, note that MOVEP does not affect the CCR nags, which is quite
sensible if you think about it You are simply sending or receiving a series of
bytes. and there are no reasonable criteria for changing the CCR.
MQVEP - SUMMA RY

MOIIEP simplifies the transfer of data to and from byte-oriented 110 devices by
automatically incrementing the operand addresses by 2 for each byte transferred.
This allows the 16-bit data bus to be assigned to two separate 8-bit liD ports.
The final, and most complex. instructions in this group of miscellaneous
data movement operations, LlNKlUNLK (Link/Unlink), require a little preamble.

LlNKIVNLK- PREAMBLE
LlNKlUNLK requires a thorough understanding of the stack, so we will recap
the salient features of the stack concept.
In Chapter 5 we saw how the stack could be used for saving data and
contexts during programs and subroutine calls. In particular, VJe saw that the
stack holds the return address needed to guide a subroutine back to the place
it was called from. The success of the stack as a preserver of data lies in the
LIFO (Last In R"t Out) mechanism - so that as yoo push data on, and pull

238

68000, 68010, and 68020 Primer

Longword MOVEP

!!!!!.

address

Register
B3

l"":'i

B1

I BO

low

hi

2N
2N+2
2N+4
2N+6

Longword MOVEP odd address

2N+ 1

f--_.

Register

1i!1""B?j'Yii"":1

- B3

I
low

hi

Word MOVE? even address

Register

~""!~
hi

low

Word MOVEP

hi

Fig.6-15

2N r-~-r---1r

2N+2

address

low

MOVEP.Z Om,d(An) and MOVEP.Z d(An),Om

Miscellaneous M68DOO Instructions

239

data from the stack, the stack is kept tidy without ycx..tr having to mrry unduly
about memory addresses. The one address pointer, namely SP = A7, keeps
track of where you are. SP always points to the last \-VQrd saved on the stack.
There are many Situations, hoI.vever, where subroutines generate temporary
or intermediate data, then call further sub-subroutines, and so on. When you
get to several levels of what v...oe call nested subroutines it can become a programmer's nighhnare keeping track of each subroutine's temporary data locations. The natural place to hold each subroutine's data is on the stack itsel~
provided v...oe can access and manipulate such areas without disturbing our
normal stack processes. In particular, VJe must never lose a subroutine's retum
address.
So far, VJe have simply pushed and pulled items to and from the top of the
stack with MOVE., Dn,-(SP) and MOVE., (SP) + ,On but there is no law against
ycx..tr delving into other parts of the stack if you want to. You can treat the stack
just like any other portion of memory using the stack pointer, SP ( = A7) , just as
y<X.l VJOUld any other address pointer. You are completely free to use SP ( = A7)
with displacements and indexes in order to access and change stack data, as
long as you observe t'M) rules:
1. Never alter the subroutine's return address (which was pushed on the stack
automatically by \oWr BSR (Branch SubRcutine) or JSR (Jump SubRcutine).
2. Make sure that when the RTS (ReTurn from Subroutine) comes along, the
value in SP is back to its correct value - because RTS will try to pull the
return address from the top of the stack. If SP is not pointing at the right
part of the stack, RTS will not recover the subroutine's return address, and
chaos will reign.

The idea behind LlNKlUNLK is to help the programmer in allocating data areas
on the stack for any sequence of nested subroutines withoot violating these rules
- VJeIl, at least, they reduce the risk.
We'll take yoo through the LlNKlUNLK sequences. It will probably take
several passes before all is clear.
THE STACK AS A DATA AREA - USING LINK AND
UN lK

The LINK and UNLKinstructions allow you to allocate and deallocate temporary
data areas, known as frames, during nested subroutines without losing any
earlier items saved on the stack, such as register values, CCR flags, and return
addresses. The LlNKlUNLK mechanism also helps you keep track of all previous
frames set up by earlier subroutines.

240

68000, 68010, and 68020 Primer

WHAT IS A FRAME!
A frame is nothing more nor less than a portion of memory in a stack, assigned
to any subroutine that needs v.orking memory space. The maximum size of
each frame is 32 K bytes - but the total number of frames you assign is limited
only by your pocketbook (how much RAM you have). Each subroutine that
uses a LINK instruction will acquire its ov.m unique frame. This frame remains
on the stack until UNLK dears it. If, say, you have four nested subroutines, each
using LINK, you I.I.OJld have four separate frames of data in your stack when
the fourth subroutine is running. When a subroutine is completed it relinquishes
or deallocates its frame before returning control to the previous subroutine.
LINK -

Allocates a frame on the stack.

UNLK - Deallocates (removes) the frame from the stack.

The basic idea is that an address register (other than SP = A7) is assigned
the job of FP (Frame Pointer). During a subroutine, you can manipulate the
frame data using FP with any of the available address modes. The rest of the
stack is undisturbed (as long as you keep within the frame) . Look upon the FP
as an address poi nter to frame data located within a stack.
With this background, let's see how LINK is set up. The general {onnat for
LINK is:

LINK

An . I<-block_size>

where An , the designated FP (Frame Pointer) , can be any address register

except A7 (because A7 is your Stack Pointer). Once you designate an An as
FP, you must use that chosen An for all subsequent LlNKlUNLK operations.
We will see that the address stored in An is changed as VJe move from one
subroutine to another, so that it always gives us the correct FP for the active
subroutine's frame.
The size of the frame in bytes is indicated by # <- block_size >. The
negative sign in <- block_size > is needed because our stacks gro...v downwards
in memory. Block_ size is a 16-bit signed number (one extension word in the
LINK instruction), so the maximum frame allOVJed is 32K bytes. Block_ size
must be an even number of bytes.
To achieve all that VJe have indicated, LINK perfonns the followi ng three
functions. We'll run them by yo.J quickly, then elaborate the why's and whendore's.

1. Save An on stack with a MOVE.L An ,-(SP ). The previous FP = An is n()I..V

safe on the stack.

Miscellaneous M68000 InslruClions

241

2. Save new value of SP in An with a MOVEA.L A7,An. Note A7 = Sp.

An is I'lQI,.V cur new, cunent FP
3. Reset SP to {SP minus block_size}. This increases the stack size by
< block_size > bytes. Our new frame of block_size bytes occupies memory
addresses from An = FP to SI'
Let us go through LINK step by step, referring to Figures 6-16, 6-17, and
6-18.
Suppose we are executing subroutine A, and AS holds the FP value for
Subroutine A's frame. The contents of A's frame are not of immediate interest,
except to note that the stack has grown (SP reducing) since A was first called.
Next, suppose that subroutine A reaches a BSR, which calls subroutine B.
As you kn()I..V, this immediately pushes S 's return address on the stack.
B is now about to execute, and we may first want to save the CCR and
some other registers on the stack. If so, we can push them on the stack in the
usual way, and they will be safe there until B returns control back to A.
Assuming B needs 512 bytes of VJOrking memory (tables, buffers, etc), the
next instruction in B IJJQUld be:

LINK

AS.#-S12

Link via AS with S12 bytes

This one line, in effect, performs these three operations:

YDVE . L

A5 , - (SP)

Save subroutine A' s FP on stack

(V.Je push current FP = AS on the stack because AS changes during LINK and

we will need to restore it later when we UNLK)

MOVEA . L

{A,: sp l .AS

A5 is now subroutine B's FP

(After step 1, SP is left pointing at A's FP on the stack. This part of the stack
will become the start of B's frame, so we save SP in AS as B's FP.)
ADDQ . L

#-SI 2. SP

(Adding minus 512 to SP is the same as increasing the stack by 512 bytes.
Between B's FP and the new SP we have allocated 512 bytes for use by B.
A~ subsequent pushes/pulls during subroutine B will take place on the enlarged
stack beyond this allocated data area. VJe can use AS = B's FP to reference
any part of the 512. byte frame without altering SP; likewise we can push/pull
the stack using SP without altering B's frame.1

242

68000, 68010, and 68020 Primer

During Subroutine A

(USP) A7

Address of top 01 A's stack

Top or
A's stack

A's stack area

Subroutine A Now Calls SubrQutine B

(USP) A7

~~~~::::::::~~~;-~I~~~~~~~~
~
Push B

R~lum address

I---.:::!:.:::..::..:.::=:::....-+....
A's stack area

Subroutine B Now poes LINK AS. #SI2

(3sleps)

Slop 1 of LINK

Push AS on slack
USP : A 7

t:.:.:..::"-=-==.:..:.___
A's stack area

AS

l!:.!==="'--_---l
Fig. 616

LINK and UNLK (Part 1)

Miscellaneous M6BOOO Inslruelions

24 3

Step 2 of LINK AS . 1-512

Save SP in AS
USP A7

r"--------..

Stack
unchanged

8's Frame Pointer

A's stack area

A5

8's Frame Pointer

SteD 3 of LINK AS, #-512

Decrement SP by 512

Stack

~1~~~~~~~~~

Allocated by
..............- - . . . . ,.......
P.o;o" to
A5
A's FP

A's Frame Pointer points 1.0 _ _ _

A's stack area

~~~ili!!!jE!!!!i!:~!if

previous Frame Pointer

Subroutine B

now proceeds using allocated stack area SP changes

(don'1 care)

Eventually Subroutine B does UNlK AS (2 Steps)

Slep 1 of UNLK AS
Restore SP from AS

(USP) A7
A's stack area

Fig. 6-17

LINK AND UNlK (Part 2)

244

68000, 68010, and 68020 Primer

SteD 2 of UNLK AS

Restore AS from stack

(MOVE.l (SP) + , AS)

(USP)

A's stack area

Now Subroutine B Does BIS Back to Subroutine A

Pull retum address for B from stack ........ PC

01 A's stack
A's slack area

A Subroutine resumes w ith stack restored exactly.

Fig.6-18

LINK and UNlK (Part 3)

We can nOVJ envisage subroutine B doing its OVJn thing, using its 512-byte
fra me on the stack. Just before B is ready to RTS or RTR (assuming we had
saved the CCR) back to subroutine A, VJe need:
UNLK

AS

Unl ink via AS

which deallocates B's frame and restores the stack automatically by performing
the following t\.VO steps:
MOVEA . L

AS , (A1=5P I

Restore stack pointer

Miscellaneous M68000 Instructions

245

(This reverses step 2 of LINK by restoring 6's FP into the stack pointer. SP now
points to where we saved A's FP in Step 1 of LINK. )
MOVE . L
(Here

{SP)+, A5

Restore A' s rP into AS

we pull A's FP from the stack and put it back in AS. This reverses step 1

of LINK.)
If we had saved the CCR on the stack, an RTR now will restore the CCR
and return us to subroutine A. If we had not saved the CCR, an RTS will return
us to subroutine A.
In either case we are back into A with exactly the same stack disposition
as when we left it for B. The stack and frame pointers are restored and B's data
area has disappeared.
In tum A will unlink and return. The nested subroutines wilt eventualty be
completed to bring us back to the main program. By this time all our temporary
frames will have been deallocated and AS is now free of the FP chore.

LlN KlUNLK - SUMMARY

We have spent some time explaining L1NKlUNLK because it reveals several

important aspects of contemporary software. The choice of the name LINK, for
example, is \AQrth pondering.
The first item in a frame is always a longu..ord containing the address of the
previous frame. So our frame pointer is actually pointing at another, earlier frame
pointer This idea of pointers pointing to pointers is not as difficult as it may
sound. It is the basis of what we call linked lists, from which comes the name
of the instruction LINK.
MORE ON PRIVILEGE

What is privilege? In the broadest sense, privilege can be established at any

level in a computer system, ranging from padlocks on the terminals, to pass\AQrdprotected programs or files, and on to global privileges by which an operating
system can guard against accidental or deliberate misuse by one user that can
crash the system. The M68000 offers some unique hardware/software combinations that offer systems designers and programmers some aSSistance in this
difficult area.
We conclude Chapler 6 with a IOOndup of the so-called privileged instructions, some of which we have already seen briefly.
Many of the privileged operations perfonn familiar tasks like MOVE and
ANDI, and there is no mystery as to what they do, but because they change

246

68000, 68010, and 68020 Primer

(or might change) vital system parameters or contexts, they are allOVJed only
when the M68()(x) is in the supervisor state. Attempting to use a privileged
instruction in the user state causes a TRAP, and we will see shortly ho..v TRAPs
are handled.
The state of the processor is indicated by the S nag (bit 13) in the status
register. If 5 is set to 1, the M68000 is in supervisor state (also called system
mode or privileged mode). If 5 is cleared to 0 , the processor is in user state (or
mode). In other IJJOrds, the M68000 must be in one or the other slale; there is
no in-bet\.veen. As the names imply, individual user programs normally run in
user mode, while operating systems run in supervisor mode. Sitting at your
terminal, you may be unaware of the fact, but the S flag is constantly swilching
betVJeen 0 and 1 as control passes to and from your job, other users' jobs, and
the OS. A notable exception, by the way, is the Apple Madntosh, which operates
in supervisor mode at all times.
The I\..vo states not only affect which instructions are legal , they also diclale
whether certain registers can be accessed. Also, the M68000 indicates its state
(S = 0 or S = 1) via signals on the Fe (Function Control) pins, allOlAling other
devices such as memory management chips, coprocessors, and so on, to detect
and react to this state. A typical application here is 10 allOVJ systems designers
to control which segments of memory are assigned to user and system areas.

USER AND SUPERVISOR STACKS

One important consequence of the "either S = or S = 1" situation is that the

same register symbol, A7. can be used for I\..vo distinct physical registers withoot
any ambiguity. You may be confused, but the chip knOVJS! In supervisor mode.
A7 = SSP (Supervisor Stack Pointer). In user mode, A7 = USP (User Stack
Pointer) .
The M68()(x) therefore maintains two distinct stack pointers and two distinct
"A7-stacks", which are often called systems stacks (supervisor system stack and
user system stack) to avoid confUSion with the multitude of " private" user stacks
that can be set up using AO through A6 as stack pointers.
Now the user-programmer, in user mode, is free to access, manipulate, and
even completely mutilate his or her user system stack using A7 (or the assembly
mnemonic, SP ) as an operand. The harm, if any, is confined 10 that user's job.
But access to the supervisor stack is privileged, and this affords a certain measure
o f security, not absolute security, but protection against careless coding. As we'll
see, the supervisor stack is constantly saving and restoring contexts for the entire
system, so any unplanned interference with A7 = SSP can be globally catastrophic.
On the other hand, the 05 often needs to access A7 = USP (for example,
it will want to save your USP when switching jobs). If we are In supervisor mode

Miscellaneous M68000 Instructions

\.\Ie

247

can't do this using A7, because A7 now means SSP. This catch-22 is avoided

by Ihe following privileged instructions.

MOVE. L
MOVE . L

USP, An
An ,USP

privileged: Move User Stack Pointer to An

Privileged: Move An to User Stack Pointer

In user mode, the above instructions \oVOUld cause a trap. Having grabbed
your stack pointer, the OS is at liberty to do what it likes to your stack data. The
MOVE. L An,US? then allows the OS to restore your stack pointer if and when
it feels the urge.

STACKS AND PRIVILEGE - SUMMARY

Summing up the privilege aspects of the tVJO systems stacks: In user mode,
there is unrestricted access using A7 or SP to the user stack, but the supervisor
stack cannot be accessed. In supelVisor mode, there is unrestricted access using
MOVE with US? to the user stack, and unrestricted access using A 7 or SSP to
the supervisor stack.

PRIVILEGE AND THE SR (STATUS REGISTER)

The 10000r byte of the 16-bit SR is our much discussed CCR (Condition Code
Register), which is freely accessible to all. You can test, move, and modify the
CCR flags in both user and supervisor modes. The upper byte of the SR, Ihe
system byte, is an entirely different story. In user mode, the system byte is READ
ONLY - wilh MOllE from SR. (Howewr the MC68010120 allow only MOllE
from CCR - see Chapler 8.) In supervisor mode, Ihe syslem byte is READ

and WRITE - with MOllE from SR and MOllE 10 SR. We can also alter the
SR wilh ANDlIORlIEORI.
The system byte nags are:

Bits 8-10
Bil13
Bil15

Three-bil 1M (lnlerrupl Mask)

5 flag (Supervisor slale ~ 1; User slale ~ 0)
T nag (Trace rnodeon = l ; Trace mode off = 0)

so the user cannot directly alter these flags with a MOVE to. What you can do
in either mode is MOVE from SR with
MOVE {. WI

SR , <adea>

Non-privileged - - read status lI'ord

allowing you 10 test any or all of the 1M, S, T, or CCR flags. (Note the MC680101
20 exceptions referred 10 above.)

248

68000,68010, and 68020 Primer

When the M68000 is initially switched on (or reset), it starts up in supervisor mode. This is quite natural and desirable since some kind of OS or booting
firmware is going to initialize the system prior to user access.
Getting from supervisor to user mode presents no problem, since in supervisor mode the OS can clear the S flag at any time with
MOVE . W

lO ,SR

Privileged Clear S flag

(and all othe r flags in SRI

or, if we do not want to clear all the SR, we can use one of the following.
EORI

N$2000 . SR

Privileged Clear S f lag

(other fl ags unchanged)

AND!

#SDFFF. SR

Pri vileged Clear S flag

(other fl ags unchangedl

Similarly, you can use

OR!

#<lIIask> . SR

Privileged

to set selected SR flags.

You may \.VOnder, then, how we ever pass from user mode to supervisor
mode if the S flag cannot be "MOVEd to" in user mode. The anS\.VeI' lies in the
M68000 concept of exception processing. An exception encountered while in
user mode will switch the processor to supervisor mode, setting S = 1 and,
depending on the exception, will save or attempt to save the processor context
in a variety of ways.
EX CEPTIONS

In M68000 parlance, exceptions cover a wide variety of events, some of which

are beyond the scope of this chapter. The follOVJing events met in user mode
will initiate exception processing:
TRAPs from detected errors
Deliberate TRAP instructions
Privilege violations
Interrupts - internal or external
Bus errors
Reset

Miscellaneous M68000 Instructions

249

Each of these switch the processor to supervisor mode, where the exception is
processed. Let's look at the first t\.vo exception types to get a feel for exception
processing and how control is eventually returned to the user.
Error TRAPS
We saw in the OIVUIDIVS instruction that divide by zero was automatically
detected, leading to a spedal TRAP. \kry briefly, this is what happens in the
trap on zero divide:

1. Switch to sUpe!Visormode (S = I)
2. Save job context on system stack
3. Go to Vector #5 in exception vector table
4. Get address of exception handling program
5. Run this program which ends with RTE (ReTurn from Exception)
6. Restore job context and switch to user mode (5 = 0)
7. Resume user job
CHK -

TRAP if Bound Exceeded

A similar type of error TRAP can be programmed to detect if values obtained

during a calculation fall ootside designated bounds:
CHI<

<dea>. Dn

TRAP if On negative or greater than <dea>

If On is within stated limits, the next instruction is taken. If On is ootside the

limits, exception processing is triggered, just like TRAP on divide by zero, but
this time we go to Vector #6 to pick up our handling program address.

TRAPV - TRAP on Overflow

TRAPV will generate a trap to Vector #7 if overflOVJ is detected.
General TRAPs
TRAP

#<Vector>

TRAP

t o #<Vector>

This is a deliberate TRAP - so there is a

w~

for the user-programmer to

get into supervisor mode. In fact, TRAP # < vector> turns out to be a powerful

systems programming tool for enlarging the instruction repertoire.

Table 6-5 shOVJs the complete Exception Vector Assignment Table, from
which you can see that there are 255 unique vectors available for exception

250

68000.68010, and 68020 Primer

Table 6-5 Exception Vector Assignments

Vector
Number(s)

Dec

Address
Hex

0
1
2
3
4
5
6
7
8
9
10
11
12'
13'
14
15

0
4
8
12
16
20
24
26

16.23 1

64
95

OOC
010
014
018
01C
020
024
028
02C
030
034
038
03C
040
OSF

24

96

060

2S

100
104
108
112
116
120
124
128
191
192
255
256
1023

064
068

26
27
28
29
30
31
32-47
48-63 1

64-255

32

36
40
44

48
52
56
60

0000
004
008

06C
070
074
078
07C
080

OBF
OCO
OFF
100
3FF

Space

Assignment

5P
SP
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO

Reset: Initial SSpl

Reset: Inilial PC'
Bus Error

Address Error
Illegal Instruction
Zero Divide
CHK Instruction

TRAPV Instruction
Privilege Violation
Trace
li ne 1010 Emula tor
li ne 1111 Emulator

(U nassigned , Reserved )
(Unassigned, Reserved )
Format Errors
Uninitialized Interrupt Vedo'

(U nassigned , Reserved)

SO
SO
SO
SO
SO
SO
SO
SO
SO

Spurious interruptj

SO

(U nassigned , Reserved )

SO

User Interrupt Vectors

level 1 Interrupt Autovector

Level 2 Interrupt Autoveclor
Level 3 Interrupt Autovector
level 4 Interrupt Autovector
level S Interrupt Autovector
level 6 Inte rrupt Autovector
l evell Interrupt Aulovector
TRAP Instruction Vectors

1. Vecto r numbers 12, 13, 16 through 23, and 48 through 63 are reserved for future enhancements
by Motorola. No user peripheral devices should be assigned these numbers.
2. ~eset vector (0) requires four words, unlike the other vectors which only requ ire two words,
and is located in the supervisor program space.
3. The spurious interrupt vector is taken when there is a bus error indication during interrupt
processing. Refer to Paragraph 4.4.2.
4. TRAP In uses vector number 32 + n.

Miscelfaneous M68000 Instructions

251

5. MC68010 only. See Return from Exception Seclion. This vector is unassigned . reserved on the
MC68OOJ, and MC68006.

routines. Some of these are fixed vectors, like CHK and TRAPV, others are
reserved for present or future systems routines, like interrupt handling. The
remaining vectors can be designated for TRAP # < vector> user applications.
As a simple example, an assembler might be VJJitten that converts, say,
COSH into the machine language eqUivalent of mAP #32. At address $80
(corresponding to vector #32) is the address of the COSH routine (whatever that
may be). Such non-M68000 instructions are sometimes known as monitor, or
service, calls. They are available to aU users, and can be made to look just like
M68OCX) instructions, complete with operands, which can be passed to the
invoked routine via registers or the stack.
CONCLUSION

At this point you have seen all the basic M68000 instructions and address modes
in action. Our examples were kept simple to isolate the " mechanics" of each
group of instructions and operands. At the same time, we tried to reveal some
of the underlying design motivations, the why that makes sense of the how. At
least you now have the essential vocabulary of "the microchip of the 1980s",
and we hope you are tempted and prepared to tackle the more cryptic texts
which tend to accompany the commercially available M68000 assemblers. May
the MOVE be with you! Before you rush away to raise havoc with your machines,
we invite you to read our final h..vo chapters on the MC68010 and MC68020.

7
The MC68010

The preceding chapters have focused spedfically on the MC68000, the first
chip in Motorola's 68000 family of micro-processors. This chapter discusses the
next member of the 68000 family, the MC6801O. Throoghout this chapter, it is
assumed that you are already familiar with the MC68000, that is, that you have
read Chapters 1 throogh 6. Since the features added to the MC68010 are of a
more advanced nature, the material in this chapter is more concentrated than
the material in other chapters.
The keyv.ord for the MC68010 is emulation, or "simulation of things that
are not really there." Most of the features added to the MC68010 VJeTe for
support of emulation. In typical emulations, nonexistent hardware is emulated
by software. For example, some printers have been manufactured which have
no fonnfeed capability. For these printers, it is common to emulate form feeds
in software by keeping track of the number of lines currently printed on a page,
then printing enough additional Iinefeeds to make up a total of 66 lines. One
of the most pov..oerful applications of emulation is in virtual memory systems,
wherein programs may directly access address locations far beyond the actual
range of the available hardware memory. Virtual memory alone \.\Jol1id have
guaranteed the MC68010 a place in history. But the MC68010 does more.
The MC68010 is also capable of emulating whole operating systems and
nonexistent (user-defined) 68000 instructions. These are commonly knovJn as
virtual machine capabilities. Such features simplify the development of new
operating systems, which is by nature a very difficult but necessary task. The
virtual machine also enables Motorola to check out (emulate) the behavior of
future members of the 68000 processor family long before the chips are actually
available, and even before the design of the new chip is finished on paper: This

252

The MC68010

253

can be done in software on the MC680l0 (or later 68000 processors). After
the new 68000 processor is available, emulation perlonns yet another valuable
function . MC68010 users who cannot upgrade their computers to a later 68CX)()
processor can emulate in software many of the features of the later processor:
It is easy to see why Motorola implemented emulation capabilities early in
the 68000 family history. From that point on, the MC68010 reduced the

research costs of all further 68000 processors.

In this chapter

VJe

will talk about virtual memory and virtual machine

capabilities, and the specific features that were added to the MC68010 to
support them. FoIIOVJing that is a discussion of the different address spaces, and
their role in the security features of virtual memory hardware. At the end of the
chapter we will discuss loop mode, which speeds up the execution of certain
small program loops; finally, VJe will discuss the MC68012 processor, a close
relative to the MC68010.

VIRTUAL MEMORY
In any computer, there is a certain amount of real hardware memory available.
In most computers, users are limited to using only this hardware memory.
Previoosly, only mainframe computers and some minicomputers used software
hicks to make it appear that there was, "virtually more memory available than
there was hard\.vare", hence the term virtual memory. In the friendliest type of
virtual memory environment, the user accesses memory withoot any restrictions,
and never knOVJs (nor needs to be bothered by) how little hardware memory is
actually available.
Does this not sound like a programmer's heaven? How is this possible, you
ask, and what is the catch? Your suspidons are indeed VJelI-founded; there are
some important drawbacks.
At any given time, the hard\.vare memory contains only part of the virtual
memory being referenced. The remainder of the virtual memory is actually
stored somewhere else, usually on a disk. For example, consider a simple virtual
memory system which only has 192K of hardware memory, but allows programs
to address up to 384K of virtual memory. In this system, memory is divided
into segments (or "pages" ) of 64K each. Hence, no more than 3 pages of
memory will be in hard\.vare memory at any time, even though 6 pages appear
to be available to any program. Page 1 is the operating system, and must always
be in hardware memory. Pages 2 through 6 make up a large user program
which is currently running, and which resides on the disk in its entirety. Figure
7-1 compares the arrangement of memory on disk, in hardware memory, and
as it appears to the virtual memory user. The virtual memory configuration is a
fantasy: it doesn't exist anywhere, except as a set of pointers to the disk and the

254

68000, 68010, and 68020 Primer

Disk Mamol'!

Pag02

Pag03

Page 4

Virtual Memory

Page 1 (OS)

Page 2

Page 3

Hardware Memory

Page 1 (OS)

Page 2

PagoS

PageS

Page.

Page 5

Page 6

Beginning Memory Configuration

Disk Memory

Page 2

Page 3

Page

Page 5

Page6

Virtual Memory

Page 1 (OS)

Page 2

Page 3

Page 4

Page 5

Hardware Memory

Page 1 (OS)

Page 2

Page 6

Second Memory Configuration

Disk. Memory

Page 2

Page 3

Page 4

Page5

Page6

Virtual Memory

Page 1 (OS)

Page 2

Page 3

Page 4

Page 5

Hardware Memory

Page 1 (OS)

Page 2

Page 6

Third Memory Configuratjpn

Fig. 7-1

68000 Vi rtual Memo ry Configurations

hardware memory. When the user program starts executing, memory is arranged
as shown in the beginning configuration in Figure 7-1 .
The virtual memory system has loaded in only the first page of the user
program at this time (page 2). Now suppose that the user program asks for
some data that is stored in page 4 of the program. As far as the user program
is concerned, nothing is known about the virtual memory system; the program
simply addresses a location within page 4, but the virtual memory system
automatically detects that page 4 is not currently in hardv.lare memory, and
fetches it from the disk. Thus, memory is now arranged as in the second memory

configuration in Figure 7-1.

The MC68010

255

Whenever the user program references data within page 4 , the virtual

memory system converts these address references into the corresponding true
hardware addresses. Note that page 4 is actually residing in the third page of
hardware memory; the user program will ask for addresses within page 4 , but
will end up getting addresses within the third page of hardware memory.
Nco! suppose that the program asks for some data within page 5 . Since
there is no unoccupied hardware memory left, either page 1, 2, or 4 must be
dumped in order to make room for page 5. The best use of resources is to
replace (or "swap" ) page 4 with page 5. If page 4 was changed while it was in
hardware memory, it must first be written back to disk in its new form. In any
case, page 5 then replaces page 4, and memory is now arranged as in the third
memory configuration shown in Rgure 7-1.
The decision about which page to swap out and the size of each page. is
a function of many things. For now, let us just say that if yoo have some good
ideas in this area your programming future will be a rosy one. Since disk accesses

are at least 100 times slOVJer than memory accesses, \.Ve see that the tradeoff in
virtual memory is having more memory available, but at a slQIJ.IeT execution
speed. Furthermore, totally unrestricted and poorly planned use of virtual memory can result in situations where excessive disk/memory swapping goes on. For
example, suppose that the program above \.Vent into a loop where page 4 and
page 5 were accessed alternately 1000 times. This would cause 1000 disk
swaps to read the same two pieces of data - a buly wasteful situation. So
remember, virtual memory should be used with caution.
In order to effidentiy implement virtual memory, it is necessary to detect
or "trap" illegal memory references and do translation of addresses from virtual
address into harch..vare address, all via external hardware, usually a memory
management unit. Without this capability, the CPU would be hopelessly bogged
oo..vn checking every memory reference in every single instruction.
When an illegal memory reference is made in a system without virtual
memory, it is not initially detected by the 68000. With no loss of time, the 68000
passes on the request to the bus, which dutifully passes it on to the memory
("call for Mr Hex FFFFFFFO!" ), which is not a real hardware memory location.
The bus detects this, and notifies the 68000. The 68000 generates a bus error
exception in the middle of the current instruction within the user program, saves
(on the system stack) infonnation about the instruction in progress when the
bus error occurred, and then goes to the OS's standard bus error processing
routine. Usually. the bus error is reported, and the user program is aborted.
How is virtual memory implemented? Imagine that some instruction such
as MOVE asks for a memory location (the virtual memory location) that is VJel.I
beyond the real hardware memory limit How is it possible for this fact to be
quickly detected and remedied? In a system with virtual memory, a hardware
memory management unit is generally present betvJeen the 68000 and the bus.
This unit intercepts each memory request, translates the virtual address into a

256

68000, 68010, and 68020 Primer

possibly different hard\.vare memory address, then fetches data from this location

and returns it to the 68000. It appealli to the progyammer and the 68000
processor that the data was actually fetched from the virtual memory location.
The memory management unit maintains a table of what virtual memory pages
are currently in hardware memory, and where they are located in hardware
memory. If the virtual address is currently not available in hardware memory,
the memory management unit generates a bus error, which suspends the current
instruction in the middle of its execution. The instruction in progress is suspended, infonnation is stored on the system stack, and the operating system's
bus error routine is activated. The bus error routine examines the information
that was saved on the system stack. If it was due to a virtual memory access,
then the appropriate disk/memory swap is done. Afterward, an RTE instruction
returns to the user program , and finishes the user instruction that was in progress.

Why is virtual memory possible on the MC680JO but not on the MC68000?
Unlike the MC68010, the information pushed on the system stack by the
MC68000 during the middle of the instruction that generated the bus error
exception is not sufficent for the RTE instruction to finish that instruction. It is
only sufficent to enable software diagnosis of what happened, so that an
informative error message can be sent to the user when his or her program is

aborted.

VIRTUAL MACHINE
The MC68010 not only supports virtual memory, but the more general concept
of a virtual machine. In virtual memory, actual disk room emulates imaginary
hardware memory. Other software and hardware emulations can be effected in
similiar wCJ.js.
For example, the concept of disk buffer caching is the exact opposite of
virtual memory; the user appears to be writing to disk, but is actually writing to
memory. In a caching system, everything read and written to the disk is also
redundantly stored in hardware memory for future use. Later on, if the same
disk data is again requested, it is fetched from the memory cache rather than
from the disk. Since memory fetches are several orders of magnitude faster than
disk accesses, the benefits should be obvious.
Another classic example of hardware emulation is a printer spooler. In some
spooling systems, the user is convinced that his program is sending data directly
to the printer, when actually it is going to a temporary file on disk, or to mag
tape. The disk file may actually be printed immediately, hours later, or never
This is of particular importance on machines with one printer and many users,
since only one user can be al10v,.0ed on the printer at a time, but it would be
unreasonable to make evel)K>I1 e1se wait for the current user to finish his
printing.

The MC68010

257

Even more sophisticated is the ability of a n Operating System (OS) to

emulate another OS. What is an OS? It is the most important program run on
any given computer: It is there when the computer is turned on, remains there
until the computer is po.vered down, and controls the execution of every other
program run on the computer. It is sometimes refered to as the monitor. In
many perronal computer.;, the
is stored in Read Only Memory (ROMI, to
protect it from accidental destruction.
How is the
program originally created? It can be done from scratch,
but only with a great degree of difficulty. A more feasible method is to use a
pre-existing
(call it OS-II to oversee the development and execution of the
new
(call it 05-21, until 05-2 has been debugged to a point where it can

as

as

as

as

survive on its OVJn. During this development phase, 05-1 is actually in control
of the computer, and subexecutes (emulates) 05-2. When any special drcum-

stances arise, control passes back to OS-I, which decides what to do, and
decides afterwards whether or not to return to 05-2. This emulation requires a
bit of trickery. The typical OS is, by profeSSion, an omnipotent creature. It is the
constant and sole controller of an entire computer system. In order to properly
that will eventually be on its ov.m, 05-1 m ust hick 05-2 into
emulate an
thinking that it too is omnipotent. On the MC68010, this is achieved by running
the emulated 05-2 in user mode, at a IQI..I.IeT privilege than the controlling
1, which is in system, or supervisor, mode. As long as the emulated 05-2
executes simple instructions, it is doing nothing more than is allowed to the
average user, and life is simple. As soon as 05-2 encounters any special conditions (for example, if hardware interrupts are received from external hardware,
or if errors occur due to bugs in 05-2) , a 68000 exception is generated, the
controlling 05- 1 emulates the request (often via a software routine) , and returns
control to 05-2. One virtual resource that the emulated 05-2 must have access
to is the system bit 05-2 must be able to set it, test it, and execute all of the
privileged 68000 instructions that require it be set 05-2 must be able to do all
of these successfully, and do them while actually remaining in user mode. The
hick is no different than the other virtual methods described above. Any of these
actions generates a 68000 exception, the controlling 05-1 carries out the request, and returns control to 05-2 .
On the MC68000, the 05-2 can determine that it is not the controlling OS
by doing a MOVE 5R,Dn and then testing the system bit. This IMJrks because
MOVE from 5R is not a privileged instruction on the MC68(x)(). Because of
this and other loopholes, the MC68000 cannot fully support emulation.
On the MC680IO, this loophole is closed by making MOVE from 5R
prtvileged. When executed from user mode, MOVE from 5R generates an
exception, the controlling 05-1 takes over, and then has the option to copy a
counterfeit 5R (with the system bit off) into On , and return. The emulated 052 has no Wi!1.J of detecting that this is actually what happened. The (unprivileged)

as

as-

258

68000, 68010, and 68020 Primer

MOllE from CCR instruction was added to the MC680lO so that the condition
codes could still be accessed IAlithout generating an exception.

Another loophole preventing the MC68000 from fully supporting emulation

is the fact that the infonnation pushed on the stack during an exception is not
suffident to complete the instruction, but only to diagnose what happened. This
was mentioned in the preceding section on virtual memory.
What is to prevent the emulated 05-2, omnipotent as it (thinks it) is, from
doing its own emulation of a third OS-3 while it is still in the emulated environment? The answer is nothing at all. If this VJere not so, the original emulation
IJJOUld not be a true emulation. Furthermore, there could be a long chain of
emulated 05-n's, each thinking it is on top, and totally incapable of determining
whether or not it really is.
The most sophisticated emulation is the emulation of a CPU by another

CPU. This allows software for a new CPU (for example, the MC68020) to be
developed and debugged on a pre-existing CPU (for example, the MC68010),
while the new CPU is still under hardware development. This CPU emulation
is possible IAlithin the 68000 processor family because its instructions sets have
been designed to be upward compatible. Thus, any instruction from any 68000
processor will execute the same on all later 68000 processors; on earlier 68000
processors, the instruction either executes the same, or is an illegal instruction
and generates an illegal instruction exception. Thus, to emulate an MC68020
instruction in an MC68010 operating system , it is only necessary to modify the
illegal instruction rcutine in the OS to check for this particular instruction, and,
if detected, emulate the instruction in software before returning.
If emulation is so versatile, why aren't more CPUs and ass emulated in
day-to-day use? The simple answer is effidency. The emulated (software) CPU
may run many times slo.ver than the true (hardware) CPU, due to the overhead

of exception processing and the use of whole routines to emulate ~ngIe instructions.
This finishes rur discusron of the major emulation features of the MC68010.
The next three sections examine the new registers and instructions that are used
to support emulation and virtual memory hardware.

VECTOR BASE REGISTER

The MC680lO has a Vector Base Register (VBR), used during emulation. It is
not present on the MC68000. It is used to support transitions betvJeen a normal
operating system environment and an emulation environment In order to appredate its Significance, we will need a little backgrcund.

When an exception is generated on the MC68000, several events take

place. Depending on the kind of exception, certain spedal registers are modified,
certain infonnation is pushed onto one or more stacks, and, last of all, a branch
is made to one of 255 possible exception rcutines. All we are concerned IAlith

The MC680 10

259

here is that final branch. For example, division by zero causes a branch to
exception routine number 5. The addresses of these 255 routines are found in
the first 256 Jon9'OOrds in memory (the first of the 256 lon9'OOrds is not an

address, but is the stack pointer at JlOI.oI.IeT-up time). Rigorously, the address of
exception routine number n is found in the longword at memory location 4n.

For example, the address of the divide-by-zero routine is at hex memory location
$14 ( = 4 x 5 ). In conventional 68CX)() terminology, n is called the exception
vector number, 4n is called the exception vector offset, the address at Iong'M)fd
4n is called the exception vector, and the table of 255 longv.ad addresses is
called the exception vector table.

NovJ imagine that the normal OS is overseeing the emulation of another

as. Based on discussions earlier in this chapter, it is easy to see that,

during

emulation , exceptions will be treated radically different than during normal

operation, since they will be heavily concerned with making sure that the
em ulated OS is kept in the dark about what is really happening. An alternate
set of exception routines will be active, having different addresses from the
normal set of routines. There are various ways to switch betvJeen tvJo sets of
exception routines, some of which do not require any new registers, but the
Simplest is to use the vector base register.
In the MC680 10, exceptions end with a branch to the address contained
at memory location 4n + VBR, where VBR represents the number currently
stored in the vector base register. Note that, if VBR is zero, this is the same as
the MC68000 exception branch. Indeed, during povJeT-up, VBR is set to zero.

Thus, an OS for the MC68000 will run exactly the same on the MC680IO.

as

When an
sets up an emulation environment, it loads a set of alternate
exception routines and sets up an alternate vector table (not located at memory
location zero) . Thereafter, to enable the alternate exception routines, it is only
necessary to move the location of the alternate vector table into VBR. This is
done with a single MOVEC instruction. To go back to norma) operation, it is
only necessary to set VBR back to zero. The overhead for switching betvJeen
sets of exception routines is thus reduced to its bare minimum, namely, one
MCNEe instruction. This quick switch not only saves time and program steps,
but also avoids a potential problem; if an interrupt occurred in the middle of a
lengthy vector table changeover, hQI..V could \Ale guarantee that the correct interrupt routine is used?
The follooiing sample program changes the value of VBR to hex $OOl ()()()()().
/oKlVE . L
MOVEe

1$100000, DO

DO , VBR

Set up new VBR value

Change vector base register

The MOVEC command is discussed in the following section.

Figure 7-2 shovls typical memory allocations for a regular operating system

and an emulated operaH"9 system. Steps 1 to 3 follow what happens during a

260

68000,68010, and 68020 Primer

Memory
Address

Contents of
location

VBR

00000000

VBR

00100000

Used during regular operation steps (1), (2), (3)

Used during emulation operation steps (4), (5), (6)

00000000

Regular
Exception
Vector
Table

(2) Look up address Vector at hex location 00000014

_ 4 x 5 (Vector Number for Divide by Zero) .. VBR
Vector is address of Divide by Zero routine (3)

00000400

Regular
Operating
System
and
Regular
Exception
Routines

(3) Divide by Zero routine

#001-255

Regular
User
Program

(1) Divide by Zero encountered here

Generating exception Vector Number 5
VBR is hex 00000000

00100000

Emulation
Exception
Vector
Table

(5) Look up address Vector at hex location 00100014

_ 4 x 5 (Vector Number for Divide by Zero) .. VBR
Vector is address of Divide by Zero routine (6)

00100400

Emulated
Operating
System
and
Emulation
Exception
Routines

(6) Divide by Zero routine

#001-255
Emulation
User
Program

fig.7-2

(4) Divide by Zero encountered here

Generating exception Vector Number 5
VB A is hex 00100000

Use of the VBR During an Emulation

The MC68010

Table 7-1
Control

Regis!er

He,
Code

Control Register Move Commands

MOVEC
Instruction

From SR
From SR

68010

ToCeR

VBR
SFC
DFC
MSP
ISP

CAC R
CAAR

MOVE

Instruction

68000
68000

To SR

From CCR
USP

800
801
000
001
803
80'

002
802

261

68010
68010
68010
68010
68020
68020
68020
68020

68000
68010
68000

Privilege
Status

Privileged
Not privileged
Privileged
Not privileged
Not privileged
Priv ileged
Privileged

Privileged
Privileged
Privileged
Priv ileged
Priv ileged
Pri vileged

divide-by-zero exception under a regular operating situation. Steps 4 to 6 follow

what happens during a divide-by-zero exception under an operating system
emulation environment. Switching back and forth between the tvx> sets of
exceptions is accomplished by simply changing the vector base register.

THE MOVEC AND MOVES INSTRUCTIONS

MOVEC is a privileged instruction on the MC68010 which moves data to and
from "control registers". An easy rule of thumb is that MOVEC perfonns all the
moves that MOVE doesn't perform. The only exception to this rule is register
USp, which can be moved using either MOVE or MOVEC. If Motorola had it to
do all over again, it \AJOUld probably have MOVEC also perform the functions of
the other special MOVE instructions, namely, MOVE USp, MOVE SR, and MOVE
CCR. This \AJOUld have made for a more homogeneous instruction set.
The chief uses of MOVEC on the MC68010 are to change the values of
the vector base register (discussed above) and the function code registers, SFC

and DFC (discussed belowl.

Table 741 summarizes all of the 68000 instructions that move control
registers. For each type of control register, the table indicates whether the register
can be moved using MOVE or MOVEC, and the first processor on which each
instruction is implemented. A blank entry indicates that the instruction is not

262

68000, 68010, and 68020 Primer

available on any existing 68000 processor. The hex code column gives the 3digit hex code used to represent each control register in the MOVEC instruction.
MC68020 instructions have been included in the table for completeness.

THE SFC AND DFC REGISTERS AND

ADDRESS SPACES
The Soorce and Destination Function Code (SFC and DFC) registers are 3-bit
registers which designate different "address spaces" . Only 68(x)() programmers
involved in the deepest system work will probably ever have to deal with these
registers. They are involved in the support of memory management and system
security. In a system that protects certain parts of memory, the SFC and DFC
are used within supervisor mode to access memory that is normally inaccessible.
In order to fully explain hOVJ the function code registers operate, it is necessary
to look at the actual 68000 hardware.
Up to 32 of the pins coming out of a 68000 processor are address lines.
When data is read from or written to memory, these lines carry the 32-bit
address of the affected memory location. Three more pins are used as function
code lines. The function code tells what kind of memory is being accessed, for
example, whether it is program memory or data memory, or whether it is user
memory or system memory. At the same time, the function code indicates a
memory bank or "address space" to look in. Technically speaking, it is possible
to spedfy up to 8 different address spaces, each having a 32-bit address range,
and each conceivably corresponding to different hardware memory. Initially, this
SOJnds equivalent to a 35-bit address range. In actuality, however, only 4 full
32 -bit address spaces are used by the 68()(X) and, in typical hardware implementations, these 4 address spaces are made to address the same 32-bit address
range of hardware memory. Hence, expectant programmers dreaming of more
than 32 bits of addressing shoold beware.
Table 7-2 lists the 8 function codes and their currently assigned address
spaces.
If the 68000 is currently in user mode (that is, the system, or supervisor,
bit is 0), and an instruction is being fetched from memory, then a function code
of 001 goes out the function code lines. When an instruction fetches data from
memory during user mode, a 010 goes out the function code lines. When the
same two operations occur in supervisor mode, a 101 or 110 goes out the
function code lines.

The fifth and last function code is the CPU space fu nction code. This
special code appears during four types of communications with external hardware devices, namely, during interrupts, breakpoints (BKPT instruction), access

The MC68QIQ

Table 7-2

Address Space Function Codes

Address

Function
Code Birs

Space

000

Unavailable -

001

User Data Space

User Program Space

010
011
100

101
11 0
111

263

reserved for future Motorola use

Reserved for user definition

Reserved for future Motorola use
Supervisor Data Space lincludes Exception Vectors 2 to 255J
Supervisor Program Space li ncludes Exception Vectors 0 and 1J
CPU Space lin MC68000, onl y used for Interrupt Acknowledgel

level control (the MC68020 instructions CALLM and RTM) , and coprocessor
communications (the MC68020 coprocessor instructions). The CPU space is
special in that it does not address memory. Instead, the 32 address lines are

used to pass various parameters.

When the 68000 reads or writes to memory, a 32-bit address is sent out,
along with one of the first four function codes. Hardware outside of the 68()(x)
decides what to do about the request. In the simplest situation, the external
hardware simply ignores the function code, uses the 32-bit address, and looks
up the location in hardware memory. In a more sophisticated situation, four
different sets of hardware memory can exist, one for each of the first four function
codes. In such a case, it is possible for an operating system, an OS data table,
a user program, and a user data table to all reside at the same numerical
address. Each can be accessed with the same address, but with a different
function code.
The function code can also be used to implement system security. This
can be done via an external memory management device, whose duty is to
make sure that users are not allQl..l.led to access certain parts of memory. For
instance, an OS might wish to allOVJ users to run programs that are in the
supervisor space (function code 110), but not allOVJ them to look at the programs
themselves (function code 101). If the address spaces for these tVJO function
codes actually correspond to different hardware memory, then the user can
never actually access the program as data. The program is thus invisible and
secure from examination. If these tVJO address spaces actually correspond to
the same hardware memory, then the user can access the program as data, and
it is necessary to enlist the aid of the external memory management device in
order to prevent the user from examining the program.

264

68000, 68010, and 68020 Primer

Say that you are on one of those v.onderful systems where there are indeed
four different sets of memory. Assume that you wish to access the contents of
address 123456 in all foor memory address spaces. The data memory address
spaces are easy to get to, but the program memory address spaces are inac
cessible. Inaccessible, that is, unless you use MOVEC and MOVES. The follow
ing example shows ho..v to access one of the four memories, the user program
space.
MOVE. L

12.00

MOVEC
MOVES . L

DO , SF'{;

123456, Dl

User program space function code = 2

Move into source function code
Get word 123456 from user program
space

Note: Changing SFC or DFC only affects the execution of the MOVES instruc
tion . It does not have any effect on the execution of other instructions.
The ability to distinguish different address spaces enables the MC68010 to
indicate to external hardware when it is accessing system programs, system
data, user programs, and user data. It is thus possible to selectively protect one
or more of these address spaces from user access via external memory man
agement hardware, without bogging down the 68000 CPU with time-consuming
checks. With proper hardware, each address space can be made to correspond
to different hardware memory. Typical implementations, hOVJever, use only one
set of hardware memory. Using the SFC and DFC regist"", the MOIIEC instruction, and the MOVES instruction within (privileged) supervisor mode, it is
possible for the OS to access all four of these address spaces.

LOOP MODf
The MC68010 automatically detects when certain 3v.ord instruction loops have
repeated more than one time, and then goes into loop mode. In this mode, the
instructions are not repeatedly fetched from memory, as VJOUld occur during
normal operation , but are locked into the CPU prefetch queue and decode
register, and not fetched again. If the loop is interrupted by any exceptions, loop
mode will resume after returning a nd going through tVJO more loop repetitions.
Thus, simple loops such as the movement of a block of bytes, the summation
of a list of numbers, and the shifting of a group of numbers, can be executed
at speeds comparable to the speed of a single (for example, block move)
instruction.
The allowable loops consist of certain 1-v..ord instructions followed by a
DBcc instruction. The ll.IJOrd instructions allQl..\.led are summarized in Table 7
3 where lea represents loop effective address modes (An), -(An), or (An) + and
rea represents Dn or An.

The MC680 I0

Table 7-3

265

MC68010 Loopable Instructions

Instructions

Operands

MOVE
ADD SUB
CMP
AN D OR
EOR
ABCD ADDX SBCD SU BX
ClR NEG NEGX NOT
TST NBCD
ASl ASR l Sl lSR
ROl ROR ROXl ROXR

lea, tea
lea, rea

lea, rea
lea,Dn

oc
or
or
or

rea, lea
On,lea
(Ax) + ,(Ay) +
Dn,lea

Dn, lea

- (Ax), - lAy)

lea
lea
lea
lea

THE MC680 12
The only difference between the MC68010 and the MC68012 is that the
MC68012 can address up to either 1024MB or 2048MB of RAM (a 30-bit or
31-bit address) , compared to 16MB on the MC68010 (a 24-bit address). For

all practical purposes, the programmer may consider them identical.

Why did Motorola make the MC68012? If an application requires more
than 24 bits of addressing, it might seem appropriate to simply use an MC68020,
which allQI.AIS a full 32 bit address. l-b..vever, there are two good reasons why
an MC68012 can be preferable: money and matenals. The MC68020 will be
priced significantly higher for a while, due to the development cost of its many
new features. Also, the MC68020 has a different pin configuration, and will not
HI inlo the sockets that fit all of the preceding members of the 68000 family.
Thus, it is possible to produce hardware using the MC68010, and later upgrade
them to a 30-bit address by simply replacing the MC68010 with an MC68012.

Upgrading to an MC68020 u.oJld require a new socket.

CONCLUSION
Starting with the MC68010, any 68000 processor can emulate all of the
instructions of any other 68000 processor. Except for the loop mode feature, all
of the features that were added to the MC68010 were solely to support these
emulation capabilities. Fully supported emulation can also be used to carry out
other very po.verfui emulation functions, such as virtual memory and virtual
machines.

8
The MC68020

In this chapter VJe discuss the additional features of the MC68020, as compared
with the MC68010. This chapter assumes that you are familiar with the 68000
family in general, and that you have read Chapter 7 on the MC680 10.
The new features of the MC68020 cover much territory. Additional features
include a full 32-bit addressing path , an instruction cache to speed up 68000
instruction execution, 7 instructions to support coprocessors such as Motorola's

MC68881 floating point coprocessor, 6 new addressing modes to support more

versatile addressing, and a master system hit to support environments with
multiple operating systems.
In addition, a variety of miscellaneoos instructions have been either extended or added , including 8 instructions to manipulate bit fields, several new

divide-and-multiply fonmats, and extended displacements on branch instructions.

Rnally, the MC68020 has a dynamic bus sizing interface, which enables
the processor to communicate with 8, 16, or 32-bit devices, making 8-, 16-,
or 32-bit data transfers, and to do them in any combination at any time. Thus,
all data alignment restrictions have been eliminated, except that instructions
must still lie on even-byte boundaries.
The processor has 120 pins, which are arranged in a square pattern on
the bottom, rather than the edges, of the chip. Hence, upgrading a system from
an older 68000 processor to a MC68020 requires a new socket.

INSTRUCTION CACHE
The instruction cachi ng system of the MC68020 is a mechanism that speeds
up the execution time of programs with small loops. It is an MC68020 feature

266

The MC68020

267

that will benefit all of its users. It can be easily enabled or disabled, requires no
change in how programs are written, and introduces no overhead in the normal
processing of the MC68020 in exchange for its advantages.
CACHING IN THE 68000 fAMilY
Motorola has used analysis of past programming experiences to gUide the design

of the 68()(x) family. The MC68020 on.-chip cache is another application of this

philosophy. Studies of assembly programs shovJ that most of their overall execution time is spent inside of fairly smaJl-sized loops. Without any kind of
instruction cache system, each time a loop executes, its instructions must be

fetched from memory. If a small loop executes more than once, the same
instructions are repeatedly fetched. This is hOUJ the MC68000 and most other
processors function.

The MC68010 introduced a medium-scale version of caching, called loop

mode. Loop mode only caches 3 instruction words, and only occurs when the
last 2 words are a OBcc instruction. See Chapter 7 for further details on loop

mode.
The MC68020 introduced a full-scale version of caching. Previously executed instructions are stored within the MC68020 processor, in a 64-longword
cache (a 256-byte internal memory area). The first time a program loop executes, no benefits are realized from the cache; each instruction is fetched from
memory, just as in the MC680 1O. Starting with the second time through the
loop, ho..vever, the cache system detects that the instructions are already within
the cache, and does not tie up the external bus fetching them again. The net
result is faster execution time.
HOW CACHE WORKS

We now detail how the cache functions. First, however, some preparation is
necessary. You should review the discussion about the function codes in Chapter
7. In that discussion, you saw how 68000 memory references involve a total of
35 hits. A 3-bit function code tells which "address space" to look in, and a 32bit address gives the harcMJare memory address within that address space. The
5 address spaces used by the 68000 and their use in the cache system are

outlined in Table 8-1.

Note that instruction fetches only occur with binary function codes 010 or

lIO. We can represenl ei!her of!hese binary function codes in general by flO.
Accesses made to the other three address spaces are not instruction fetches,
and are thus not cached. Whenever an instruction word is fetched on the

268

68000, 680/0, and 68020 Primer

Table 81

Caching of Address Spaces

Function

Code

Address Space

Cache Capability

001

User Data Space

User Program Space
Supervisor Data Space
Supervisor Program Space
CPU Address Space

Not cached
Cachable
Not cached
Cachable
Does not access memory

010
101

110
111

MC68020, the entire even-VJOrd-boundary longv.urd containing that VJOrd is

fetched. Hence, the last tVJO bits in the address of the longv.urd fetched are
always zero. Thus, we may figuratively view the 35 bits in the memory fetch
parameters as:

Function Code

Hardware Memory Address

(3 bits)

(32 bits)

flO

tttttttt tttttttt tttttttt iiii i ioo

The 24 t-bits are called the cache tag, and the 6 ibits are called the cache

index. It is the 6bit cache index that determines which of 64 positions the
instruction longword will occupy in the cache. If two instruction longwords have
the same cache index, then only one of them can be in the cache at any given
time. Thus, any t1M:J lon!jlM)rds located exactly 256 (or 256nl bytes apart in
memory will not be able to coexist within the cache. Note that this allocation
method satisfies two basic criteria: it is simple (that is, fast) to carry out by the
processor, and it guarantees that any contiguous segment of up to 64longv.oords
in memory will fit into the cache at the same time.
In the instruction cache, 5 quantities are maintained for each instruction
10ngVJOrd, as follows:
Cache index
Cache tag

Cache FC2

= The leftmost bit of the function code (1 for supervisor program space, 0 for user program space)
= 1 if cache data is valid, if not valid
= The contents of memory location address if valid bit is 1
(undefined if the valid bit is 0)

Valid bit
Cache data

Address[7:2]
Address(31:8]

~
~

6 bits of the 10n!jlM)rd address

The upper 24 bits of the 10n!jlM)rd address

The MC6B020

Table 82a

269

Initial Program Instructions

Address

Hex

oo l 000F4

OO lOOOF6

aaaa
bbbb

oo l000FB

ecce

OO IOOOFA

dddd

oolOooFC

eeee

OO IOOOFE

fflf

00100 100
00 100102

gggg

hhhh

Table 8-2b Contents of Instruction Cache at Start of

Program
Index

Valid

00

04-F4

F4

0
0
0

FB
FC

Fe2

Tag

Dafa

The cache index is a number from 0 to 63, and defines which of the 64
cache positions to look up. The other four quantities are stored at that position

in the cache.
CACHE EXAMPLE

When the MC68020 first powers up, all of the valid bits are cleared to zero.
Table 8-2a sho\.vs a sample program at startup, and Table 8-Zb shows the initial
state of the instruction cache. Note that the actual instructions stored at the
locations sh""" in Table 8-2a are represented figuratively by the hex numbers
"aaaa" through "hhhh".

270

68000,68010, and 68020 Primer

Table 83a

Program Instructions After Six Instructions

Have Been Executed
Address

Hex

00 1OOOF4

aaaa

001000F6
001000F8
001000FA
001000FC

bbbb

001000FE

eeee

....

dddd

flf!

00100100
00100102

gggg
hhhh

Table 8-3b Contents of Instruction Cache After Six

Program Instruct ions Have Been Executed
Index

Valid

00
04F4

F4
F8
FC

FCl

Tag

Data

00 1001

gggghhhh

0
0
0

001000
00 1000
00 1000

aaaabbbb
eeecdddd
eeeeffff

The first instructions executed by the MC68020 are all cache " misses",
that is, they are not in the cache, a nd have to be fetched from external memory.
For each cache miss, the appropriate cache tag, cache FC2, and cache data are
stored in the cache, and the valid bit is set to 1 to indicate that valid data is now
present at that cache position.
In Table 8-30 the ;nslructions al hex locations 00lOOOF6 through 00100100
have been executed , as indicated by boldface type. Table g-3b shOVJS that the
instruction cache has also been suitably updated, that is, the valid bits for all
affected cache positions have been set to 1, and the appropriate cache FC2,
cache tag, and cache data values have been stored. Note that the cache picked

up the entire lon9"Ord at hex location 001OOOF4, ewn though only the loo.er
order I,.V()rd was needed. This is because the cache only reads longv.A:>rds on

The MC68020

271

longv..ord boundaries. Similiarly, the cache picked up the entire longvJOrd at hex

location 00100100, even though only the higher order Imrd was needed. Note
also that when the last two hex digits of the program address went from FE to
00, the cache index wrapped aroJnd from the end of the cache to the beginning.
If a cached instruction is executed again while it is still in the cache, a hit
is made. When a hit occurs, the instruction is fetched directly from the cache,
and no external bus cycles are required. For example, in Rgure 8-2, if the
instruction represented by hex digits "gggg" happens to be a branch to instruction " aaaa" at hex location OOlOClOF4, then a hit will occur because instruction
"aaaa" is already stored in the cache. Note that instruction "aaaa" was never
actually executed, but was previoosly fetched along with instruction " bbbb"

because these two instructions are part of the same longword. Rigorously speak.
ing, a cache hit occurs whenever the cache index, cache tag, and cache FC2 for
an instruction fetch matches a cache entry from a previous "miss".

CAC HE REG ISTE RS

In support of the cache system , tv..o new control registers have been added to

the MC68020, namely, the CAche Control Register ICACR) and the CAche
Address Register ICAARI. Both are 32-bit registers, although only 4 bils of the
CACR and 6 bits of the CAAR are currently used. In addition, the MOVEC
instruction has been revised to allow access to these registers.
The CACR contains four bits that allow the user some control over the
cache. Except for these four operations, the cache is automatic and inaccessible.
The four bits are:

1 bit 2 bit 4 bit 8 bit -

Enabte cache lEI

Freeze cache IFI
Ctear Cache Entry ICE); uses CAAR
Clear cache ICJ

If the E bit is 0, no caching occurs; all instructions will be fetched from

external memory. If the E bit is 1, caching occurs. On power-up, the E bil is 0,
so it must be set before caching can begin. This can be done via the foll()\.\,/jng
instructions:
MOVE . L 11, DO
MOVEC

DO, CACR

Set up an E bit
Move into CACR

If the F bit is 0, caching goes on as described above. If it is 1, then the

cache becomes read only; hits are processed as before, but misses do not create

272

68000, 68010, and 68020 Primer

new cache entries. This could be of use during emulations when the programmer
wishes the emulation routine not to change the cache. It can also be used in
certain cases to get better cache results. One such case is discussed below under
"Cache limitations". The F bit can be set as follows:
MOVE . L
MOVEC

' 3, 00
00 , CACR

Set up an F bit and an

Move into CACR

E:

bit

Or, alternately,
MOVEC CACR , DO

OR!

12, 00

MOVEC DO, CACR

Read current CACR

Set F bit, don' t change other bi ts
write new CACR

If the C bit is read, it will always be frund to be zero. If the C bit is set,
hO\.lJeVel', it causes the entire cache to be cleared. The C bit can be set as follows:

MOVE .L 15 ,00
MOVEC

DO, CACH

Set up a C bit and an E bit

Move into CACR

The CE bit is similiar to the C bit, except that it only clears one cache entry.
If the CE bit is read, it will always be zero. If the CE bit is set, the cache entry
designated by CAAR is cleared. This entry is given by the cache index (bits
17:2)) of CAAR.

CACHE LIMITATIONS
The cache system is simple in execution, and is modestly sized. Hence, there
are situations where the programmer should be aware of the limitations of the
cache. Keep in mind that in all the situations described bel()IJJ an active cache
is always as fast or faster than an inactive cache. Thus, enabling the cache can
only improve execution speed.
First, the instruction cache may fai l to improve the execution of large
program loops. The cache is limited to 256 bytes. If a loop is greater than 256
bytes and is executed many times, the cache will not have enough room to store
all of the instructions. Some instructions will have to be repeatedly refetched to
replace others.
Second, routines used in both user and supervisor modes may be refetched,
even if they are already in the instruction cache. The cache considers user and
supervisor memory accesses to be distinct. In a typical hardware situation (as
explained in Chapter 7) all four address spaces actually end up referendng the
same hardware memory. In another environment, there could be four entirely

Th e MC68020

273

separate address banks. Because this is all determined outside of the MC68020
chip, the MC68020 itself has no W"l of knowing what is actually happening.
Therefore, it has to assume the \UOI"St case, name1y, that sUpeMsor and user
instruction (program) references are accessing distinct memory banks.
If an instruction is accessed while in supetvisor mode (function code 110),
then immediately accessed again while in user mode (function code 010) the
MC68020 has no w~ of knOVJing if sUpeMsor instruction addresses and user

instruction addresses are actually in separate hardware memory, al'd the MC68020
is forced to refetch the instruction.
Third, data accesses are not cached. For example, say that the follOVling
instructions are executed:
MOVE . L 13, (AO )
MOVE . L (Al ), (A2)

Both MOVE instructions, including the immediate field , are cached. The
memory data areas, hovJever, are not cached. Thus, if these instructions are
executed again , the data area (AO) will be refetched. There are good reasons
for not caching data areas. One reason is that to do so would require the cache
to allow for four address spaces, versus tv.Q. Another reason is that since data
areas are subject to be changed, proper caching of data areas would require
caching of both inputs and outputs.
Fourth, the cache may have to be cleared at certain critical times. For
example, if a program is loaded into memory, and if the previous contents of
that area of memory are still in the cache, then the cache has to be cleared (or
at least disabled) . OthetWi.se, false hits will occur, leading to disastrous results.
Fifth , tv.Q or more very short program loops may be unimproved by caching.
Consider an uncommon but possible situation where part A of a program resides
at hex memory locations xxxxxxOO through xxxxxx7F, and part B of it resides
at yyyyyyOO through yyyyyy7F Note that each segment occupies 3210ngv...ords,
that is, half of the cache, but both will unfortunately be stored in the same half
of the cache, due to the way that the cache stores and addresses its data. If it
turns out that A and B alternate back and forth, then the cache will never make
a single hit because each segment keeps replacing the previous segment in the
cache. At this point, the freeze bit comes to the rescue. If the F bit in the CACR
is set to 1 after one execution of A, then part B will not make any hits, but part
A always will. Is not half a cache better than none?
Sixth, if a self-modifying program is cached, wrong results may occur. Self-

modifying programs are totally at odds with the 68000 design philosophy, so
this particular problem shouJd come as no surprise. If a 68()(x) instruction is
cached, then modified, it is left unchanged in cache memory. In the event of a
subsequent hit, the old version of the instruction (in cache memory) will be used

274

68000,68010, and 68020 Primer

in place of the new one (in external memory). The problem here is that the user
is treating his or her program as data output, and the cache is not designed to
cache data or output
For example, the following program finds the first condition code that tests
positive in the comparison of DO and D 1. It modifies itself. and then loops
through the modified instruction.
LOOP

CMP . L

00,01

These two registers stay the

TEST

BIll
LEA

fINISH
TEST.AO

ADD.'

ISlOO , (AO )

BR

LOOP

This is changed to LS.CC.CS,etc

Pick up address of test
instruction
Change the 4-bit condition code
above
Do another compare & test
pick up the Bcc instruction
Isolate the condition code
Mask off all but the last 4
hi ls

FINISH MOVE.W
ASR
AND

(AO) ,D2
#$8 , D2
,SF,02

,_

If caching is active, the &c instructions will all execute as BHI. If caching
is not active, all is okay. The best solution is to avoid selfmodifying programs.
The wisest solution to the above problem is to substitute code that checks each
of the 16 condition codes in 16 separate instructions. A few extra !J..Ords of
program will avoid a very sticky problem. The next best solution is to disable
caching and lock out all other users during the self-modifying routine. After the
routine is done, the code should be returned to its original state, the cache
enabled. and the other users unlocked.

NEW ADDRESSING MODES

The MC68020 introduces several additional addressing modes that aUOOJ for
more displacements, larger displacements, a scaling factor, and an additional
level of indirection. The beginning programmer will probably encounter few (if
any) situations where these new addressing modes are useful. He may conclude
that they simply save an extra instruction here and there. As more complex
programming situations arise, hOVJeVeT, the programmer will find increasing
usefulness in these new (and more complex) addressing modes. It is hoped that
the examples described in this section will help thi' process along.
The new MC68020 addressing modes consist of six variants to two of the
12 basic 68000 addreSSing modes. Three variants are variants of mode 110,
whose original fonn is called address register indirect with index and 8-bit

Th e MC68020

275

displacement; the other three variants are variants to mode 110011 , whose
original fonn is called program counter indirect with index and 8 -bit displacement. These tv..o sets of variants are implemented in a parallel fashion. Because
of this parallelism, we need only to discuss one of the tVJO sets in detail; the
other set follows by simple analogy.
Because of the complexity of these addressing modes, two points shoold
be clarified before proceeding.
First, the new addressing modes add together several numbers, including
signed, unsigned, 32-hit, 16-bit, and S-bit numbers. Throughout this section it
is assumed that whenever numbers are added together in address calculations
ailS-bit and 16-bit numbers are first sign-extended to 32-hits, then added. This
applies to all fields: immediate fields, shortened register values, and memory

references.
Second, assemblers on various computers may use slightly different syntaxes to represent the 68000 addressing modes. This is especially true of the
variants discussed below, since so many parameters and operations are involved.
These syntactical differences, however, should be obvious and easily translatable.
In the next five sections, we describe the original form of one addressing

mode

011

the MC68000, the "address register indirect with index and 8-bit

displacement" mode, and its three variants available on the MC68020. For the
original addressing form and its variants, we give sample effective addresses, all
built around the use of an ASCII-to-EBCDIC conversion table. As the variants
become more complex, so do the examples.

ADDRESS REGISTER AND MEMORY

INDIRECT WITH INDEX
This addressing mode has bit pattern 110 ITT, where ITT is the 3 -bit number of
an address register (AO to A7). The title address register and memory indirect
with index applies to all five forms of this addressing mode available on the

MC68020, including the original MC68000 fonn and three MC68020 variants.
As previously mentioned, the original form of this addressing mode, available on all 68000 processors, is called address register indirect with index and
8-bit displacement. It is represented by (dB,An,Rn .SIZE), where:

d8 is any 8-bit signed displacement (values from - 128 to + 127)

An is any address register
Rn is any address or data register

SIZE is either W (for word) or L (for longword)

The effective address is equal to the sum of dB, An, and Rn.SIZE. Note

that d8 and Rn.SIZE are both sign-extended before being added to An.

276

68000. 680 TO. and 68020 Primer

A useful example of this original form is given by (O,AO,DO.W). If AO

contains the base of an ASCII-to-EBCDIC conversion table, and if DO contains
an ASCII byte, then (O,AO,DOW) is the effective address of the corresponding
EBCDIC byte.
SCALE FACTOR

The MC68020 allows the inclusion of a scale factor in the effective address,
represented by (dB,An,Rn.SIZE*SCALE), where SCALE has the value 1, 2, 4,
or B.
Evaluation is similiar to the evaluation of the original fonn. The effective
address is equal to the sum of dB, An, and Rn.SIZE'SCALE. Note that dB and
Rn.SlZE*SCAlE are both sign extended before being added to An.
An example using the scale factor is given by (O,AO,DO.W*2). As in the
example given above for the original fonn, AO contains the base of an ASCIIto-EBCDIC conversion table. This time, however, the conversion table contains
two bytes per entry; the first byte indicates if the ASCII byte can be converted
to EBCDIC, and the second byte gives the actual EBCDIC byte. Thus, il DO
contains an ASCII byte, then (O,AO,DO. W2) is the effective address of the
conversion indicator, and (l,AO,DO. W2) is the effective address of the EBCDIC
byte.
In the original MC68000 lonn and in this MC68020 scaled lonn, dB can
have a zero value, but dB, An, and Rn must all be present. This is in contrast
to the three variants described below, where all registers and displacements are
optional.
ADDRESS tNG MODE VARtANT #1

This variant is called address register indired with index and base displacement,
and is represented by (bd,An, Rn.SIZE'SCALE) , where bd is a base displacement 01 0, 16, or 32 bits.
All three of the parameters bd, An,Rn are optional. This optional usage is
convenient whenever any of these registers is not needed, and a dummy (zerovalue) register is not immediately available for calculating the effective address.
Evaluation of variant #1 is Similar to the evaluation of the original fonn . If
any of the three parameters are not present, they are evaluated as zero. The
effective address is evaluated as the sum of bel, An, and Rn.SIZE*SCAlE.
Rn.SIZE'SCALE is sign-extended.
An example using this form is given by (displace! ,AO,DO.W*2). This time,
let AO be the base of a general data area, which contains several tables, one of
which is our familiar ASCII-to-EBCDIC conversion table. If displacel is the

The MC68020

277

displacement of our conversion table from the base of the general data area,

and DO contains an ASCII byte, then (displace1 ,AO ,DO.W*2) and

(displace! + 1,AO,DO.W2) are the effective addresses of the conversion indicator and the EBCDIC byte (explained above in the example for the scale

factor).
Note that a data indirect addressing mode, represented by (On), can be
generated using variant # 1. This is accomplished by opting not to use bd and
An, and using a data register for Rn.

ADDRESSING MODE VARIANT #2

This variant is called memory indired post-indexed, and is represented by

([bd,An),Rn .SIZE*SCALE,od), where od is an outer displacement of 0, 16, or

32 bits.
Evaluation of variant #2 is similiar to the evaluation of variant # 1, except
that one extra level of indirection occurs midway in the effective address calculation. All foof of the parameters bd,An,Rn,od are optional. Any parameters not
present are evaluated as zero. The effective address is evaluated by first taking
the sum of bd and An, then fetching the contents of the longv.ord at this memory

address, and finally taking the sum of this memory longword, Rn.SIZE*SCALE,
and od.
An example using this fonn is given by ([displacel ,AO) ,DO.W*2) . This
time, suppose that the data tables are not in one place, but are scattered all
ovet The starting address of each table is known, however, and all these

addresses are gathered together into a master address table, whose base is given
by AD. The quantity displacel is now a displacement in this master address
table, pointing to a number which in tum points to our conversion table. The
expression (displace 1 ,AD] itself represents the base of our conversion table, and
{(displacel ,AOJ,DO.W*2) is the effective address of the tvJo-byte entry for the

conversion of an ASCII byte in DO to EBCDIC.

ADDRESSING MODE VARIANT #3
This variant is called memory indirect pre-indexed, and is represented by

((bd,An,Rn.SIZE*SCALE),od).
Evaluation of variant #3 is similiar to the evaluation of variant #2 , except
that the extra level of indirection occurs at a different point in the effective
address calculation. All four of the parameters bd,An,Rn,od are optional. Any
parameters not present are evaluated as zero. The effective address is evaluated
by first taking the sum of bd, An, and Rn.SIZE*SCALE, then fetching the

278

68000, 68010, and 68020 Primer

contents of the iongword at this memory address, and finally taking the sum of
this memory longIOOI'd and od.
Note that variant #2 and variant #3 differ only in whether the index is
added before (variant #3) or after (variant #2) the memory reference is made.

PROGRAM COUNTER AND MEMORY

INDIRECT WITH INDEX
This addressing mode has bit pattern 111 011 . The title program counter and
memory indirect with index applies to all five loons of this addressing mode
available on the MC68020, including the original MC68000 fonn and three
MC68020 variants.
The entire preceding discussion regarding the address and memory indirect with index addressing mode and its three MC68020 variants, applies analogously to the program-ca.mter-and-memory-indirect-with-index addressing mode.
The only difference bet\.veen these tv.u sets of addressing modes is that the
program counter (PC) is used in place of an address register (An) . Thus,
wherever "address register" appears in the preceding discussions, substitute the
words " program counter", wherever "An" appears, substitute "PC", and wherever "memory indirect" a ppears, substitute " PC memory indirect",
Note that in each of the effective address examples presented earlier; the
ASCII-to-EBCDIC conversion table can be located anywhere in memory. If the
table is located within the program itsel~ however, then the "program counter
and memory indirect with index" addressing modes should be used, because
they do not require the use of an address register (An),
For example, consider the effective address example presented above for
variant #1. In the original example, the ASCII-toEBCDIC conversion table
could be located anywhere in memory. II the table is actually located within the
program itself, then it is better to use the PC-relative addressing mode
(label,PC,OO.w*2), rather than addressing mode (displacel ,AO,OO.w*2). Using the latter mode, AD is unnecessarily tied up , a nd has to be preloaded with
data area base address via an " LEA label,AO" instruction.
Tables 84 and 85 summarize the new addressing modes, and their effective address syntaxes.

TRACE BITS TO AND T1

The trace bits allOVl the monitoring of one program by another program. For
example, it is possible for a master program Pl to monitor a slave program P2 on an instructionbyinstruction basis. This is done using the trace bit TI ,

The MC68020

Table 84

279

Add ress Register and Memory Indirect with

Index: Mode 110 rrr

Formal

CPU

Effective Address Syntax

Parameters

Original
Original

68000
68020

(d8,An,Rn .SIZE)

Variant "# I

68020
68020
68020

Requ ired
Required
O ptional
Optional
Optional

Variant #2

Variant # 3

Table 8-5

(dB,An , Rn .SIZESCALE)
Ibd,An, Rn. SIZE'SCALE)
Ilbd,Anl ,Rn .SIZE'SCALE,od)
([ bd, An, Rn .SIZP SCALE I, od)

Program Counter and Memo ry Indirect with

Index: Mode 111 011

Format

CPU

Effective Address Syntax

Parameters

Ori ginal
Original
Variant "# 1
Vari ant # 2
Variant # 3

68000
68020
68020
68020
68020

Id8,PC, Rn.SIZE)
Id8,PC , Rn.SIZE'SCALE)
Ibd,PC, Rn.SIZE'SCALE)
II bd, PC) , Rn. SIZE ' SCALE,od)
Ilbd,PC,Rn .SIZE'SCALEI,od)

Required
Required

Optional
Optional
Oplional

which is bit 15 in the status register: When this bit is set to 1, a trace exception
occurs at the end of each instruction. Thus, P-I must set the Tl bit using the
privileged instruction and begin executing the P-2 program. After each instruction of the P-2 program, a trace exception is generated by the 68000. Control
is returned to P-l, P-l analyzes what happened, then does an RTE. The whole
process repeats until P-l decides to stop.
Tradng allOVJS for the creation of programs which must be able to monitor
the results of individual instructions. Such programs include assembler debugging utilities, and programs to analyze hO\.V often each instruction gets executed.
When the other trace bit TO (bit 14 in the status register) is set to 1, a trace
exception occurs only when a change in program fiOOJ occurs, such as after a
BRA or JMP instruction.
In the MC68000, trace bit TO is not used, and is always zero; furthermore,
trace bit Tl is the only trace bit, and is called the T bit. The function of the trace
bits is thus upward compatible, that is, MC68000 programs using the trace
function will run correctly on the MC68020. The exception is: if some adven-

280

68000,68010, and 68020 Primer

Table 8-6

Trace Bits

TI

TO

Trace Function

No trace
Trace on Flow Change (Bcc, jMP,DBce)
Trace on each instruction
[Reserved by Motorola !

o
1

turoos programmer has been fiddling with the TO bit on the MC68000, then
such programs may fail to execute correctly on the MC68020.

COPROCESSOR SUPPORT
The MC68020 has 7 additional instructions which support communications
between the MC68020 and coprocessors. Coprocessors are processors that
satisfy certain hardware interface requirements established by Motorola. One of
the main requirements is that the coprocessor must have certain interface registers that are necessary for communications with the host processor.
A complete discussion of coprocessors \M)IJld include details of the functions
of each 68000 coprocessor instruction, a description of Motorola's hardware
interface reqUirements, and the spedfic functions of each available coprocessor.
In this section IJ.Ie will limit our discussion to an overview of the 68000 coprocessor instructions, and hovJ the 68000 actually communicates with the coprocessor hardware. The goal of this section is to clarify, from the 68000 programmer's
point of view at least, how instructions and data get from the 68000 to the
coprocessor. VJe will also consider what happens when a coprocessor is not yet
physically present in a computer system, and is being emulated in software until
some future installation date.
If the immediately following paragraphs are confUSing, you should review
the section on function codes in Chapter 7.
COPROCESSOR HARDWARE COMMUNtCATION

First, IJ.Ie look at what is happening on the hardware level. In order to properly
communicate with the MC68020 coprocessor instructions, a coprocessor is
required to have a standard set of 13 interface registers (control register, command register, condition register, etc. ) totaling 32 bytes in all. VJe will be using
one of these registers, the coprocessor command register, in succeeding exam-

The MC68020

281

pies. It is always located at address position 10 (decimal) within the 32 bytes.

When the 68000 chip actually communicates with a coprocessor, it either reads
from or writes to one or more of the coprocessor registers. In order to do this,
the 3 function code lines of the 68000 send out bits 111 , indicating a spedaJ
CPU space access; the 32 address lines of the 68000 send out 32 bits in the
following format:
xxxx

XXX){

xxxx 0010 ccex xxxx xxxr rrrr

and the 32 data lines of the 68000 may send out 32 bits of data.
When the function code is 111, the 32 bits on the address line are not
interpreted as a full 32-bit address (as with the other four function codes) , but

are broken dO\..VJ1 into smaller bit fields of information used to determine the
final location of the special CPU space 110. Thus, the 0010 bits above indicate
that this is a coprocessor communication (as opposed to some other kind of

CPU space transfer), eec is the coprocessor code (0 to 7) that indicates which
coprocessor is being accessed, and mrr is the coprocessor register address (0
to 31 decimal) . The bit fields represented by x are not currently used.
The coprocessor codes are currently allocated as follows:

000

001
010-101
110-111

MC68851 paged memory management unit

MC68881 floating point coprocessor
(Reserved for Motorola!
(Reserved for users!

As part of the coprocessor interface, it is necessary for either the coprocessor

or some intermediary hardware to detect when the above signals have been
sent oot from the 68000, to recognize them as coprocessor communications,
and to respond accordingly.
If the 68000 is trying to write to the coprocessor, then the proper response
for the coprocessor is to take the data being sent to it (via the 32 data lines from
the 68(00), and store it in coprocessor ccc at register location mn. If the 68000
is trying to read from the coprocessor, then coprocessor ccc shoold send the
contents of register location mrr to the 68000 over the data lines.
That covers the hardware end of the coprocessor interface. Next we will
see how the programmer actually sends oot the function codes and address bits
which access the desired coprocessor:

COPROCESSOR SOFTWARE COMMUNtCATtON

I-hw does the average programmer communicate with the coprocessor? In

general, you will use an assembler that supports your coprocessor: Yoo will

282

68000, 680/0, and 68020 Primer

include various coprocessor instructions in your programs to communicate with

the coprocessor, as explained in the documentation for ~r coprocessor. And
finally, the assembler will create object code with the correct parameters for that
coprocessor. Note that the same kind of communication with different coprocessors will result in different object code, due to different coprocessor 10 codes,
and different coprocessor command languages.
For example, suppose that a hypothetical coprocessor exists, called the
MC99999, which monitors pov.oer consumption by polling hundreds of meters.
The MC68020 communicates once to the MC99999 to get it started. and the
coprocessor then spends several seconds or minutes doing the actual polling,
thus relieving the 68000 of this burdensome task. The MC99999 leaves the
numerical results of the polling in memory, and infonns the MC68020 when it
is done.
One of the MC68020 coprocessor instructions, the cpGEN instruction,
sends a GENeral 16-bit command to the command register of a coprocessor.
Suppose that the MC99999 has a coprocessor code of 2, that the receipt of a
single 16-bit POLL instruction in its command register causes the MC99999 to
begin its poll cycle, and that, in MC999991anguage, a POLL Instruction is hex
$1234. A hypothetical assembler which supports the MC99999 IOOUld accept
this instruction:
cpCEN

MF.:J'ER , POLL

Our hypothetical assembler IOOUld associate the symbol "METER" with

the MC99999's coprocessor code (namely, 2), and IOOUld assemble the POlL
command into its proper MC99999 bit pattern (hex $1234). A cpGEN instruction assembles into tv..o words that are generally represented as follows:

lCccOOOXxxxxx

I
where Ccc is the coprocessor code, Xxxxxx is an optional effective address (not
used by the MC99999), and the second \.\lOrd is the actual instruction sent to
the coprocessor. Thus, our particular cpGEN instruction assembles as:

000

o o

0
1

o
o

0
0

o
o

000

Now that we have looked at hovJ the coprocessor interface functions, both
in hardware and in software, let's look at what happens when one or more parts
of that interface are missing.

The MC68020

283

EMULATION OF THE MC68020 COPROCESSOR

INSTRUCTIONS

Is the MC68020 itself indispensable for coprocessor communications? No. It is

simply easier, faster, and uses fewer registers than the MC68010.
The MC99999 cpGEN instruction discussed in the previous section is
equivalent to the following MC68010 instructions:
MOVE . L
MOVEC

17 , 00
DO , OFC

MOVE . L

#$OOO24 00A, AO

MOVE . L
MOVES

#$12 34, 01

CPU space fun ct ion code

Move t o dest inat ion fun ct ion code
regi s ter
Set up bits for ccc=2, rrrrr=IO
(decimal )

01 , (AD )

Set up data to move

Move 01 to coprocessor 2 regis ter
10 (dec)

Note that the MC68020 accomplishes all this in only one instrUction , and

without using registers DO,DI ,AO.

Since all of the above instructions exist on the MC68010, the coprocessor

software instructions can be emulated on the MC6801O. Since the MOVES and
MOVEC instructions do not exist on the MC68000, however, the coprocessor

software instructions can not be emulated on the MC68(x)(). We will now discuss
the coprocessor capabilities available to the MC68000 and MC680IO.

COPROCESSORS ON THE MC68010

If an MC99999 is connected to an MC68010, it is necessary to emulate the
MC68020 software coprocessor instructions using MC68010 instructions.
A more elegant solution, however; VJOUld be as follows. Indude the coprocessor instructions (for example, cpGEN ) in the MC68010 program , even
though these instructions are not part of the MC68010 instruction set. Change
the MC68010 assembler so that it assembles the coprocessor instructions into
the same bit patterns as the MC68020 assembler, or use an MC68020 assembler. Finally, change the unimplemented 1111 instruction exception routine to
check for these bit patterns and emulate them in software.
Later on , if the computer is upgraded to an MC68020, the coprocessor
interface will function fully, without any changes in the software.

COPROCESSORS ON THE MC68000

Unfortunately, the MC68(X)() is not capable of communicating with coprocessors
at all, because it lacks not only the MC68020 coprocessor instructions, but also

284

68000, 68010, and 68020 Primer

the MC68010 instructions, MOVEC and MOVES. The best the MC68000 can
do is emulate the MC99999 hardware in software.
Software emulation of coprocessor hardware is not always possible. For a
coprocessor with spedalized hardware functions like the MC99999, emulation
may be impossible. For some coprocessors, emulation can be accomplished
using another piece of hardware. And for some coprocessors, such as the
MC68881 floating point coprocessor, software emulation is completely possible.
Indeed, there are probably many 68000 systems right now that are running
MC68881 software emulations.
The advantages of emulating hardware features in software are manifold.
First, it allows the MC99999 manufacturer to model the chip's behavior in
software, before having to invest in actual hardware development. Second, it
allows the manufacturer to implement the MC99999 in software at customer
sites before the MC99999 is actually available. The emulation will probably be
several times slQV.IeT than the actual MC99999, but in the computer \OOrld, a
slOVJ routine is better than no routine at all.
Third, when the MC99999 or MC68881 is finally available, it only has to
be plugged in, along with an MC680 10 or MC68020, and the coprocessor
interface will function with no software changes necessary.

MISSING COPROCESSORS ON THE MC68020

If there is no actual MC99999 present, and the MC68020 attempts to communicate with it, the MC68020 will be notified of this fact after one bus cycle,
and will execute an unimplemented 1111 instruction exception. All this occurs
automatically.
The unimplemented 1111 instruction exception routine is free to either
report that the MC99999 is missing, or to emulate the MC99999 hardware in
software and then return. As discussed in the previous section, if the MC99999
is emulated in software, and the MC99999 is later plugged into the computer,
then no software changes are necessary.

NONSTANDARD COPROCESSOR HARDWARE

What happens in the situation where an MC68020 is connected to a coprocessor
having a nonstandard coprocessor interface? The MC68020 coprocessor instructions will not be able to communicate correctly with the coprocessor, and
hence cannot be used. They must be replaced by routines which explidtly use
MOVEC, MOVES, and MOVE to communicate to the proper addresses within
the coprocessor:. These routines will be similar, but not identical to the MC68010
routines which emulate the MC68020 coprocessor instructions.

The MC68020

Table 8-7

285

Summary of Coprocessor Commands

Mnemonic

Description of Operation

cpGEN
cpScc
cpOScc

Sends a general instruction to the coprocessor

like Sec, but uses coprocessor condition codes
like DBce, but uses coprocessor condition codes

cpTRAPcc

Like TRAPcc, but uses coprocessor condition codes

cpSce

cpSAVE

like Bee, but uses coprocessor condi tion codes

Saves slalus of coprocessor [privileged]

cpRE5TORE

Restore status of coprocessor [privileged]

SUMMARY OF MC68020 COPROCESSOR COMMANDS

The seven coprocessor instructions on the MC68020 aU have the following bit
patterns for the primary instruction I.OOrd:

1111Cc c lnsX xxxxx

where ecc is the 3-bit coprocessor code, Ins indicates the instruction, and
Xxxxxx is dependent upon the instruction. Note that the first foor bits of each
instruction are 1111 . As with other 68000 instructions, some of the coprocessor
instructions are follQl..Ved by additional v.ords which are displacements, data, or
condition codes.

THE MASTER BIT

The Master (M) bit is used to support environments where multiple operating
systems (privileged jobs) are running concurrently. The M bit distinguishes the
master operating system from all the others. It should be noted that, except for
deep operating systems programming, the average 68000 programmer will
probably never have to be concerned with the M hit.

USER AND SUPERVISOR MODES

The M hit is an extension of the S bit, and the S bit is the basic mechanism
used by the 68000 to control privileged operations. In order to clarify the function

286

68000,68010, and 68020 Primer

of the S bit and M bit, VJe first explain the primary motivation for having both
of them.
Certain processor functions are considered so important that they are
accessible only to privileged users, or privileged programs (for example, an
operating system). In the 68000, these functions include

An irrevocable abort of all current processing (RESET,STOP)

Errors of all kinds (bus error, address error, instruction error, zero divisor,
coprocessor error)

User traps
External hardware interrupts

The 68000 simplifies the concept of privilege to the simplest possible

mechanism, namely, at any given time the 68000 is either in a privileged
(supervisor) mode, or in an unprivileged (user) mode. Whenever any of the
conditions listed above occurs, control is yanked away from the current program
(whether supervisor or user) , the privileged (Supervisor) mode is entered, and
one of several special routine decides what to do about what just happened. In
some of these routines, the decision of hCMJ to proceed will critically depend on
whether the original program was in the supervisor or user mode.
Once the privilege mechanism has been set up in this way, t\.vo more
privileged functions suddenly surface, namely:

Changing bet\.veen supervisor and user mode

Querying the current mode (MC680lO)

Requesting the supervisor mode is a privileged function, and requires a

privileged routine to decide whether or not to grant it. Even querying the current
mode ("Am I nCMJ in supervisor mode?" ) is a privileged function. This privilege
is necessary in order to allCMJ for situations where the main operating system
emulates another operating system. The emulated operating system actually
runs in user mode, but thinks it is in supervisor mode. It must be kept in user
mode so that the main operating system can intercept any queries that the
emulated system may make regarding his mode and set up a counterfeit response to keep him fooled.
There are only tvJo privilege levels inherent in the 68000 privilege system,
but more can be artificially implemented in software. Simply keep everyone at
user mode (that is, with no actual privileges) , and assign each one a privilege
level (for example, 0 to 255). Anytime someone executes a privileged function,
control will be taken away and the controlling routine will check the assigned
privilege level and will emulate what should actually be allowed.

Th e MC68020

287

IMPLEMENTATION O F USER, SUPERVISO R, AND

MASTER MO DES
In the MC68000, bit 13 in the status register is called the S bit, or supervisor
bit. It is used to indicate whether the processor is currently in user mode (5 bit
0) or supervisor mode (5 bit 1). Certain instructions are considered privileged,
and are only allCMled when the processor is in supervisor mode. These instructions are: instructions that change the S bit. instructions that read the S bit
(MC6801O), and the MOllE USp, MOIIEC, MOVES, RESET, STop, and RTE
instructions.
If a privileged operation is attempted in user mode, a privilege violation

exception is generated. All other exceptions occur in the same way, whether they
occurred while in user mode or supervisor mode.
There are two stacks, each having their own stack pointer. The User Stack
Pointer (US?) is in effect during user mode, and the Supervisor Stack Pointer
(SSP) is in effect during supervisor mode. The stack pointer currently in use is

always referenced by A7, whether it is US? or SSP. When any exception occurs,
a block of information (called a stack frame) is pushed onto the supervisor
stack, the supervisor mode is set, and the exception routine is entered . When
the routine is done, the stack frame is cleared from the supervisor stack, and
control usually returns to the place where the exception occurred (unless it is
irrecoverable) .
In the MC68020, a second bit is assigned for use, in conjunction with the
S bit. It is bit 12 in the status register, and is called the M bit, or master bit. In
user mode (S = 0), things run just like on the MC68O(X). In supervisor mode
(S = 1), however, t\.VO possible submodes are possible. When the master bit is
clear (M = O) , the interrupt mode is in effect, and A7 references the Interrupt
Stack Pointer (lSP) , which points to the interrupt stack. When the master bit is
set (M = 1), the master mode is in effect, and A7 references the Master Stack
Pointer (MSP) , which points to the master stack. The stack pointer currently in
use is always referenced by A7, whether it is USp, IS?, or MSP.
When the M bit is cleared to 0, a ll of the mode and stack changes happen
just like on the MC68000, with the understanding that the supervisor stack
being used is always the interrupt stack. When M is set to I, h~, the
treatment of exceptions changes in t\.VO ways. First, exceptions now create stack
frames on the master stack, instead of the interrupt stack. Second, during an
external hardware interrupt exception , the usual stack frame is created on the
master stack, but then the same stack frame is also created on the interrupt
stack, and the master bit is cleared, causing a change to the interrupt mode.
Thus, a user who is nonnally in master mode operates off of the master
stack, but during the processing of external hardware interrupt exceptions, the
user operates off of the interrupt stack, just as with other jobs.

288

68000, 68010, and 68020 Primer

Each exception processing usually ends with an RTE instruction, which

returns to the previous mode and stack. In the case of the double stack frame
situation described above, HTE clears both stack hames, and returns through
both modes.

NEW INSTRUCTIONS ON THE MC68020

Several categories of changes VJere made to the MC68020 instruction set. Many
old instructions VJere extended in their operations, and many new instructions
were added. The final section in this chapter covers all instructions that are either
new or extended on the MC68020.
BRANCH INSTRUCTIONS SUPPORT 32-BIT
DISPLACEMENTS

The Bec, BRA, and BSH instructions nCMI support 32-bit displacements. The
original single-lJJOrd instruction fonnats contain an 8-bit op code and an 8-bit
displacement. If the 8-bit displacement is zero, then the follQ\.lling IJJOrd is used
as a 16-bit displacement
In the MC68020, if the S-bit displacement is 255 (dedmal), then the
foU()I...Ving tv..o IJJOrds are used as a 32-bit displacement. The assembly programmer generally does not need to knCMI these particulars. The assembler automatically decides the best fonnat to use.
LINK INSTRUCTION SUPPORTS 32-BIT
DISPLACEMENTS

The LINK instruction originally allOVJed only a 16-bit displacement, but nCMI
supports both 16-bit and 32-bit displacements.
EXTEND BYTE TO LONGWORD

The EXTB. L instruction sign extends a byte to a lonQVJOrd in a data register.

The original MC68000 instructions are EXT.W, which Sign-extends a byte to a
IJJOrd, and EXT.L, which Sign-extends a IJJOrd to a 10nQVJOrd. On older 68000
processors, it is necessary to do both an EXT. Wand EXT. L in order to get the
equivalent of one EXTB.L instruction.

The MC68020

289

CHK SUPPORTS LONGWORD UPPER BOUNDS

The MC68000 CHK instruction checks a data register against a INOrd upper
bound. The MC68020 CHK instruction checks a data register against either a
VJOrd or Ion9'-VOl'd upper bound. There is no apparent change in the instruction
syntax, but the assembler will allOVJ bounds greater than 16 bits, and will
automatically decide which format is best to assemble.

CHK2 (NEW INSTRUCTION)

This is a further generalization of the CHK insbuction. A new CHK2 (check

two bounds) instruction allows either a data or address register to be checked
against a lower and upper bound , both of which are byte, word, or longword .
All combinations of the above are allowed. The syntax is CHK2 < cea > ,Rn
where ea is the location of the lower bound, and the upper oound must imme-

diately follow the lower bound in memory, eITher 1, 2, or 4 bytes away,

depending on the operand length.
CMP2 (N EW INSTRUCTION )

A new CMP2 (compere two bounds) instruction operates just uke the CHK2
instruction, except that , instead of a trap occurring on an out-ot-bounds condition, the condition codes are set, leaving the user to subsequently branch as
desired . The syntax is CMP2 <cea> ,Rn and the condition codes are set as
follows:
N
Z
V
C

Undefined
Set if Rn is equal to either bound, cleared otherwise
Undefined
Set if Rn is out of bounds, cleared otherwise

X Not affected
CAS AND CAS2 (NEW INSTRUCTIONS)
CAS and CAS2 are compare and swap instructions, and both guard against
multiuser accesses to the same areas. They can be viewed as extensions of the
original MC68000 TAS instruction. In a multiuser environment the simplest
method of guarding against the problem of simultaneous updates to the same
data is to set up a flag somewhere that (by mutual agreement) can only be set
(or "CAAlned") by one user at a time. The TAS instruction allows the user to test

290

68000, 68010, and 68020 Primer

if a flag is set and if it isn't, sets it Most important, TAS guarantees that no one
else will have access to this flag during the entire read-modify-write process.
Thus, TAS satisfies the minimum requirements for Implementing multiuser
safeguards. The user is then free to execute the update routine, because he or
she kno..vs that no one else will gain access until he or she clears the flag. The
other jobs must cooperate by not executing the update routine until they have
possession of this flag. In addition the lucky possessor of the flag should cooperate by keeping the flag set for as short a time as possible. If this is done, then
whenever a program fails to get ownership of the flag via a TAS, it can safely
loop forever until it finally gets the flag, because the understanding is that this
will not take very long.
Even in a single-user environment, TAS is needed because there are still
multiusers in the fonn of external interrupts, all of which can occur at any time
and at varying frequencies. The ability to temporarily lock out certain resources
becomes critical in order to process these requests.
CAS goes one step further than TAS , and CAS2 goes tvJo steps further.
They have the following instruction fonnats:
CAS
CAS2

DC , Ou , ea
Ocl : 0c2 , Dul : Du2 . (Rnl ): (Rn2)

CAS compares Dc and ea; if they are the same, then Du replaces ea. In
the Simplest application, ea is a counter that is subject to be incremented by
more than one user. The procedure is to read ea into Dc (the old or compare
value), create the new value in Du (the new or update value), then execute the
CAS instruction . If it fails , simply try again. Caution: If the Dc counter undergoes
constant and rapid updating, then it is probably safer to use TAS; otherwise,
several users may get hopelessly locked up rehying their updales.
CAS2 is similiar to CAS, except that it does tvJo comparisons. If either
compare fails, the update is not made. Note that whereas CAS allows any

alterable memory-effectiw address mode, CAS2 only allows (address or data)

register indirect modes. The caution above regarding the use of CAS also applies
here.
DI Y AND MUL SUPPO RT NEW FORMATS

Sel.eral additional multiply and divide formats haw been added to the MC68020.
All fannats use one or tvJo data registers and one data-effective address as
source operands, and leave the results in one or more data registers. FollOVJing
are all of the fannats available on the MC68020, including the previous fonnats.

The MC68020
Table 66

DIVU.w
DIVU.L
DIVU.L
DIVULL
DIVS.W
DIVS. L
DIVS.l
DIVSL.L
MULU.W
MULU.L
MULU.L
MUlS .W
MULS.L

MUlS.l

Divide and Multiply Formats

Processor

Operation of Instruction

/nsuuclion
dea,Dn
dea,Dq
dea ,Or:Dq
dea ,Dr:Dq
dea,Dn

dea,Dq
dea ,Dr:Dq

dea ,Or:Oq
dea,On
dea,D I
dea ,Dh,DI
dea,Dn

dea ,DI
dea ,Dh:DI

291

Dn(32)
Dq(32)
D"Dq(64)
Dq(32)
On(32)
Dq(3 2)
D"Dq(64)
Dq(32)
de.(16)
de.(32)
dea(32)
dea(16)
dea(32)
dea(32)

dea(16)
dea(32)
dea(32)
dea(3 2)
I dea(16)
I dea(32)
I dea(32)
I dea(32)
x On(16)

x DI(32)
x D1(32)

x On(16)

x DIIJ2)

x 01 (32)

I
I
I
I

~
~

DnI 16,,16q)
Dq(3 2)
D'(32) , Dq(32)
D,(32) , Dq(3 2)

= On(16r:16q)
~

~
~
~

DqIJ2)
D'(3 2) , Dq(32)
D' (32) , Dq(32)
Dn(32)
D1 (32 )
Dh,DI(64)
Dn(32)
D1(32)
Dh ,DI(64)

68000

68020
68020
68020
68000

68020
68020
68020
68000
68020
68020
68000
68020
68020

The various subscripts used with the data registers are n for any register, r for a
remainder, q for a quotient, h for a high order lonQ\-VOrd, and 1for a low order
longword. The numbers 16, 32, and 64 indicate word, loogword, and quadword
respectively.

PACK AND UNPK (NEW INSTRUCTIONS)

PACK simplifies the conl.<!!'Sion of ASCII and EBCDIC numbers 10 BCD, and
UNPK Simplifies the conl.<!!'Sion from BCD back to ASC II and EBCDIC. In a
likely situation, a sequence of ASCII or EBCDIC digits is obtained from an input
device (for example, a tenninal, tape, or disk file); they are converted to internal
BCD format USing the PACK instruction; and BCD computations are done on
them using the ABCD, SBCD, and NBCD instructions. Afterwards, they are

converted back to ASCII or EBCDIC using the UNPK instructiOl1; finally, they
are sent to an output device. The formats available are:

PACK -(Ax) ,-(AY),#adjustment

PACK DX,Dy, #adjustment
UNPK -(Ax),-(Ayl, #adjustment
UNPK Dx,Dy,#adjustment

292

68000, 68010, and 68020 Primer

PACK takes a word from the source operand, adds the adjustment word to

it, then writes the second and f"'nth hex digits (bits (11:81 and 13:011 of the
result to the destination byte. For ASCII conversions, the adjustment is -3030
(hex) = CFDO (hex). For EBCDIC conversions, the adjustment is -FOFO (hex)
= OFIO (hex). A string of digits of any length can be converted using a twoinstruction loop consisting of a pre-decrement PACK command and a oSec
command. Thus, a string of digits of any length can be converted as follows:
MOVE. L
MOVEA. L
MOVEA . L
LOOP

I<size-l>, DO
t<packend> , AO
N<Unpackend> , Al

PACK

- (AD), - (AI ), #$CFDO

DBF

DO , LOOP

sel up digil tounl

ending of packed digits
ending of unpatked
digits
convert from ASCII
slop when count is - 1

UNPK takes a byte from the source operand, creates a word from it whose
second and fourth hex digits are the two hex digits from the source byte and
whose first and third hex digits are zero, adds the adjustment to it, then writes
the word to the destination address. For ASCII conversions, the adjustment is

+3030 (hex). For EBCDIC conversions, the adjustment is + FOFO (hex).

TST AND CMPI SUPPORT ALL ADDRESStNG MODES

On the MC68000, TST (TeST) and CMPI (CoMPare Immediate) only allow
alterable data effective addresses (adea). On the MC68020, TST.B and CMPI.B
remain restricted to adea, but TSTW, CMPI.W, TST.L, and CMPI.L may
operate on any effective address. The net effect of this change is to include the
PC addreSSing modes, and the address register direct mode.

TRAPcc (NEW tNSTRUCTION)

TRAPcc is a new instruction on the MC68020 which generates a trap if a given
condition code is true. All 16 conditions are allO'vlled, including the "always

trap" (TRAPT) and "never trap" (TRAPF) cases. Optionally, a word or longword
may follow the TRAPcc instruction; it is not used by the processor, but is available
to the user's trap routine. Forms available are as follows:

TRAPcc
TRAPcc. W
TRAPcc . L

'dI6
Id32

The MC6B020

Table 8-9

293

Summary of Bit Field Instruct ions

Mnemonic

Operands

Description of Operation

BFElITS

ea {offset:widlh} ,On

BFEXTU

ea {offset:width } ,On

BFFFO

ea {offset:width} ,On

BFINS
BFCLR

ON,ea{ offsel:width}

Extract signed bit field (extend)

Extract unsigned bit field (zero filll
Find first one bit in bit field
Insert (low order) bits into fteld

ea{offset:width}

Test BF, set (CRt then clear all bits

BFSET

eat offset:width}

BFCHG
BFTST

ea {offsetwidth}
eat offsetwidth}

Test SF, set (CR, then set all bits to

ones
Test bit field, then complement
Test bit field

to zeros

COPROCESSOR INSTRUCTIONS (NEW)

See the section on coprocessors, elsewhere in this chapter.

MOVEC SU PPORTS NEW CONTROL REGISTERS
MOVEC nOVJ reads and writes to the cache registers CMR and CACR. See
Chapter 7 for details on the MOVEC instruction .

BIT FIELD INST RUCT IONS (NEW)

There are eight bit-manipulation instructions on the MC68020. In each, the
main operand is a bit field of 1 to 32 bits. This bit field is referenced off of either
a data register or a byte in memory. either of whose leftmost (highest order) bits
is considered bit number zero. The actual bit field is designated by a bit offset
from bit number zero, and the bit width (I to 32). If a second operand is present,
it is a data register.

In Table 8-9:

ea is an effective address.
Offset is the bit offset. either an immediate value of 0 to 31 or a data

register value from -2,147,483,647 to +2, 147,483,648.

Width is the bit field width, either an immediate value of 0 to 3 1, or a

data register value from 0 to 3 1 (taken modulo 32). Zero represents a
value of 32.

On is a data register.

294

68000, 680/0, and 68010 Primer

BelQI,A,I are examples of bit field instructions:

BFEXTUDO {8: 151. Dl
BrCLR
(AO) {2: 5)
BrrFO

(AOI{ DO :32J. Dl

move 2nd byte of DO t o 01

clear middle 4 bits of memory
byte (AO )
find first 1 bit start i ng at
DO - th bit of lIIemory byte (AO );
search 32 bi ts .

CONCLUSION

Whereas the MC680l0 concentrated on one critical function (emulation) , the

MC68020 introduced a variety of new features. Compared to the MC6801O,
the MC68020 has 256 times as m uch address range, faster execution due to
the on-board cache, and faster communication with co-processors. S ix additional addressing modes, enhanced instructions, and new instructions save
programming time, program room, and execution time. Branch instructions
VJere revised to allOVJ for full 32-bit branches. Multiply and divide nOVJ fu lly
support 64-bit products and dividends. Finally, the new bit field operations
significantly increase the speed and pov..!eI" of instructions that change individual
bits; this aids in the updating of disk directory bitmaps, and is critically important
in the handling of real-time graphics displays.

A
M68000 InstructionsNumber of Operands
No Operand:

NOP
ILLEGAL
RESET'
RTE' /RTRIRTS

TRAPII
Single Operand:

ASUASR &cJBRNBSR

CLR
EXT
JMP/JSR

NBCD
NEGINEGX
NOT
PEA

RTD
Sec
STOP'
SWAP

TAS
TRAP
TST

UNLK
295

296

68000, 68010, and 68020 Primer

Two Operands:

ABCD
ADD/ADDNADDUADDQ/ADDX
AND/ANDUANDI-CCRIANDI-SR*
ASUASR BCHGIBCLRlBSETIBTST
CHK
CMP/CMPAlCMPUCMPM

DBce
DIVSIDIVU
EORIEORUEORI-CCRlEORI-SR*
EXG

LEA
LINK
LSULSRMOVEIMOVE-from-CCRIMOVE-to-CCRIMOVE-to-SR'IMOVE-from-SR"
MOVE-USP'IMOVEAlMOVEC" /MOVEMIMOVEPIMOVEQIMOVES'*
MULSIMULU
ORIORUORI-CCRIORI-SR*
ROURORIROXUROXRSBCD
SUBISUBAISUBUSUBQ/SUBX
legend: - ,., can have one or two operands
= privileged MC68000
.. = privileged MC680 10

B
M68000 Addressing Mode

Types

< ea >
< rea >
< dea >
< mea>
< cea>
< aea >
< adea >

~
~

Any Effective Address

Register Effective Address
Data Effective Address

=
= Memory Effective Address
~
~

< amea >

< acea>

Control Effective Address

Alterable Effective Address (data or memory)
Alterable Data Effective Address
Alterable Memory Effective Address
Alterabte Control Effective Address

Mode

eo rea dea mea ceo aea adea amea acea

Dn
An
(An)
(An) +
-(An)
diAn)
d(An,Xi)
Abs.w
Abs.L
d(PC)
d(PC,Xi)

297

298

68000,68010, and 68020 Primer

Mode

eo reo dea

mea ceo aea adea amea acea

Immed
bd(An,Xj)
bd (PC,Xi)
[bd,An),Xi,od
[bd,An,Xi) ,od
[bd, PC),Xi,od
)bd, PC,Xi) ,od

68020
68020
68020
68020
68020
68020

Addressing Mode Description

Common to All M68000 Family:

Dn
An

Data register direct

} .
. t d' t Jomtly ca lled
Tess
regiS
er
lree
Add

..

(An)
(An) +
-(An)

Address register indirect

Address register indirect with postincrement
Address register indirect with predecrement

d16(An)

Address register indirect with offset-also written as d(An) or

d8(An,XLZ)

Address register indirect with offset and index-also written as

register direct

< label> (An)

d(An,Xi) or < label >(An ,Xi)
AbsW
Abs.L

Absolute short address-also written as xxx. W or < label >

Absolute long address-also written as xxx. L or < label >

d16(PC)

Program counter with offset (relative mode)- also written as

d(PC) or < label > (pC) or < label >
Program counter with offset and index (relative mode)-also
written as d(PC,Xi) or < label>(PC,Xi) or < label>(Xi)

d8(PC,XLZ)
Immed

Immediate data operand-also written as # < data>

MC68020 Variations and Additions:

bd(An,Xi.Z s)

Address register indirect with base displacement and

index [similar to d(An,Xi) but bd can be d16 or d32)

bd (PC,Xi.Zs)

Program counter with base displacement and index

[similar to d(PC,Xi) but bd can be d16 or d32)

[bd,An) ,Xi.Zs,od

Memory indirect post-indexed

(bd,An,Xi.Zs ),od

Memory indirect preindexed

M68000 Addressing Mode Types

[bd,PC),Xi.Zs,od

PC memory indirect post-indexed

[bd,PC,Xi.Zsl,od

PC memory indirect pre-indexed

299

(NOTE Some books use "displacement" in place of "offset")

< label >

Is a user-supplied symbol indicating the location of an

instruction or data field. Some instructions treat
< label > as a d8 or dI6 relative offset; others,
depending on assembler directives available to the
programmer, are treated as Abs.L, Abs.W or d(PC)
modes.

AbbrelJiations:
On
An

Xi
z
Z
5

PC
d
bd
od

xxx

Arry data register, DO - 07

Any address register, AO - A7
A~ On or An used as an index register
Data size code (l, W or B)
Data size code (L or W)
Scale factor (1, 2, 4 or 8)
Program coonter (20, 24 or 32 bits)
A 2'5 complement or sign-extended offset, or displacement (d16, d8,
d3 etc indicates the number of bits)
A 2'5 complement base displacement (16 or 32 bits)
A 2'5 complement outer displacement [16 or 32 bits)
A~ valid absolute address

c
A468000Insuuc6on~Legal

A40des
(See Appendix B for register and
Mnemonic

mode definitions.)

Function

Legal Modes

Data Size(sJ
Of' Attribute

ABeD

Add Dedmal

Dm,Dnor

-(Am),-(An j

AOO

Add Binary

< ea>,Dn Of

l.,W,B

Dn,<amea>
AOOA
AIlDl

< ea>,An
lI < data>. < adea>
N< d3>,<aea >
Om,On or

AOOQ
AOOX

Add Address
Add Immediate
Add Quick
Add Extended

AND

AND LogkaJ

ANDI
ANDI->CCR
ANDI->SR-

AND Immediate
AND Immediate CCR
AND Immediate SR

ASUASR

Arithmetic Shift

Om,On or

ASUASR

Arithmetic Shift

# < d3>,Dn
< amea>

Bcr
Bcr.S

Branch Condition
Branch Cond. Short

BCHG

Bit Test/Change

L,W
L,W,8

L,IIJ.{B)
L,W.S

-(Am).-(An)

< dea>,Dn or
Dn,<amea>
# <data>,<adea>
# < d8>,CCR

# <dI6>.SR

<label.>
<label>
Dm,Dnor

L,W,S

L,W,B
B
W
L,W,B (Om mod 64)
W (shift coon! ;;: I)
16 bit dlsp.
8 bit disp.
L (Om mod 32)

# <d5>,00
BCHG

Om, <amea> or

# <d3>. < amea>

300

B (Om modS)

M68DDO Instruction s/Legal Modes

Mnemonic

Fundlon

Legal Modes

BCLR
BRA
BSET
BSR
BTST

Bit TesllClear
Branch Always
Bit TestlSet
Branch Subrootine
Bit Test

EORI Status Reg.

Exchange Registers
Extend sign

same as BCHG
< label>
same as BCHG
same as BRA
Om,Dnor
1I- <d5> .Dn
Om,< mea> or
1I- <d3>,<mea>
< dea >, Dn
<adea>
<ea> .Dn
<ea>,An
# <data>,<aciea >
(Am) + ,(An) +
Om,<label>
<dea>,Dn
On,<adea>
# <data>, <adea>
# <d8>,CCR
# <d16>,SR
Hm,An
On

1I1ega)

no opemnd

JumplJMP Subroutine

<cea>
<cea>,An
An,# <d16>
same as ASUASR
<ea>, <adea>
CCR, <adea>
<dea>.CCR
SR, <adea>
SR,<adea>
< dea>,SR
USp,An or An,USP
<ea>,An
Rc,Rn or Rn,Rc
< reg.1i51>.<acea> +
<cea > + ,<reg. list>
On,d(An) or
d(An),Dn
* < d8>,Dn
Rn,DFC<amea> or
SFC<amea>, Rn
<dea>. Dn
<adea>
<adea>

W
B
LWB

noopemnd

unslzed

BTST
CHK
CLR
CMP
CMPA

CMPI
CMPM

DB<,
DIVSIDIVU
EOR
EORI
EORI->CCR

EORI->SRt
EXG
EXT
ILLEGAL
JMP/JSR
LEA
LINK

LSULSR
MOVE
MOVE<-CCR

MOJE->CCR
MOVE<-SR

MCWE<-SR" t
MOVE->SR
MCWEUSPt

Check""" Bounds
Clear Opemnd

Compare
Compare Address
Compare Immediate
Compare Memory
Dec. Branch Cond.
Divide SignlUnsign.

Exclusive OR
Exclusive OR Immed.
EORI CondoCodes

LoodE_Add

UnklAllocate
Logical Shift
Mow <!ala
Mow !rom CCR
MooJe to CCR
Mow !rom SR
~toSR

MOVEM

Mow USP
Mow Add..,.
Mow C",trl. """
Molle Multi Reg.

MOVEP

Moo..,.e Periph. Data

MOVEQ

Mow Qukk
MooJe Address Space

MOVEA

MCWEC t

MOJES"
MULSIMULU
NBCD
NEG/NEGX

NOP

Multiply SlgnlUnsign
Negate Decimal
Negate!Nega'e Ext.
No operation

301

Data Size(5)
or Attribute

8 or 16 bit disp.
L 10m mod 32)
B 10m mod 8)
W

L,W,B
L,W,{B}
L,W

L,W,S
L,W,B
16 bit disp.
W
L,W,B

L,W.S
B
W
L
L,W

unsized
L

unsized
LW,{B}
W ,,,,,,,, B only)
W ,,,,,,,, B only)
W

W (t for 68010 only)

W (t all models)
L
L,W
L

L,W ( + plus -(An))

L,W(+ plus + (An))
L,W

L (sign ext 32)

L,W.S

302

68000, 68010, and 68020 Primer

Mnemonic

Function

Legal Modes

Data Sfz:e(s)
Of Attribute

NOT
OR
ORI
ORI->CCR
ORI->SR'
PEA
RESET'

RCXJROR
ROXUROXR
RTD ""
RTf'

RTE -- '

RTR
RTS
SBCD

logical Complement

<adea>

Indush.< OR l.ogi<aJ
Indus/\.e OR Immed.
ORI Cond. coo..
OR! Status Reg.

same as AND

Push Effective Addt

Reset External Dev.
Rotate leftIRIght
Rotate with Extend
Retum/Deatlocale
Retum from Exception
Return Restore CCR

&,

Return from Subl'lXlline

$ubtrncl Decimal
Set Conditionally

STOP'

Load SRlSlop

SUB
SUBA
SUBI
SUBQ
SUBX
SWAP
TAS

Subtract Binary

TRAP
TRAP\!

TST
UNLK

Subtract Address
Subtract Immediate
Subtract Quick
Subtract with Extend
Swap Regster Halves
Test and Set operand
Trnp
Trap on 0verfl0.N

L.W,B

same asANDI
same as ANOI->CCR
same as ANDI-> SR

<oea>
no """"nd
same as ASUASR
same as ASUASR
# < d I6>
no""""nd
no""""nd
no """"nd
no""""nd

unslzed (sign ex132)

unsized
unsized
unsized

unsized

same asABCD

< adea>
# < d16>
same as ADD
same as ADDA
same as ADO!

unslzed

same as AOOQ

same as AOOX
On

<adea>
# < d4>

W
B

Test operand

no """"nd
<adea>

unsized
unsized
L,W,B

Unlink

An

unsaed

{8} reminds you thai Byte data size not a1b,i..oed for An operands.
# < data> "" up to 32 bits of immediate data.
N< dn >

- n bits of Immediate data.

- M68000 privileged Instruction.

"" MC68010 privileged instruction.
- MC68010 on~

Rc

- control register (SFC. DFC,USP or VSR).

D
A468000lnsYucuon
Summary

This appendix is a reference for all of the instructions implemented thus far in
the 68000 processor family, that is, all of the instructions on the MC68000, the
MC68O!O, and the MC68020. Included are the instruction bit parterns, addressing mode bit patterns, and allOVJable addressing modes for each instruction.
This appendix does not describe the actual execution of these instructions; that
material constitutes the first 8 chapters of this primer. We will be looking at the
68000 instruction set in very general tenns, and will hopefully impart to you
some tips that will help you to memorize the complete instruction set.

68000 ADDRESSING MODES

The 68000 processor family uses a rich set of addressing modes. There are 12
basic addressing modes, and some additional implied addressing modes for

certain instructions. The MC68020 further enlarges the functions of two of the
basic addressing modes, giving it a total of 18 variations on the basic 12
addressi ng modes. See Chapter 8 for further details on these addressing mode
variations.
Table 0 1 contains information on these 18 addressing modes. The first
column contains the full name/description of each addressing mode. Note that
some of these descriptions are somewhat long.
The " CPU" column indicates which members of the 68000 family haw
this addressing mode available; a blank refers to all 68000 processors, a "20"
refers to the MC68020 only.
303

304

68000,68010, and 68020 Primer

The "Mod Reg" column contains the actual 6-bit codes for each address
mode. Actual binary register numbers are represented by " m ", which can be
"000" to " Ill".
The next four columns define four categories of addressing modes. These
categories are very helpful for summarizing the legal addressing modes of each
68000 instruction .

Register
(REA)

These addressing modes refer to registers. This includes address

register direct and data register direct.

Data
(DEA)

These addressing modes refer to data operands. This includes

all modes except address register direct. Many 68000 instructions that operate on data are prevented from altering the address registers. This is part of the 68000 philosophy that the
benefits obtained from preventing erroneous operations to the
address registers (which can waste lots of development time),
far out\.veigh the extra programming steps necessary to do legitimate operations to the address registers.

Memory

These addreSSing modes refer to memory operands. This includes all modes except the two register direct modes. Two
instructions are restricted to MEA because they are truly memory based operations, namely, TAS and MOVES. OR, AND,
ADD, and the 4 shift instructions also impose the MEA restriction
on some of their instruction fonnats , in order to avoid duplication
of functions. For example, ADD 00,01 is allOVJed in the fonnat
ADD " ,D! , but not allowed in the fonnat ADD DO, .. (to avoid
duplication). Thus, the fonnat ADD DO,ea only allows MEA as
destination, whereas the fonnat ADD ea,Dl allOVJs any EA as
source.

(MEA)

Control

(CEA)

Alterable

(AxEA)

These addressing modes refer to memory locations, without

specifying if they are byte, word, or longv..ord in size. This applies
to the destinations of jump commands (Jxx), and to indefinitesized destinations (LEA,PEA,MOVEM,BFxxxx).
These refer to operands which may be changed. This excludes
the PC relative and immediate modes. Motorola is inferring that
programs may not alter themselves. In actuality, 68000 programs can change themselves, but an extra instruction (usually

an LEA) must be used to do this. This is part of the 68000

philosophy that the benefits obtained from preventing erroneous
program self-changes (which can waste lots of development

time), far outweigh the extra programming steps necessary to

pre-irrlexed
Absolute short
Absolute long
Program crunler indirect
with displacement

~irdlR!d

post-indexed

~irdlR!d

~t

Data register direct

Address register direct
Address register Indirect
Address register indirect
with postinaement
AddJess _
im"'"
with predeoemenl
Address register indirect
with displace!r<nt
Address register indirect
with irdex and 8-bi!
displac"""t
Address register mired
with index and base

Address Mode Name

20

20

20

CPU

m
m
m

100
101
110
110

III

111
111

110
000
001
010

m
m
m
m

000
001
010
011

110

Reg

Mod

X
X

Resta'
(RI

Table D-l

X
X
X

X
X

X
X
X

X
X

Memo<y

(MI

Dow
(DI

X
X
X

(el

CoWoI

Effective Addressing Modes

X
X

X
X
X
X

A/reroble
(AI

addr .W
addr .L
(dI6,PC)

IIIxI,An,Rnj,od)

IIIxI,AnI,Rn,od)

(IxI,An,Rn)

(dB,An,Rn)

(d I6,An)

-IAn)

An
(An)
(An) +

On

Assembl>
Syntax

15

15

1-3

0
0
0
0

E>tenslon
"",ds

'"-=
'"

3
3

'g.c"

'"'"
:5

;:

306

68000, 68010, and 68020 Primer

hJ

- -"' -"' '"

'?

'""
Ii

"8.

:lI

:lI

'""
~ Ii

0;

La 'li

Ii
:lI

""

J~

j~
J'
~

--

- -- -=

--

],1],1

:1!

~- :. ;

~- .lI

li'"
"11 _ ~ 11

8 ..... 0

0 -...............
-

--__.....

........
--_ .........
<" ...........

--],1],1

~
._

H~
~H

~
.-

~ .~

L ___

U1HInnun

M68000 Ins/ru e/ion Summar y

307

do legitimate changes. If you plan to make many selfreferences

within a program, ~mply do a " LEA label I ,An" at the very
beginning, then do all self-references using "label2-labeilIAn}".
By ccmbining the abo..e categories, other categories can be created, namely,
the alterable data, alterable memory, and alterable control categories. For example, alterable data addresses are those addresses which are both alterable
addresses and data addresses.
The "Assembler Syntax" column contains a figurative representation of
the actual characters used to code each address mode in a 68000 program.
The actual assembler you use on a particular computer may have slightly
different syntax. The symbol An represents any register from AO to A7, On
represents DO throogh 07 , Rn represents An or On. dB represents any unsigned
number 0 to 255 or any signed number -128 to + 127, d16 represents unsigned
to 65536 or signed -32768 to +32767 , d32 represents unsigned 0 to
4294967295 or signed -2147483648 to + 2147483647. #n represents d8,
d 16, or d32 in byte, VJOrd, or longword instructions respectively.

ADDRESSING MODE ORTHOGONALITY AND

LEGALITY
An important design feature of the 68000 instruction set is the orthogonality
between its instructions and addressing modes. Comple te addressing orthogonality would mean that every instruction is able to use every addressing mode
in all of its operands (source, destination, counter, etc.), thereby promoting
convenience and flexibility in assembly programming. Few processors, ho\.vever,
have been designed with complete orthogonality because there are disadvan
tages. High orthogonality often comes at the expense of instruction set pov.rer;
typically, many unimportant instruction/addressing combinations occupy bit
patterns that could be better used by more pov..oerful instructions. The 68000
instruction set is a state of the art optimization, both highly orthogonal and very
powerful .
Each 68000 instruction consists of an operator a nd 0 or more operands.
For example, some instructions with various numbers of operands a re

RTN
BR

LABEL

OR.W
CAS2.W

DO,4 IAO}
DO:DI ,D2:D3,4 IAO}

ooperands
1 operand
2 operands
5 operands

308

68000, 68010, and 68020 Primer

In most instructions, each operand is either allOVJed to be only one of the

12 addressing modes, or is allOVJed to be any of the 12 addressing modes which
is "legal". An im)X>rtant goal for all 68000 programmers is to fully understand
Motorola's criteria for "legal" addressing modes. These criteria are consistently
applied throughout the 68000 instruction set Without an understanding of these
criteria, the 68000 instruction set will appear to lack much of its actual orthogonality. Armed with such understanding, complete memorization of the 68000
instruction set is possible.
An example should clarify all of this. The OR instruction given above is
one of a group of OR instructions, all having the general fono
OR. size

On .<destinati on>

and the 16-bit patterns represented by

1000SdrlSzDestin
Explanations of the abbreviations Sdr, Sz, and Destin are nol necessary
for this discussion, but may be found beiOVJ. There are tVJO operands in this
instruction. The second operand must always be data register direct mode, but
the first may be any "legal" addressing mode. In this group of OR instructions,
fully 5 of the 12 addressing modes are illegal. Furthermore, the 5 illegal modes
violate three general rules of legality. The illegal modes, with their associated
rule violations are:
1. PC relative or immediate: These may never be altered.
2. An: Data operations are not usually allOVJed to An.
3. On: This duplicates the function of another group of instructions.

Rule 1 is rigorously true for all 68000 instructions which alter the destination
operand. Rule 2 is mostly true, but a few necessary operations are allOVJed to
An, namely, MOllE, ADD, SUB, ADDQ, and SUBQ. Some assemblers allow
you to use these "loophole" instructions without complaint. Some, hCMlevef,
require you to substitute MOJEA, ADDA, and SUBA for MOVE, ADD, and
SUB when the destination is an address register. The net result is the same, but
inadvertent program errors are reduced. To understand Rule 3, we need to
knOlN that there is a second group of OR instructions, all having the fono :
OR. size

<source>. Dn

M6BOOO Ins/ru c/ion Summary

309

and the 16-bit patterns represented by

IOOODdrOSzSource
If both of these OR groups allowed for the case

OR. size Dnl,Dn2

then there would be more orthogonality in the instruction set, but less povJer,
because fewer bit patterns would be available for other instructions. Indeed,
some of the bit patterns made available by Rule 3 , above, are used to code the
NBCD instruction. As a programmer, yoJ need not \..VOrry about Rule 3 , because
any 68000 assembler will automatically assemble an OR.size Dnl ,Dn2 instruction as the correct bit pattern. If you are coding an assembler (or dis-assembler) ,
however, Rule 3 is of critical importance.
The above example will hopefully make more palatable the follOVJing rigorous list of rules (and their exceptions) governing 68000 illegal addressing
modes:
L PC relative modes or immediate mode are illegal destinations if altered. This
is the reason for the "alterable" address modes category (AEA) . Note that
" test" instructions do not alter their destinations, even though they "simu-

late" a subtraction from the destination. Exceptions: TST and CMPI with
these address modes are illegal, even though they do not alter their destinations. On the MC68020, TST.W, TST.L, CMPIW, and CMPI.L are legal

in all modes, but TSTB and CMPI.B are not

2 . Duplicate functions are handled by only one of the instructions. For example,
in all shift instructions, "op #1 ,On" is legal while "op On" isn't. Exceptions:
CM? #c,Dn and CM?! #c,Dn are equivalent in function, but are assembled
as different instructions (both with 2 \..VOrds). The same is true for the corre-

sponding cases involving ADD/ADDI, SUB/SUBI, AND/ANDI, and ORIORI.

Note: if I < = c < = 8, then ADDQ #c,Dn and SUBQ #c,Dn are also
possible, and are a third equivalent to the ADD/ADDI and SUB/SUBI cases
considered above, but take one less I.VOrd. Hence, ADDQ and SUBQ are
not considered to be duplicated (or triplicated) functions.
3. Many data operations are not allowed with An (address registers). This is
the reason for the "data" address categories. The {ollOVJing sub-rules cover
all cases, and are in cumulative order, that is, later rules override earlier rules
in the sequence.

310

68000, 68010, and 68020 Primer

a. An never partidpates in arr:t byte operations.

b. An does not interact with special data registers. Exception: the MOJES
ccmmand may move arry special register to or from any data or address
register.
c. An may partidpate in straight moves. Thus, EXG, and MCNE are OK.
MOJE.B is excluded by Rule 3a. Note that An may be moved fromIto
spedal address registers (USP, for example) but not fromIto spedal data
registers (CCR,SR), by Rule 3b.
d An may be tested (not permanently changed). Thus, CMP (except CMPBI,
CMPA, and TST (except TST.B) are OK.
e. An is al1()1..1Jed a few addition and subtraction calculations, namely ADD
Anl ,Dn2 and SUB Anl,Dn2 (except byte size); ADDA, SUBA, ADDQ,
SUBQ (except byte size). The following are not all""",d: ADD Dnl ,An2
and SUB Dnl,An2. Note that ADD! #c,An and SUBI #c,An are excluded
by Rule 2.

4. LEA, PEA, MOIIEM, Jxx, and BFxxxx use only control address operands.
Exceptions: MOJEM also allows (An) + as source and -(An) as destination;
BFxxxx also alkY..vs Dn as a bit field operand.
S. Completely pointless calculations are illegal. Exception: 8TST #a,#b should
be replaced by AND! or OR! to CCR.

THE 68000 INSTRUCTION SUMMARY TABLE

- PRELIMINARIES
Table 0 -2 summarizes the instruction sets of all five CPU processors in the
68000 family, namely, the MC68008, MC68000, MC6801O, MC68012, and
MC68020. The MC68008 and MC68000 instruction sets are identical, as are
the MC68010 and MC68012 instruction sets. Hence, in the table, we only need
to distinguish MC68000, MC680IO, and MC68020 instructions. In addition,
shict upward compatibility has been designed into the 68000 CPU family. That
is, any instruction that is legal on any CPU in the 68000 family is also a legal
instruction on all later CPUs. Thus, MC68000 instructions execute the same
on aU five processors, MC68010 instructions execute the same on the MC68010,
MC68012, and the MC68020, and MC68020 instructions execute only on the
MC68020.
By deSign, Table D-2 is compac~ uses lots of abbreviations, and does not
include exhaustive details of how each instruction functions. For details and
examples of each instruction, see Chapter 4. The following sections explain the
symbols used in each column of Table 0-2.

M68000 In struction Summary

311

INSTRUCTION COLUMN
The first column in Table D-2 gives the standard Motorola mnemonic for each
instruction. Other assemblers may use minor variants of these mnemonics. The
following abbreviations are used:

Code

Rep~n~

.s

.B, .W, .L for byte, word, and lonQ\UOrd instructions, respectively

.W and .L for v..ord and longv.ord instructions, respectively
[blank I. .W, and .L for none, """d, and lon9"Ord operands

.s2

.s3

(TRAPcc and cpTRAPcc only)

cc

A condition code [CC,CS,EQ,G E,GT, HI , LE , LS , LT,MI ,

NE,PL,VC,VS)

CPU COLUMN
This column indicates whether an instruction is a MC68000 instruction (blank),

MC68010 instruction (" 10"), or MC680Z0 instruction ("ZO" ). See the notes
above about upward compatibility in the 68()(x) family.

SYNTAX COLU MN
This column gives the general syntax of the instruction as it appears in actual
programs. In cases where a source and destination operand appear, the source
operand is first Thus, if ever in doubt, remember that 68000 instructions "ADD

first operand to second operand", "SUBtract first from second", " MULtiply first
into second", "DIVide first into second".
For a fe\.V instructions, tvJo syntaxes are given. In these instructions, there
is always a D bit or a Q bit in the instruction code map (explained beIOVJ). The
first syntax corresponds to a D or Q bit of 0, and the second corresponds to a

DorQbitofl.
Abbreviations used in the syntax column are:

Code

Represents

Dn,Dnl,DnZ
An ,Anl ,AnZ
Rn,Rnl ,RnZ

Arty data register (DO to 07 )

Arty address register (AO to A7)
Any An or Dn
Program c"mter (lon9"Ord)
Status register ("",rd)
Condition code register (byte)

PC
SR
CCR

312

68000, 68010, and 68020 Primer

SSP
USP
SP
Rc
d3
d4
d5
d8
d16

d32
#n

Dc,Dcl ,Dc2
DU,Dul ,Du2
reglist
label

Supervisor stack pointer (longword)

User stack pointer (longword)
Active stack pointer (longword, synonymous with A7)
My cootrol register (USP,MSP,ISp,VBR,SFC,DFC,CI'CR,CAAR)
An unsigned 3-bit number from 0 to 7 (except for the BKPT
instruction, 0 represents a value of 8)
An unsigned 4-bit number from 0 to 15 (a trap vector)
An unsigned 5-bit number from 0 to 31 (a bit position number)
An unsigned 8-bit number 0 to 255, or signed 8-bit number
- 128 to + 127
An unsigned 16-bit number 0 to 65536, or 16-bit signed number -32768 to + 32767
An unsigned 32-bit number 0 to 4294967295, or 32-bit signed
number-2147483648 to +2147483647
#d8 for byte instructions, #d 16 for ..oord instructions, and #d32
for lonQ'NOrd instructions ea,ea l ,ea2 an effective address (see
Table 0 -1 for the 12 modes). In most instructions, not all of the
12 modes are legal; the SRC and DAT columns in Table 0 -2
indicate which modes are legal (see explanation of SRC and
DAT columns belOVJ).
Ar"Py On, used for comparisons.
Arty On, used for updates.
A list of 0 to 16 registers (aU An or On) , separated by commas.
Source code: a label found elsewhere in the program. Object
code: a d8, dI6, or d32 offset from the current position.

Ar"Py expression contained within braces (eg, {#n}) is optional; it may either
be present or omitted (left blank). Any commas, parentheses, colons, or hyphens
correspond to actual program code.

INSTRUCTION CODE MAP COLUMN

This column contains bit-by-bit descriptions of the assembled Instructions. Each
bit is given as a 0 bit, a 1 bit, or as part of a bit "field". Each bit field begins
with a capital letter, and may be 1 to 32 bits in length. The bit fields used are

described below.

52

A 2-bit size indicator (OO=by te, 01 = word ,

10 ~ longword).
A I -bit size indicator ( O ~ word , 1 ~ Iongword ). Exception: CHK reverses the bit (see note Q to Table 0 -2).

M68000 Instruction Summary

Siz
Q

Source
Destin
llndes
Sar
Dar
Sdr,Ddr
Sdar,Ddar

Fefadr
Tefadr
Fdr
Tdr
Far
Tar
Fdar
Tdar
Udr
Cdr

313

A 3bit operand size indicator (010 = word ,

011 = longword, 100= none).

A I-bit size indicator for MULx and DlVx (0 = longword,
I =quadword).
A fu1l6-bit source effective address. 12 possible address
modes can be encoded in these 6 bits. See Table 0 1
for a summary of all 12 modes.
A 6--bit destination effective address (see Table 0 1).
Same as Destin, except the first and last 3 bits are
swapped. Occurs only in the MOVE instruction.
A 3bit source address register.
A 3bit destination address register
3bit data registers (source, destination) .
4-bit data or address registers (source, destination). An
address register is indicated by a Obit, follO\..lJed by the
3bit address register number. A data register is indicated
by a I bit, followed by the 3-bit data register number
A l bit direction indicator, which determines whether
various fields are source or destination . In general, when
an instruction contains a 0 bit all " from" fields are
source, and "to" fields are destination. When the 0 bit
is 1, all " hom" fie1ds are destinations, and all " to" fields
are s<xuces. All fields affected by the 0 bit are included
in the next eight entries.
A 6.bit " from" effective address. It is source when 0 bit
is 0, destination when 0 bit is 1.
A 6-bit " to" effective address. It is destination if 0 bit is
0 , source if 0 bit is 1.
A 3 -bit "from" data register. It is source when 0 bit is
0, destination when 0 bit is 1.
A 3bit "to" data register It is destination when 0 bit is
0, source when 0 bit is 1.
A 3-bit " from" address register. It is source when 0 bit
is 0 , destination when D bit is 1.
A 3 -bit "to" address register. It is destination when 0
bit is 0, source when 0 bit is 1.
A 4-bit " from" data or address register. It is source when
bit is 0 , destination when 0 bit is 1.
A 4-bit "to" data or address register It is destination
when 0 bit is 0 , source when D bit is 1.

A 3-bit update data register (for CAS,CAS2).

A 3-bit compare data register (for CAS,CAS2 ).

314

68000,68010, and 68020 Primer

Hdr
Imm
Immediat
Displace

A 3-bit high order word data register (for MULx and

DIV,).
Immediate data field (3-bit).
Immediate data field (8-bit, 16-bit, 32- bit).
Immediate address displacement field (8- bit, 16-bit, 32-

bit).
Cnt

A 3-bit shift count.

Argcount
Bitno

8-bit argument byte coont (for CALLM).

A 5 -bit or 3-bi t bit position number (for
BTST,BCHG,BCLR,BSET).
A 3-bit vector (for BKPT).

Vee
Vect
Registerlistmask

A 4-bit vector (for TRAP).

A 16-bit field selecting 0 to 16 registers (for MOVEM).

The order is DO at bit 0 through A7 at bit 15, except for
pre-decrement address mode, when it is reversed ,
A I -bit sign indicator for MULx and DIVx (0 = unsigned,

Bitoff

1 ~ signed).
A I -bit rotation dire'.tion indicator (0 = right, O= left) .
A 6-bit field specifying a bit offset, either 0 n n n n n

Bitwid

indicating a 5-bit immediate value, or 1 0 0 n n n,

indicating data register On .
A 6-bit field spedfying a bit width (same fonnat as

Bitoff).
Coprocessorcommd

Cpi
Cpcond
Control regis

A 16-bit co-processor instruction.

A 3-bit co-processor id code.
A 6-bit co-processor condition code.
A 12-bit control register code. Codes defined are:

0000 0000 0000

0000 0000 0001
0000 0000 0010
1000 0000 0000
1000 0000 0001
1000 0000 0010
1000 0000 0011
1000 0000 0100
Cond

~
~

~
~
~
~

SFC
DFC
CACR
USP
VBR
CAAR
MSP
ISP

(68010)
(68010)
(68020)
(68010)
(68010)
(68020)
(68020)
(68020)

A 4-bit condition code. Codes defined are:

0000
0010
0 100
0110

~
~

~
~

True
High
Carry Clear
Not Equal

0001
0011
0101
0111

~
~

~
~

False
Low/Same
Carry Set
Equal

M68000 Inslruclion Summary

1000 ~
1010 ~
1100 ~
1110 =

Overflow Clear IDOl

Plus
GreaterlEqual
Greater Than

~ Overflow
1011 = Minus

1101
1111

~
~

315

Set

Less Than
Less/Equal

Each 68(X)() instruction is 1 to 11 VJOrds in length, and consists of 1 to 3

VJOrds for the basic instruction follo.ved by 0 to 10 address extension words.
Table 0 -1 lists only the basic instruction words. Arry 16-bit word patterns
surrounded by parentheses are optional, e.g. , whenever an immediate field can
have 16 or 32 bits, the second 16 bits will always be shown surrou nded by
parentheses. For each of the 12 addressing modes, the address extension word(s)
always have the same format. Table 0-1 lists the number of address extension
\.VOrds possible for each addressing mode. Because o f their regularity, address
extension VJOrds are not included in Table 0 -2.

SRC AND DST COLUMNS

The SRC and DST columns summarize the legal addressing modes for source
and destination operands in a few symbols. The symbols are consistent, concise,
and conducive to memorization.
If only one of the 12 basic addressing modes is legal in an operand, it is
represented by one of the following symbols: On , An, (An), (An) +, -(An) ,
diAn), Sp, (SP) +, -(SP), I, where all of the symbols should be self-explanatory,
except for I, which represents an immediate field.
A " Q" code indicates that the operand is a 3-bit immediate value.
If several addressing modes are legal in an operand, then they are represented by one of the following category codes: EA, REA, DEA, MEA, CEA,
AEA, ADEA, AMEA, N:.EA. These categories are explained earlier in this
appendix. EA represents all addressing modes.
Special registers are represented by the symbols CCR, SR, PC , USp, which
should also be self-explanatory. A "cr" symbol represents any of the control
registers USp, MSp, ISp, VBR, SFC, DFC, CACR, CAAR
A few cases require additional notation:
(On)

&

Represents data indirect addressing

Used to join groups, for example "CEA&Dn" means "any control
address or Data Direct addressing"
Used to subtract parts of one group from anothet; for example,
"DEA- I" means any DEA except immediate mode addresses
Used to indicate two operands: " Dn,An" means one On operand
and one An operand; " Dn,Dn" means two On operands

316

68000, 68010, and 68020 Primer

Observant assembler programmers may notice that in operands where only

one addresssing mode is allONed, that addressing mode's code often matches
the last 6 bits in the instruction. For example, the SWAP command implidtly
uses only data register direct addressing, which corresponds to a &.bit code of
DOOm. The last 6 bits of SWAP are, indeed, these same 6 bits. But, beware,
this agreement occurs only about half of the time.
CONDITION CODES COLUMN

This column indicates which condition codes are affected by each instruction.
Symbols used are

o
1

Code
Code
Code
Code
Code

is unchanged by instruction
is set to 0
is set to 1
is changed
is left with undefined value

PRIVCOLUMN

This column indicates which instructions are privileged. Privileged instructions

may only be executed when the syste m bit is set to 1. Otherwise, an exception
is generated.
NOTES COLUMN

Letters in this column refer to footnotes at the end of the table.

I mm e d i a t x x x x x x x x

o 0 0 0 0 S z 0 lIS 0 U r c e CEA

#o,CCR

#n,SR

ea,Rn

20

20 ea,Rn

ORI.W
('oSR)

CMP2.s

CHK2.s

AIlEA

000 0 S d r 1 1 IDe s tin DIl

oooordrlDSOOlfar d(An)

DIl,ea

d16(Aol),DIl2
DIll,d16(An2)

BSET

~s2

Dis P I ace x x x x x x x x DIl

AIlEA

000 0 S d r 1 1 ODe s tin Do

DIl,ea

BCLR

Do
diAn)

AIlEA

o 0 0 0 S d rIO 1 Des tin Do

BCHG

Dn,ea

DIl,ea

BTST

IlEA

REA

000 0 S d r IO ODe s tin DIl

o dar 1 0 0 0 0 0 0 0 0 0 0 0

o 0 0 0 0 S z 0 lIS 0 U r c e CEA

n dar 0 0 0 0 0 0 0 0 0 0 0 0

REA

SR

o0
0 0 0 0 0 0 0 1 1 1 1 1 0 0

CCR

00000 0 0 0 0 0 1 1 1 100
000 0 0 0 0 0 I m m e d i a t

(x x x x x x x x x x x x x x x x l

ORI.B
('oCCR)

--,- -

--*--

--,---,--

-U'U'

-U'U'

....
..,.,
,

-**00

AIlEA

Condition
Codes PrifJ Notes

o 0 0 0 0 0 0 0 S zOe s tin
I mm e d i a t x x x x x x x x

DST

XNZVC

SRC

FED C B A 9 8 765 4 3 2 1 0

Instruction Code Map

#n,a

CPt! Syntax

68000 Instruction Summary

ORLs

Instruction

Table D-2

-...

3
3

11c
0
g.

'"5'

8'"

i::
a.

20 Dcl :Dc2.DuI :Du2,(Rnl :Rn2) 0 0 0 0 1 S z 0 I 1 1 I I I 0 0

CAS2.,

o d ar 0 0 0 U d rOO 0 Cdr
o d ar 0 0 0 U d r OO 0 Cdr

00001 S z 0 liD est i n

000 0 0 0 0 U d rOO 0 Cdr

20 Dc,Du,ea

CAS.'

[).,

[).,

00000 1 101 IS o u r c e CEA

o 0 0 0 0 0 0 0 A r g C0 Un t

1 lOS z Des tin

I mm e d i a t x x x x x x x x
tx x x x x x x x x x x x x x x x)

o0 0 0 0

(x x x x x x x x x x x x x x x xl

20 1d8,ea

'n,ea

AOOI.s

xxxxxxxx

00000 1 0 0 S zOe s t i n
I mme d
a t xx xx xxx x

100 1 1 1 1 100

CAll.M

#n,ea

SUB!.,

d i

0 0 0

m me

00000 1 101 1 00 S dar REA

Id16,SR

AND!.W
Ito SRI

o
o0

0 0 0 0 1 000 1 1 I 100
0 0 0 a 0 0 0 I m me d I a t

o0

SRC

20 Rn

#dS,CCR

ANOI.B
IloCCR)

(x x x x x x x x x x x x x x x x)

o 0 0 000 lOS zOe s tin

I mm e d i a t x x x x x x x x

I_CodeMop

RIM

'n,ea

CPU Symx

ANDI.s

Instruction

IAn) & I[).,)

AMEA

A/JEA

A/JEA

SR

CCR

A/JEA

DST

-""

....
_

"'"

.....

,.".

,.,"

-**00

1m)

Cad"",
Codes Prill Notes

~,

0>
0

"-

0>
0

0>
0
0

'"

'"

'n,ea

Id8,CCR

IdI6,SR

Ernl.s

EOOLB
(toCCRI

EORI,W
(to SRI

eal,ea2

ea,An

eal,ea2

" ,An

M:!/E.B

M:WEA.L

M:!/E.L

M:NEA.W

10 ea,Rn
Rn,..

1d5,ea

BSET

WES.s

#d5,ea

BCLR

[.1 'n,ea

#d5,ea

BCHG

CMPI.s

IdS,ea

BTST

0 0 0 0 0 0 0 008 i t

n0

0 0 0 0 0 0 0 0 0 Bit n
0

0 0 0 0 0 0 0 0 0 Bit

n0

0 0 1 0 1 001 1 1 1 100

m me d i a t x x x x x x x x

00

de s S ou r c e EA
lOa rOO 1 S o u r c e EA

o 0 lOT i

00 1 0 Dar 0 0 1 Sou r c e EA

OOOlTindesSource DEA

o 0 0 0 1 1 l O S z F e fad r AMEA [qJ

T da r D a 0 0 0 0 0 0 0 0 0 0 REA

An

ADEA

An

AIlEA

AMEA [o[

REA

s:

Co

'"
8

**00

-**00

-----

-'",.,

3
3

if

...

;;-

.,

.....

"00

--,--

--,--

_. ,.-

--*--

Ix x x x x x x x x x x x x x x xl

ADEA

SR

CCR

ADEA

ADEA

AIlEA

ADEA

IlEA- I

I mme d i a t x x x x x x x x

0000 11 O O SzOe s t i n

o0

o 0 0 0 0 0 0 0 I mm e d i a t

0000101000 1 11100

o 0 0 0 1 0 lOS zOe s lin

I mme d i a t x x x x x x x x
Ix x x x x x x x x x x x x x x xl

o0

OOOOlOOOllDestin

o0

o 0 0 0 1 000 1 ODe s ti n

o0

0 0 1 0 0 0 0 ODe s t i n
0 0 0 0 0 000 0 B i t n 0

o a 0 0 1 0 0 0 0 I De s tin

o0

o0

SR,ea

MCWEW

AIlEA

AIlEA
An,Pc

o 1 001 0 0 0 0 ODe 5 tin

o 0 1 0 1 0 0 0 0 0 0 0 lOa r
Dis pIa c e x x x x x x x x

ea,CR

ea

20 An,Id32

MCWEW
(loSR)

NBCD
UNKL

o S zOe s tin

xxxxxxxxxxxxxxxx

o 1 000 1 1 0 lIS 0 U r c e IlEA

a0

CCR

AIlEA

o1

eo

NCTs

CCR

o 1 000 100 lIS 0 u r c e IlEA

ea,eeR

MCWEW
(loCCR)

o 0 S z Des tin

o]
000

AIlEA

o 1 0 0 0 0 1 0 1 IDe s tin eCR

ea

10 CCR,ea

AIlEA

Dn
An

NEG.s

MCWEW
(/rom CCRI

o 1 0 0 0 0 1 0 5 z Des tin

ea

0 U r c e CEA

CLR.s

lIS

ea,An

o 0 Dar 1

o 1 0 ODd r 1 S 0 Sou r c e IlEA

AIlEA

-**00

AIlEA

*u*u'

**00

..

" ,

- 0100

_UUU

.....

Codes

DST

o I 0 0 0 0 0 0 1 IDe 5 tin eCR

Tin d es Sou r c e EA

SRC

AIlEA

Code Map

o 1 0 0 0 0 0 0 S z Des tin

001

Instruction

LEA

CHKs2

ea,Dn

ea

NEGKs

[el

eal,ea2

MCWEW

[/rom SRI

CPU Sy",",

1_

Coo:fitiOll

[pi

iii

Iii

[al

Priu Notes

"
,

0
."

'"

Q.

'"
,

'"
,2

..,'"

1 1 0 0 ODd r

1 S 0 0 ODd

0"

0"

-iSPI

0"

o 1 0 0 1 I 1 0 0 1 0 0 Vee t (ij

1d4

An,ld16

mAP

UNK.W

UNlK

o1

US~An

(USPI

RESET

o1

An,USP

MOVE

USP

a r An
001 1 100 1 1 1 000 0

0 0 1 1 1 0 0 1 1 ODS

USP
An

Sp,An

o1

An

0 0 1 1 1 0 0 1 0 1 lOa r

An,Pc

III

0",0"

0",0"

AIJEA

EA

AIJEA

o 1 001 1 100 101 0 0 a r

An,(SP)+

ODd r T Q 0 0 0 0 0 0 0 H d r

ea,Dn
ea,DnLDn2
ea,Dnl ,Dn2

2Q
2Q
DlVSLUDlVULL 2Q

o 100 1 1 000 1 Sou r c e IlEA

IDe s tin

DIVS.UDIVU.L

1 0 0 1 0 1 0 1

OIOOllOOOOSource [)fA
ODd r T Q 0 0 0 0 0 0 0 H d r

o 1 0 0 1 0 lOS z Des lin

010010001 S T e fad r aURfA

foCEA&-iAnI
Reg i s t e r 1 i s l mas k CEA&(An)+ aD REA

o 1 001 000
o 1 0 0 100 1

o 1 0 0 1 0 0 0 0 1 Sou r c e CEA

MULS.UMUW.L 2Q ea,Dn
20 ea,Dnl,Dn2

ea

ea
ea

010010 1 011111100

2Q

0 0 I 0 0 0 0 100 ODd

o 100 1 0 0 0 0 100 1 Vee

o1

ILLEGAL

TAS

TSls
TSIWITSU

ea,<egIist

~ea

0"

EXTB.L

MOJEM.s2

0"

EXT.s2

2Q

ea

PEA

#d3

8KPT

10

0"

SIII'J'

-'''0

_uo

-"00

-"00

-----

- *'00

-**00

-**00

X
X

Ivl

Ibl

lei

191

...,
'"

,
'"3c

g.

1<c

;;

8'"
c

RC,Rn
Rn,Rc

#d3,ea

ea

On,labet

AOOQ.s

Sec

DBcc

SUBQs

#d3,ea

20 (In)

ea

JMP

mAPcc.s3

ea

10

JSR

MClJEC

001 1 1 0 0 1 1 101 1 1 ISPI+

o1

1 0 0 1 1 1 0 1

Ole 0 n d 1 IDe s tin

PC

AEAlkl

On,1

010 1 I m m 1 S zOe 5 tin Q

1 ace x x x x x x x x
It I

ADEA

AEAlkl

PC

PC

REA

ItI
CCR,PC

PC

PC

SR,PC

SR

DST

o 1 Ole 0 n d 1 1 1 l i S i z It I
(x x x x x x x x x x x x x x x x l
(x x x x x x x x x x x x x x x x l

Dis

o 1 Ole 0 n d 1 100 1 0 d r

IDe s tin CEA

010 1 I m m 0 S zOe s t i n

o 1 0 0 1 1 1 0 1 ODe s tin CEA

o 1 00 1 1 100 1 1 1 1 0 IOcr
T dar Con t r 0 1 reg i s

1 1 101 1 0 It I

ISPI+

RTR

o0

0 1

001

o1

TRAPV

1 1 100

001 1 100 1 1 1 0 1 0 0 ISPI+ III

o 100

1 0010

001 1 1 001 1 100 1 1 ISPI +

001 1 100 1

SRC

RTS

RID

10

RTE

NO!'
0 0 1 1 100 1 1 1 000 1

Instruction Code Mop

STOP

CPU Syntax

o1
o1

,-

.....

Ibl ldl

Idl

lei

X Ihl

X 151

.....

.....

Ccnlitioo
Ccxks Priv Notes

~l,

-"

'"0

Q.

'"0

'"
0
0
,0

'"
'"
'"

10

BSR

OllOCondDisplace J

1 0 0 0 Dar 1 0 0 0 0 1 S a r

1 0 0 0 D d riO 1 0 0 0 S d r Dn
A d jus t e n t x x x x x x
lOOODarlO lOOl Sar -(An)
A d jus t men t x x x x x x

100 O Dd r 1 1 0 0 0 0 S d r Dn
A d jus t men t x x x x x x
lOOODarllOOOlSar -(An)

-{An ll,-{An21

20 Dnl ,Dn2,ldl6

20 -{Anl l,-{An2I,'dI6

20 Dnl,Dn2,#dI6

20 -{Anll,-{An2I,#dI6

SBCD

PID\

PID\

UNPK

UNPK

A d jus t men t x x x x x x

~An )

r Dn

-{Ani

Dn

-{Ani

Dn

-{Ani

Dn

0 0 0 S d

o0

1 0 0 ODd r

SBCD

Dn

Dn
AMEA

Dn

PC

PC

PC

lO OOodr Tll Source [)fA

" ,Dn
Dnl ,Dn2

1 0 0 0 T d r 0 S z F e fad r IlEA
Dn

..,Dn
Dn,"

1 1 0 d r 0 I mme d i a t

o1

IdB,Dn

Ix x x x x x x x x x x x x x x xl

o 1 100 0 0 1 0 i s pIa c e
(0 i s pIa c e x x x x x x x xl

(x x x x x x x x x x x x x x x xl

OllOOOOODisp l ace I
(0 i s p I ace x x x x x x x xl

(0 i s pIa c e x x x x x x x xl
(x x x x x x x x x x x x x x x xl

DfVUWIDIVSW

r.K:IJEQ I.LI
OO.S

labEl

10

BRA

labEl

IfI labEl

Ba:

U U

u-u

-0

-" 00

-*'00

1,1

lei

lei

lei

'"

s:

'"

'"'"

'"3

g.

5'

"-

8c

o,

I OO lDar

S zOO
S a r

-iAnl

CMPM.s

OnI ,Dn2

AnI ,An2

EXG [.L)
IOn)

EXG I.L)

IAn)

-(AnI),-(An2)

" 'On
OnI,Dn2

ABeDI.B)

ABeD I. B)

MUW,WIMULS,W

" 'On

[AnI )+,1An2) +

Ern.s

On, ..

CMPAs2

AND.,

" 'On
ea,An
1

TIl Sou r c e

[]fA

0
0

S d r

o 0 S a r

o0

0 S d

On,On
O OISar An,An

o0

OOOOlSar -iAn)

o ODd rI O 000 0 S d r On

o ODd

On

[]fA

-(An)

On

On

On
AMEA

[An) +

S zOO 1 S a r (An) +

o 0 T d r D 5 z F e fad r

lOa r

1 1 0 0 0 a r

1 0

An

On

-(An)

On

An

On
AMEA

DST

S zOe s tin On

lOa r S l I S 0 u r c e EA

lOllS d r

101 1 0 d r 0 S z Sou r c e EA [kl

-(AnI),-(An2)

SUBll,

100 1 0 d r 1 S zOO 0 S d r On

CMP,

OnI ,Dn2

SUBll,

100 1 Dar 5 lIS 0 u r c e EA

1 0 1 0 .

ea,An

SUBAs2

SRC

o 0 1 T d r 0 S z F e fad r EA [k[
On

I_CodeMap

Us..-defi.-.d

" 'On
On,,,

CPU Syrtax

SUB.s

Instruction

tUtU'

'U*U'

-"'0

-" 00

-,.,.

-"00

-,.,.

....
_

.....

[wi

Condiion
Codes Priv Notes

'"'l'

00>
0

"-

!='

00>
0

!='

00>

'"'"

,.,On
On,ea

ea,An

Onl,Dn2

-(An ll,-(An21

1d3,On

Onl,Dn2

1d3,On

Onl ,Dn2

1d3,On

Onl,Dn2

1d3,On

Onl ,Dn2

ea

ea

ea

ea

ea {ollseto""'lh}

AlJ().s

ADCt\s2

AlJ()l(s

AlJ()l(s

ASR.slASLs

ASR.slASL.s

LSR.sIlSLs

LSR.sIlSLs

ROXR.slROXL.s

ROltR.sIROXLs

ROR.s/ROLs

ROR,s/ROLs

ASRiASL (WI

LSRILSL (WI

ROXRIROXL (WI

RORIROL (WI

IlfIST

20

Onl,An2

EXG (.LI
(On,AnI

DarlSzOOlSar --{An)

t RS

0 0 R I

Des tin

1 0 1 0 0 0 1 1 0 est
OOOOBiLoffBitw

n
d

OOllRIIDestin

100 lOR 1 IDe s tin

1 000 I R lID est i n

o0

l OS d r R S z 1 I I 0 d r On

CEA & On

AMEA

AMEA

AMEA

AMEA

On

On

1 0 Cn t RS z 0 1 1 0 d r

On

On

ODd r On

z 0 1 ODd r Q

1 1 0 5 d r RS z 1

o Cn

On

On

o C n t R S zOOID d r Q
lOS d r R S z 1 0 1 0 d r On

On

On

-(Ani

On

An

On
AMEA

lOS d r R S z 1 0 ODd r On

lO C ntRSzOOOOdr Q

SzOOO$ dr On

Dar 5 lIS 0 U r c e EA

1 1 0 1 0 d r

1 1 0 1 T d r 0 S z F e fad r EA(kl
On

o 0 5 d r 1 1 000 1 S a r ~An

..

"00

"0'

'''0'

"'0*

"0'

"0-

"'0*

"'0'

'''0*

.. 'a

."

.... ,
" ...

'"'"
'"

,0

'"3

0
"n0
,c'

'"000'"

l:

On

1 1 1 0 1 0 1 1 l i S 0 u r c e CEA&On
ODdrBitoffsitwid

20

20 ea

cpGEN

cpSccl.B)

20

20

BF1NS

cpDBccl.w)

11 1 0111111Destin On
Bit 0 f fBi t wid

20 ea {offsetwKlth)

BFSET

On,~bO

lop """""",,I

On,ea {offsetwKlth)

1 1 1 0 1 1 1 0 1 IDe s tin
f fBi t wid

20 ea {offsetwKlth),On

BFFFO

r c e CEA &Dn
wid

o 0 0 0 0 0 0 0 0 0 C P con d
Dis pIa c e x x x x x x x x

llllCpiOOlOOlDdr On,1

1 1 l I e p i 0 OlD est i n
0 0 0 0 0 0 0 0 C pC 0 n d

o0

Cop roc e s S 0 reo m m d

1 1 l i e p i 0 0 ODe 5 tin

oS d r

o 0 0 0 Bit 0

1 1 1 0 1 1 0 1 lI S 0 U
ODd r Bit 0 f fBi t

1 1 1 0 1 100 1 IDe s t i n
f fBi t wid

20 ea {offsetwKlth)

BfCUl

o 0 0 0 Bit 0

20

BfEXJS

ea {offsetwKlth),On

I>CEA&On

1 110 1 0 1 0 1 IDe s t i n
f fBi t wid

o 0 0 0 Bit 0

20 ea {offsetwKlth)

BFCHG

PC

ADEA

I>CEA&On

I>CEA&On

On

I>CEA&On

On

1 1 1 01001 l I S 0 U r c e CEA&Dn
ODd r Bit 0 f fBi t wid

OST

20 ea {offsetwKlth),On

SRC

BFEXTU

I_eadeM",

CPUS,.-

1_

-*'00

-00

- *'00

-**00

-*'00

-"00

-*'00

Inl

Coo.. Priu Notes

c_

'l'

'"'"0
P
,
"'"'"0

'"'"
,8

'"

....
'"

20 Dn,label

20 eo

20 ea

cpBcc.s2

cpSAVE

cpRESTORE

lIe p
0 0 0 0
x x x xx
x x x x x

1 1

i 001 1 lIS i
0 0 0 0
p con
x x x x x x x x x
x x x x x x x x x
z
d
xl
xl

1 1

C P i 1 0 ODe s t I n

lIe p I 1 0 1 Sou r c e CEA & IAnI+

1 1 1

I I I 1 C P i 0 1 S C P con d
Dis p I ace x x x x x x x x
(x x x x x x x x x x x x x x x xl

{x
(x

o0

PCEA&-(Anl - - ---

PC

lhl MOVEC supports more control registers on the MC68020

columns preceding Table D~2,

(~

list). for a list of the control registers, see the

e~ptilnil!ion

of the instruction code nloll>

Igl BKPT has evolved as follows:

MC68000-Not implemented.
MC6801 O-Generates a breakpoint bus cycle with address space bits 1 '1 and J2-bit address o.
MC68020-Generates a breakpoint bus cycle wi th the breakpoint vector on address lines A2, AJ, A4, and z('ro on addressed lines AO, AI; a response
is also gel1l"rated, either') 16--bit instruction, or an illegal instruclion excepti on.

lei Certain instructions have extended functions in the MC68020. Bec, BRA, BSR allow J2-bit displacements; CHK allows J2-bi t eKlensions (CHK. W legal
on MC68000, CHK.L legal on MC68020); CMPI, TST su pport PC relative addressing modes.
If) ikc, BRA, BSR allow 8--bit, 16-bit, i1nd J2-bit displacements as follows:
MC68000~tf the 8--bit displilcement is 0, then a 16-bit displacement follow s.
MC68020~lf the 8--bit displacement is hex FE then a J2-bi t displacement follows.

lal The S bit field in CHK is reversed from other instructions (O=longword, 1 =wmd). This is bec.lU'~e the longword format is an MC68020 feature (not
originally designed).
Ibl ILleGAL is the only instruction pattern guaranteed to always be an illegal instruction, All other patterns art! reserved lor luture expansion by Motorola.
TRAPF has no effect in an MC68020 program (like a NOP), but in a MC680 10 program will cause an illegal instruction exception. Hence, Motorola
recommends pUlling a TRAPF instru<:lion al the beginning of any MC68020 program that is no1 b.lckwilrds compatible with the MC680 10. If the program is
ever run on the MC68010, it will not cause serious trouble.
Icl An immediate value 01 is interpreted as 8 in ADDQ, SU8Q, and the shift instructions.
Idl Condition codes ()(X)(I (T) and 0001 (FI are not available in Bcc and cpBcc. Note that BRA has a bit pallern corresponding to "BRT", and BSR has a bit
pattern corresponding to " BRF". DBcc, cpDBcc, Sec, cpScc, and TRAPcc allow all condition codes.

20 {in}

cpTRAPcc.s3

"'"

,~

g.

a2"

Dn(word quO! , word rem)

Dntlong quot)
onl(longrem) , Dn2t1ongquotJ
onl(1ong rem), on2(long quot)

registers.

Iwllnstructions starting with bilS 10 10 are reserved lot user definition. They generate interrupts, and are variously called emulate, user-defioed, iUeg;al . and
unde4'ined instructions. On the MC68000 and MC68010. instructions stolrting with bits 1111 generate interrupts similar to the 1010 Instructions, but on the
MC680 20 they are used lot the co-processor instructions.

III TRAP, TRAPcc, TRAP\! gener.rte exceptions, and affcct 5e11efa1

I'll The d iv ision commands formats are:
I ea(word)
DIVx.Wea, Dn
DN(long)
I ea(long)
Dn(long)
DIVx.l ea, on
on l :on2(qu ad)
olVx.l ca,on l :on2
I ea(long)
oIV)(l.l ea,Dn I :on2
on l (long)
l ea(long)

(sl RTf properly returns from any exception. RTE pops 4 to 44 words from the SSP or ISP, restores the PC and SR, and (when appropriate) restores other
internal processing registers. Note: bus and address errors on tile MCb3000/MC68003 generate a stack format whi ch does not fit into the general RTE return
scheme. In these Colse5, 4 words must be popped from the stack before doing an RTE .

(rl Displacement also added to SP (lHo instruction).

Ipl MOVE (rom SR is not privileged in MC68000, but is in MC680I OIMC68020. This is necessary in order for the MC6801 0 to support system emulations. If
an emulolling operolting system is ilCtlJillly running in user stolte, it must not be aware that is not in supervisor mode. 8'1' trapping any MOVE ' rom SR instructions,
thi s can be accomplished.
Iq l MOVES I"llOYeS across different address spilces, so Its itddresSlng modes are correspondingly limited.

Inl cpGEN: the legal olddressing modes and condition code changes ilre dependent on the coprocessor,

Iml Note that CAS2 allows dolta Indlre(:\ addresSing. that is, IOn),

IkJ Address registefS are illeg;al in byte operationS.

Iii MOVE from CCR and MOVE to CCR are techniCollly word operations. &>Ih require word leven) olddresses, but only IT1O\Ie the CCR byte. In a(khtlon, MOVE
from CCR dears the upper byte 01 the destination,

~.

::?

,'"

5.

'"

W
N

f
M68000 Resources

The follOVJing symbols to the right of a listing indicate the categories of items
available from a supplier (note that many of the systems mentioned in this list

are now becoming available in 68020 versions):

K
SBC
Sys

Kits
Single board computers

Complete systems
Software

X
U
Chip

Cross compilers
Unix (or Unixrelated)
Second source manufacturer
KlSBC/X

Allen Systems
2151 Fairfax Road
Columbus, OH 43221
(614) 488-7122

FX-688 SBC inc MC68008/6551 USART @ $350 inc 8K EPROMl2K RAM

Cross assemblers for Apple II/John B. Allen
SysiS/U

Alpha Microsystems

PO Box 18347
Irvine, CA 92714
AM-100UAM-1000/ W,rk Stations and Multiuser Systems MC68000 under
AMOS, PC-DOS and UNlMOS. $5,000 to $100,000 +
329

330

68000, 68010, and 68020 Primer

Alycon Corporation
8716 Production ......nue
San Diego, CA 92121
(714) 578-0860

S/SyslSBCIU

REGULUS OS (Unix + )/A68KPM SBC with LSI-II bus compatlblily

256K basic model @ $2900; APX extended proc @ $29,900
VO processor @ $2,345
Apple Computers
20525 Mariani Avenue
Cupertino, CA 95014

SysiS

Macintosh/Big MacIXUlisa
Laser printer uses 10M Hz MC68010 + I Mb RAM + .5 Mb ROM
Arete Systems Corp.
San Jose, CA
(408) 263-9711

SysiSIU

Dual 68000lUnix engine, Model 1124/under Unix V or RMiCOS

Atari

SysiS

1196 Borregas .......

Sunnyvale, CA 94086
MC68000-based 520ST personal computer @ $800. Built-in color. sound.
512K RAM , 8 MHZ CPU. Runs TOS ' , GEM ' (Digital Research Inc. ).
AT&T

SysiSIU

PO Box 967
Madison Square Station
New York, NY 10159
PC7300 uses 68010/512K-1 floppy/lOMb hardlbuilt by Convergent Technologylbuilt in 1200 baud modem @ $4,000-7,000

Boston Systems Office

469 Moody Street
Waltham, MA 02154
(617 ) 894-0760
Software development for most microslDECIIUMDS-lO OS/UMDS-30

S/UIX

M68000

CCA Uniworks
Four Cambridge Center
Cambridge, MA 02142
(6171492-8860

Resources

331

S/U

CCA EMACS ~ Full screen text editor under UNIX

Elisp = extension language

Charles River Data Systems. Inc.

983 Concord Street
Framingham, MA 01701
(6171655-1800

Sys/S/u

Universe 68/05 32bit versabuS/12.5 mhlMC68000 Vo pro<

Universe 2203 VMElUNOS ~ realtime ext of UNIX V

Chromatics
2558 Mountain Industrial Boulevard
Tucker, GA 30084

Sys/S

CGC 7900 Color Graphics Computer/under lORIS OS

Codata Systems, Inc.

(CONTEL CODATA 1
285 N Wolfe Road
Sunnyvale, CA 94086

Sys/S/U

UniSoft UniPlus + /CTS-300/lntel MultibuslMERLIN OS/ Model 3300 ~ multiuser 84Mb @ $13,500/ 33 Mb @ $9,600/ 12Mb @ $7,6OO/

Commodore International
1200 Wilson Drive
Westchester, PA 19380
(2151431 -9100

Sys/S

AMIGA MC68000-based business/home computer @ $1295

Built-in GraphicslSou ndlAmiga DOS
Compupro, Inc.
3506 Breakwater Court
Hayward, CA 94545

Wide range of CP/M-68K single/multi-user systems

Sys/S

332

68000, 680/0, and 68020 Primer

Control Systems. Inc.

1317 Central Avenue
Kansas City. KS 66102

UCSD 2.0 Pascal compilerlinterpreter for M68000

Converge nt Technologies

SysiSIU

Data Systems Division

3055 Patrick Henry Drive
Santa Clara, CA 95050
(4081 980-0850
$20,000 16-user MegaFrame with 68010 10MHz
MiniFrame starter at $5,000

Unix VI cobol;fortran-77;basic;pascal;C
See also AT&T PC7300

Cromemco. Inc.

SysiSIU

280 Bernardo Avenue

PO Box 7400
Mountain View, CA 94039
(415) 969-4710
UNIX VI System 100 with 4 Mb up to System 300 with 16 Mb

CYPHER

SBC/KIS

Mote! Computers, Ltd.

174 Betty Ann Drive

Willowdale, Ontario
M2N 1X6, Canada
(416) 221 -2340

MC68000/Z80 SBC, kit or assembled/under CP/M88

Digital Research. Inc.
PO Box DRI
Monterey, CA 93941

S/U

CP/M 68K = version of CP/M for M68000

DUAl Systems Corporation

720 Channing Way

Berkeley, CA 94710
(415) 549-3854

SysiS/U

M68000 Resources

333

Instrumentation/process control

Model 83/80 UNIXlI 68KS-7;68KS-8 UNIX V7

UniSoft UniPlus + on 5- 100
Educational Microcomputer Systems

SBCIKIXIS

PO Box 16115
Irvine, CA 92713
(714) 854-8545

M68000 macro eros ass lor IBM PC @ $199

SBC @ $695 16K EPR0MI20K RAMl2xRS-232C/debug monitor
EFCIS

Chip

(Thomson-CSF & French Atomic

Energy Commission)
45 ave de I' Europe

78140 Velizy-Villacoublay
France
M68()(x) second source
Emulogic, Inc.
362 University Pf.ienue

XIS

Westwood, MA 02090
ECL-32 11 OSI assm!basiclC/fortranipascal
Enertec. Inc.
19 Jenkins AJenue

Lansdale, PA 19446
(2 15) 362-0966
Micro concurrent Pascal for M68000/interpreter-kemel 3.2K
farbware

SIX

1329 Gregory
Wilmette, IL 60091
(312) 251 -5310
Xa55mblr A68K11inker L68K1 + LlB68K for CP/M and PC-DOS @. $200- 250
C source @ $700
Forward Technology
2175 Martin AJenue

Santa Clara, CA 95050

(408) 988-2378

SysiSIU

334

68000, 68010, and 68020 Primer

FT-68X has XenixilOMhz Multibus Grafics cnilr

GenradIFuturedata

SfX

5730 Buckingham Parkway

Culver City, CA 90230

Pascal cross compiler

Hemenway Associates. Inc.

10 1 Tremont Street, Suite 208

Boston, MA 02 108

Roating Point package/Pascal compiler

H eurikon Corporation

SBCIU/S

3201 Latham Oct""

Madison, WI 5371 3
(800) 356-9602
(608) 271-8700
Minibox = UniSoft UniPlus + 1 HK68
PolyForthlRegulusl6-slot Multibus

= SBC with DR CP/M 68K

Hewlett-Packard
19447 Pruneridge Awnue
Cupertino, CA 95014

SyslSlU

HP 9826A1HP 900012001 HP-UX as

Portable UNIX on HP Integral PC @ $4990 inc HP-UX,PAM,HP Windows
Hitachi America Ltd

Chip

1800 Bering Oct""

San Jose, CA 95112
Licensed second source M6800/68000
CMOS version expected soonl = HD68000 available in normal 64pin
DIP PLUS new flat-pack for low-pov.Ier!low-space portables

Honeywell, Inc,
Billerica, MA
(617) 671 -2744
M68000-based Unisoft UniPlus + port
Workstation = MicroSystem NX @ $8,895-9,500

SysiS/U

M6BOOO Resources

IBC
Integrated Business Computers
21621 Nordhoff Street
Chatsworth, CA 91311
(8181 882-9007

335

SysiSIU

IBC Ensign = UniSoft UniPlus + port/32 station multi-user/8Mb

SysiS

IBM
Instruments Division
Orchard Park
PO Box 332
Danbury, CT 06810

Model 9000 @ $5,695 basic ~ 128K RAMlI28K ROMNERSABUS compatible

IEEE-488 interface! Optional 4x5mb or 4xlOmb hard disk

ICL, Ltd,

SysiS

Putney Bridge t-blse

London, England

Version of Sinclair QUMC68008 with telephone/modem

Inner Access Corporation
517K Marine View

SyslKlSBCIS

Belmont CA 94002
(4151591 -8295
MultiUser-16 @ $9,995 OEM ~ 8 user/500Kl40 Mb/Mirage 05/5-100
MC68000 processor board @ $695IMC68010 version @ $795
Matching VO board @ $695
Interleallnc.

SysiS

Tech Publishing System TPS-2000 on MC68010 @ $37,500 +

Intermetrics. Inc.
733 Concord Avenue

Cambridge, MA 02138
(6171661 -0072
Cross asm/pascaVc - for all M68000s
Runs on VAXNMSIUNIX also ApollO/Sun

SIXIU

336

68000, 68010, and 68020 Primer

IPI
Industrial Programming, Inc.
100 Jericho Quadrangle
Jericho, NY 11753

SyslSBClS

MTOS-68K1/assmfC/pascaV18K single-user
MTOS-68KF - ROM for OmnibytelMicrobar MC68000 SBC
Lattice. Inc.

SIU

Lattice C compiler for all M68000s

Lexidata Corporation

SysiSIU

755 Middlesex Tumpike

Bilerica, MA
Graphics system 8000fUniSoft UniPlus + port

Manx Software Systems

SIXIU

PO Box 55
Shrewsbury, NJ 07701
(BOO) 221-0440
C compilers/cross compilers all M68000-based UNIX systems

Mark Williams Company

SIXIU

1430 West Wrighru.ood Road

Chicago, IL 60614
(312) 472-6659
Unix compatible multi-user, multi-tasking COHERENT OS (tm)
C-compilers cross/native for M68000IPDP-1112BOOO18086
MOB Systems. Inc.

SysiS/U

1995 N. Batavia Street

PO Box 5508
Orange, CA 92667-0508
(714) 998-6900
Micro/32 runs under Regulus OS

Metacomco

Monterey, CA
LISP 68000 for creating expert systems

M68000 Resources

MicroDaSys, Inc.

337

SysiSiU

1541 S. Manhattan Place

Los Angeles, CA 900 19
(2131731-1475
68K Miniframe runs XENIX luses MC6809 MMU. Plans for VENIX (VM version)
Microfocus. Inc.

SysiS

2465 E. Bayshore Road

Suite 400

Palo Alto, CA 94303

(41 5) 856-4161
Animator Visual Programming! COBOL debugging aids

Microsoft

S/UIX

10800 NE 8th Street

Bellevue, WA 98004
(206) 426-9400
XENIX ~ version of UNIX v7/assm/basicic/fortran 77/Cobol-74 for M68000
and 8086/8088
Microware Systems Corporation

S/U

1866 NW 114th Street

Des Moines, IA 50322
(5 15) 224-1929

05-9

UNIX-like OS; runs on most M6809/68000s from ROM-based control

systems up to mediumscale time-sharing systems. 16K ROM abie written in

M68000 assm. C/pascaUbasicicobol

Morrow Designs. Inc.
600 McCormick Street
San Leandro, CA

SyslS/U

TRICEP ~ $2,500 per user/4 -8 users/UniSoft UniPlus + port/UN IX vi

512K + 4CRTs+ 16Mb disk @ $10,495// with 32Mb disk @ $12,495
Mostek Corporation

1215 w",t Crosby Road

Carrollton, TX 75006
Licensed second source

Chip

338

68000, 68010, and 68020 Primer

Motorola Microsystems
3102 North 56th Street
Phoenix. AZ 85018

SyslKlS

VERSAdoslstructured Macro assmlpascallfortran-77

Wide range of Software Development aids
Motorola Semiconductor Products, Inc.
Uterature Department
PO Box 20924
Phoenix. AZ 85036

Books/tech lit
Motorola Semiconductors, Inc.
3501 Ed Bluestein Boulevard
Austin, TX 78721
(512) 440-2122

Chip/SIXlKlU

EXORcisor- MEX68KDM Design rnodule-MACSbug 8K monitor

VERSAbusNMM-liersarnodule rnonoboard micro
VME bus/subset of versabus

Multj Solutions. Inc.

123 Franklin Corner Road_ SUite 207
lawrenceville. NJ 08648
(609) 896-4100

SIX

51 OS on M68000 for DataMedia 932/1BM 90001NCR Tower/Compupro 68K1

Dual CPUI IBC Ensign! Stride! SORD 68J Pertec 32001 FORCE
Wide range of Cross assemblers/compilers for M68000 and most micros

Network Research Corporation

1101 Colorado Avenue
Santa Monica , CA 90401
(213) 394-9508

LAN software-interconnects M68ooo/DEC-VAXen/IBM -PC, more

OASYS Inc.
60 Aberdeen !we.
Cambridge. MA 02138
(617) 491 -4180

Cross development toolslC and macro assemblers

SIX

M6BOOO Resources

Omnibyte Corporation
245 W. Roosevelt Road
West Chicago, IL 60185

339

SBClK

Multibus 0B68K1 SBC

Oregon Software
6915 S.w. Macadam ..... nue
Portland, OR 97021
1(800) 874-8501
(503) 226-7760

SIX

Pascal-2 native/cross all M68ooo-based UNIX systems

Perkin-Elmer
Oceanport, NJ

SysiSlU

Wide range single/multi-user systems (UniSoft UniPlus + port)

Pertec Computer Corporation

SysiS/U

Irvine, CA

(714) 660-0488

Model 3220 multiproc/5 stations/53 Mb @ $14,000

Phase One
Suite 830, 7700 Edgewater Dr;""
Oakland, CA 94621
(415) 562-8085

SysiS

OAS IS OS on Intel 808618 and M68000132-users

Phase Zero. Ltd.
2509 N Campbell ......
Suite 130

SIX

Tucson, AZ 857 19

ASSEM68K Apple lUll + 132K) to MC68000 cross assm. @ $95

MINOS 1.0 OS for Apple III +IE) and dtack grounded 68000AP board gi_
direct miC language control of MC68000
PIXEL Computers, Inc.

260 Fordham Road

Wilmington, MA 01887
Pixel BOliO MHz M68000 with UniSoft UniPlus+ port

SysiSIU

340

68000. 68010. and 68020 Primer

Plexus
Model P/35 and wide range UNIX

SysiSIU
~tations

Pyramid
PO Box 7295
Mountain View, CA 94039

SysiS

Wide range multiuser business/scientific systems

Radio Shack Computers

SysiS/U

A Division of Tandy Corporation

300 One Tandy Center
Fort Worth, TX 76102
Model TRS16 Professional & Business PC
RDS
Relational Database Systems, Inc.
2471 East Bayshore Road, Suite 600
Palo Alto, CA 94303

S/U

INFORMAXlFile-it!/C-ISAM on most M68000-based UNIX systems

Relational Technology, Inc.

2855 Telegraph Avenue

Berkeley, CA 94705
(415) 845-1700
INGRES - Relational Database Management for M68000-based UNIX systems
RELMS
Relational Memory Systems, Inc.
1650-B Berryessa Road
San Jose, CA 95133
(408) 729-3011

IXiS

ICEBOXISPICE software development systems

Wide range of Assemblers/Cross Assemblers for Intellec and iPDS
Rockwell International

Electronic Devices Division

PO Box 3669, RC55
Anaheim, CA 92803

licensed second sauce

Chip

341

M68000 Resources

Ryan McFarland Corporation

609 Deep Valley Drive

Rolling Hills Estates, CA 90274
(213 ) 541 -4828
RMCOBOl compiler for M68000-based UNIX systems
SyslSBC/s1X

SBE, I nc.
4700 San Pablo Mnue
Emeryville, CA 94608
(415)652 1805

SBE350/300/250 multiuser systems run Regulus OS (see Alycon)ILEX68

Wide range of M68000based SBCs and software

PROBUG for M68KIO or M68KI 2 or M68CPU (tm )
IEEE796 multibus SBC'slIMb on board RAM

S ignetics/Phillips
811 East Arques Avenue

Chip

Sunnyvale, CA 94086

Licensed second 500rce

SysiSIU

S ilicon Graphics
Mountain View, CA

Graphics Workstation M68000-based UNIX

SysiS

Sinclair Electronics

Cambridge, England
QL (Quantum Leap) MC68008 horne computer under $1,000
S moke S ignal

SysiSIU

Westlake Village, CA
(818) 8899340
UNIX desktop family ~ VARl68K (MC68008

Regulus os) $7,900- 25,000

Southwind Software, Inc.

4520 E. 47th 51. So.
Wichita, KS 67210
(316) 788-5537
IPT (I ntegrated Productivity Tools) for NCR Tower, 1632 and Plexus P135

342

68000, 68010, and 68020 Primer

SRITEK, Inc.
10230 Brecksville Road
Cleveland. OH 44141
(216) 5269433

KlSBC/S/U

MC68000 llersabuslmicrocard to run XENIX on IBM XT @ $1995$2995

including software
Stride Micro

SysiSIU

(formerly Sage Computers)

4905 Energy Way
Reno, NV 89502
(702) 3226868
Stride 400 seriesl multiuser/multiOSNMEbus @ $2,900 $60,000

Sun Microsystems. Inc.

SysiS/U

2550 Garcia Alx!nue

Mountain View, CA 94043

(415) 960 1300
Model 2/250 UNIX IM>rkstation under $10,000 (lOMHz 68010)
Range of multiuser VM systems eg Model 2/120 = 1Mb, Model 21170 = 2
Mb
Graphicsl10 Mb per sec Ethernet

Swift Computers. Ltd.

England

Mirage OS for M68000based multiuser systems

Symbiont Systems. Inc.

SysiS

PO Box 44652
Lafayette, LA 705044652
(318) 984-6545
Series 70/400 = multiuser 12MHz M68000 under MIRAGE OS

System Kontakt
6 Preston Court
Bedford, MA 11730
Cross assm/pascal compiler M68000 and DEC PDP II

SIX

M68000 Resources

Technical Systems Consultants. Inc.

1200 Kent Avenue
West lafayette, IN 47906

343

SIX

UniFLEXImacro and cross assmlbasidClpascal

Tecmar. Inc.

KlS

M68000-based hard disc - links to Apple ImageWriter and modem

Daisy chains on AppleTalk LAN
TeleSoh
10639 Roselle Street
San Diego, CA 92121

SIX

Pascal/ADA software deveiopm.?nt tools for M68000

Texas Instruments. Inc.
PO Box 402430
Dallas, TX 75240
1(800) 527-3500

SysiS/KiU

The Nu Machine = MC68010 10MHz UNIX

32 bit dataladdress 37.5 Mb per sec bandwith NuBus
with Multibus converter! under Motorola System Vl68 OS
UniPres5 Sohware. Inc.
2025 Lincoln Highway
Edison, NJ 08817
(201) 985-8000

SIX/U

EMACS/MINIMACS full screen/multi-window editors for M68000 systems. AMSTERDAM compiler kit = C; Pascal compilers/cross compilers for M68000 and
Intel 8086/8 running under UNIX
UNISOFT Systems
739 Allston Way
Berkeley, CA 94710
(415) 644-1230

UNIX porting for over 90 microcomputers from 60 manufacturers

UniSoft UniPlus + available on most M68000-based systems
ASM68 assemblers and cross assemblers for VAXen, etc.
IPrrcp rlelloorkingirecord and file locking

S/XiU

344

68000, 68010, and 68020 Primer

Victory Computer Systems. Inc.

1610 Berryessa Road
San Jose, CA 95133
(408) 295-7370

SBc/StU

UniSoft UniPlus + NME bus SBe has M68000 + 256K dual-ported RAMI
OS = VRTX
Whitesmiths. Ltd.
PO Box 1132
Ansonia S tation
New York, NY 10023

SIXIU

C/pascal compilers for M68000based UNIX and versados systems

Wicat Systems
Orem, UT

Sys/SIU

UNIX "",!<stations/multiuser systems under UniSoft UniPlus + iMCS OS/I50WS

Xidak. Inc.
530 Oak Grove I've., Suite 10 1
Menlo Park, CA 94025
(415) 324-8745

SIX

MAINSAIL = applications software development language for M68000-based

UNIX systems (and others)

F
ASCII Table Numerical Conversions

I I
I>EC

HEX

X"

X ..

0
I
2
3
4
5
6
7
8
9
10
II
12
13
14
15
16
17
18
19

OCT

Binary

X.

X,

00
01
02
03

00
01
02
03

04
05
06
07
08
09
OA
OB

04
05
06
07
10
II
12
13
14
15
16

OC
00
OE
OF
10
II
12
13

17
20
21
22
23

000 0000
000 0001
000 0010
000 0011
000 0100
000 0101
000 0110
00001 11

000 1000
000 1001
000 1010
000 10 11

000 1100
000 1101

0001110
000 1111
0010000
001000 1
00100 10
00100 11

ASCII

NUL
SOH
STX
ETX
EOT
ENO
ACK
BEL
BS
HT
LF
VT
FF
CR
SO
51
OLE
DCI
DC2
DC3

345

346

DEC
X"
20
21
22
2l

24
25
26
27
28
29
30
31
32

33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61

68000,68010, and 68020 Primer

HEX
X..

OCT
X.

14
15
16
17
18
19
lA
lB
lC
lD
IE
IF
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C

24
25
26
27
30
31
32
33
34
35
36
37
40
41
42
43
44
45
46
47
50
51
52
53
54
55
56
57
60
61
62
63

3D

ASCII

Bina ry

X,
001 0100
00 1 0101
00 1 0 110

0010111
001 1000
001 1001
00 1 1010
001 10 11
001 1100

001 1101
001 1110
001 I1 1I

0100000
0100001
01000 10
0 1000 11

DC4
NAK
SVN
ETB
CAN
EM
SUB
ESC
FS

as

RS
US
SP
"

0100100
0100101

$
%

01001 10
0100111

&

0101000
0101001

(
)

0 101010
01010 11
0101100

0101101
0 101110
0 101111

0110000
0 110001
0 110010

0110011

64

011 0100

65
66
67
70
71
72
73
74
75

0110101
0110110
0110111
0111000
011 1001

0
1
2
3
4
5
6
7
8
9

011 1010
011 1011
011 1100

<

011 1101

ASCII Table -

IDX~~ I
62
63
64

65
66
67
68
69
70
71
72

73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90

91
92
93
94
95

HEX
X"
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
48
4C
4D
4E
4F
50
51
52
53
53
55
56
57
58
59
5A
58
5C
5D
5E
5F

96

60

97
98
99
100
101
102
103

61
62
63
64

65
66
67

OCT

Binary

X,
76

X,
011 1110
011 1111
100 0000

100 0001

100 0010
100 0011

77

100
101
102
103
104
105
106
107
110
III

112
113
114
11 5
116
11 7
120
121
122
123
124
125
126
127
130
131
132
133
134
135
136
137
140
141
142
143
144
145
146
147

ASCII

>
1

100 0101
100 0110

D
E
F

1000100

1000111

100 1000
100 1001

H
I

100 1010
100 101\
100 1100
100 1101
100 1110
100 1111
1010000

K
L
M
N
0

1010001
1010010

P
Q
R

1010011

1010100

T
U

1010101
1010110
101 0111
101 1000
101 1001
101 1010

101 1011
101 1100
101 1101
10 1 1110
10 1 1111
110 0000
110 0001
1100010

X
Y
Z

1100011
1100100
110 0101

a
b
c
d
e

1100110
1100111

f
g

Numerical Conversions

347

348

68000, 68010, and 68020 Primer

IDX~~ I
104
IOl
106
107
108
109
110
III
112
113
114
II I
116
117
11 8
119
120
121
122
123
124
12l
126
127

HEX
X"

OCT

Binary

X,

X,

68
69
6A
68

IlO
III
Il2
Il3
Il4
III
Il6
Il7
160
161
162
163
161
16l
166
167
170
171

6C

60
6E
6F
70
71

n
73

74
7l
76
77

78
79
7A
78
K
70
7E
7F

172
173

174
175

176
177

1101000

ASCII
h

110 1001

1101010
110 1011
1101100
1101101

J
k

1101110

m
n

110 1111
1110000

1110001
1110010
1110011
1110100

III 0101
III 0110
1110111

III 1000
III
III
111
111
III
III
I JJ

1001
]010
1011
11 00
1101
II JO

1111

,q
s
u

Y
l

DEL

Index
memory indirect pre-Indexed, 277
program counter addressing with offset,
159
program C(l.mter and memory indirect with
index, 278-279
program coonler with offset and Index, 163
register direct, 107
relative, 158
ADDX.225
ADEA, 166, 168
AEA. 166, 168
ALU, see Arithmeticllogic unit
AMEA, 166. 168
AND, 14, 173 176
AND!, 181 , 183
Applications software, 37
Artthmeticllogic unit (ALU), 22, 28
ASCII, 10, 186, 193.215. 276, 291: see

ABeD, 229, 291

Absolute address

Ioog, 117
short. 117
PCEA, 166
ADD, 94, 98, 127. 128
ADDA. 127

_ 18
ADDI, 113
AOOQ, 1l0 1l2
Address, 30
byt~ 30
linear; 62

wKlth, 22
Addressing mode(s), 53, 106-109
68020 variants, 274-280
absolute, 11 6-119
address register and memory indirect YJilh

also. Appendix F

index, 275-279
address register direct, 107

ASL, 156, 194

ASR, 157, 194

address register Indirect, 124-126

Assembler, 58
Assembly language, 58

address register indirect post-increment,

128
address register indirect pre-decrement,
133
address register indired with offset, 147

Base displacement. 276

&c, 103, 209, 288
BCD, see Binary coded decimal
BCHG, 2OG-2OS
BCLR, 2()6.208

address register indirect with offset and

Index, 149

dassHicalion, 166
data register direct. 107

BCS, lOS

Immediate, 109-116

BEQ, 98, 103

SF, see Bit fieki
BFCHG, 293

"""""Y, 107
memory indirect posHndexed, 277

34 9

350

Index

BFCLR.293
BFEXTS.293
BFEXTU,293
BFFFO.293
BFFINS.293
BFSET,293
BFTST.293
Binary arithmetic. 68
Binary coded decimal (BCD), 10, 229-233,
291
Binary digits, 46
Binary search, 197, 199
Bit field (BF), 293
Bits, 4-6
BM!. l OS, 152

BNE. l OS
Boole, George, 14
Boolean algebra. 14-16
BPL. 105
BRA. 98. 288
Branch displacement, 100
Branching. 27, 98-106
BSET. 206208
BSR. 142.239.288
BTST.204
Buffer. 121
Bu,
address, 21
contention. 27
control. 21
data, 21. 66
sizes, 62
system, 20

VME. 43
BVS.98. 103
Byte. 89, 74
CAAR, see Cache address register
Cache. 266274
address register (CAAR). 271
control register (CACR) . 271
data. 268
limitations. 272-274
tag, 268
CACR, see Cache control register

CALLM.263
Carry. 81-83
CAS. 289290
CAS2. 289290
CCR, see Condition code ~ster
CEA, 166. 168
Central processing unit (CPU), 1
address space, 268
space function code, 262

CHK. 249. 289

CHK2.289
CLR, I09 11O

CMR 210. 214

CMP2.289
CMPA. 214. 216-217
CMPI. 214, 292
CMPM. 214. 216

Code. 36
Comments, 97
Compatibility. 36
Compiler, 56
Concurrency, 28
Condition code register (CCR), 27. 70, 73,

81.8990. 98
Context, 145-146
Coprocessor. 28
code. 282
command languages, 282
command register, 282
commands, 285
emulation, 283
hardware communiclltion, 280281
nonstandard, 284
on the MC68000. 283
on the MC680lO, 283
software communication, 281
support, 280
cpBcc,285
cpDBcc.285
q>GEN. 282. 285

",RESTORE. 285
opSAVE.285
cpScc,285
cp"ffiAPcc, 285
CPU. see Central processing unit

0...
size codes, 94
size-code, 79
size letter, 66
structures, 109
fetch. 26
DSec. 209. 217-222
OC, see Define constant
DEA. 166. 168
Dectmal. 7
Deromp;IeB. 60
Define constant (DC), 120 122, 161
Define storage (DS), 120-122, 161
Destination function code register (DFC),
262

DFC. see Destination function code register

DIP. see Dual inline package

Index
Directives
OC,12O-122
05, 120-122
ORG, 119-122

Direct memory access (DMA), 34, 36

Disassemblers, 60
~, 153- 155

DIVS, 153, 291

DlVSL,291
DlVU, 153,291
DlVUL. 291
DMA, see Direct memory access
OMAC,36
OS, see Define SIOl1tge
Dual inline package (DIP), 51
Dynamic bus sizing, 266

EA. see Effective address

EBCDIC, 276, 291
EDSAC,53
Effective address (EA), 70, lOS, 147, 166
Emulation, 65, 252
EOR, IS, 176, 182
EORI. 181, 184
Exception vector table, 249-250, 259
Exceplion$,

248

Execute cycle, 27
EXG, 233-235
EXT, 224, 288
EXTB.L. 288
FC, see Function control
FIFO, see Rrsl In first out
Rrmware, 38
Rrst In first out (AFO), 138
Flag, 70
C, 81-83, 89
carry, 73
CCR, 81 , 89
extend, 73
N,89
negative, 73
~,73

SS,88
V. 81-83, 89

X,82.89
Z, 89

zero, 73

351

Function code, 262-264

Function control (FC), 34, 88
Gates. 16-18
HCMOS, see High-density complementary
metal oxide semiconductor

Hexadecimal, 13
High-density complementary metal oxide

semkonduct", (HCMQSJ, 41
Housekeeping, 135

YO, see Input/Output

Index,73
IndMsible,212
Information theory, 3
[nputlOutput (VOl. 21
Instructlon(s),91-93
decode<,6 1
decoding, 26
fetch, 25
formats, 92-94
MC68020 additions, 288-294
MC68020 extensions. 288-294

"",tax. 93
unimplemented. 283
lnterrupl
mask, 87
priaity IewI., 71 , 87
Inverter. 16
JMP, 160-161

JSR. 160, 239

K, 6

Label, 98-106, 118

Language(s)
assembly, 58
machine, 56
high-level, 56

Last in first out (LIFO), 89, 138

LEA, 161
Least significant bit (LSB), 8, 74
LIFO, see Last in first out
LINK, 233, 237-245, 288
Logical operators, 14-16

Aip-flop, 19

L~,8-9,74

Floating-point coprocessor (FPCP), 40

FP, see Frame pointer
FPCP. see Floating-point coprocessor
Frame pointer (FP). 240
Frames, 239-245

Loop counter, 218, 222

Loop mode, 264-265
LSB, see Least significant bit
LSL. 187-194
LSR. 187-194

352

Index

M6800, 235
Machine language, 56
MACSS, see Motorola's a"'vanced computer
system on silicon
Mass memory, 34
Master bit, 285
MC6800, 48, 53
MC68008, 22, 40, 49, 62, 71
MC68012, 40, 49, 62, 265
MC6885I , 281
MC68881 , 40, 266. 281

MEA, 166, 168

Memory, 21
linear, 3223
model, 6266
segmentation , 3223
size, 31
speed , 31
Memory management unit (MMU), 34
Memorymapped 110, 235
Metal oxide semiconductors (MOS), 41
Microcode, 53, 58
Microprocessing unit (MPU), 1-2
Microprogram, 25, 54
Microsequencer, 54
Million instructions per second (MIPS), 27
MIPS, see Million instructions per second
MMU, see Memory management unit
Mnemonic, 58
Models)
1's complement, 11
2's complement. 11 , 79
addressing, see Addressing models)
master, 287
su~, 34 , 88, 285. 287
trace, 73, 88
unSigned, II
u~, 34, 88 , 285. 287
Monitor calls, 251
MOS, see Metal oxide semiconductors
Most significant bit (MSB) , 8, 74
Motorola's advanced computer system on
stlicon (MACSS), 47-49
MOVE, 98
from CCR. 247
from SR. 247
to SR. 247
MCNE.B. 78, 94
MClJE.L. 76
MOJE.W, 77
MOJEA, 126
MKJVEC, 259, 261 , 271 , 283,293

MC/JEM, 136-138

MKJVEp, 233, 235-237

MClJEQ, 114
MOJES, 261 , 283
MPU. see Microprocessing unit
MSB . .see Most significant bit
MULS, 151
Multiprecision, 225-229
Multiplexing. 22
Multiplication, 151 -152
multiprecision, 228
Multiprocessing, 29
Multitasking, 31
MULU, 151

NAND, 15
Nanocode, 54. 58
Nanosecond. 20
NBCD. 230. 232. 291
NEG, 222-223
NEGX, 226
Nesting. 89, 146
Nibble, 89
N~ 172
NOT. 14. 173 174
Octal, 13
Opcode, 93
ap.,a"", 93
destination, 94
scurce, 94
Operating system (OS), 31 . 37-38
OR. 14, 176, 179
ORG, 119, 160
ORI, 18 1
OS, .see Operating system
Outer displacement. 277
Owrl\ow, 82-83
C>wrlay., 31
PACK. 291
Package. 36
Pagels), 34. 253
fault, 34
Parity, 193
PC. see Program counter
PEA. 16 1
Pinouts, 51 52
Pins. number of. 51
Pipelining, 28
Portability, 36
Prefetch, 28
_lege, 88, 245-248, 261
Processor state word (PSW), 70

Index
Program(s)

RTR. 146

position independem, 158

reIocatable, 158
security. 60
,.jf-modHy,,,", 165
Program counter (PC), 25, 7().71, 100, 158

RTS, 143, 239

Programming

levels, 55-61
structured, 211 , 219
Pseucb-op codes, 119
PSW, see Processor state 1,\,Q'd

353

.S modifier, 194
SEW:D, 230, 233. 291
SCALE, 276

Sec, 208-211
Semophoreo. 29. 212
Service calls, 251
SFC, see Source function code register
Shift count, 188
Shifts

RAM,

see Random access memory

Random access memory (RAM)_ 21. 29

disk, 35
\datiltty. 34
Random logic. 53

Range, 96
REA, 166

Read c.vc\e, 22
Read-modify-write, 212
RegiSter(s), 29
PCR. 271
address, 70-75, 83-84

arithmetic, 79
CAAR. 271

cache, 271
data. 7075
destination, 77

OFC. 262
index, 149
model. 68-75

number,51
range, 11 12, 79-81
segmentation, 32

arithmetic, 156-157, 194-197

1ogic:a\, 187 194
Sign-bit, 12,79
extension, 84-86
Software engineering, 38
Sou.rce function code register (SFC), 262

SP, see Stack pointer

SR, see Status register
SSp, see Supervisor stack pointer
Stack(s), 70, 89, 138 141
popping, 138
pulling, 138
pushing, 138
user,246
Stack pointer (SP), 70-71, 89, 140
supervisor, 146
"'" 73
Status register (SRJ, 70, 73. 84, 185, 247
S~286

String manipulation. 130

SUB, 115
SUBA, 128, 216
SUBf. 115

SFC, 262

SUBQ, 1I5

size-codes, 76
source, 77
status, 84, 87
sym~ 74
type. 51

Subroutine, 141-145

width, 22
RESET, 286

Resource, 212
ROl.2oo
ROM. 21

ROO. 200
RORG_ 160-161

Rotates, 200-204
ROXL, 201
ROXR, 201
RTf, 249. 256
RTM.263

SUBX.226

Supervisor data space, 263, 268

Supervisor program space, 263, 268
Supervisor stock pointer (SSP), 146
SWAP, 153, 203,233
Swapping, 31, 255
System(s)
byte, 84

clock, 20
pointer, 89
software, 37
stacks,89

TAS, 212-214, 28'<

Trace bits, 278-280

354

Index

Tracing, 278-280

1RAP. 246, 249

User stack point~ 73

USp, see User stack pointer

""""",",, 154

zero divide, 154

TRAPcc, 292
Traps, 88
TRAP\/, 154,249
TST, 131 , 292
Turing, Alan M., 14

VBR, see \kctor base register

Vector base register (VBR), 258-261
Very large-scale Integration (VLS!), 4041
Virtual machine, 252, 256-258
Virtual memory (VM), 34-35, 253256
VLSI, see Very largescale integration
VM. see Virtual memory

UNLK, 233. 237-245

UNPK, 291

\-Vi.lkes. Maurice. 53

User data space, 263. 268

User program space. 263. 268

Write qde, 22

1M>l. 8-9. 74

MORE
FROM
SAMS
o

MaclntoshTIII Programming
Techniques - MlcrosofP BASIC 2.0
An IntennedLatalactvanced IeYeI book on programming
techniques in Microsoft BASIC. Allows programmefS to
access the ulllit!es in Macintosh's ROM tool kit.
Contains many sample programs with emphasis on
graphics on the Macintosh, file access, creating and
using windows, and learning to create custom p4J1I
down menus. David C. W!Ilen.

ISBN ().6]2.22411-9 . . . . .... . ....... . ...... .. $22.95

Inside the Amiga

This excellent guide lor Commodore's new

68lX).based machine emphasizes both the Internal
architecture and programming capabilities 01 this stateolth&-art graphics computlW". Many of the programming
leatures are highlighted with C examples.
The Waite Group.

ISBN ().61222468-2 ......................... $19.95

Microcomputer Projects with the 68000

A compretlensive guide to the coostructloo of a

o AI Techniques and Languages

68CXX).based microcomputer and detailed description of

A hands-on introduction to the hottest topic In

microcomputers-anilicialinleiligeoce. SUmmatizes

Motorola* 's new chip. learn about the chip's speed

and ability to address large amounts 01 memory.
assembly language programming, Tiny C, as well as
Interlacing applications. William Barden.

Ihree languages commonly used lor AI programming:

lao<>, Lisp, and Prolog. Several programs are written in
easyto-leam Logo for fh!l' Maclnl osh. Many 01 these AI
programs appear In an appendix In Lisp form for other
systems. Prolog-the most common WOf1d.w\de AI
language-is also explained. l ogo listings are
annotated according to the purpose 01 the code and
the relationship 01 the AI concepts being discussed.
Dan Shafer.

ISBN <HIn-22447-X . . . . . . . . . . . . .

. .... $24.95

C Programming Techniques for the

Macintosh
This Intermediate level programming book provides a
thOrough undeBtandlng of the C programming
language as It Is uniquely designed for the Macintosh.
Allows you to access over 500 ROM toot kit routines,
and shows you how to use the routines to c\eYeIop a
programming application In C. Eyes and Medneiks.

ISBN ().67222461-5 ......... S1a95

MacPascal Programming Techniques

An excellent book for beginning and Intennediate

Pascal programmers. Guides you In using the
Innovative Pascal language developed by Think
Technologies lor the Macintosh. DIscusses In detail
how to access the ROM toot kit , and how to create
applications and programs In Pascal.
cassidy and Stelnberg.

ISBN().672-22440-2 ...... . .... .

.' . . S15.95

ISBN ().61222458-5 ................. $21.95

16-Bit Microprocessors

You'll lOOk lar and wide to lind the comparison

information on the six 1(;.blt CPUs contained In th is
book. Full textual coverage and benchmatk
comparisons are presented for the alB6. Z8000 family,
LSI 11 , 9900, 68000, and the NSl6000 fami ly.
TItus. Titus, Baldwin, Hubln and ScanlOn.

ISBN ().67221fl)5.4 . . . . . .

. ..... SI5.95

Printer Connections Bible

Atlastl A book that teaches non-technlCal people how

to connect a computer to a printer. Covers major
computerfprlnter combinations. supplies detailed
diagrams 01 required cables. DIP.swltch lng settings, etc.
The \:loc)I( Is graphically oriented with diagrams
Illustrating numerous printer/computer combinations.
House and Marble.

ISBN ().6J2.22406-2 ................ $16.95

Modem Connections Bible

Put what where? This comprehensive volume
describes modems and how they work. Detailed
diagrams explain how to hook up ma}or brands o f
microcomputers. Find out what happens with the
R&232C interface. A must lor microcomputer users
and technicians. Curtis and MaJhor.

ISBN ().6J2.2244&X ............... $16.95

Macintosh User's Guide

Computer Dictionary (4th Edition)

The introductory section of this complete user's guide

contains a comparison with 5 othel" bestselling mlcms.
What fOllOws is an extremely well-written, wellillustrated, and at1racHY9Iy presented explanation of
lundamental and adVanced applications 01 the
Macintosh. You'll want It right next to your Mac.
Gordon McComb.

Contains OYer 12,OtXlentr\eS with 1.000 new temlS,

most of which pertain to robotics, artificial Intelligence.
and lactory automation. Inctudes definitiOns, acronyms,
abbreviations, and extensive cfOSSofeferenclng. A must
for teachers, scientists, computer person nel. engil""l88B.
students, and people In business. Charles J. Sippi.

ISBN ().6722232S-7 ............. $16.95

ISBN ().6n222()5..X ......................... $24.95

o The 68000: Principles and Programming

The Motorola 68OCJO Is Ihe first 16-b1l microprocessor to
have a 32-b1t Internal archlteclUre. Increasing Interest In
ls.t>it chips makes an understanding of this CPU
essenlial fOf microcomputer professionals and
hobbyists alike. Subjects covered Include Motorola's
assembler. 6IJXX) Instruction set, pinouts,
and Interfacing. An excellent treatment of an Important
subject. leo J. Scanlon,
CfQSSoffi8CfO

ISBN~n.21~

, .... , ... , ... ,.....

.$16.95

6801 , 68701 , and 6803 Microcomputer

Programming and Interfacing
This book will provide you with a detailed presentation
01 the 5801 slngle-chlp microcomputer and Its varIOus
versions, the 68701 and 6E03. 110 conliguratloos,
operating modes, ROM (EPROM) timer, serial
communications interface. and dlgltaJ.to.analog
converters are discussed. RevIew Questions and
answers are provided at the end of each chapter.
tncludeS three appendices IOf easy ref8fence.
Andrew C. Staugaard, Jr.
tSBN~n.2172&O

Mastering Serial Communications

ThIs Intermedlatafactvanced book Is written IOf

technicians and programmers Interested In
asynchronous aerial communications. Part One
explains the history and technical details 01
asynchronous communications. while Part Two
addresses the specifics of the technical programmer
with an emphasis on popular UARTs and psetJdo.
assembly language. Joe campbell.
ISBN ().6722245().X ......................... $21.95

......................... $14.95

The Local Area Networtl; Book

Defines and discusses localized comput8f netwonts as

a versatile means 01 oommunication. You'll learn how
netWOfXs developed and what local netWOfXs can do;
what's necessary in components, techniQues,
standards, and protocols; now some LAN products
wor1< and how real LANs operate: and how to plan a
network from scratCh. E. G. Broonef.
ISBN (Hin22254X .......................... $7.95

Look for these sams Books at your local bookstore.

To order direct, call 8:X>-42SSAMS or fill out the form below.

_..............................................................................................................................................................................
..
Please send me the books whose titles and numbers I have listed below.
Name (p lw$. ptlnr) _ _ _ _ _ _ _ _ _ _ _ __

Address _ _ _ _ _ _ _ _ _ _ _ _ __

Cily _ _ _ _ _ _ _ _ _ _ _ __
StatelZlp _ _ _ _ _ _ _ _ _ _ _ __

--;:====:-::c===,-__
_
'or

Signature _ _

(1"I1IirH

Enclosed Is a check Of money order IOf $ _ _ _ __

(Plus $2.00 postage and
Charge my: 0
Account No.

VISA 0

handling).
MasterCard

ExP'~'..
~I~Ion~OO~"~;=:;=:;=:;::=;

I I I I II I I I II I I I 1,---1'---'-~

~tN"

Mail 10: Howard W . Sarns &

c.'II Pl/n::"-...)

Co., Inc.

Dept. OM
4300 West C2nd Street
Indianapolis, IN 46268