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Experiment - 1

AIM: To design and implement half adder.

DESIGN: VHDL code for Half-Adder was written and simulation waveform was
generated. The truth table is as follows:

Ao Bo So Co
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

BLOCK DIAGRAM :

LOGIC DIAGRAM :
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VHDL Code :

library ieee;
use ieee. std_logic_1164.all;
entity half_adder is
port(a0,b0:in std_logic; c0,s0:out std_logic);
end half_adder;
architecture and_2 of half_adder is
begin
s0 <= a0 xor b0;
c0 <= a0 and b0;
end and_2;
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Experiment – 2
AIM: To design and implement full adder.

DESIGN: VHDL code for Full-Adder was written and simulation waveform was
generated. The truth table is as follows:

Ak Bk Ck-1 Sk Ck
0 0 0 0 0
0 1 0 1 0
1 0 0 1 0
1 1 0 0 1
0 0 1 1 0
0 1 1 0 1
1 0 1 0 1
1 1 1 1 1

BLOCK DIAGRAM :

LOGIC DIAGRAM
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VHDL Code :

library ieee;
use ieee.std_logic_1164.all;
entity fulladder is
port (ak,bk,ck-1:in std_logic; sk,ck: out std_logic);
end fulladder;
architecture fulladder of fulladder is
begin
sk<=ak xor bk xor ck-1;
ck<=(ak and bk)or (bk and ck-1) or (ck-1 and ak);
end fulladder;
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Experiment – 3
AIM: - To design and implement 8:1 Multiplexer.

DESIGN: - VHDL code for 8:1 Multiplexer was written and simulation waveform was
generated. The truth table is as follows:

O/P = I0 + I1 + I2 + I3 + I4 + I5 + I6 + I7

BLOCK DIAGRAM :
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VHDL Code :

library ieee;
use ieee.std_logic_1164.all;
entity mux8 is
port(x0,x1,x2,x3,x4,x5,x6,x7,s0,s1,s2:in bit;y:out bit);
end mux8;
architecture mux of mux8 is
begin
process(x0,x1,x2,x3,x4,x5,x6,x7,s0,s1,s2)
begin
if(s2='0'and s1='0'and s0='0')then
y<=x0;
elsif(s2='0'and s1='0'and s0='1')then
y<=x1;
elsif(s2='0'and s1='1'and s0='0')then
y<=x2;
elsif(s2='0'and s1='1'and s0='1')then
y<=x3;
elsif(s2='1'and s1='0'and s0='0')then
y<=x4;
elsif(s2='1'and s1='0'and s0='1')then
y<=x5;
elsif(s2='1'and s1='1'and s0='0')then
y<=x6;
elsif(s2='1'and s1='1'and s0='1')then
y<=x7;
end if;
end process;
end mux;
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Experiment – 4
AIM: - To design and implement 3:8 Decoder.

DESIGN: - VHDL code for 3x8 Decoder was written and simulation waveform was
generated. The truth table is as follows:

LOGIC DIAGRAM
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VHDL Code :

library ieee;
use ieee.std_logic_1164.all;
entity decoder3X8 is
port (A,B,C:in bit; I:out bit_vector(0 to 7));
end decoder 3X8;
architecture dec_dataflow of decoder 3X8 is -- Architecture Declaration
begin
I(0)<=(not C)and (not B)and (not A);
I(1)<=(not C)and (not B)and A;
I(2)<=(not C)and B and (not A);
I(3)<=(not C)and B and A;
I(4)<=C and (not B)and (not A);
I(5)<=C and (not B) and A;
I(6)<=C and B and (not A);
I(7)<=C and B and A;
end dec_dataflow;
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Experiment – 5
AIM: To design and, implement 4-bit comparator.

DESIGN: VHDL code for 4-bit comparator was written and simulation waveform was
generated. The truth table is as follows:

BLOCK DIAGRAM :
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VHDL Code :

library ieee;
use ieee.std_logic_1164.all;
entity comparator is
port(A,B: in std_logic_vector(3 downto 0);
less :out std_logic;
equal : out std_logic;
greater : out std_logic);
end comparator;
architecture comp of comparator is
begin
process(A,B)
begin
if (A<B) then
less <= '1';
equal <= '0';
greater <= '0';
elsif (A=B) then
less <= '0';
equal <= '1';
greater <= '0';
else
less <= '0';
equal <= '0';
greater <= '1';
end if;
end process;
end comp;
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Experiment – 6
AIM: - To design and, implement a BCD to seven-segment decoder.

DESIGN: - VHDL code for a BCD to seven-segment decoder was written and simulation
waveform was generated. The truth table is as follows:

BLOCK DIAGRAM:
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VHDL Code:

library ieee;
use ieee.std_logic_1164.all;
entity seven_seg is
port(bcd:in bit_vector(0 to 3);
led:out bit_vector(0 to 6));
end seven_seg;
architecture seg of seven_seg is
begin
led<="1111110" when bcd="0000" else
"0110000" when bcd="0001" else
"1101101" when bcd="0010" else
"1111001" when bcd="0011" else
"0110011" when bcd="0100" else
"1011011" when bcd="0101" else
"1011110" when bcd="0110" else
"1110000" when bcd="0111" else
"1111111" when bcd="1000" else
"1111011" when bcd="1001" else
"0000000" ;
end seg;
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Experiment – 7
AIM: To design and implement a 1:8 demultiplexer.

DESIGN: - VHDL code for a 1:8 demultiplexer was written and simulation
waveform was generated. The truth table is as follows:

S2 S1 S0 X7 X6 X5 X4 X3 X2 X1 X0
0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 1 0 0 0 0 0 0 1 0 0
0 1 1 0 0 0 0 1 0 0 0
1 0 0 0 0 0 1 0 0 0 0
1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 0 0

BLOCK DIAGRAM :

D0

D1

D2

INPUT D3

DATA D4

D5

D6

D7

S0 S1 S2
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VHDL Code:

library ieee;
use ieee.std_logic_1164.all;
entity demux8 is
port(data,s0,s1,s2:in bit;x0,x1,x2,x3,x4,x5,x6,x7:out bit);
end demux8;
architecture demux of demux8 is
begin
process(data,s0,s1,s2)
begin
if(data='1')then
if(s2='0'and s1='0'and s0='0')then
x0<=data;
elsif(s2='0'and s1='0'and s0='1')then
x1<=data;
elsif(s2='0'and s1='1'and s0='0')then
x2<=data;
elsif(s2='0'and s1='1'and s0='1')then
x3<=data;
elsif(s2='1'and s1='0'and s0='0')then
x4<=data;
elsif(s2='1'and s1='0'and s0='1')then
x5<=data;
elsif(s2='1'and s1='1'and s0='0')then
x6<=data;
elsif(s2='1'and s1='1'and s0='1')then
x7<=data;
end if;
end if;
end process;
end demux;
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Experiment – 8
AIM
AIM: To design and iimplement
mplement serial in parallel out (shift register) of 4 bit data
data.

DESIGN
DESIGN:: - VHDL code fo
forr serial in parallel out was written and simulation waveform was generated
generated.

BLOCK DIAGRAM :

LOGIC DIAGRAM :
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VHDL Code :

library ieee;
use ieee.std_logic_1164.all;
entity sipo1 is
port(d,pr,cr,clk: in bit;q0,q1,q2,q3: buffer bit);
end sipo1;
architecture sipo of sipo1 is
begin
process(pr,cr,clk)
begin
if(pr='1' and cr='1' and clk='1') then
q0<=d;
q1<=q0;
q2<=q1;
q3<=q2;
elsif(pr='1' and cr='0') then
q0<='0';
q1<='0';
q2<='0';
q3<='0';
elsif(pr='0' and cr='1') then
q0<='1';
q1<='1';
q2<='1';
q3<='1';
elsif(pr='0' and cr='0') then
q0<='1';
q1<='1';
q2<='1';
q3<='1';
end if;
end process;
end sipo;
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Experiment – 9
AIM
AIM: To design and implement serial in serial out (shift register) of 4 bit data
data.

DESIGN
DESIGN:: - VHDL code fo
forr serial in serial out was written and simulation waveform was generated
generated.

BLOCK DIAGRAM :

LOGIC DIAGRAM :
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VHDL Code :

library ieee;
use ieee.std_logic_1164.all;
entity siso is
port(d,pr,cr,clk:in bit;z:out bit);
end siso;
architecture siso of siso is
signal q0,q1,q2:bit;
begin
process(d,pr,cr,clk)
begin
if(pr='1' and cr='1' and clk='1')then
q0<=d;
q1<=q0;
q2<=q1;
z<=q2;
elsif(pr='1' and cr='0')then
q0<='0';
q1<='0';
q2<='0';
z<='0';
elsif(pr='0' and cr='1')then
q0<='1';
q1<='1';
q2<='1';
z<='1';
elsif(pr='0' and cr='0')then
q0<='1';
q1<='1';
q2<='1';
z<='1';
end if;
end process;
end siso;
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