Session - 06 - Encoder Decoder
Session - 06 - Encoder Decoder
23EC1202
DIGITAL DESIGN & COMPUTER ARCHITECTURE
Session - 06
INSTRUCTIONAL OBJECTIVES
LEARNING OUTCOMES
Boolean Expression: 𝑌2 = 𝐼7 + 𝐼6 + 𝐼5 + 𝐼4 𝑌1 = 𝐼7 + 𝐼6 + 𝐼3 + 𝐼2 𝑌0 = 𝐼7 + 𝐼5 + 𝐼3 + 𝐼1
APPLICATIONS OF ENCODER
Encoder Navigation
Compass Binary output
Direction
Q2 Q1 Q0
North 0 0 0
North-East 0 0 1
East 0 1 0
South-East 0 1 1
South 1 0 0
South-West 1 0 1
West 1 1 0
North-West 1 1 1
INTRODUCTION TO DECODER
X Y Z F7 F6 F5 F4 F3 F2 F1 F0
0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 1 0 0 0 0 0 0 1 0 0
0 1 1 0 0 0 0 1 0 0 0
1 0 0 0 0 0 1 0 0 0 0
1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 0 0
APPLICATIONS OF DECODER
𝒀𝟎 Addition
𝒀𝟏
Subtraction
0 𝑪𝟎 𝒀𝟐
Multiplication
0 𝒀𝟑
𝑪𝟏 Decoder Division
𝒀𝟒
AND
0 𝑪𝟐 𝒀𝟓
OR
𝒀𝟔
NOT
𝒀𝟕
XOR
EN
Implementation of Boolean Function using Decoder
S C
TRADITIONAL ENCODE-DECODE
MODEL OF COMMUNICATION
SELF-ASSESSMENT QUESTIONS
A. 2
B. 3
C. 4
D. 8
SELF-ASSESSMENT QUESTIONS
4. In a 2-to-4 Decoder, if the input is 01, which output line will be active?
A. Output 0
B. Output 1
C. Output 2
D. Output 3
TERMINAL QUESTIONS
Reference Books:
1. Computer System Architecture by M. Moris Mano
2. Fundamentals of Digital Logic with Verilog HDL by Stephen Brown and ZvonkoVranesic