DVD 860

DVD PLAYER

SERVICE MANUAL

1. GENERAL DESCRIPTION
1.1 ES6008/ES6018
The ES6008/ES6018 Vibratto DVD processor is a single-chip MPEG video decoding chip
that integrates audio/video stream data processing, TV encoder, four video DACs with
Macrovision. copy protection, DVD system navigation, system control and housekeeping
functions.
The Vibratto DVD processor is built on the ESS proprietary dual CPU Programmable
Multimedia Processor (PMP) core consists of 32-bit RISC and 64-bit DSP processors and offers
the best DVD feature set.
These features can be listed as follows:
General Features:

Single-chip DVD processor based on ESS proprietary dual CPU PMP core.

Integrated NTSC/PAL encoder.

Four integrated 10-bit video DACs.

DVD-Video, VCD 1.1, 2.0, and SVCD

Interface for ATAPI devices and A/V DVD loaders.

Interface for Compact Flash, Memory Stick and SmartMedia cards.

Direct interface of 8- or 16-bit SDRAM up to 128-Mb capacity.

Direct interface for up to four banks of 8-/16-bit EPROM or Flash EPROM for up to 16-MB
capacity.

Video Related Features:

Macrovision 7.1 for NTSC/PAL interlaced video.

Simultaneous composite video and S-video outputs, or composite and YUV outputs, or
composite and RGB outputs.

8-bit CCIR 601 YUV 4:2:2 output.

On-Screen Display (OSD) controller with 3-bit blending provides display with 256 colors in 8
degrees of transparency.

Subpicture Unit (SPU) decoder supports karaoke lyric, subtitles, and EIA-608 compliant Line
21 Captioning.

Audio Related Features:

Dolby Digital (AC-3) and Dolby Pro Logic.

Dolby Digital S/PDIF digital audio output.

High-Definition Compatible Digital. (HDCD) decoding.

Dolby Digital Class A and HDCD certified.

SRS TruSurround ..

CD-DA.

MP3.

Karaoke.

1.2 MEMORY
1.2.1 System SRAM Interface
The system SRAM interface controls access to optional external SRAM, which can be
used for RISC code, stack, and data. The SRAM bus supports four independent address spaces,
each having programmable bus width and wait states. The interface can support not only SRAM,
ROM/EPROM and memory-mapped I/O ports for standalone applications are also supported.
1.2.2 DRAM Memory Interface
The Vibratto provides a glueless 16-bit interface to DRAM memory devices used as video
memory for a DVD player. The maximum amount of memory supported is 16 MB of Synchronous
DRAM (SDRAM). The memory interface is configurable in depth to support 128-Mb addressing.
The memory interface controls access to both external SDRAM or EDO memories, which can be
the sole unified external read/write memory acting as program and data memory as well as
various decoding and display buffers.

1.3 DRIVE INTERFACES

The Vibratto supports the AT Attachment Packet Interface (ATAPI), Integrated Drive
Electronics (IDE), and other parallel and serial port interfaces used by many types of DVD
loaders. These interfaces meet the specifications of many DVD loader manufacturers. An ATAPI
drive is connected via the standard 34 pin dual row PC style IDE header

1.4 FRONT PANEL

The front panel is based around an Futaba VFD and a common NEC front panel
controller chip, (uPD16311). The ES6008/ES6018 controls the uPD16311 using
several control signals, (clock, data, chip select). The infrared remote control signal is
passed directly to the ES6008/ES6018 for decoding.

1.5 REAR PANEL

A typical rear panel is included in the reference design. This rear panel supports:
- Six channel or two channel audio outputs
- Optical and coax S/PDIF outputs.
- Composite, S-Video, and SCART outputs
The six-video signals used to provide CVBS, S-Video, and RGB are generated by the
ES6008/18s internal video DAC. The video signals are buffered by external circuitry.

Six channel audio output by the ES6018 in the form of three I 2S (or similar) data
streams. The S/PDIF serial stream is also generated by the ES6008/18 output by the
rear panel. A six channel audio DAC (AK4356) are used for six channel audio output
with ES6018, and similarly one AK4382A Audio DAC is used for two channel audio
output with ES6008 or ES6018.

2. SYSTEM BLOCK DIAGRAM and ES6008/18 PIN DESCRIPTION

2.1 ES6008/18 PIN DESCRIPTION

2.1 SYSTEM BLOCK DIAGRAM

A sample system block diagram for the ES6008/18 Vibratto DVD player board design is
shown in the following figure:

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Note: Audio input through Audio ADC is used only for the case of the
karaoke and this device currently does not support the karaoke option.

3. AUDIO OUTPUT
The ES6008 supports two-channel analog audio output while ES6018 supports sixchannel analog audio output. In a system configuration with six analog outputs, the
front left and right channels can be configured to provide the stereo (2 channel)
outputs and Dolby Surround, or the left and right front channels for a 5.1 channel
surround system.
The ES6008 also provides digital output in S/PDIF format. The board supports both
optical and coaxial S/PDIF outputs.

4 AUDIO DACS

The ES6008/18 supports several variations of an I2S type bus, varying the order of the
data bits (leading or no leading zero bit, left or right alignment within frame, and MSB
or LSB first) is possible using the ES6008/18 internal configuration registers. The I 2S
format uses four stereo data lines and three clock lines. The I 2S data and clock lines
can be connected directly to one or more audio DAC to generate analog audio output.
The two-channel DAC is an AKM AK4382A. The DACs support up to 192kHz sampling
rate.
The outputs of the DACs are differential, not single ended so a buffering circuit is
required. The buffer circuits use National LM833 op-amps to perform the low-pass
filtering and the buffering.

5 VIDEO INTERFACE
5.1 Video Display Output
The video output section controls the transfer of video frames stored in memory to the internal TV
encoder of the Vibratto. The output section consists of a programmable CRT controller capable of
operating either in Master or Slave mode.
The video output section features internal line buffers which allow the outgoing luminance and
chrominance data to match the internal clock rates with external pixel clock rates, easily

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facilitating YUV4: 2:2 to YUV4: 2:0 component and sample conversion. A polyphase filter
achieves arbitrary horizontal decimation and interpolation.
Video Bus
The video bus has 8 YUV data pins that transfer luminance and chrominance (YUV) pixels in
CCIR601 pixel format (4:2:2). In this format, there are half as many chrominance (U or V) pixels
per line as luminance (Y) pixels; there are as many chrominance lines as luminance.
Video Post-Processing
The Vibratto video post-processing circuitry provides support for the color conversion, scaling,
and filtering functions through a combination of special hardware and software. Horizontal upsampling and filtering is done with a programmable, 7-tap polyphase filter bank for accurate
non-integer interpolations. Vertical scaling is achieved by repeating and dropping lines in
accordance with the applicable scaling ratio.
Video Timing
The video bus can be clocked either by double pixel clock and clock qualifier or by a single pixel
clock. The double clock typically is used for TV displays, the single for computer displays.
Video Interface Registers
VID_SCN_HSTART
The write-only Video Screen Horizontal Start Address register contains the 13-bit horizontal pixel
starting address of the active video display.
VID_SCN_HEND
The write-only Video Screen Horizontal End Address register contains the 13-bit horizontal pixel
ending address of the active video display.
VID_SCN_VSTART
The write-only Video Screen Vertical Start Address register contains the 13-bit vertical scan line
starting address of the active video display.
VID_SCN_VEND
The write-only Video Screen Vertical End Address register contains the 13-bit vertical scan line
ending address of the active video display.
VID_SCN_VERTIRQ
The write-only Video Screen Vertical Line Interrupt register is selectable by software and contains
the line in which a vertical interrupt will occur. Line 0 is the top of the screen, as defined by the
leading edge of the VSYNC pin. Typically, an interrupt is set either just before or just after the
active video display.
VID_SCN_HBLANK_START
The write-only Video Screen Horizontal Blanking Interval Start Address register contains the 13bit starting address of the horizontal blanking interval for the active video display.
VID_SCN_HBLANK_STOP
The write-only Video Screen Horizontal Blanking Interval End Address register contains the 13-bit
ending address of the horizontal blanking stop interval for the active video display.
VID_SCN_VBLANK_START
The Video Screen Vertical Blanking Interval Start Address register contains the 13-bit starting
address of the vertical blanking interval for the active video display.
VID_SCN_VBLANK_STOP

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The write-only Video Screen Vertical Blanking Interval Stop Address register contains the 13-bit
ending address of the vertical blanking stop interval for the active video display.
VID_SCN_HSYNCWIDTH
The write-only Video Screen Horizontal Sync Width Pulse register contains the 13-bit value of the
horizontal sync pulse width for the active video display. This register is needed only if sync
direction is output
VID_SCN_HSYNCPERIOD
The write-only Video Screen Horizontal Sync Period register contains the 13-bit value for the
period of the horizontal sync pulse used by the active video display. It is needed only if sync
direction is output.
VID_SCN_VSYNCPERIOD
The write-only Video Screen Video Sync Period register contains the 13-bit value for the period of
the vertical sync pulse used by the active video display. This register is needed only if sync
direction is output.
VID_SCN_VSYNCPIXEL
The write-only Video Screen Vertical Sync Pixel register defines which pixel VSYNC will change
on for the active video display. The number of pixels delayed from HSYNC that VSYNC will
change on either the rising or falling edge of VSYNC. This register is needed only if sync direction
is output
VID_SCN_VSYNCWIDTH
The write-only Video Screen Vertical Sync Pulse Width register defines the width of the 6-bit
vertical sync pulse. It is needed only if sync direction is output
VID_SCN_VERTCOUNT
The read-only Video Screen Verital Counter register contains the current line of the vertical
counter, and starts its counting at VSYNC line 0. This register is typically used for testing only.
VID_SCN_HORIZCOUNT
The read-only Video Screen Horizontal Counter register contains the current pixel of the
horizontal counter, and starts its counting at HSYNC pixel 0. This register is typically used for
testing only.
VID_SCN_COUNTER_CTL
The write-only Video Screen Counter Control register contains counter control bits for the inverted
blank sync, inverted horizontal sync, and inverted vertical sync functions. This register initializes
to 0x00 after reset.
VID_SCN_OUTPUTCNTL
The Video Screen Output Control register contains the control logic used to control the clamping
and filtering characteristics of the signal being output to the video display.
VID_SCN_ITERFACECNTL
The Video Screen Interface Control register contains the control logic used to determine the
signal output characteristics to the video display.
VID_SCN_RESETS
The Video Screen Reset register contains the control logic for reset events, including the reset
pan and scan, horizontal filtering and DMA enabling functions. This register is set to 1 on reset.
VID_SCN_STATUS

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The Video Screen Status register contains the status bits for the video section.
VID_SCN_OSD_HSTART
The OSD Video Screen Horizontal Start Address register contains the horizontal starting address
value for the OSD, as referenced from the active display window.
VID_SCN_OSD_HEND
The OSD Video Screen Horizontal End Address register contains the 13-bit horizontal ending
address value for the OSD, as referenced from the active video display.
VID_SCN_OSD_VSTART
The OSD Video Screen Vertical Start Address register contains the 13-bit vertical starting address
value for the OSD, as referenced from the active video display.
VID_SCN_OSD_VEND
The OSD Video Screen Vertical End Address register contains the 13-bit vertical ending address
value for the OSD, as referenced from the active video display.
VID_SCN_OSD_MISC
The OSD Video Screen Miscellaneous register contains the control logic and status bits for the
OSD controller.
VID_SCN_OSD_PALETTE
These 16 registers contain the OSD palette.

6 SDRAM MEMORY
The memory bus interface generates all the control signals to interface with external memory. The
Vibratto supports different configurations using the memory configuration bits SDCFG[1:0] (bits
12:11), the SD8BIT bit (bit 14), and SD64M bit (bit 15) in the BUSCON_DRAM_CONTROL
register. Configurations can be implemented in many ways. The following table lists the typical
SDRAM configurations used by the Vibratto.

Typical SDRAM Configurations:

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The memory interface controls access to both external SDRAM or EDO memories, which can be
the sole unified external read/write memory acting as program and data memory as well as
various decoding and display buffers. At high clock speeds, the Vibratto memory bus interface
has sufficient bandwidth to support the decoding and displaying of CCIR601 resolution images at
full frame rate.

7 FLASH MEMORY
The decoder board supports AMD class Flash memories. Currently 4 configurations
are supported:
FLASH_512K_8b
FLASH_1024K_8b
FLASH_512Kx2_8b
FLASH_512Kx2_16b
The Vibratto permits both 8- and 16-bit common memory I/O accesses with a removable storage
card via the host interface.

8 SERIAL EEPROM MEMORY

An I2C serial EEPROM is used to store user configuration (i.e. language
preferences, speaker setup, etc.) and software configuration.. Industry standard
EEPROM range in size from 1kbit to 256kbit and share the same IC footprint and
pinout. The default device is 2kbit, 256kx 8, SOIC8 SGS Thomson ST24C02M1 or
equivalent.

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9 ATA/IDE LOADER INTERFACE

The host interface can directly support ATAPI devices such as DVD drives or I/O
controllers. PIO modes 0 through 4 are supported. The ATA/IDE interface can directly control two
devices through the use of the HCS1FX# and HCS3FX# signals. The ATA/IDE interface of the
Vibratto uses a command execution protocol that allows the operation of audio-CD and DVD
loaders to coexist on the same type of interface cable that most computers use for CD loaders
and hard disk drives.
Note: The decoder board supports the standard ATAPI electrical connections,
but the software protocol within the drive is not always supported according to ATAPI
specifications. Custom software may need to be developed and tested to support
ATAPI drives from different manufacturers.

10 AUDIO INTERFACE AUDIO

COMPONENT CONFIGURATION

SAMPLING

RATE

AND

PLL

The ES6008/18 Vibratto audio mode configuration is selectable, allowing it to interface

directly with low-cost audio DACs and ADCs. The audio port provides a standard I 2S interface
input and output and S/PDIF (IEC958) audio output. Stereo mode is in I 2S format while six
channels Dolby Digital (5.1 channel) audio output can be channeled through the S/PDIF. The
S/PDIF interface consists of a bi-phase mark encoder, which has low skew. The transmit I 2S
interface supports the 128, 192, 256, 384, and 512 sampling frequency formats, where sampling
frequency Fs is usually 32 kHz, 44.1 kHz, 48 kHz, 96 kHz, or 192 kHz. The audio samples for the
I2S transmit interface can be 16, 18, 20, 24, and 32-bit samples.
For Linear PCM audio stream format, the Vibratto supports 48 kHz and 96 kHz. Dolby
Digital audio only supports 48 kHz. The ES6008/18 Vibratto incorporates a built-in programmable
analog PLL in the device architecture in order to generate a master audio clock. The MCLK pin is
for the audio DAC clock and can either be an output from or an input to the ES6008/18 Vibratto.
Audio data out (TSD) and audio frame sync (TWS) are clocked out of the Vibratto based on the
audio transmit bit clock (TBCK). Audio receive bit clock (RBCK) is used to clock in audio data in
(RSD) and audio receive frame sync (RWS).

11 FRONT PANEL
11.1 VFD CONTROLLER
The VFD controller is a NEC uPD16311. This controller is not a processor, but
does include a simple state machine which scans the VFD and reads the front panel
button matrix. The 16311 also includes RAM so it can store the current state of all the
VFD icons and segments. Therefore, the 16311 need only be accessed when the VFD
status changes and when the button status is read. The ES6008/ES6018 can control
this chip directly using PIO pins or can allow the front panel PIC to control the VFD.

12 MISCELLANEOUS FUNCTIONS
12.1 RESET CIRCUITRY
Two different chips are supported to provide the power-on-reset and
pushbutton reset function: Telcom Semiconductor TC1270, or Dallas DS1811.

12.2 VOLTAGE REGULATORS

There are two +5V linear regulators to generate +5V for the analog circuitry
from +12V. A smaller DPAK surface mount device can be used in most circumstances,

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but in applications were more than 150mA are required, a TO-220 through-hole
package can be used.
The ES6008/18 requires 2.5V to operate. This voltage is generated from +5V.

13 CONNECTORS

13.1 ATAPI DRIVE STANDARD CONNECTOR

The I/O connector is a 40-pin connector as shown in figure A.1, with pin assignments as shown in table
A.1. The connector shall be keyed to prevent the possibility of installing it upside down. A key is provided
by the removal of pin 20. The corresponding pin on the cable connector shall be plugged.
The cable plug, not the receptacle, governs the pin locations. The way in which the receptacle is mounted
on the printed circuit board affects the pin positions, and pin 1 shall remain in the same relative position.
This means the pin numbers of the receptacle may not reflect the conductor number of the plug. The
header receptacle is not polarized, and all the signals are relative to pin 20, which is keyed.
By using the plug positions as primary, a straight cable can connect devices. As shown in figure A.1,
conductor 1 on pin 1 of the plug shall be in the same relative position no matter what the receptacle
numbering looks like. If receptacle numbering was followed, the cable would have to twist 180 degrees
between a device with top-mounted receptacles, and a device with bottom-mounted receptacles.

40

20
Circuit board

1
2
Circuit board
40
Figure A.1 - 40-pin connector mounting

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20

1
2

Table A.1 - 40-pin connector interface signals

Signal name
Connector
Conductor
contact
RESET1
1
2
DD7
3
3
4
DD6
5
5
6
DD5
7
7
8
DD4
9
9
10
DD3
11
11
12
DD2
13
13
14
DD1
15
15
16
DD0
17
17
18
Ground
19
19
20
DMARQ
21
21
22
DIOW23
23
24
DIOR25
25
26
IORDY
27
27
28
DMACK29
29
30
INTRQ
31
31
32
DA1
33
33
34
DA0
35
35
36
CS037
37
38
DASP39
39
40

Connector
contact
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

Signal name
Ground
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15
(keypin)
Ground
Ground
Ground
CSEL
Ground
reserved
PDIAGDA2
CS1Ground

Recommended part numbers for the mating connector and cable are shown below, but equivalent parts may
be used.
Connector (40 pin)
Strain relief

3M 3417-7000 or equivalent
3M 3448-2040 or equivalent

Flat cable (stranded 28 AWG)

Flat cable (stranded 28 AWG)

3M 3365-40 or equivalent
3M 3517-40 (shielded) or equivalent

13.2 SCART CONNECTORS

Pinout of the scart connector:
1 Audio Right Out
2 Audio Right In
3 Audio Left / Monu Out
4 Audio Gnd
5 Blue Gnd
6 Audio Left / Mono In
7 Blue
8 Control Voltage

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9 Green Gnd
10 Comms Data 2
11 Green
12 Comms Data 1
13 Red Gnd
14 Comms Data Gnd
15 Red
16 Fast Blanking
17 Video Gnd
18 Fast Blanking Gnd
19 Composite Video In
20 Composite Video Out
21 Shield
Some cheaper SCART cables use unshielded wires, which is just about acceptable for
short cable lengths. For longer lengths, shielded co-ax cable become essential.

Scart Signals:
Audio signals
0.5V RMS, <1K output impedance, >10K input impedance.
Red, Green, Blue
0.7Vpp 2dB, 75R input and output impedance. Note that the Red connection (pin 20)
can alternatively carry the S-VHS Chrominance signal, which is 0.3V.
Composite Video / CSync
1Vpp including sync, 2dB, 75R input and output impedance.Bandwidth = 25Hz to
4.8MHz for normal TV Video de-emphasis to CCIR 405.1 (625-line TV)
Fast Blanking
75R input and output impedance. This control voltage allows devices to over-ride the
composite video input with RGB inputs, for example when inserting closed caption
text. It is called fast because this can be done at the same speeds as other video
signals, which is why it requires the same 75R impedances.
0 to 0.4V: TV is driven by the composite video input signal (pin 19).
Left unconnected, it is pulled to 0V by its 75R termination.
1V to 3V: the TV is driven by the signals Red, Green, Blue and composite
sync. The latter is sent to the TV on pin 19. This signal is useful when using a
TV to display the RGB output of devices such as home computers with TVcompatible frame rates. Tying the signal to 5V via 100R forms a potential
divider with the 75R termination, holding the signal at around 2V.
Alternatively, if a TTL level (0 to 5V) negative sync pulse is available, this will
be high during the display periods, so this can drive the blanking signal via a
suitable resistor.
Control Voltage
0 to 2V = TV, Normal.
5 to 8V = TV wide screen
9.5 to 12V = AV mode

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14. CIRCUIT DESCRIPTION

14.1 POWER SUPPLY:

Socket PL1 is the 220VAC input.

Socket PL4 is used for the power button on the front panel.
2.5A fuse F1 is used to protect the device against short circuit.
Line filters and capacitors TR2, C2, TR4 and C3 are used to block the
parasitic coming from the mains. They also prevent the noise, produced in the
circuit, from being injected to the line.
Voltage is rectified by using diodes D1, D5, D6 and D4. Using capacitor C1
(100f) a DC voltage is produced. (310- 320VDC).
The current in the primary side of the transformer TR3 comes to the SMPS
IC (IC3 TOP223Y). The SMPS IC has a three-pin TO-220 case and a cooler
is mounted on it. It has a built-in oscillator, overcurrent and overvoltage
protection circuitry and runs at 100kHz. It starts with the current from the
primary side of the transformer and follows the current from the feedback
winding.
Feedback current is rectified with diode D7 and filtered with capacitor C4 and
enters the optocoupler IC2 (CQY80NG). Depending on the control current
coming from the secondary side, SMPS IC keeps the output voltage constant
by controlling the duty cycle of the 100kHz signal (PWM) at the primary side
of the transformer.
Voltages on the secondary side are as follows: -12 Volts at D8, 5 Volts at D9,
15 Volts at D10, -22 Volts at D13.
Using resistors R5, R4 and R27, 5V output is divided properly for D14
operation.
D14 TL431 is a constant current regulator. TL431 watches the 5 volts and
supplies the required current to IC2. There are a LED and a photo transistor
in IC2. The LED inside the IC2 transmits the value of the current from D14 to
phototransistor. Depending on the current gain of the phototransistor IC3
keeps the voltage on the 5-volt-winding constant.
Adjustable voltage regulator IC5 (LM317) supplies 12 Volts. 12 Volts is
obtained by using resistors R19, R20 and R21.
When the device enters stand-by mode, transistor Q2 starts to conduct and
pulls the adjust pin of IC5 to ground, where this cuts 12Volts off.
IC6 is also an LM317 that produces 3.3 Volts output from its 5 volts input.
22 Volts is used to feed the VFD (Vacuum Fluorescent Display) driver IC on
the front panel. Using diode D17 22V is decreased about 5.6V and
connected to the filament winding to produce the DC offset for the filaments.

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Transistor Q3 and zener diode D18 are used to regulate +12 Volts. This
voltage is used to feed op-amps on the back panel.

14.2 FRONT PANEL:

All the functions on the front panel are controlled by U1 (ES6008/18) on the
mainboard.
U1 sends the commands to IC2 uPD16311 via socket PL1 (pins 3,4 and 5).
There are 16 keys scanning function, 2 LED outputs, 1 Stand-by output and
VFD drivers on IC2.
Pin 52 is the oscillator pin and is connected via R5 56K.
LED D6 is red in stand-by mode and green when the device is on. When
entering stand-by mode, pin 48 goes HIGH (+5V) and controls the transistor
Q2 on the power board.
Vacuum fluorescent display MD2 is specially designed for DVD.
The scanned keys are transmitted via IC2 pin 5 and 6 to U1 on the
mainboard.
IR remote control receiver module IC3 (TSOP1836) sends the commands
from the remote control directly to U1.
Socket PL2 carries the VFD filament voltage and 22 Volts.

14.3 BACK PANEL:

There are 1 SCART connector (PL4), 2 pieces RCA audio jacks, for audio
output, 1 coaxial digital audio output JK3 and 1 laser digital audio output PL5
on the back panel.
TOTX176 is used for laser output.
For coaxial audio output SPDIF from socket PL1 pin 18 is used. SPDIF enters
the pins 1,3,5,9, and 11 of IC3. Connecting gates in parallel a buffer is
constructed. C51 is used for DC coupling. Resistors R58 and R55 divide the
signal, which is transmitted out via JK3 (RCA jack)
Left and right audio outputs are on PL7.
Q27 and Q28 are used to suppress the noises during turn on and turn off.
There are two op-amps in IC2 and they are used for left and right audio
channels. For one channel, resistors R94 and R44 are used to adjust the gain
and using R112 and C39 a filter circuit is created. For the other channel,
these components are R96 and R113 for gain, R113 and C36 for filter.
Op-amp outputs the left audio via C40, R108 and R48, right audio via C41,
R109 and R49 to SCART and RCA jacks.
SCART pin 8 controls 16:9 and 4:3 mode using Q10 and Q9
When the BPPI00 output of PL1 becomes 5 Volts, 4:3 mode is selected and
16:9 mode is selected when this output becomes 0. The circuit is adjusted to
output 12 Volts for 4:3 mode and 6 Volts for 16:9 mode.

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Transistors Q7 and Q8 transmits these voltages when the device is turned on

and cuts them off when it is turned off.
FBL on pin 16 transmits 5 Volts via transistors Q22 and Q21 when the device
is on.
Socket PL2, which is coming from the mainboard, transmits RED, GREEN,
BLUE and VIDEO signals to SCART over the buffer stage constructed with
transistors Q1, Q2, Q18 and Q6
LUMA and CHROMA signals of S-Video are transmitted to JK4 (S-Video
socket) via transistors Q4 and Q16 respectively.

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CIRCUIT SCHEMATICS

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