Registers and Counters
Registers and Counters
Registers and Counters
Synchronous Circuits
We deal mostly with synchronous circuits
several exceptions in this chapter
Parallel Load
The first and most obvious thing to do with a
register
The D F-F loads data at every cycle. We
want to control that
Very easy: put an AND gate before the clock
!!WRONG!!
No logic before the clock! It is not purebred
synchronous otherwise
Still useful: asynchronous circuits are used
widely.
We can also add an asynchronous clear. We
use the letter R for this to distinguish it from
the C of the clock
Shift Registers
Shift is a very common operation
mult/divide by 2, 4, 8 etc
serial load/store
Data Transfer
We can transfer data serially
With an AND gate and two simple shift
registers, we can do it (asynchronously)
We omit many small details though...
like we need a counter
Serial Adder
Serial adders have some advantages
little hardware
no worries about carry propagation delays
really high clock speeds
can have any number of bits
We Need...
Two serial registers
one full adder
one F-F to remember the carry
clock circuitry
a bit of intuition
Input
Next
State
Output
xy
0
0
0
0
1
1
1
1
00
01
10
11
00
01
10
11
0
0
0
1
0
1
1
1
0
1
1
0
1
0
0
1
Flip-Flop
Inputs
Input
Next
State
Output
Flip-Flop
Inputs
xy
JK
0
0
0
0
1
1
1
1
00
01
10
11
00
01
10
11
0
0
0
1
0
1
1
1
0
1
1
0
1
0
0
1
0X
0X
0X
1X
X1
X0
X0
X0
Counters
We are interested mainly in binary counters
We start with asynchronous counters
they are called ripple counters
Ripple Counters
In asynchronous circuits we are allowed to
play with the clock
We use trailing edge F-F (we could use
leading edge too)
T F-F are ideal for counters
But D F-F can also be used
Basic Operation
When counting up a F-F flips when the
preceding F-F goes from high to low
A T F-F should have its input connected to 1
A D F-F should have its input connected to
the complement of its output.
Synchronous Counters
Thats what we know how to do well!
We can use the standard design procedures
Or observe that a bit toggles if all its
predecessors are 1
the opposite for down-counters
Down Counters
We can easily convert the up-counter to
down-counter
We only need to use the complement of the
output of a F-F instead of its straight output
State Table
Present
State
Next
State
ABC
ABC
000
001
010
011
100
101
110
111
001
010
100
xxx
101
110
000
xxx
Flip-Flop Inputs
State Table
Present
State
Next
State
Flip-Flop Inputs
ABC
ABC
J K J K JK
000
001
010
011
100
101
110
111
001
010
100
xxx
101
110
000
xxx
0X
0X
1X
XX
X0
X0
X1
XX
0X
1X
X1
XX
0X
1X
X1
XX
1X
X1
0X
XX
1X
X1
0X
XX
Ring Counters
Timing signals can be generated by a regular
counter plus a decoder
Alternatively can be generated by a ring
counter
A single bit is shifted along a circular shift
register
Advantages-Disadvantages
More F-F but less combinational logic
Much less complex wiring
Reinitialization after an error is hard (we
need to be able to specify which F-F are set
and which are reset during start-up)
Johnson Counter
The shift register is a switch tail ring
Needs half the F-F
Needs a few two-input gates
Advantages-Disadvantages
Needs half the number of F-F
Needs only 2-input gates
But it still needs gates
And still needs more than log N F-F
How about error recovery?
Error Recovery
There are two ways:
Detect the illegal state and reset every F-F
Nudge the counter towards a legal state by
assigning
D_c = (A+C)B
It will eventually go to a legal state.
Structural Version
We have to define the building block
Then instantiate it several times
Structural Version
moduleSHFTREG(I,select,lfin,rtin,A,CLK,Clr);
input[3:0]I;//Parallelinput
input[1:0]select;//Modeselect
inputlfin,rtin,CLK,Clr;//Serialinputs,clock,clear
output[3:0]A;//Paralleloutput
//Instantiatethefourstages
stageST0(A[0],A[1],lfin,I[0],A[0],select,CLK,Clr);
stageST1(A[1],A[2],A[0],I[1],A[1],select,CLK,Clr);
stageST2(A[2],A[3],A[1],I[2],A[2],select,CLK,Clr);
stageST3(A[3],rtin,A[2],I[3],A[3],select,CLK,Clr);
endmodule
A Synchronous Counter
Not much harder given that Verilog has the
addition operation built in
The only tricky thing is the carry-out
Synchronous Counter
modulecounter(Count,Load,IN,CLK,Clr,A,CO);
inputCount,Load,CLK,Clr;
input[3:0]IN;//Datainput
outputCO;//Outputcarry
output[3:0]A;//Dataoutput
reg[3:0]A;
assignCO=Count&~Load&(A==4'b1111);
always@(posedgeCLKornegedgeClr)
if(~Clr)A=4'b0000;
elseif(Load)A=IN;
elseif(Count)A=A+1'b1;
elseA=A;//nochange,defaultcondition
endmodule
Ripple Counter
Yes, even asynchronous circuits can be
described in Verilog
Use structural specification for the counter
and behavioral for the F-F that constitutes
the building block.
Ripple Counter
moduleripplecounter(A0,A1,A2,A3,Count,Reset);
outputA0,A1,A2,A3;
inputCount,Reset;
//Instantiatecomplementingflipflop
CFF0(A0,Count,Reset);
CFF1(A1,A0,Reset);
CFF2(A2,A1,Reset);
CFF3(A3,A2,Reset);
endmodule
Complementing F-F
moduleCF(Q,CLK,Reset);
outputQ;
inputCLK,Reset;
regQ;
always@(negedgeCLKorposedgeReset)
if(Reset)Q=1'b0;
elseQ=#2(~Q);//Delayof2timeunits
endmodule