RAM ROM and Plds
RAM ROM and Plds
RAM ROM and Plds
The data outputs at any time represents the value stored at the memory
location specified on the address lines.
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k inputs
2^k x n
ROM
n outputs
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Uses an address decoder such that the k address lines selects one word of the 2k
words of data stored in the ROM.
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
D(n-1)
D(2)
D(1)
D(0)
A(0)
A(1)
A(2)
A(k-1)
address
decoder
read
Each of the 2k n bits inside of the ROM are programmable via opening and/or closing
switches.
E&CE 223 Digital Circuits and Systems (A. Kennings)
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c
b
a
A(0)
A(1)
A(2)
3-to-8 decoder
011 (3)
011 (3)
110 (6)
100(4)
100(4)
001 (1)
010 (2)
001 (1)
READ EN
8 x 3 ROM
D(2)
f2
D(1)
f1
D(0)
f0
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Types of ROM
Several technologies for implementing ROM:
PROM (Programmable Read-Only Memory):
PROM contains fuses giving logic value of 1 to all bits in device. Programming
means blowing fuses to give some bits a logic value of 0.
Once programmed, thats it programming cannot be changed.
EPROM (Electrically Programmable Read-Only Memory):
Can be erased by exposure to UV light. Otherwise, same as PROM.
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Textbook
ROM are described in Chapter 7, Section 7.5 of the textbook.
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data inputs
n
k
address
read
2^k x n
RAM
write
n
data outputs
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select
select
input
S
output
input
1 bit
memory
output
read/write
read/write
Note: circuit is not really made like this, but this will function correctly to explain
the concept
E&CE 223 Digital Circuits and Systems (A. Kennings)
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D(2)
1 bit
memory
D(1)
1 bit
memory
D(0)
1 bit
memory
1 bit
memory
A(0)
select
A(1)
1 bit
memory
A(2)
1 bit
memory
1 bit
memory
1 bit
memory
input
1 bit
memory
output
read/write
A(k-1)
address
decoder
1 bit
memory
1 bit
memory
1 bit
memory
1 bit
memory
read/write
D(n-1)
D(2)
D(1)
D(0)
data outputs
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data input
data input
data input
data ouput
data ouput
data ouput
data ouput
data input
Can also share data lines with both input and output data using tri-state buffers
(enabled by the read/write signal):
select
input
read/write
D(n-1)
D(2)
D(1)
D(0)
1 bit
memory
output
read/write
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Textbook
RAM is described in Chapter 7, Sections 7.2 and 7.3 of the course textbook.
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AND plane
OR plane
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x2
x3
f1 f2
E&CE 223 Digital Circuits and Systems (A. Kennings)
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x1
x2
x3
f1
f2
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x2
x3
f1
f2
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to AND plane
Above circuit (plus SOP from the AND plane and OR gate) form a MacroCell.
Several MacroCells together in the same IC is called an SPLD.
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Using a Complex Programmable Logic Device (CPLD) is the next step if we have a
large complicated circuit
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IO block
IO block
PAL-like
block
PAL-like
block
IO block
IO block
PAL-like
block
PAL-like
block
PAL-like
block
IO block
IO block
PAL-like
block
PAL-like
block
Interconnection wires
IO block
PAL-like
block
IO block
Typical architecture (each PAL-like block has many inputs e.g., 36 - , many product
terms e.g., 80 and several outputs e.g., 16).
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MacroCell
1
MacroCell
MacroCell
Product
Term
Array
(PTA)
Product
Term
Matrix
(PTM)
MacroCell
MacroCell
MacroCell
MacroCell
36
MacroCell
MacroCell
In addition to programming the AND plane and MacroCells, also need to program the
multiplexer select lines to route the correct signals into the PAL block.
E&CE 223 Digital Circuits and Systems (A. Kennings)
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Textbook
SPLD and CPLD are described in Chapter 7, Section 7.8 of the textbook.
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Logic
Standard
Logic
Programmable
Logic Devices
SPLDs
ASIC
Gate
Arrays
CPLDs
Cell-Based
ICs
FPGAs
Full custom
ICs
FPICs
The key idea is that FPGAs are custom-designed like ICs (ASICs), but are also
software-reprogrammable
You can in some sense think of an FPGA as a grid of wires connecting together
logic gates. The joints between the wires are defined when you configure the
device.
These wires have fuses between them and the fuses can be blown or
connected in software.
At least, that was the original idea (Programmable Array Logic) now they are
far more sophisticated.
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Instead of just AND/OR gates, FPGAs now use lookup table and flip-flop blocks,
and include onboard memory (block RAM), hardware integer multipliers, fast I/O
interconnects etc.
We use the term to refer to hybrid computers that include both conventional
microprocessors and FPGA reconfigurable logic.
switch block
IO block
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
Logic
IO block
Logic
IO block
Logic
IO block
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IO
IO
Logic
IO
IO
Logic
Routing resources around the logic blocks need to be programmed so signals get
routed to where they are needed.
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0/1
0/1
D S Q
0/1
0/1
output to
routing fabric
0/1
0/1
x1
x2 x3
inputs from
routing fabric
Can implement any 3-input function by properly programming the configuration bits.
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Types of FPGA
FPGA typically SRAM-based devices, but can be had in PROM, EPROM or EEPROM
types.
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