Handouts DSD 13 PLD FPGA PDF

11/11/2014
Programmable Logic Devices

Programmable Logic Device (PLD) is an integrated circuit
with internal logic gates and/or connections that can in some
way be changed by a programming process.
Designing With
Examples:
PROM
Programmable Logic Array (PLA)
Programmable Array Logic (PAL) device
Complex Programmable Logic Device (CPLD)
Field-Programmable Gate Array (FPGA)
A PLDs function is not fixed

Can be programmed to perform different functions
EC6101 Digital System Design Monsoon 2014
Why PLDS?
PLD
Programmable logic technology advances rapidly,
and manufacturers are continually offering devices
with increased capabilities and speeds.
Major players in PLDs
Fact:
It is most economical to produce an IC in large volumes
But:
Many situations require only small volumes of ICs

Many situations require changes to be done in the field, e.g.
Firmware of a product under development
A programmable logic device can be:
Produced in large volumes

Programmed to implement many different low-volume design
PLD
Altera
Atmel
Cypress
Lattice
QuickLogic
Xilinx
PLD
PLDs are an alternative to custom ASICs.
Disadvantage of PLDs
A PLD consists of general-purpose logic resources

that can be connected in many permutations
according to an engineers logic design.
The main benefit of PLD technology is that a
design can be rapidly loaded into a PLD,
bypassing the time consuming and expensive
custom IC development process.
The penalty paid for the hidden logic that

implements the programmable connectivity
between logic gates.
higher unit cost
slower speeds
increased power consumption
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11/11/2014
PLD Hardware Programming

Technologies
PLD vs. ASIC
In the Factory - Cannot be erased/reprogrammed by user
Based on 2003 data
Mask programming (changing the VLSI mask) during

manufacturing
Programmable only once

Fuse
Anti-fuse
Reprogrammable (Erased & Programmed many times)

Volatile - Programming lost if chip power lost
Single-bit storage element
Non-Volatile - Programming survives power loss

UV Erasable
Electrically Erasable
Flash (as in Flash Memory)

(PLDs)
Used symbol in PLD
All use AND-OR structure- differ in which is programmable

Fixed
AND array
(decoder)
Inputs
Programmable
connections
Programmable
OR array
Outputs
Programmable read-only memory (PROM)
Most PLD technologies have gates with very high

fan-in
Fuse map: graphic representation of the selected
connections
Inputs
Programmable
connections
Programmable
AND array
Fixed
OR array
Outputs
Programmable array logic (PAL) device
Inputs
Programmable
connections
Programmable
AND array
Programmable
connections
Programmable
OR array
Outputs
Programmable logic array (PLA)

9
Read-Only Memory (ROM)
10
ROM Internal Logic
ROM: A device in which permanent binary

information is stored using a special device
(programmer)
k inputs
2k x n ROM
(address)
n outputs
(data)
k inputs (address) 2k words each of size n bits

(data)
ROM DOES NOT have a write operation
ROM DOES NOT have data inputs
The decoder stage

produces ALL
possible minterms
32 Words of 8 bits
each
5 input lines
(address)
Each OR gate has a
32 input
A contact can be
made using
fuse/anti-fuse
Internal Logic of a 32x8 ROM
Word: group of bits stored in one location

11
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11/11/2014
Combinational Circuit
Implementation with ROM
Programming a ROM
I4
0
0
0
0
1
1
1
1
Inputs
I3 I2 I1
0
0
0
0
0
0
0
0
1
0
0
1
.
.
.
1
1
0
1
1
0
1
1
1
1
1
1
Outputs
A7 A6 A5 A4 A3 A2 A1 A0
1
0
1
1
0
1
1
0
0
0
0
1
1
1
0
1
1
1
0
0
0
1
0
1
1
0
1
1
0
0
1
0
.
.
.
0
0
0
0
1
0
0
1
1
1
1
0
0
0
1
0
0
1
0
0
1
0
1
0
0
0
1
1
0
0
1
1
I0
0
1
0
1
0
1
0
1
ROM = Decoder + OR gates

Implementation of a combinational circuit is
easy
Store the truth table by programming the ROM
Every ONE in truth table specifies a closed circuit

Every ZERO in truth table specifies an OPEN circuit
Example: At address 00011 The word 10110010 is stored
Only need to provide the truth table
13
Example 1
Example 1 (cont.)
Inputs
Example: Design a combinational circuit using ROM. The circuit

accepts a 3-bit number and generates an output binary
number equal to the square of the number.
Solution: Derive truth table:
Inputs
14
Outputs
Outputs
A2
A1
A0
B5
B4
B3
B2
B1
B0
SQ
16
A2
A1
A0
B5
B4
B3
B2
B1
B0
SQ
25
36
49
16
25
36
49
ROM truth table specifies the required connections
A0
B1 is ALWAYS 0 no need to generate it using the ROM

B0 is equal to A0 no need to generate it using the ROM
Therefore: The minimum size of ROM needed is 23X4 or 8X4
15
B0
0
B1
8 X 4 ROM
B2
B3
A1
B4
A2
B5
16
Example 2
Example 2
Problem: Tabulate the truth for an 8 X 4 ROM that implements the following
four Boolean functions:
A(X,Y,Z) = Sm(3,6,7); B(X,Y,Z) = Sm(0,1,4,5,6)
C(X,Y,Z) = Sm(2,3,4); D(X,Y,Z) = Sm(2,3,4,7)
Problem: Tabulate the truth for an 8 X 4 ROM that implements the following
four Boolean functions:
A(X,Y,Z) = Sm(3,6,7); B(X,Y,Z) = Sm(0,1,4,5,6)
C(X,Y,Z) = Sm(2,3,4); D(X,Y,Z) = Sm(2,3,4,7)
Solution:
Solution:
Inputs
17
Outputs
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11/11/2014
Sequential Circuit
Implementation with ROM
inputs X
Combinational
Circuits
Example
Example: Design a sequential circuit whose state table is given, using a
ROM and a register.
outputs Z
next state
present state
State Table
FFs
We need a 8x3 ROM (why?)

3 address lines and 3 data lines
sequential circuit = combinational circuit + memory

Combinational part can be built with a ROM as shown
previously
Number of address lines = No. of FF + No. of inputs
Number of outputs = No. of FF + No. of outputs
19
Types of ROMs
A Programmable Logic Array (PLA) performs the

same basic function as the ROM.
A PLA with n inputs and m outputs can realize
m functions
of n variables
A PLA consists of
An AND array to realize product terms
An OR array to realize the output functions
Thus, a PLA implements SOP expressions.
By a semiconductor company
PROM (Programmable ROM)

User can blow/connect fuses with a special programming
device (PROM programmer)
Only programmed once!
EPROM (Erasable PROM)

Can be erased using Ultraviolet Light
Electrically Erasable PROM (EEPROM or E2PROM)

Like an EPROM, but erased with electrical signal
21
PLA Basic Structure
20
Programmable Logic Array
A ROM programmed in four different ways:

ROM: Mask Programming
22
Building Logic Functions with PLA
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11/11/2014
PAL
Programmable Logic Array (PLA)
AND array and OR array

are programmable
XOR is available to
complement an output if
needed
The Programmable Array Logic (PAL) is a

special case of the PLA
AND array is programmable
OR array is fixed
A PAL is less expensive than the more
general PLA.
Example:
3 inputs/2 outputs
F1 = A B + A C + A B C
F2 = (AC + BC)
25
Full adder using PAL
Building Logic Functions with PLA
27
Fixed OR array and programmable

AND array
Feed back is used to support more

product terms
AND output can not be shared
here!
Example:
4 inputs/4 outputs with fixed 3input OR gates
W = A B C + A B C D
X=?
Y=?
Z=?
28
A Complex Programmable Logic Device

integrates many PLAs (or PALs) onto a single
chip.
In addition to the individual PLAs (or PALs)
being programmable, the interconnection between
these components is also programmable.
A small digital system can be realized using
A single CPLD
Necessary memory elements (i.e. flip-flops)
Opposite of ROM
CPLD
Programmable Array Logic (PAL)
26
29
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11/11/2014
CPLD Architecture
CPLD
I/Os
PAL Block
I/Os
PAL Block
Central Switch Matrix
Dedicated
inputs
PAL Block
I/Os
PAL Block
I/Os
Architecture of the Xilinx XCR3064XL CPLD

(Figure based on figures and text owned by Xilinx, Inc., Courtesy of Xilinx, Inc. Xilinx, Inc. 1999-2003. All rights reserved.)
Clock/
Inputs
The CPLD is an array of PAL-like devices, interconnected by a switch matrix.
31
32
CPLD
FPGA
CPLD Function Block and Macrocell

(A Simplified Version of XCR3064XL)
33
What is an FPGA?
Why FPGAs?
By the early 1980s most of the logic circuits
in typical systems where absorbed by a
handful of standard large scale integrated
circuits (LSI).
Field Programmable Gate Arrays

Field programmability is achieved through switches
(Transistors are controlled by memory elements or fuses)
Switches control the following aspects
Microprocessors, bus/IO controllers, system timers,..
Interconnection among wire segments

Configuration of logic blocks
Every system still had the need for random

glue logic to help connect the large ICs:
generating global control signals (for resets etc.)
data formatting (serial to parallel, multiplexing, etc.)
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11/11/2014
Why FPGAs?
Why FPGAs?
Systems had a few LSI components and lots
of small low density SSI (small scale IC)
and MSI (medium scale IC) components.
Custom ICs where sometimes designed to

replace the large amount of glue logic:
reduced system complexity and manufacturing cost,
improved performance.
However, custom ICs are relatively very expensive to
develop, and delay in introduction of product to market
(time to market) because of increased design time.
Note: need to worry about two kinds of costs:

cost of development, sometimes called non-recurring
engineering (NRE)
cost of manufacture
37
Two competing implementation

approaches
Why FPGAs?
ASIC
Application Specific
Integrated Circuit
Therefore the custom IC approach was only viable

for products with very high volume (where NRE
could be amortized), and which were not time to
market sensitive.
FPGAs were introduced as an alternative to custom
ICs for implementing glue logic:
designed all the way from

behavioral description to
physical layout
designs must be sent for
expensive and time
consuming fabrication in
semiconductor foundry
improved density relative to discrete SSI/MSI components

(within around 10x of custom ICs)
with the aid of computer aided design (CAD) tools circuits
could be implemented in a short amount of time (no physical
layout process, no mask making, no IC manufacturing)
FPGA
Field Programmable
Gate Array
no physical layout design;
design ends with a
bitstream used to configure
a device
bought off the shelf and
reconfigured by
designers themselves
39
FPGAs vs ASICs
40
Comparison
FPGAs
ASICs
38
Summary
Off-the-shelf
High performance
Low development costs
Low power
Short time to the market
Low cost (but only
in high volumes)
Reconfigurability
41
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11/11/2014
FPGA Design process

Design and implement a simple unit permitting to
speed up encryption with RC5-similar cipher with
fixed key set on 8031 microcontroller. Unlike in
the experiment 5, this time your unit has to be
able to perform an encryption algorithm by itself,
executing 32 rounds..
FPGA Design process (contd..)
Specification (Lab Experiments)
Implementation
Timing simulation
On-paper hardware design

(Block diagram & ASM chart)
Configuration
VHDL description (Your Source Files)

Library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
On chip testing
Functional simulation
entity RC5_core is
port(
clock, reset, encr_decr: in std_logic;
data_input: in std_logic_vector(31 downto 0);
data_output: out std_logic_vector(31 downto 0);
out_full: in std_logic;
key_input: in std_logic_vector(31 downto 0);
key_read: out std_logic;
);
end AES_core;
Synthesis
Post-synthesis simulation
43
Design Steps Involved in

Designing With FPGAs
FPGA building blocks
Logic block
I/O
Programmable logic blocks

Implement combinational and
sequential logic
Programmable interconnect
Wires to connect inputs and
outputs to logic blocks
Interconnection switches
Programmable I/O blocks

Special logic blocks at the
periphery of device for
external connections
I/O
FPGA - Generic Structure
Understand and define design

requirements
Design description
Behavioural simulation (Source
code interpretation)
Synthesis
Functional or Gate level
simulation
Implementation
Place and Route
Timing or Post layout simulation
Programming, Test and Debug
I/O
44
I/O
45
46
Classification of FPGAs
Families of FPGAs differ in:
physical means of implementing user programmability,
Granularity
how logic is organised
47
I.
Based on physical means of implementing user

programmability
Can be classified into three categories:

SRAM based
Fuse based
EPROM/EEPROM/Flash based
48
11/11/2014
Anti-fuse Programming Technology
SRAM Programming Technology

Employs SRAM (Static RAM) cells to
control pass transistors and/or
transmission gates
SRAM cells control the configuration of
logic block as well
Volatile
Though implementation differ, all anti-fuse programming

elements share common property
Needs an external storage

Needs a power-on configuration
mechanism
In-circuit re-programmable
Uses materials which normally resides in high impedance state

But can be fused irreversibly into low impedance state by
applying high voltage
Lesser configuration time

Occupies relatively larger area
OTP devices
Fuse blown = connection established
49
50
Antifuse FPGAs
Anti-fuse Programming
Technology
Very low ON Resistance (Faster implementation of

circuits)
Limited size of anti-fuse elements; Interconnects occupy
relatively lesser area
Offset : Larger transistors needed for programming
One Time Programmable
Cannot be re-programmed (Design changes are not
possible)
Retain configuration after power off
Advantages
Highest density - a mere cross
point - 10X the density of SRAM
Lowest switch resistance - 25
Ohms
Very low capacitance 1 fF per
node.- approaching the metal line
capacitance
non- volatile
Nearly impossible to reverse
engineer
Radiation hard - Space appns Live within 1 millisecond of the
power supply reaching spec
voltage
Software is easy to place and
route
52
FPGA Comparison
SRAM
Antifuse
Flash
EPROM
Worst
Best
Worst
Medium
Power
Varies
Near Best
Best
Worst
Density
Medium
Second
Best
Worst
Worst
Best
Medium
Medium
Routing Cell size
1/10
1/7
1/-5-
Reprogrammable
Yes
No
Yes
Yes
Speed
EPROM Programming Technology

Two gates: Floating and Select
Normal mode:
No charge on floating gate
Transistor behaves as normal n-channel transistor
Floating gate charged by applying high voltage
Threshold of transistor (as seen by gate) increases
Transistor turned off permanently
Re-programmable by exposing to UV radiation
Disadvantages
Requires programmer
Requires a socket - a problem for
devices with > 200 pins
Requires one to two transistors per
wire for programming
Some antifuse defects not testable
until programming
51
EPROM, EEPROM or Flash Based

Programming Technology
Radiation
53
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11/11/2014
II. Based on Granularity
III. Based on how logic is organised
1. Coarse Grained (SRAM Based) - e.g. Altera, Xilinx
Symmetrical Array
Large complex logic blocks

Dedicated functions, fast carry etc.
Re-programmable
Unpredictable propagation delays
Row Based
Sea of Gates
LB
LB
LB
LB
LB
LB
LB
LB
LB
LB
LB
LB
LB
LB
LB
LB
LB
LB
LB
LB
LB
LB
LB
LB
2. Fine Grained (Antifuse Based) - e.g. Actel
Sea of small logic blocks

Predictable propagation delays
High performance timing
One time programmable (OTP)
55
MUX Implementation
FPGAs are also classified based on how the

logic blocks are implemented.
Required function
a
b
MUX based
LUT based
Truth Table
abc y
a
b
y
1
0
1
0
1
0
1
1
58
Manufacturers are already specialised!

Different companies make different types of
FPGAs!
Programmed LUT
SRAM Cells
1
0
1
0
1
0
1
1
8:1 Multiplexer
000
001
010
011
100
101
110
111
57
LUT Implementation
Required function
56
a bc
59
60
10
11/11/2014
Idealized FPGA Logic Block
LUT Implementation
n-bit LUT is implemented as a 2n x 1 memory:
inputs choose one of 2n memory locations.
memory locations are normally loaded with values from
users configuration bit stream.
Inputs to mux control are the Configurable Logic Block
(CLB) inputs.
Result is a general purpose logic gate.
n-LUT can implement any function of n inputs!
look up table (LUT) implements combinational logic

Register for sequential circuits
Additional logic (not shown):
Carry logic for arithmetic functions
Expansion logic for functions requiring more than 4 inputs
61
Modulo-4 counter: Specification
62
FPGA Implementation of Modulo-4 Counter
An Example
Modulo-4 counter: Logic Implementation
63
Commercially Available Devices
64
Classification of PLDs
Architecture differs from vendor to vendor

Characterized by
Structure and content of logic block
Structure and content of routing resources
65
66
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11/11/2014
Xilinx family of FPGAs
FPGA Comparison Table
Artix 7
Kintex 7
Virtex 7
Virtex 6
Virtex 5
Virtex IV
Virtex II Pro
Virtex II
Spartan 3 (1.2V)
Spartan 2E (1.8V)
Spartan 2 (2.5V)
Spartan XL (3.3V)
XC4000
XC3000
XC2000
67
68
General Architecture of Xilinx FPGAs

Layout of Part of a Programmable
Logic Cell Array
Xilinx calls the logic cells as CLBs

69
70
Internal configuration memory

cells
Xilinx 3000 series FPGAs

Consists of an array of
Internal configuration memory cells
64 Configurable Logic Blocks (CLBs) and
64 Input-Output interface blocks(I/O Blocks)
71
72
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11/11/2014
Xilinx 3000 series Logic Cell
Combinatorial Logic Options
73
Flip-flops with Clock Enable
74
Parallel Adder-Subtracter Logic Cell
75
Signal Paths Within Adder-Subtractor

Logic Cell
77
76
Xilinx 3000 Series I/O Block
78
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11/11/2014
Direct Interconnects
Between Adjacent CLBs
General-purpose Interconnects
79
80
Programmable Switch Matrix

programmable switch element
Package Marking
After Programming
Spartan-3E QFP Package Marking Example

81
Package Marking
82
Spartan-3E FPGAs
Spartan-3E BGA Package Marking Example

83
84
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11/11/2014
Spartan-3E FPGAs
Xilinx Spartan-III FPGAs
85
Xilinx Virtex FPGAs
86
Educational Board
87
88
Reference
1. Fundamentals of Logic Design, Charles H Roth.
2. Digital System Design using VHDL, Charles H Roth.
2. Xilinx FPGA data sheets and manuals.
89
90
15

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11/11/2014

Programmable Logic Devices

A PLDs function is not fixed

EC6101 Digital System Design Monsoon 2014

Many situations require only small volumes of ICs

A programmable logic device can be:

Produced in large volumes

PLDs are an alternative to custom ASICs.

A PLD consists of general-purpose logic resources

The penalty paid for the hidden logic that

PLD Hardware Programming

PLD vs. ASIC

In the Factory - Cannot be erased/reprogrammed by user

Based on 2003 data

Mask programming (changing the VLSI mask) during

Programmable only once

Reprogrammable (Erased & Programmed many times)

Non-Volatile - Programming survives power loss

EC6101 Digital System Design Monsoon 2014

Programmable Logic Devices

Used symbol in PLD

All use AND-OR structure- differ in which is programmable

Programmable read-only memory (PROM)

Most PLD technologies have gates with very high

Programmable array logic (PAL) device

Programmable logic array (PLA)

EC6101 Digital System Design Monsoon 2014

Read-Only Memory (ROM)

ROM Internal Logic

ROM: A device in which permanent binary

EC6101 Digital System Design Monsoon 2014

k inputs (address) 2k words each of size n bits

The decoder stage

Internal Logic of a 32x8 ROM

Word: group of bits stored in one location

EC6101 Digital System Design Monsoon 2014

ROM = Decoder + OR gates

Every ONE in truth table specifies a closed circuit

Only need to provide the truth table

EC6101 Digital System Design Monsoon 2014

Example: Design a combinational circuit using ROM. The circuit

EC6101 Digital System Design Monsoon 2014

EC6101 Digital System Design Monsoon 2014

ROM truth table specifies the required connections

B1 is ALWAYS 0 no need to generate it using the ROM

EC6101 Digital System Design Monsoon 2014

EC6101 Digital System Design Monsoon 2014

EC6101 Digital System Design Monsoon 2014

We need a 8x3 ROM (why?)

sequential circuit = combinational circuit + memory

A Programmable Logic Array (PLA) performs the

PROM (Programmable ROM)

EPROM (Erasable PROM)

Electrically Erasable PROM (EEPROM or E2PROM)

PLA Basic Structure

EC6101 Digital System Design Monsoon 2014

Programmable Logic Array

A ROM programmed in four different ways: