Scribd Logo
Upload

Welcome to Scribd!

  • 65 views

    Latch Free Clock Gating

    Uploaded by

    Narendra Achari
    Clock gating is a technique to reduce power consumption by turning off the clock to circuits when they are not in use. It can reduce over 50% of dynamic power in a design. There are two types of clock gating - latch-free and latch-based. Latch-free clock gating uses simple logic gates but may cause issues if the enable signal changes between clock pulses. Latch-based clock gating adds a level-sensitive latch to hold the enable signal state through the entire clock pulse, avoiding these issues. Modern EDA tools support automatic insertion of clock gating cells to implement this technique without requiring changes to RTL code.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd

    Latch Free Clock Gating

    Uploaded by

    Narendra Achari
    65 views3 pages
    Clock gating is a technique to reduce power consumption by turning off the clock to circuits when they are not in use. It can reduce over 50% of dynamic power in a design. There are two types of clock gating - latch-free and latch-based. Latch-free clock gating uses simple logic gates but may cause issues if the enable signal changes between clock pulses. Latch-based clock gating adds a level-sensitive latch to hold the enable signal state through the entire clock pulse, avoiding these issues. Modern EDA tools support automatic insertion of clock gating cells to implement this technique without requiring changes to RTL code.

    Original Description:

    clock gating

    Original Title

    Clock Gating

    Copyright

    © © All Rights Reserved

    Available Formats

    DOCX, PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Clock gating is a technique to reduce power consumption by turning off the clock to circuits when they are not in use. It can reduce over 50% of dynamic power in a design. There are two types of clock gating - latch-free and latch-based. Latch-free clock gating uses simple logic gates but may cause issues if the enable signal changes between clock pulses. Latch-based clock gating adds a level-sensitive latch to hold the enable signal state through the entire clock pulse, avoiding these issues. Modern EDA tools support automatic insertion of clock gating cells to implement this technique without requiring changes to RTL code.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    65 views3 pages

    Latch Free Clock Gating

    Uploaded by

    Narendra Achari
    Clock gating is a technique to reduce power consumption by turning off the clock to circuits when they are not in use. It can reduce over 50% of dynamic power in a design. There are two types of clock gating - latch-free and latch-based. Latch-free clock gating uses simple logic gates but may cause issues if the enable signal changes between clock pulses. Latch-based clock gating adds a level-sensitive latch to hold the enable signal state through the entire clock pulse, avoiding these issues. Modern EDA tools support automatic insertion of clock gating cells to implement this technique without requiring changes to RTL code.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 3

    Clock Gating

    Clock tree consume more than 50 % of dynamic power. The components of this power are:
    1) Power consumed by combinatorial logic whose values are changing on each clock edge
    2) Power consumed by flip-flops and
    3) The power consumed by the clock buffer tree in the design.
    It is good design idea to turn off the clock when it is not needed. Automatic clock gating is
    supported by modern EDA tools. They identify the circuits where clock gating can be inserted.
    RTL clock gating works by identifying groups of flip-flops which share a common enable
    control signal. Traditional methodologies use this enable term to control the select on a
    multiplexer connected to the D port of the flip-flop or to control the clock enable pin on a flipflop with clock enable capabilities. RTL clock gating uses this enable signal to control a clock
    gating circuit which is connected to the clock ports of all of the flip-flops with the common
    enable term. Therefore, if a bank of flip-flops which share a common enable term have RTL
    clock gating implemented, the flip-flops will consume zero dynamic power as long as this enable
    signal is false.
    There are two types of clock gating styles available. They are:
    1) Latch-based clock gating
    2) Latch-free clock gating.

    Latch free clock gating


    The latch-free clock gating style uses a simple AND or OR gate (depending on the edge on
    which flip-flops are triggered). Here if enable signal goes inactive in between the clock pulse or
    if it multiple times then gated clock output either can terminate prematurely or generate multiple
    clock pulses. This restriction makes the latch-free clock gating style inappropriate for our singleclock flip-flop based design.

    Latch free clock gating

    Latch based clock gating


    The latch-based clock gating style adds a level-sensitive latch to the design to hold the enable
    signal from the active edge of the clock until the inactive edge of the clock. Since the latch
    captures the state of the enable signal and holds it until the complete clock pulse has been
    generated, the enable signal need only be stable around the rising edge of the clock, just as in the
    traditional ungated design style.

    Latch based clock gating

    Specific clock gating cells are required in library to be utilized by the synthesis tools. Availability
    of clock gating cells and automatic insertion by the EDA tools makes it simpler method of low
    power technique. Advantage of this method is that clock gating does not require modifications to
    RTL description.

    References
    [1] Frank Emnett and Mark Biegel, Power Reduction Through RTL Clock Gating, SNUG, San
    Jose, 2000
    [2] PrimeTime User Guide

    You might also like