Problems 373

7. If a 1-of-16 decoder with active-LOW outputs exhibits a LOW on the decimal 12 output, what
are the inputs?
(a) A3A2A1A0 = 1010 (b) A3A2A1A0 = 1110
(c) A3A2A1A0 = 1100 (d) A3A2A1A0 = 0100
8. A BCD-to-7 segment decoder has 0100 on its inputs. The active outputs are
(a) a, c, f, g (b) b, c, f, g
(c) b, c, e, f (d) b, d, e, g
9. If an octal-to-binary priority encoder has its 0, 2, 5, and 6 inputs at the active level, the active-
HIGH binary output is
(a) 110 (b) 010
(c) 101 (d) 000
10. In general, a multiplexer has
(a) one data input, several data outputs, and selection inputs
(b) one data input, one data output, and one selection input
(c) several data inputs, several data outputs, and selection inputs
(d) several data inputs, one data output, and selection inputs
11. Data distributors are basically the same as
(a) decoders (b) demultiplexers
(c) multiplexers (d) encoders
12. Which of the following codes exhibit even parity?
(a) 10011000 (b) 01111000
(c) 11111111 (d) 11010101
(e) all (f) both answers (b) and (c)

PROBLEMS
Answers to odd-numbered problems are at the end of the book.

Section 61 Half and Full Adders

1. For the full-adder of Figure 64, determine the outputs for each of the following inputs
(a) A = 0, B = 1, Cin = 0 (b) A = 1, B = 0, C in = 1
(c) A = 0, B = 0, C in = 0
2. What are the half-adder inputs that will produce the following outputs:
(a) = 0, C out = 0 (b) = 1, C out = 0
(c) = 0, Cout = 1
3. Determine the outputs of a full-adder for each of the following inputs:
(a) A = 1, B = 0, C in = 0 (b) A = 0, B = 0, C in = 1
(c) A = 0, B = 1, C in = 1 (d) A = 1, B = 1, C in = 1

Section 62 Parallel Binary Adders

4. For the parallel adder in Figure 669, determine the complete sum by analysis of the logical
operation of the circuit. Verify your result by longhand addition of the two input numbers.

1 0 1 1 1 0

A B Cin A B Cin A B Cin

Cout Cout Cout

4 3 2 1

FIGURE 669
374 Functions of Combinational Logic

5. Repeat Problem 4 for the circuit and input conditions in Figure 670.

1 1 0 1 1 0 1 0 0 1

A B Cin A B Cin A B Cin A B Cin A B Cin

Cout Cout Cout Cout Cout

6 5 4 3 2 1

FIGURE 670

6. The circuit shown in Figure 671 is a 4-bit circuit that can add or subtract numbers in a form
used in computers (positive numbers in true form; negative numbers in complement form). (a)
Explain what happens when the Add /Subt. input is HIGH. (b) What happens when Add /Subt.
is LOW?

A3 B3 A2 B2 A1 B1 A0 B0

Add/Subt.

A B Cin A B Cin A B Cin A B Cin

Cout Cout Cout Cout

3 2 1 0

FIGURE 671

7. For the circuit in Figure 671, assume the inputs are Add /Subt. 5 1, A = 1010, and B = 1101.
What is the output?
8. The input waveforms in Figure 672 are applied to a 2-bit adder. Determine the waveforms for
the sum and the output carry in relation to the inputs by constructing a timing diagram.

A1

A2

B1

B2

Cin

FIGURE 672
 Problems 375

9. The following sequences of bits (right-most bit first) appear on the inputs to a 4-bit parallel
adder. Determine the resulting sequence of bits on each sum output.
A1 1010
A2 1100
A3 0101
A4 1101
B1 1001
B2 1011
B3 0000
B4 0001
10. In the process of checking a 74HC283 4-bit parallel adder, the following logic levels are observed
on its pins: 1-HIGH, 2-HIGH, 3-HIGH, 4-HIGH, 5-LOW, 6-LOW, 7-LOW, 9-HIGH, 10-LOW,
11-HIGH, 12-LOW, 13-HIGH, 14-HIGH, and 15-HIGH. Determine if the IC is functioning properly.

Section 63 Ripple Carry and Look-Ahead Carry Adders

11. Each of the eight full-adders in an 8-bit parallel ripple carry adder exhibits the following propa-
gation delay:
A to and Cout: 20 ns
B to and Cout: 20 ns
Cin to : 30 ns
Cin to Cout: 25 ns
Determine the maximum total time for the addition of two 8-bit numbers.
12. Show the additional logic circuitry necessary to make the 4-bit look-ahead carry adder in
Figure 617 into a 5-bit adder.

Section 64 Comparators
13. The waveforms in Figure 673 are applied to the comparator as shown. Determine the output
(A = B) waveform.

A0 COMP
A0 0
A
A1 A1 1
A=B
B0 B0 0
B
B1 B1 1

FIGURE 673

14. For the 4-bit comparator in Figure 674, plot each output waveform for the inputs shown. The
outputs are active-HIGH.

A0 COMP
A0 0
A1
A1
A
A2 A2
A3 3
A3 A>B
A>B
VCC A=B A=B
B0
A<B A<B
B1 B0 0
B1
B2 B
B2
B3 B3 3

74HC85

FIGURE 674
376 Functions of Combinational Logic

15. For each set of binary numbers, determine the output states for the comparator of Figure 621.
(a) A3A2A1A0 = 1010 (b) A3A2A1A0 = 1101 (c) A3A2A1A0 = 1001
B3B2B1B0 = 1101 B3B2B1B0 = 1101 B3B2B1B0 = 1000

Section 65 Decoders
16. When a LOW is on the output of each of the decoding gates in Figure 675, what is the binary
code appearing on the inputs? The MSB is A3.

A0
A0
A1
A1
A2 A2
A3 A3

(a) (b)

A0

A1
A0
A1 A2
A2
A3 A3

(c) (d)

FIGURE 675

17. Show the decoding logic for each of the following codes if an active-HIGH (1) output is
required:
(a) 1101 (b) 1000 (c) 11011 (d) 11100
(e) 101010 (f) 111110 (g) 000101 (h) 1110110
18. Solve Problem 17, given that an active-LOW (0) output is required.
19. You wish to detect only the presence of the codes 1010, 1100, 0001, and 1011. An active-
HIGH output is required to indicate their presence. Develop the minimum decoding logic with
a single output that will indicate when any one of these codes is on the inputs. For any other
code, the output must be LOW.
20. If the input waveforms are applied to the decoding logic as indicated in Figure 676, sketch the
output waveform in proper relation to the inputs.

A0
A0
A1
A1 Y
A2

A2

FIGURE 676
 Problems 377

21. BCD numbers are applied sequentially to the BCD-to-decimal decoder in Figure 677. Draw
a timing diagram, showing each output in the proper relationship with the others and with the
inputs.

BCD/DEC
0
A0 1
2
A0 1
A1 3
A1 2
4
A2 A2 4
5
A3 8
A3 6
7
8
9

74HC42
FIGURE 677

22. A 7-segment decoder/driver drives the display in Figure 678. If the waveforms are applied as
indicated, determine the sequence of digits that appears on the display.

BCD/7-seg
A0
a
A1 A0 1 b
A1 2 c
A2
A2 4 d
A3 A3 8 e
f
g

FIGURE 678

Section 66 Encoders
23. For the decimal-to-BCD encoder logic of Figure 637, assume that the 9 input and the 3 input
are both HIGH. What is the output code? Is it a valid BCD (8421) code?
24. A 74HC147 encoder has LOW levels on pins 2, 5, and 12. What BCD code appears on the
outputs if all the other inputs are HIGH?

Section 67 Code Converters

25. Convert each of the following decimal numbers to BCD and then to binary.
(a) 4 (b) 7 (c) 12 (d) 23 (e) 34
26. Show the logic required to convert a 10-bit binary number to Gray code and use that logic to
convert the following binary numbers to Gray code:
(a) 1010111100 (b) 1111000011 (c) 1011110011 (d) 1000000001
27. Show the logic required to convert a 10-bit Gray code to binary and use that logic to convert
the following Gray code words to binary:
(a) 1010111100 (b) 1111000011 (c) 1011110011 (d) 1000000001
378 Functions of Combinational Logic

Section 68 Multiplexers (Data Selectors)

28. For the multiplexer in Figure 679, determine the output for the following input states: D0 = 1,
D1 = 0, D2 = 0, D3 = 1, S0 = 0, S1 = 1.

MUX
S0 0
G 03
S1 1
D0 0
Y
D1 1
D2 2
D3 3

FIGURE 679

29. If the data-select inputs to the multiplexer in Figure 679 are sequenced as shown by the wave-
forms in Figure 680, determine the output waveform with the data inputs specified in Problem 28.

S0

S1

FIGURE 680

30. The waveforms in Figure 681 are observed on the inputs of a 74HC151 8-input multiplexer.
Sketch the Y output waveform.

S0

S1
Select
inputs
S2

Enable
D0

D1

D2

D3
Data
inputs
D4

D5

D6

D7

FIGURE 681

Section 69 Demultiplexers
31. Develop the total timing diagram (inputs and outputs) for a 74HC154 used in a demultiplexing
application in which the inputs are as follows: The data-select inputs are repetitively sequenced
through a straight binary count beginning with 0000, and the data input is a serial data stream
carrying BCD data representing the decimal number 2468. The least significant digit (8) is first
in the sequence, with its LSB first, and it should appear in the first 4-bit positions of the output.
 Problems 379

Section 610 Parity Generators/Checkers

32. The waveforms in Figure 682 are applied to the 4-bit parity logic. Determine the output wave-
form in proper relation to the inputs. For how many bit times does even parity occur, and how
is it indicated? The timing diagram includes eight bit times.

Bit
time

A0

A1

A2

A3

FIGURE 682

33. Determine the Even and the Odd outputs of a 74HC280 9-bit parity generator/checker for
the inputs in Figure 683. Refer to the function table in Figure 656.

EVEN

ODD

A0

A1

A2

A3

A4

A5

A6

A7

FIGURE 683

Section 611 Troubleshooting

34. The full-adder in Figure 684 is tested under all input conditions with the input waveforms
shown. From your observation of the and Cout waveforms, is it operating properly, and if
not, what is the most likely fault?

A
B A

Cin
B
Cout

Cin
Cout

FIGURE 684
380 Functions of Combinational Logic

35. List the possible faults for each decoder/display in Figure 685.

BCD/7-seg BCD/7-seg BCD/7-seg

a a a
b b b
1 1 0 1 0 1
0 2 c 0 2 c 1 2 c
0 4 d 0 4 d 1 4 d
1 8 e 1 8 e 0 8 e
f f f
g g g

(a) (b) (c)

FIGURE 685

36. Develop a systematic test procedure to check out the complete operation of the keyboard
encoder in Figure 639.
37. You are testing a BCD-to-binary converter consisting of 4-bit adders as shown in Figure 686.
First verify that the circuit converts BCD to binary. The test procedure calls for applying BCD
numbers in sequential order beginning with 010 and checking for the correct binary output.
What symptom or symptoms will appear on the binary outputs in the event of each of the fol-
lowing faults? For what BCD number is each fault first detected?
(a) The A1 input is open (top adder).
(b) The Cout is open (top adder).
(c) The 4 output is shorted to ground (top adder).
(d) The 32 output is shorted to ground (bottom adder).

BCD tens digit BCD units digit

B3 B2 B1 B0 A 3 A2 A1 A0

4 3 2 1 4 3 2 1 Cin
B A

Cout 4 3 2 1

4 3 2 1 4 3 2 1 Cin
B A

Cout 4 3 2 1

64 32 16 8 4 2 1

7-bit binary output

FIGURE 686
 Problems 381

38. For the 7-segment display multiplexing system in Figure 649, determine the most likely cause
or causes for each of the following symptoms:
(a) The B-digit (MSD) display does not turn on at all.
(b) Neither 7-segment display turns on.
(c) The f-segment of both displays appears to be on all the time.
(d) There is a visible flicker on the displays.
39. Develop a systematic procedure to fully test the 74HC151 data selector IC.
40. During the testing of the data transmission system in Figure 658, a code is applied to the D0
through D6 inputs that contains an odd number of 1s. A single bit error is deliberately intro-
duced on the serial data transmission line between the MUX and the DEMUX, but the system
does not indicate an error (error output = 0). After some investigation, you check the inputs
to the even parity checker and find that D0 through D6 contain an even number of 1s, as you
would expect. Also, you find that the D7 parity bit is a 1. What are the possible reasons for the
system not indicating the error?
41. In general, describe how you would fully test the data transmission system in Figure 658, and
specify a method for the introduction of parity errors.

Applied Logic
42. Use a 74HC00 (quad NAND gates) and any other devices that may be required to produce
active-HIGH outputs for the given inputs of the state decoder.
43. Implement the light output logic with the 74HC00 if active-LOW outputs are required.

Special Design Problems

44. Modify the design of the 7-segment display multiplexing system in Figure 649 to accommo-
date two additional digits.
45. Using Table 62, write the SOP expressions for the and Cout of a full-adder. Use a Karnaugh
map to minimize the expressions and then implement them with inverters and AND-OR logic.
Show how you can replace the AND-OR logic with 74HC151 data selectors.
46. Implement the logic function specified in Table 614 by using a 74HC151 data selector.

TABLE 614
Inputs Output
A3 A2 A1 A0 Y

0 0 0 0 0
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0
0 1 0 1 0
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1

47. Using two of the 6-position adder modules from Figure 613, design a 12-position voting
system.
48. The adder block in the tablet-bottling system in Figure 687 performs the addition of the 8-bit
binary number from the counter and the 16-bit binary number from Register B. The result from
382 Functions of Combinational Logic

Tablets/bottle
7 8 9 Encoder
4 bits Decoder
4 5 6 Register A A
Decimal
1 2 3 2-digit BCD BCD to
to BCD 7-seg
0 . #

Keypad

Code
converter 8 bits

8 bits BCD to Comp

binary A
A=B
B Total tablets bottled
8 bits

Valve
Counter Adder 16 bits
Sensor A Register B
8-bit binary
16-bit binary
Code Decoder
B Cout converter B
Conveyor Binary BCD to
control to BCD 7-seg

MUX

16 bits

Switching sequence
control input
FIGURE 687

the adder goes back into Register B. Use 74HC283s to implement this function and draw a
complete logic diagram including pin numbers. This is similar to the system in Section 14.
49. Use 74HC85s to implement the comparator block in the tablet-bottling system in Figure 687
and draw a complete logic diagram including pin numbers. The comparator compares the 8-bit
binary number (actually only seven bits are required) from the BCD-to-binary converter with
the 8-bit binary number from the counter.
50. Two BCD-to-7-segment decoders are used in the tablet-bottling system in Figure 687. One is
required to drive the 2-digit tablets/bottle display and the other to drive the 5-digit total tablets
bottled display. Use 74HC47s to implement each decoder and draw a complete logic diagram
including pin numbers.
51. The encoder shown in the system block diagram of Figure 687 encodes each decimal key
closure and converts it to BCD. Use a 74HC147 to implement this function and draw a
complete logic diagram including pin numbers.
52. The system in Figure 687 requires two code converters. The BCD-to-binary converter changes
the 2-digit BCD number in Register A to an 8-bit binary code (actually only 7 bits are required
because the MSB is always 0). Use appropriate fixed-function IC code converters to implement
the BCD-to-binary converter function and draw a complete logic diagram including pin numbers.

Multisim Troubleshooting Practice

53. Open file P06-53. For the specified fault, predict the effect on the circuit. Then introduce the
fault and verify whether your prediction is correct.
 Answers 383

54. Open file P06-54. For the specified fault, predict the effect on the circuit. Then introduce the
fault and verify whether your prediction is correct.
55. Open file P06-55. For the observed behavior indicated, predict the fault in the circuit. Then
introduce the suspected fault and verify whether your prediction is correct.
56. Open file P06-56. For the observed behavior indicated, predict the fault in the circuit. Then
introduce the suspected fault and verify whether your prediction is correct.

ANSWERS
SECTION CHECKUPS
Section 61 Half and Full Adders
1. (a) = 1, C out = 0
(b) = 0, C out = 0
(c) = 1, C out = 0
(d) = 0, C out = 1
2. = 1, C out = 1

Section 62 Parallel Binary Adders

1. C out 4 3 2 1 = 11001
2. Three 74HC283s are required to add two 10-bit numbers.

Section 63 Ripple Carry and Look-Ahead Carry Adders

1. Cg = 0, Cp = 1
2. Cout = 1

Section 64 Comparators
1. A 7 B = 1, A 6 B = 0, A = B = 0 when A = 1011 and B = 1010
2. Right comparator: A 6 B = 1; A = B = 0; A 7 B = 0
Left comparator: A 6 B = 0; A = B = 0; A 7 B = 1

Section 65 Decoders
1. Output 5 is active when 101 is on the inputs.
2. Four 74HC154s are used to decode a 6-bit binary number.
3. Active-HIGH output drives a common-cathode LED display.

Section 66 Encoders
1. (a) A0 = 1, A1 = 1, A2 = 0, A3 = 1
(b) No, this is not a valid BCD code.
(c) Only one input can be active for a valid output.
2. (a) A3 = 0, A2 = 1, A1 = 1, A0 = 1
(b) The output is 0111, which is the complement of 1000 (8).

Section 67 Code Converters

1. 10000101 (BCD) = 10101012
2. An 8-bit binary-to-Gray converter consists of seven exclusive-OR gates in an arrangement like
that in Figure 640 but with inputs B0B7.

Section 68 Multiplexers (Data Selectors)

1. The output is 0.
2. (a) 74HC153: Dual 4-input data selector/multiplexer
(b) 74HC151: 8-input data selector/multiplexer
384 Functions of Combinational Logic

3. The data output alternates between LOW and HIGH as the data-select inputs sequence through
the binary states.
4. (a) The 74HC157 multiplexes the two BCD codes to the 7-segment decoder.
(b) The 74HC47 decodes the BCD to energize the display.
(c) The 74HC139 enables the 7-segment displays alternately.

Section 69 Demultiplexers
1. A decoder can be used as a multiplexer by using the input lines for data selection and an
Enable line for data input.
2. The outputs are all HIGH except D10, which is LOW.

Section 610 Parity Generators/Checkers

1. (a) Even parity: 1110100 (b) Even parity: 001100011
2. (a) Odd parity: 11010101 (b) Odd parity: 11000001
3. (a) Code is correct, four 1s. (b) Code is in error, seven 1s

Section 611 Troubleshooting

1. A glitch is a very short-duration voltage spike (usually unwanted).
2. Glitches are caused by transition states.
3. Strobe is the enabling of a device for a specified period of time when the device is not in transition.

RELATED PROBLEMS FOR EXAMPLES

61 = 1, Cout = 1
62 1 = 0, 2 = 0, 3 = 1, 4 = 1
63 1011 + 1010 = 10101
64 See Figure 688.

1 1 1
2 2 2
A A A
3 3 3
4 1 4 1 4 1
1 2 1 2 1 2
2 3 2 3 2 3
B 4 B 4 B 4
3 3 3
4 4 4

C0 C4 C0 C4 C0 C4

Lowest-order adder Highest-order adder

FIGURE 688

65 See Figure 689.

A0 = 1 0
B0 = 0
0 not equal
A1 = 0
B1 = 1 0

FIGURE 689

66 A 7 B = 0, A = B = 0, A 6 B = 1
 Answers 385

67 See Figure 690.

68 See Figure 691.
69 Output 22

0 Comp 0 Comp 0 Comp 0 Comp

A A A A

3 3 3 3
A>B A>B A>B A>B A>B A>B A>B A>B A0
+5 V A=B A=B A=B A=B A=B A=B A=B A=B
A<B A<B A<B A<B A<B A<B A<B A<B
A1
0 0 0 0 A2 X
B B B B

3 3 3 3 A3
Lowest-order comparator Highest-order comparator
A4

FIGURE 690 FIGURE 691

610 See Figure 692.

611 All inputs LOW: A0 = 0, A1 = 1, A2 = 1, A3 = 0

A0
A1
A2
A3
0
1
2
3
4
5
6
7
8
9

FIGURE 692

All inputs HIGH: All outputs HIGH.

612 BCD 01000001
7 00000001 1
7 00101000 40
Binary 00101001 41

613 Seven exclusive-OR gates

614 See Figure 693.

S0
S1
Y
FIGURE 693
386 Functions of Combinational Logic

615 D0: S 3 = 0, S 2 = 0, S 1 = 0, S 0 = 0
D4: S 3 = 0, S 2 = 1, S 1 = 0, S 0 = 0
D8: S 3 = 1, S 2 = 0, S 1 = 0, S 0 = 0
D13: S 3 = 1, S 2 = 1, S 1 = 0, S 0 = 1
616 See Figure 694.

EN MUX

A0 0
A1 G 07
A2 2
0
1 Y = A2 A1A0 + A2 A1A0 + A2 A1A0
+5 V 2
3
4
5
6
7

74HC151

FIGURE 694

617 See Figure 695.

EN MUX

A1 0
A2 G 07
A3 2
A0 0
1 Y = A3 A2 A1A0 + A3 A2 A1A0
2
+ A3 A2 A1A0 + A3 A2 A1A0
3
4 + A3 A2 A1A0 + A3 A2 A1A0
5
6 + A3 A2 A1A0 + A3 A2 A1A0
7

74HC151

FIGURE 695

618 See Figure 696.

S0
S1
D0
D1
D2
D3
FIGURE 696

TRUE/FALSE QUIZ
1. T 2. F 3. F 4. F 5. T
6. F 7. T 8. F 9. T 10. F

SELF-TEST
1. (a) 2. (b) 3. (a) 4. (b) 5. (d) 6. (c)
7. (c) 8. (b) 9. (a) 10. (d) 11. (b) 12. (f)
 Problems 439

11. The output pulse width of a nonretriggerable one-shot depends on

(a) the trigger intervals (b) the supply voltage
(c) a resistor and capacitor (d) the threshold voltage
12. An astable multivibrator
(a) requires a periodic trigger input (b) has no stable state
(c) is an oscillator (d) produces a periodic pulse output
(e) answers (a), (b), (c), and (d) (f) answers (b), (c), and (d) only

PROBLEMS

Answers to odd-numbered problems are at the end of the book.

Section 71 Latches
1. If the waveforms in Figure 770 are applied to an active-HIGH S-R latch, draw the resulting Q
output waveform in relation to the inputs. Assume that Q starts LOW.

S Q
S

R
R Q

FIGURE 770

2. Solve Problem 1 for the input waveforms in Figure 771 applied to an active-LOW
S - R latch.

FIGURE 771

3. Solve Problem 1 for the input waveform in Figure 772.

FIGURE 772

4. For a gated S-R latch, determine the Q and Q outputs for the inputs in Figure 773. Show them
in proper relation to the enable input. Assume that Q starts LOW.

S S Q

EN
EN

R R Q

FIGURE 773
440 Latches, Flip-Flops, and Timers

5. Determine the output of a gated D latch for the inputs in Figure 774.

EN

FIGURE 774

6. Determine the output of a gated D latch for the inputs in Figure 775.

EN

FIGURE 775

7. For a gated D latch, the waveforms shown in Figure 776 are observed on its inputs. Draw
the timing diagram showing the output waveform you would expect to see at Q if the latch is
initially RESET.

EN

FIGURE 776

Section 72 Flip-Flops
8. Two edge-triggered J-K flip-flops are shown in Figure 777. If the inputs are as shown, draw
the Q output of each flip-flop relative to the clock, and explain the difference between the two.
The flip-flops are initially RESET.

J Q J Q
CLK

J CLK C CLK C

K K Q K Q

(a) (b)

FIGURE 777

9. The Q output of an edge-triggered D flip-flop is shown in relation to the clock signal in Figure
778. Determine the input waveform on the D input that is required to produce this output if
the flip-flop is a positive edge-triggered type.

CLK

FIGURE 778

10. Draw the Q output relative to the clock for a D flip-flop with the inputs as shown in
Figure 779. Assume positive edge-triggering and Q initially LOW.

CLK

FIGURE 779
 Problems 441

11. Solve Problem 10 for the inputs in Figure 780.

CLK

FIGURE 780

12. For a positive edge-triggered D flip-flop with the input as shown in Figure 781, determine the
Q output relative to the clock. Assume that Q starts LOW.

CLK

FIGURE 781

13. Solve Problem 12 for the input in Figure 782.

CLK

FIGURE 782

14. Determine the Q waveform relative to the clock if the signals shown in Figure 783 are applied
to the inputs of the J-K flip-flop. Assume that Q is initially LOW.

CLK
PRE

J
J Q

K C

K Q
PRE

CLR CLR

FIGURE 783

15. For a negative edge-triggered J-K flip-flop with the inputs in Figure 784, develop the Q output
waveform relative to the clock. Assume that Q is initially LOW.

CLK

FIGURE 784
442 Latches, Flip-Flops, and Timers

16. The following serial data are applied to the flip-flop through the AND gates as indicated in
Figure 785. Determine the resulting serial data that appear on the Q output. There is one clock
pulse for each bit time. Assume that Q is initially 0 and that PRE and CLR are HIGH. Right-
most bits are applied first.
J1: 1 0 1 0 0 1 1; J2: 0 1 1 1 0 1 0; J3: 1 1 1 1 0 0 0; K1: 0 0 0 1 1 1 0; K2: 1 1 0 1 1 0 0;
K3: 1 0 1 0 1 0 1
17. For the circuit in Figure 785, complete the timing diagram in Figure 786 by showing the Q
output (which is initially LOW). Assume PRE and CLR remain HIGH.

CLK

J1

PRE J2
J1
J2 J Q J3
J3
CLK C K1
K1
K2 K Q K2
K3
CLR K3

FIGURE 785 FIGURE 786

18. Solve Problem 17 with the same J and K inputs but with the PRE and CLR inputs as shown in
Figure 787 in relation to the clock.

CLK

PRE

CLR

FIGURE 787

Section 73 Flip-Flop Operating Characteristics

19. What determines the power dissipation of a flip-flop?
20. Typically, a flip-flop is limited in its operation due to hold time and setup time. Explain how.
21. The datasheet of a certain flip-flop specified that the minimum HIGH time for the clock pulse
is 20 ns and the minimum LOW time is 40 ns. What is the maximum operating frequency?
22. The flip-flop in Figure 788 is initially RESET. Show the relation between Q output and the
clock pulse if the propagation delay tPLH (clock to Q) is 5 ns.

HIGH

D Q

CLK C
30 ns
Q

FIGURE 788

23. The direct current required by a particular flip-flop that operates on a +4 V dc source is found
to be 8 mA. A certain digital device uses 16 of these flip-flops. Determine the current capacity
required for the +4 V dc supply and the total power dissipation of the system.
 Problems 443

24. For the circuit in Figure 789, determine the maximum frequency of the clock signal for
reliable operation if the set-up time for each flip-flop is 3 ns and the propagation delays (tPLH
and tPHL) from clock to output are 6 ns for each flip-flop.

HIGH

QA
JA JB QB

C C
QA
KA KB QB

Flip-flop A Flip-flop B
CLK

FIGURE 789

Section 74 Flip-Flop Applications

25. A D flip-flop is connected as shown in Figure 790. Determine the Q output in relation to the
clock. What specific function does this device perform?

D Q

CLK C

FIGURE 790

26. For the circuit in Figure 789, develop a timing diagram for eight clock pulses, showing the QA
and QB outputs in relation to the clock.

Section 75 One-Shots
27. Determine the pulse width of a 74121 one-shot if the external resistor is 1 kV and the external
capacitor is 1 pF.
28. An output pulse of 3 ms duration is to be generated by a 74LS122 one-shot. Using a capacitor
of 50,000 pF, determine the value of external resistance required.
29. Create a one-shot using a 555 timer that will produce a 0.5 s output pulse.

Section 76 The Astable Multivibrator

30. A 555 timer is configured to run as an astable multivibrator as shown in Figure 791.
Determine its frequency.
+VCC

(4) (8)
R1
(2) (7) 2.0 k

R2
(6) 4.3 k
555

(3) (5) C
0.1 F
(1)

Output

FIGURE 791
444 Latches, Flip-Flops, and Timers

31. Determine the values of the external resistors for a 555 timer used as an astable multivibrator
with an output frequency of 10 kHz, if the external capacitor C is 0.004 mF and the duty cycle
is to be approximately 80%.

Section 77 Troubleshooting
32. The flip-flop in Figure 792 is tested under all input conditions as shown. Is it operating prop-
erly? If not, what is the most likely fault?

+V +V

Q Q
J J

C C

K K

(a) (b)

Q Q
J J

C C

K +V K

(c) (d)

FIGURE 792

33. A 74HC00 quad NAND gate IC is used to construct a gated S-R latch on a protoboard in the
lab as shown in Figure 793. The schematic in part (a) is used to connect the circuit in part (b).
When you try to operate the latch, you find that the Q output stays HIGH no matter what the
inputs are. Determine the problem.

+5 V GND

(4)
S (6) (10) (8)
(5) (9) Q

R
74HC00

EN

(12) S
(2)
(3) (13) Q
(1) (11) EN
R

(a) (b)

FIGURE 793
 Problems 445

34. Determine if the flip-flop in Figure 794 is operating properly, and if not, identify the most
probable fault.

J
J Q
CLK
C

K
K Q

FIGURE 794

35. The parallel data storage circuit in Figure 735 does not operate properly. To check it out, you
first make sure that VCC and ground are connected, and then you apply LOW levels to all the D
inputs and pulse the clock line. You check the Q outputs and find them all to be LOW; so far,
so good. Next you apply HIGHs to all the D inputs and again pulse the clock line. When you
check the Q outputs, they are still all LOW. What is the problem, and what procedure will you
use to isolate the fault to a single device?
36. The flip-flop circuit in Figure 795(a) is used to generate a binary count sequence. The gates
form a decoder that is supposed to produce a HIGH when a binary zero or a binary three state
occurs (00 or 11). When you check the QA and QB outputs, you get the display shown in part
(b), which reveals glitches on the decoder output (X) in addition to the correct pulses. What is
causing these glitches, and how can you eliminate them?

CLK

QA QB G1 QA
D D

CLK C C G3 X QB

QA QB
G2 X

Glitch Glitch
(a) (b)

FIGURE 795

37. Determine the QA, QB and X outputs over six clock pulses in Figure 795(a) for each of the
following faults in the bipolar (TTL) circuits. Start with both QA and QB LOW.
(a) D input open (b) QB output open
(c) clock input to flip-flop B shorted (d) gate G2 output open
38. Two 74121 one-shots are connected on a circuit board as shown in Figure 796. After observ-
ing the oscilloscope display, do you conclude that the circuit is operating properly? If not, what
is the most likely problem?

Applied Logic
39. Using 555 timers, redesign the timing circuits portion of the traffic signal controller for an
approximate 5 s caution light and 30 s red and green lights.
40. Repeat Problem 39 using 74121 one-shots.
41. Repeat Problem 39 using 74122 one-shots.
42. Implement the input logic in the sequential circuit unit of the traffic signal controller using only
NAND gates.
43. Specify how you would change the time interval for the green light from 25 s to 60 s.
446 Latches, Flip-Flops, and Timers

0.47 F 0.22 F

47 k 47 k
1

74121 74121 2

Ch1 5 V Ch2 5 V 1 ms

VCC 1 2 GND

FIGURE 796

Special Design Problems

44. Design a basic counting circuit that produces a binary sequence from zero through seven by
using negative edge-triggered J-K flip-flops.
45. In the shipping department of a softball factory, the balls roll down a conveyor and through a
chute single file into boxes for shipment. Each ball passing through the chute activates a switch
circuit that produces an electrical pulse. The capacity of each box is 32 balls. Design a logic
circuit to indicate when a box is full so that an empty box can be moved into position.
46. List the design changes that would be necessary in the traffic signal controller to add a 15 s
left turn arrow for the main street. The turn arrow will occur after the red light and prior to the
green light. Modify the state diagram from Chapter 6 to show these changes.

Multisim Troubleshooting Practice

47. Open file P07-47. For the specified fault, predict the effect on the circuit. Then introduce the
fault and verify whether your prediction is correct.
48. Open file P07-48. For the specified fault, predict the effect on the circuit. Then introduce the
fault and verify whether your prediction is correct.
49. Open file P07-49. For the observed behavior indicated, predict the fault in the circuit. Then
introduce the suspected fault and verify whether your prediction is correct.
50. Open file P07-50. For the observed behavior indicated, predict the fault in the circuit. Then
introduce the suspected fault and verify whether your prediction is correct.
51. Open file P07-51. For the observed behavior indicated, predict the fault in the circuit. Then
introduce the suspected fault and verify whether your prediction is correct.

ANSWERS

SECTION CHECKUPS
Section 71 Latches
1. Three types of latches are S-R, gated S-R, and gated D.
2. SR = 00, NC; SR = 01, Q = 0; SR = 10, Q = 1; SR = 11, invalid
3. Q = 1

Section 72 Flip-Flops
1. The output of a gated D latch can change any time the gate enable (EN) input is active. The
output of an edge-triggered D flip-flop can change only on the triggering edge of a clock pulse.
2. The output of a J-K flip-flop is determined by the state of its two inputs whereas the output of a
D flip-flop follows the input.
3. Output Q goes HIGH on the trailing edge of the first clock pulse, LOW on the trailing edge of
the second pulse, HIGH on the trailing edge of the third pulse, and LOW on the trailing edge of
the fourth pulse.
 Answers 447

Section 73 Flip-Flop Operating Characteristics

1. (a) Set-up time is the time required for input data to be present before the triggering edge of
the clock pulse.
(b) Hold time is the time required for data to remain on the inputs after the triggering edge of
the clock pulse.
2. The 74AHC74 can be operated at the highest frequency, according to Table 74.

Section 74 Flip-Flop Applications

1. A group of data storage flip-flops is a register.
2. For divide-by-2 operation, the flip-flop must toggle (D = Q).
3. Six flip-flops are used in a divide-by-64 device.

Section 75 One-Shots
1. A nonretriggerable one-shot times out before it can respond to another trigger input. A retrig-
gerable one-shot responds to each trigger input.
2. Pulse width is set with external R and C components.
3. 11 ms.

Section 76 The Astable Multivibrator

1. An astable multivibrator has no stable state. A monostable multivibrator has one stable state.
2. Duty cycle = (15 ms/20 ms)100% = 75%

Section 77 Troubleshooting
1. Yes, a negative edge-triggered J-K flip-flop can be used.
2. An astable multivibrator using a 555 timer can be used to provide the clock.

RELATED PROBLEMS FOR EXAMPLES

71 The Q output is the same as shown in Figure 75(b).
72 See Figure 797.

S
R
EN

Q Uncertainty
FIGURE 797

73 See Figure 798.

74 See Figure 799.

CLK 10 1 2 3 4 5 6

D D 10
EN Q
Q Q
FIGURE 798 FIGURE 799

75 See Figure 7100.

76 See Figure 7101.
CLK 1 2 3 4 5
J CLK
K D
Q Q
FIGURE 7100 FIGURE 7101
448 Latches, Flip-Flops, and Timers

77 See Figure 7102.

CLK 1 2 3 4 5 6 7 8 9

PRE
CLR

FIGURE 7102

78 See Figure 7103.

PIN 1 (1CLK)
PIN 2 (1J)
PIN 3 (1K)
PIN 4 (1CLR)
PIN 15 (1PRE)

PIN 5 (1Q)

FIGURE 7103

79 25 = 32. Five flip-flops are required.

710 Sixteen states require four flip-flops (24 = 16).
711 CEXT = 7143 pF connected from CX to RX/CX of the 74121 with no external resistor.
712 CEXT = 560 pF, REXT = 27 k. See Figure 7104.

+5 V
74LS122
(1)
1 &
(2) (8)
Q Output pulse
(3)
(4)
Trigger (6)
(5) Q

RI CX RX/CX
(9) (10) (11)

N/C
CEXT REXT
560 pF 27 k

+5 V
FIGURE 7104

713 R1 = 91 k
714 Duty cycle  32%

TRUE/FALSE QUIZ
1. F 2. T 3. F 4. T 5. F 6. T 7. T 8. F 9. T 10. F

SELF-TEST
1. (a) 2. (c) 3. (b) 4. (d) 5. (d) 6. (d)
7. (a) 8. (c) 9. (d) 10. (d) 11. (c) 12. (f)
 Problems 551

9. Which one of the following is an example of a counter with a truncated modulus?

(a) Modulus 8 (b) Modulus 14
(c) Modulus 16 (d) Modulus 32
10. A 4-bit ripple counter consists of flip-flops that each have a propagation delay from clock to Q
output of 12 ns. For the counter to recycle from 1111 to 0000, it takes a total of
(a) 12 ns (b) 24 ns
(c) 48 ns (d) 36 ns
11. A BCD counter is an example of
(a) a full-modulus counter (b) a decade counter
(c) a truncated-modulus counter (d) answers (b) and (c)
12. Which of the following is a valid state in an 8421 BCD counter?
(a) 1010 (b) 1011
(c) 1111 (d) 1000
13. Three cascaded modulus-10 counters have an overall modulus of
(a) 30 (b) 100
(c) 1000 (d) 10,000
14. A 10 MHz clock frequency is applied to a cascaded counter consisting of a modulus-5 counter,
a modulus-8 counter, and two modulus-10 counters. The lowest output frequency possible is
(a) 10 kHz (b) 2.5 kHz
(c) 5 kHz (d) 25 kHz
15. A 4-bit binary up/down counter is in the binary state of zero. The next state in the DOWN
mode is
(a) 0001 (b) 1111
(c) 1000 (d) 1110
16. The initial count of a modulus-13 binary counter is
(a) 0000 (b) 1111
(c) 1101 (d) 1100

PROBLEMS
Answers to odd-numbered problems are at the end of the book.

Section 91 Finite State Machines

1. Represent a decade counter with the terminal state decoded as a state machine. Identify the
type and show the block diagram and the state diagram.
2. Identify the type of state machine for the traffic signal controller in Chapter 6. State the reason
why it is the type you specified.

Section 92 Asynchronous Counters

3. For the ripple counter shown in Figure 965, show the complete timing diagram for eight clock
pulses, showing the clock, Q0, and Q1 waveforms.

D0 Q0 D1 Q1

CLK C C

Q0 Q1

FIGURE 965
552 Counters

4. For the ripple counter in Figure 966, show the complete timing diagram for sixteen clock
pulses. Show the clock, Q0, Q1, and Q2 waveforms.

D0 Q0 D1 Q1 D2 Q2

CLK C C C

Q0 Q1 Q2

FIGURE 966

5. In the counter of Problem 4, assume that each flip-flop has a propagation delay from the trig-
gering edge of the clock to a change in the Q output of 8 ns. Determine the worst-case (longest)
delay time from a clock pulse to the arrival of the counter in a given state. Specify the state or
states for which this worst-case delay occurs.
6. Show how to connect a 74HC93 4-bit asynchronous counter for each of the following moduli:
(a) 9 (b) 11 (c) 13 (d) 14 (e) 15

Section 93 Synchronous Counters

7. If the counter of Problem 5 were synchronous rather than asynchronous, what would be the
longest delay time?
8. Show the complete timing diagram for the 5-stage synchronous binary counter in Figure 967. Verify
that the waveforms of the Q outputs represent the proper binary number after each clock pulse.

HIGH

Q0 Q1 Q2 Q3
J0 J1 J2 J3 J4 Q4

C C C C C

K0 K1 K2 K3 K4

CLK
FIGURE 967

9. By analyzing the J and K inputs to each flip-flop prior to each clock pulse, prove that the dec-
ade counter in Figure 968 progresses through a BCD sequence. Explain how these conditions
in each case cause the counter to go to the next proper state.

HIGH

Q0
J0 J1 Q1 J2 Q2 J3
Q3

C C C C

Q3
K0 K1 K2 K3

FF0 FF1 FF2 FF3

CLK

FIGURE 968
 Problems 553

10. The waveforms in Figure 969 are applied to the count enable, clear, and clock inputs as indi-
cated. Show the counter output waveforms in proper relation to these inputs. The clear input is
asynchronous.

CTEN
CTEN CTR DIV 16
CLK CLK C
CLR CLR
CLR
Q0 Q1 Q2 Q3

FIGURE 969

11. A BCD decade counter is shown in Figure 970. The waveforms are applied to the clock and
clear inputs as indicated. Determine the waveforms for each of the counter outputs (Q0, Q1, Q2,
and Q3). The clear is synchronous, and the counter is initially in the binary 1000 state.

CTR DIV 10

CLK C

CLR

Q0 Q1 Q2 Q3

FIGURE 970

12. The waveforms in Figure 971 are applied to a 74HC163 binary counter. Determine the Q
outputs and the RCO. The inputs are D0 = 1, D1 = 1, D2 = 0, and D3 = 1.

CLK

CLR

ENP

ENT

LOAD

FIGURE 971

13. The waveforms in Figure 971 are applied to a 74HC161 counter. Determine the Q outputs and
the RCO. The inputs are D0 = 1, D1 = 0, D2 = 0, and D3 = 1.

Section 94 Up/Down Synchronous Counters

14. Show a complete timing diagram for a 3-bit up/down counter that goes through the following
sequence. Indicate when the counter is in the UP mode and when it is in the DOWN mode.
Assume positive edge-triggering.
0, 1, 2, 3, 2, 1, 2, 3, 4, 5, 6, 5, 4, 3, 2, 1, 0
15. Develop the Q output waveforms for a 74HC190 up/down counter with the input waveforms
shown in Figure 972. A binary 0 is on the data inputs. Start with a count of 0000.

CLK

CTEN

D/U

LOAD
FIGURE 972
554 Counters

16. Repeat Problem 15 if the D/U input signal is inverted with the other inputs the same.
17. Repeat Problem 15 if the CTEN is inverted with the other inputs the same.

Section 95 Design of Synchronous Counters

18. Determine the sequence of the counter in Figure 973.

Q0 Q1
D0 D1 D2
Q2
C C C

CLK
FIGURE 973

19. Determine the sequence of the counter in Figure 974. Begin with the counter cleared.

HIGH

J0 J1 J2 J3
Q0 Q1 Q2 Q3
C C C C

K0 K1 K2 K3

CLK
FIGURE 974

20. Design a counter to produce the following sequence. Use J-K flip-flops.
00, 10, 01, 11, 00, c
21. Design a counter to produce the following binary sequence. Use J-K flip-flops.
1, 4, 3, 5, 7, 6, 2, 1, c
22. Design a counter to produce the following binary sequence. Use J-K flip-flops.
0, 9, 1, 8, 2, 7, 3, 6, 4, 5, 0, c
23. Design a binary counter with the sequence shown in the state diagram of Figure 975.

0 Up

11 Down 3

9 5

FIGURE 975
 Problems 555

Section 96 Cascaded Counters

24. For each of the cascaded counter configurations in Figure 976, determine the frequency of the
waveform at each point indicated by a circled number, and determine the overall modulus.

1 2 3
1 kHz DIV 4 DIV 8 DIV 2

(a)

1 2 3 4
100 kHz DIV 10 DIV 10 DIV 10 DIV 2

(b)

1 2 3 4 5
21 MHz DIV 3 DIV 6 DIV 8 DIV 10 DIV 10

(c)

1 2 3 4 5
39.4 kHz DIV 2 DIV 4 DIV 6 DIV 8 DIV 16

(d)

FIGURE 976

25. Expand the counter in Figure 938 to create a divide-by-10,000 counter and a divide-
by-100,000 counter.
26. With general block diagrams, show how to obtain the following frequencies from a 10 MHz
clock by using single flip-flops, modulus-5 counters, and decade counters:
(a) 5 MHz (b) 2.5 MHz (c) 2 MHz (d) 1 MHz (e) 500 kHz
(f) 250 kHz (g) 62.5 kHz (h) 40 kHz (i) 10 kHz (j) 1 kHz

Section 97 Counter Decoding

27. Given a BCD decade counter with only the Q outputs available, show what decoding logic is
required to decode each of the following states and how it should be connected to the counter.
A HIGH output indication is required for each decoded state. The MSB is to the left.
(a) 0001 (b) 0011 (c) 0101 (d) 0111 (e) 1000
28. For the 4-bit binary counter connected to the decoder in Figure 977, determine each of the
decoder output waveforms in relation to the clock pulses.

BIN/DEC
0
CTR DIV 16 1
2
3
4
Q0 5
1 6
Q1
2 7
Q2
8
4
Q3 9
8 10
11
12
CLK 13
C 14
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 15
EN

FIGURE 977
556 Counters

29. If the counter in Figure 977 is asynchronous, determine where the decoding glitches occur on
the decoder output waveforms.
30. Modify the circuit in Figure 977 to eliminate decoding glitches.
31. Analyze the counter in Figure 942 for the occurrence of glitches on the decode gate output. If
glitches occur, suggest a way to eliminate them.
32. Analyze the counter in Figure 943 for the occurrence of glitches on the outputs of the decod-
ing gates. If glitches occur, make a design change that will eliminate them.

Section 98 Counter Applications

33. Assume that the digital clock of Figure 948 is initially reset to 12 oclock. Determine the
binary state of each counter after sixty-two 60 Hz pulses have occurred.
34. What is the output frequency of each counter in the digital clock circuit of Figure 948?
35. For the automobile parking control system in Figure 951, a pattern of entrance and exit sensor
pulses during a given 24-hour period are shown in Figure 978. If there were 53 cars already in the
garage at the beginning of the period, what is the state of the counter at the end of the 24 hours?

Entrance
sensor

Exit
sensor
0 24 hrs
FIGURE 978

36. The binary number for decimal 57 appears on the parallel data inputs of the parallel-to-serial
converter in Figure 953 (D0 is the LSB). The counter initially contains all zeros and a 10 kHz
clock is applied. Develop the timing diagram showing the clock, the counter outputs, and the
serial data output.

Section 910 Troubleshooting

37. For the counter in Figure 94, show the timing diagram for the Q0 and Q1 waveforms for each
of the following faults (assume Q0 and Q1 are initially LOW):
(a) clock input to FF0 shorted to ground
(b) Q0 output open
(c) clock input to FF1 open
(d) D input to FF0 open
(e) D input to FF1 shorted to ground
38. Solve Problem 37 for the counter in Figure 912(b).
39. Isolate the fault in the counter in Figure 96 by analyzing the waveforms in Figure 979.
40. From the waveform diagram in Figure 980, determine the most likely fault in the counter of
Figure 915.

CLK 1 2 3 4 5 6 7 8
CLK 1 2 3 4 5 6 7 8
Q0
Q0

Q1 Q1

Q2 Q2
0

FIGURE 979 FIGURE 980

 Problems 557

41. Solve Problem 40 if the Q2 output has the waveform observed in Figure 981. Outputs Q0 and
Q1 are the same as in Figure 980.

CLK 1 2 3 4 5 6 7 8

Q2

FIGURE 981

42. You apply a 5 MHz clock to the cascaded counter in Figure 941 and measure a frequency of
76.2939 Hz at the last RCO output. Is this correct, and if not, what is the most likely problem?
43. Develop a table for use in testing the counter in Figure 941 that will show the frequency at the
final RCO output for all possible open failures of the parallel data inputs (D0, D1, D2, and D3)
taken one at a time. Use 10 MHz as the test frequency for the clock.
44. The tens-of-hours 7-segment display in the digital clock system of Figure 948 continuously
displays a 1. All the other digits work properly. What could be the problem?
45. What would be the visual indication of an open Q1 output in the tens portion of the minutes
counter in Figure 948? Also see Figure 949.
46. One day (perhaps a Monday) complaints begin flooding in from patrons of a parking garage
that uses the control system depicted in Figures 951 and 952. The patrons say that they enter
the garage because the gate is up and the FULL sign is off but that, once in, they can find no
empty space. As the technician in charge of this facility, what do you think the problem is, and
how will you troubleshoot and repair the system as quickly as possible?

Applied Logic
47. Propose a general design for generation of the 3-bit FLRCALL code and the Call pulse by the
pressing of a single button.
48. Propose a general design for generation of the 3-bit FLRREQ code and the Request pulse by
the pressing of one of seven buttons.
49. What changes are required to the logic diagram in Figure 964 to modify the elevator control-
ler for a four-story building?

Special Design Problems

50. Design a modulus-1000 counter by using decade counters.
51. Modify the design of the counter in Figure 941 to achieve a modulus of 30,000.
52. Repeat Problem 51 for a modulus of 50,000.
53. Modify the digital clock in Figures 948, 949, and 950 so that it can be preset to any desired time.
54. Design an alarm circuit for the digital clock that can detect a predetermined time (hours and
minutes only) and produce a signal to activate an audio alarm.
55. Modify the design of the circuit in Figure 952 for a 1000-space parking garage and a 3000-
space parking garage.
56. Implement the parallel-to-serial data conversion logic in Figure 953 with specific fixed-
function devices.
57. In Problem 19 it was found that the counter locks up and alternates between two states. It turns
out that this operation is the result of a design flaw. Redesign the counter so that when it goes
into the second of the lock-up states, it will recycle to the all-0s state on the next clock pulse.

Multisim Troubleshooting Practice

58. Open file P09-58. For the specified fault, predict the effect on the circuit. Then introduce the
fault and verify whether your prediction is correct.
59. Open file P09-59. For the specified fault, predict the effect on the circuit. Then introduce the
fault and verify whether your prediction is correct.
60. Open file P09-60. For the specified fault, predict the effect on the circuit. Then introduce the
fault and verify whether your prediction is correct.
558 Counters

61. Open file P09-61. For the observed behavior indicated, predict the fault in the circuit. Then
introduce the suspected fault and verify whether your prediction is correct.
62. Open file P09-62. For the observed behavior indicated, predict the fault in the circuit. Then
introduce the suspected fault and verify whether your prediction is correct.

ANSWERS
SECTION CHECKUPS
Section 91 Checkup
1. A finite state machine is a sequential circuit having a finite number of states that occur in a
specified order.
2. Moore state machine and Mealy state machine
3. The Moore state machine has an output(s) that is dependent on the present internal state only.
The Mealy state machine has an output(s) that is dependent on both the present internal state
and the value of the inputs.

Section 92 Asynchronous Counters

1. Asynchronous means that each flip-flop after the first one is enabled by the output of the pre-
ceding flip-flop.
2. A modulus-14 counter has fourteen states requiring four flip-flops.

Section 93 Synchronous Counters

1. All flip-flops in a synchronous counter are clocked simultaneously.
2. The counter can be preset (initialized) to any given state.
3. Counter is enabled when ENP and ENT are both HIGH; RCO goes HIGH when final state in
sequence is reached.

Section 94 Up/Down Synchronous Counters

1. The counter goes to 1001.
2. UP: 1111: DOWN: 0000; the next state is 1111.

Section 95 Design of Synchronous Counters

1. J = 1, K = X (dont care)
2. J = X (dont care), K = 0
3. (a) The next state is 1011.
(b) Q3 (MSB): no-change or SET; Q2: no-change or RESET; Q1: no change or SET;
Q0 (LSB): SET or toggle

Section 96 Cascaded Counters

1. Three decade counters produce , 1000; 4 decade counters produce , 10,000.
2. (a) , 20: flip-flop and DIV 10
(b) , 32: flip-flop and DIV 16
(c) , 160: DIV 16 and DIV 10
(d) , 320: DIV 16 and DIV 10 and flip-flop

Section 97 Counter Decoding

1. (a) No transitional states because there is a single bit change
(b) 0000, 0001, 0010, 0101, 0110, 0111
(c) No transitional states because there is a single bit change
(d) 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110
 Answers 559

Section 98 Counter Applications

1. Gate G1 resets flip-flop on first clock pulse after count 9. Gate G2 decodes count 12 to preset
counter to 0001.
2. The hours decade counter advances through each state from zero to nine, and as it recycles
from nine back to zero, the flip-flop is toggled to the SET state. This produces a ten (10) on
the display. When the hours decade counter is in state 12, the decode NAND gate causes the
counter to recycle to state 1 on the next clock pulse. The flip-flop resets. This results in a one
(01) on the display.

Section 99 Logic Symbols with Dependency Notation

1. C: control, usually clock; M: mode; G: AND
2. D indicates data storage.

Section 910 Troubleshooting

1. No pulses on TC outputs: CTEN of first counter shorted to ground or to a LOW; clock input of
first counter open; clock line shorted to ground or to a LOW; TC output of first counter shorted
to ground or to a LOW.
2. With inverter output open, the counter does not recycle at the preset count but acts as a full-
modulus counter.

RELATED PROBLEMS FOR EXAMPLES

91 See Figure 982.
CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Q0
Q1
Q2

Q3

FIGURE 982

92 Connect Q0 to the NAND gate as a third input (Q2 and Q3 are two of the inputs). Connect the
CLR line to the CLR input of FF0 as well as FF2 and FF3.
93 See Figure 983.

UP/DOWN
CLK
Q0
Q1
Q2
Q3

0 15 14 13 12 13 14 15 0 1 0 15 14 15 0
FIGURE 983

94 See Table 914.

TABLE 914
Present Invalid State D Inputs Next State
Q2 Q1 Q0 D2 D1 D0 Q2 Q1 Q0

0 0 0 1 1 1 1 1 1 valid state
0 1 1 0 0 0 0 0 0
1 0 0 1 1 1 1 1 1
1 1 0 1 0 1 1 0 1 valid state
000 S 111
011 S 000 S 111
100 S 111
110 S 101
560 Counters

95 Three flip-flops, sixteen 3-input AND gates, two 4-input OR gates, four 2-input OR gates,
and one inverter
96 Five decade counters are required. 105 = 100,000
97 fQ0 = 1 MHz/[(10)(2)] = 50 kHz
98 See Figure 984.
99 8AC016 would be loaded. 164 - 8AC016 = 65,536 - 32,520 = 30,016
fTC4 = 10 MHz/30,016 = 333.2 Hz
910 See Figure 985.
CLK
Q2 Q0
Q1 5 Q1
0
Q0 Q2
FIGURE 984 FIGURE 985

TRUE/FALSE QUIZ
1. T 2. F 3. T 4. F 5. T 6. F 7. T 8. F 9. T 10. F

SELF-TEST
1. (c) 2. (a) 3. (b) 4. (c) 5. (b) 6. (c) 7. (d) 8. (c)
9. (b) 10. (c) 11. (d) 12. (d) 13. (c) 14. (b) 15. (b) 16. (a)