COMPREHENSIVE VIVA-VOCE REPORT

ON SUBJECTS STUDIED ACCORDING TO B.TECH SYLLABUS OF THE

ELECTRONICS AND COMMUNICATION ENGINEERING

Submitted to

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

MAHAVEER INSTITUTE OF SCIENCE AND TECHNOLOGY

(Approved by AICTE)

and affiliated to

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY,

HYDERABAD

In the partial fulfillment of the requirements for the award of degree of

BACHELOR OF TECHNOLOGY

in ELECTRONICS AND COMMUNICATION ENGINEERING

submitted by

CHITUPROLU RAJESH KUMAR 13E31A0412

GUIDE CO-ORDINATOR HEAD OF DEPT.

M.Cheenya N.Ravi Kumar Dr.V. Gunashekar Reddy

Asst.Professor Asst.Professor Professor & HOD

Department of Electronics and Communication Engineering

MAHAVEER INSTITUTE OF SCIENCE AND TECHNOLOGY

Vyasapuri, Bandlaguda, post:Keshavagiri,

Hyderabad-500 005

2016-2017

Mahaveer Inst of Science & Tech, ECE Department Page 1

MAHAVEER INSTITUTE OF SCIENCE AND TECHNOLOGY

( Affiliated to JNTU Hyderabad and approved by AICTE)

Vyasapuri, Bandlaguda, Post: Keshavagiri,

Hyderabad-500 005

CERTIFICATE

This is to certify that a COMPREHENSIVE VIVA-VOCE on subjects studied according to

the

B.Tech syllabus of the ELECTRONICS AND COMMUNICATION ENGINEERING

which is being submitted by

CHITUPROLU RAJESH KUMAR 13E31A0412

In partial fulfillment for the award of Degree of Bachelor of Technology in Electronics and
Communication Engineering to the Mahaveer Institute of Science and Technology, affiliated
to Jawaharlal Nehru Technological University and is a bonafide record of work carried out
by them under our supervision during the academic year 2016-2017.

1. ANTENNA WAVE PROPAGATION

2. ELECTROMAGNETIC AND TRANSMISSION LINES

3. MICRO PROCESSOR AND MICRO CONTROLLER

GUIDE CO-ORDINATOR HEAD OF DEPT.

M.Cheenya N.Ravi Kumar Dr.V. Gunashekar Reddy

Asst.Professor Asst,Professor Professor & HOD

Mahaveer Inst of Science & Tech, ECE Department Page 2

ACKNOWLEDGEMENT

The satisfaction that accompanies the successfully completion of the task would be put
incomplete without the mention of the people who made it possible, whose constant guidance
and encouragement crown all the efforts with success.

We express deep sense of gratitude to .M.Cheenya, Assistant professor, ECE department. His
valuable guidance, constant encouragement and fruitful suggestions during the entire period
of project.

We would like to thank our professor and project coordinator N.Ravi Kumar in the
department of Electronics and Communication Engineering for his guidance, encouragement
and suggestions in the completion of project.

We heart fully thank our beloved Head of Department Dr.V.Gunashekhar Reddy for his great
encouragement and cooperation throughout the project and for providing lab facilities.

We would like to thank our beloved Principal K.S.S.S.N.Reddy for providing necessary
infrastructure in our college.
We also thank or librarian for providing us the books and other necessary material for this
seminar. I would like to thank the staff and friends who supported me directly and indirectly
for their good wishes and constructive criticism, which lead to sucessful completion of this
report.

CHITUPROLU RAJESH KUMAR 13E31A0412

Mahaveer Inst of Science & Tech, ECE Department Page 3

S.NO TOPICS
ANTENNA WAVE PROPAGATION
1 Chapter 1
1.1 Introduction

1.2 Basic antenna properties

2 Chapter 2- YAGI YUDA ANTENNA

2.1 Introduction

2.2 Description

2.3 advantages

2.4 applications

3 Chapter 3-HELLICAL ANTENNA

3.1 Introduction

3.2 Description

3.3 Applications

3.4 Limitations

4 Chapter 4-HORN ANTENNA

4.1 Introduction

4.2 Description

4.3 Application

4.4 Limitation

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ELECTROMAGNETIC AND TRANSMISSION LINES
1 Chapter 1
1.1 Introduction

2 Chapter 2- COULOMBS LAW

2.1 Introduction

2.2 Electric field

2.3 Coulombs constant

3 Chapter 3-GAUSSS LAW

3.1 Introduction

3.2 Equation involving E-field

3.3 Application

3.4 Limitations

4 Chapter 4- ELECTRIC FIELD AND

ELECTRIC FLUX DENSITY

4.1 Introduction
4.2 Maxwell flux
4.3 Maxwell equation

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MICRO PROCESSOR AND MICRO CONTROLLER

1 Chapter 1- MICRO PROCESSOR AND MICRO

CONTROLLER

1.1 Introduction

2 Chapter 2- 8086 MICROPROCESSOR

2.1 Introduction

2.2 Working

3 Chapter 3- 8086 ARCHITECTURE

3.1 Introduction

3.2 Architecture

3.3 Applications

ANTENNA WAVE PROPAGATION

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 CHAPTER 1
1.1 Introduction

Antennas couple propagating electromagnetic waves to and from circuits and

devices, typically using wires or apertures In practice complicated solutions of
Maxwells equations for given boundary conditions are usually not required for
system design and analysis because the antenna properties have already been
specified by the manufacturer, and must only be understood. Section 3.1
characterizes these general transmitting and receiving properties of antennas,
which are derived in subsequent sections.

1.2 Basic antenna properties

There are many types of antanna, but the basic antenna used are the following

1. Yagi yuda Antenna

2. Helical Antenna
3. Horn Antenna

Te description of the above are given below

CHAPTER 2

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YAGI YUDA ANTENNA

2.1 Introduction
The Yagi antenna design has a dipole as the main radiating or driven
element. Further 'parasitic' elements are added which are not directly connected
to the driven element.

These parasitic elements within the Yagi antenna pick up power from the dipole
and re-radiate it. The phase is in such a manner that it affects the properties of
the RF antenna as a whole, causing power to be focussed in one particular
direction and removed from others.

Fig : basic antenna

2.2 DESCRIPTION:

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The parasitic elements of the Yagi antenna operate by re-radiating their signals
in a slightly different phase to that of the driven element. In this way the signal
is reinforced in some directions and cancelled out in others. It is found that the
amplitude and phase of the current that is induced in the parasitic elements is
dependent upon their length and the spacing between them and the dipole or
driven element.

There are three types of element within a Yagi antenna:

Driven element: The driven element is the Yagi antenna element to which
power is applied. It is normally a half wave dipole or often a folded dipole.

Reflector : The Yagi antenna will generally only have one reflector. This is
behind the main driven element, i.e. the side away from the direction of
maximum sensitivity.

Further reflectors behind the first one add little to the performance. However
many designs use reflectors consisting of a reflecting plate, or a series of
Mahaveer Inst of Science & Tech, ECE Department Page 9
 parallel rods simulating a reflecting plate. This gives a slight improvement in
performance, reducing the level of radiation or pick-up from behind the
antenna, i.e.in the backwards direction.

Typically a reflector will add around 4 or 5 dB of gain in the forward

direction.

Director: There may be none, one of more reflectors in the Yagi antenna. The
director or directors are placed in front of the driven element, i.e. in the
direction of maximum sensitivity. Typically each director will add around 1 dB
of gain in the forward direction, although this level reduces as the number of
directors increases.

The antenna exhibits a directional pattern consisting of a main forward lobe and
a number of spurious side lobes. The main one of these is the reverse lobe
caused by radiation in the direction of the reflector. The antenna can be
optimised to either reduce this or produce the maximum level of forward gain.
Unfortunately the two do not coincide exactly and a compromise on the
performance has to be made depending upon the application.

2.3 ADVANTAGES
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The Yagi antenna offers many advantages for its use. The antenna provides
many advantages in a number of applications:

Antenna has gain allowing lower strength signals to be received.

Yagi antenna has directivity enabling interference levels to be minimised.

Straightforward construction. - the Yagi antenna allows all constructional

elements to be made from rods simplifying construction.

The construction enables the antenna to be mounted easily on vertical and

other poles with standard mechanical fixings

The Yagi antenna also has a number of disadvantages that need to be

considered.

For high gain levels the antenna becomes very long

Gain limited to around 20dB or so for a single antenna

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Some of the Yagi antenna theory can be complicated, but a basic understanding
of how a Yagi antenna works can be given sufficient for design purposes.

The different elements of the Yagi antenna react in a complex and interrelated
way to provide the overall performance.

In order to be able to develop a Yagi antenna it is necessary to have at least a

basic understanding of the Yagi antenna theory.

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CHAPTER 3

HORN ANTENNA

3.1 INTRODUCTION
A horn antenna is used to transmit radio waves from a waveguide (a
metal pipe used to carry radio waves) out into space, or collect radio
waves into a waveguide for reception. It typically consists of a short
length of rectangular or cylindrical metal tube (the waveguide), closed at
one end, flaring into an open-ended conical or pyramidal shaped horn on
the other end. The radio waves are usually introduced into the waveguide
by a coaxial cable attached to the side, with the central conductor
projecting into the waveguide to form aquarter-wave monopole antenna.
The waves then radiate out the horn end in a narrow beam. In some
equipment the radio waves are conducted between

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 the transmitter orreceiver and the antenna by a waveguide; in this case the
horn is attached to the end of the waveguide. In outdoor horns, such as
the feed horns of satellite dishes, the open mouth of the horn is often
covered by a plastic sheet transparent to radio waves, to exclude
moisture.

3.2 DESCRIPTION

The waves travel down a horn as spherical wavefronts, with their origin at
the apex of the horn, a point called the phase center. The pattern
of electric and magnetic fields at the aperture plane at the mouth of the horn,
which determines the radiation pattern, is a scaled-up reproduction of the fields
in the waveguide. Because the wavefronts are spherical, the phase increases
smoothly from the edges of the aperture plane to the center, because of the
difference in length of the center point and the edge points from the apex point.
The difference in phase between the center point and the edges is called
the phase error. This phase error, which increases with the flare angle, reduces
the gain and increases the beamwidth, giving horns wider beamwidths than
similar-sized plane-wave antennas such as parabolic dishes.

At the flare angle, the radiation of the beam lobe is down about -20 dB from its
maximum value.

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As the size of a horn (expressed in wavelengths) is increased, the phase error
increases, giving the horn a wider radiation pattern. Keeping the beamwidth
narrow requires a longer horn (smaller flare angle) to keep the phase error
constant. The increasing phase error limits the aperture size of practical horns to
about 15 wavelengths; larger apertures would require impractically long
horns. This limits the gain of practical horns to about 1000 (30 dBi) and the
corresponding minimum beamwidth to about 5 - 10.

Because the wavefronts are spherical, the phase increases smoothly from the
edges of the aperture plane to the center, because of the difference in length of
the center point and the edge points from the apex point. The difference in phase
between the center point and the edges is called the phase error. This phase
error, which increases with the flare angle, reduces the gain and increases the
beamwidth, giving horns wider beamwidths than similar-sized plane-wave
antennas such as parabolic dishes.

Fig: small aperture

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3.3 TYPES OF HORN ANTENNA

This list contains both the common types of horn antenna as well as more
specialist types. Horns can have different flare angles as well as different
expansion curves (elliptic, hyperbolic, etc.) in the E-field and H-field directions,
making possible a wide variety of different beam profiles.

Pyramidal horn (a, right) a horn antenna with the horn in the shape of a
four-sided pyramid, with a rectangular cross section. They are a common type,
used with rectangular waveguides, and radiate linearly polarized radio waves.

Sectoral horn A pyramidal horn with only one pair of sides flared and the
other pair parallel. It produces a fan-shaped beam, which is narrow in the plane
of the flared sides, but wide in the plane of the narrow sides. These types are
often used as feed horns for wide search radar antennas.

E-plane horn (b) A sectoral horn flared in the direction of the electric or E-
field in the waveguide.

H-plane horn (c) A sectoral horn flared in the direction of the magnetic or H-
field in the waveguide.

Conical horn (d) A horn in the shape of a cone, with a circular cross section.
They are used with cylindrical waveguides.

Exponential horn (e) A horn with curved sides, in which the separation of the
sides increases as an exponential function of length. Also called a scalar horn,
they can have pyramidal or conical cross sections. Exponential horns have
minimum internal reflections, and almost constant impedance and other
characteristics over a wide frequency range. They are used in applications

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requiring high performance, such as feed horns for communication satellite
antennas and radio telescopes.

Corrugated horn A horn with parallel slots or grooves, small compared with
a wavelength, covering the inside surface of the horn, transverse to the axis.
Corrugated horns have wider bandwidth and smaller side lobes and cross-
polarization, and are widely used as feed horns for satellite dishes and radio
telescopes.

Dual-mode conical horn (The Potter horn ) This horn can be used to
replace the corrugated horn for use at sub-mm wavelengths where the
corrugated horn is lossy and difficult to fabricate.
Diagonal horn This simple dual-mode horn superficially looks like a
pyramidal horn with a square output aperture. On closer inspection, however,
the square output aperture is seen to be rotated 45 relative to the waveguide.
These horns are typically machined into split blocks and used at sub-mm
wavelengths.
Ridged horn A pyramidal horn with ridges or fins attached to the inside of the
horn, extending down the center of the sides. The fins lower the cutoff
frequency, increasing the antenna's bandwidth.

Septum horn A horn which is divided into several subhorns by metal

partitions (septums) inside, attached to opposite walls.

Aperture-limited horn a long narrow horn, long enough so the phase error is
a negligible fraction of a wavelength so it essentially radiates a plane wave. It
has an aperture efficiency of 1.0 so it gives the maximum gain and
minimum beamwidth for a given aperture size. The gain is not affected by the

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length but only limited by diffraction at the aperture. Used as feed horns in radio
telescopes and other high-resolution antennas.

Corrugated horn A horn with parallel slots or grooves, small compared with
a wavelength, covering the inside surface of the horn, transverse to the axis.
Corrugated horns have wider bandwidth and smaller side lobes and cross-
polarization, and are widely used as feed horns for satellite dishes and radio
telescopes.

Diagonal horn This simple dual-mode horn superficially looks like a

pyramidal horn with a square output aperture. On closer inspection, however,
the square output aperture is seen to be rotated 45 relative to the waveguide.
These horns are typically machined into split blocks and used at sub-mm
wavelengths.

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 Fig: types of horn antenna

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3.3 APPLICATIONS:

As shown in Fig.3, different frequency band antennas are placed on

aircraft/missile body for different communication

Fig: Aircarft missile

Antenna placed at nose of the aircraft is a part of guidance RADAR system,

which will guide the aircraft. Various jamming antenna are placed on different
parts of aircraft for jamming the enemy signals. Antenna placed at the belly of
the aircraft for data link application. All these antennas are operated on different
frequency bands, so care should be taken that to avoid the interference of
radiation pattern of all these antennas. Also when these antennas are placed on
the aircraft body, its radiation pattern gets distorted, so one should design an
antenna such that it will meet our application.

CHAPTER 4

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HELICAL ANTENNA

4.1 INTRODUCTION

A helical antenna is an antenna consisting of a conducting wire wound in the

form of a helix. In most cases, helical antennas are mounted over a ground
plane. The feed line is connected between the bottom of the helix and the
ground plane. Helical antennas can operate in one of two principal modes
normal mode or axial mode.

In the normal mode or broadside helix, the dimensions of the helix (the diameter
and the pitch) are small compared with the wavelength. The antenna acts
similarly to an electrically short dipole or monopole, and the radiation pattern,
similar to these antennas isomnidirectional, with maximum radiation at right
angles to the helix axis. The radiation is linearly polarised parallel to the helix
axis. These are used for compact antennas for portable and mobile two-way
radios, and for UHF television broadcasting antennas.

In the axial mode or end-fire helix, the dimensions of the helix are comparable
to a wavelength. The antenna functions as a directional antenna radiating a
beam off the ends of the helix, along the antenna's axis. It radiates circularly
polarised radio waves. These are used for satellite communication.

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Fig: helical antenna

3.2 DESCRIPTION

If the diameter and pitch (axial distance between successive turns)

of the helix are significantly less than a wavelength, the antenna is called
a normal-mode helix. The antenna acts similar to a monopole antenna, with
an omnidirectional radiation pattern, radiating equal power in all directions
perpendicular to the antenna. However, because of the inductance added by the
helical shape, the antenna acts like a inductively loaded monopole; at
its resonant frequency it is shorter than a quarter-wavelength long. Therefore
normal-mode helices can be used as electrically short monopoles, an alternative
to center- or base-loaded whip antennas, in applications where a full sized
quarter-wave monopole would be too big. As with other electrically short
antennas, the gain, and thus the communication range, of the helix will be less
than that of a full sized antenna. Their compact size makes "helicals" useful as
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antennas for mobile and portablecommunications equipment on the HF, VHF,
and UHF bands.

Fig: A common form of normal-mode helical antenna

An effect of using a helical conductor rather than a straight one is that the
matching impedance is changed from the nominal 50 ohms to between 25 to
35 ohms base impedance. This does not seem to be adverse to operation or
matching with a normal 50 ohm transmission line, provided the connecting feed
is the electrical equivalent of a 1/2 wavelength at the frequency of operation.

Another example of the type as used in mobile communications is "spaced

constant turn" in which two or more different linear windings are wound on a
single former and spaced so as to provide an efficient balance
betweencapacitance and inductance for the radiating element at a particular
resonant frequency.

Many examples of this type have been used extensively for 27 MHz CB
radio with a wide variety of designs originating in the US and Australia in the
late 1960s. Multi-frequency versions with plug-in taps have become the
mainstay for multi-band Single-sideband modulation (SSB) HF
communications.

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Most examples were wound with copper wire using a fiberglass rod as a former.
This flexible radiator is then covered with heat-shrink tubing which provides a
resilient and rugged waterproof covering for the finished mobile antenna.

These popular designs are still in common use as of 2010 and have been
universally adapted as standard FM receiving antennas for many factory
produced motor vehicles as well as the existing basic style of aftermarket HF
and VHF mobile helical. The most common use for broadside helixes is in the
"rubber ducky antenna" found on most portable VHF and UHF radios

Axial Mode Helical

When the helix diameter and pitch are at or above the wavelength of
operation, the antenna operates in the axial mode. This is anonresonant traveling
wave mode, in which instead of standing waves, the waves of current and
voltage travel in one direction, up the helix. Instead of radiating linearly
polarized waves normal to the antenna's axis , it radiates a beam of radio waves
with circular polarisation along the axis, off the ends of the antenna. The main
lobes of the radiation pattern are along the axis of the helix, off both ends. Since
in a directional antenna only radiation in one direction is wanted, the other end
of the helix is terminated in a flat metal sheet or screen reflector to reflect the
waves forward.

In radio transmission, circular polarisation is often used where the relative

orientation of the transmitting and receiving antennas cannot be easily
controlled, such as in animal tracking and spacecraft communications, or where
the polarisation of the signal may change, so end-fire helical antennas are
frequently used for these applications. Since large helices are difficult to build

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and unwieldy to steer and aim, the design is commonly employed only at higher
frequencies, ranging from VHF up to microwave.

The helix in the antenna can twist in two possible directions: right-handed or
left-handed, as defined by the right hand rule. In an axial-mode helical antenna
the direction of twist of the helix determines the polarisation of the radio waves:
a left-handed helix radiates left-circularly-polarised radio waves, a right-handed
helix radiates right-circularly-polarised radio waves. Helical antennas can
receive signals with any type of linear polarisation, such as horizontal or
vertical polarisation, but when receiving circularly polarised signals the
handedness of the receiving antenna must be the same as the transmitting
antenna; left-hand polarised antennas suffer a severe loss ofgain when receiving
right-circularly-polarised signals, and vice versa.

The dimensions of the helix are determined by the wavelength of the radio
waves used, which depends on the frequency. In axial-mode operation, the
spacing between the coils should be approximately one-quarter of the
wavelength (/4), and the diameter of the coils should be approximately the
wavelength divided by pi (/). The length of the coil determines
how directional the antenna will be as well as its gain; longer antennas will be
more sensitive in the direction in which they point.

Terminal impedance in axial mode ranges between 100 and 200 ohms. The
resistive part is approximated by:

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 where R is resistance in ohms, C is the circumference of the helix, and is
the wavelength. Impedance matching to standard 50 or 75 ohm coaxial cable
is often done by a quarter wave stripline section acting as an impedance
transformer between the helix and the cable termination.

Helical antenna for WLANcommunication, working frequency app. 2.4 GHz

The maximum directive gain is approximately:

where N is the number of turns and S is the spacing between turns.

The half-power beamwidth is:

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 The beamwidth between nulls is:

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3.4 APPLICATIONS
A helical antenna is primarily used for broadcast and the Longwave bands.

The loop can be used for improving the performance of a poorly designed
broadcast receiver . Depending on the type of antenna that is in the receiver
determines how the loop can be attached.

A helical when properly balanced can be used to "null down"

weep Harmonics, or other locally generated interference.
Helical stick antennas also work well in low-frequency applications such as
RFID (card/tag readers)used in fleet management, parking gates, airports,
access doors, and inventory control applications

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ELECTROMAGNETIC AND TRANSMISSION
LINES

CHAPTER 1

INTRODUCTION:

Electromagnetic theory is a discipline concerned with the study

of charges at rest and in motion. Electromagnetic principles are
fundamental to the study of electrical engineering and physics.
Electromagnetic theory is also indispensable to the
understanding, analysis and design of various electrical,
electromechanical and electronic systems. Some of the
branches of study where electromagnetic principles find
application are: Electric charge is a fundamental property of
matter. Charge exist only in positive or negative integral
multiple of electronic charge, -e, e= 1.60 10 -19 coulombs. [It
may be noted here that in 1962, Murray Gell-Mann
hypothesized Quarks as the basic building blocks of matters.
Quarks were predicted to carry a fraction of electronic charge
Mahaveer Inst of Science & Tech, ECE Department Page 29
and the existences of Quarks have been experimentally
verified.] Principle of conservation of charge states that the
total charge (algebraic sum of positive and negative charges) of
an isolated system remains unchanged, though the charges
may redistribute under the influence of electric field. Kirchhoff's
Current Law (KCL) is an assertion of the conservative property
of charges under the implicit assumption that there is no
accumulation of charge at the junction. Electromagnetic theory
deals directly with the electric and magnetic field vectors where
as circuit theory deals with the voltages and currents. Voltages
and currents are integrated effects of electric and magnetic
fields respectively. Electromagnetic field problems involve three
space variables along with the time variable and hence the
solution tends to become correspondingly complex. Vector
analysis is a mathematical tool with which electromagnetic
concepts are more conveniently expressed and best
comprehended. Since use of vector analysis in the study of
electromagnetic field theory results in real economy of time
and thought, we first introduce the concept of vector analysis.

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CHAPTER 2

COULUMBS LAW

2.1 INTRODUCION: The magnitude of the electrostatic force of

interaction between two point charges is directly proportional to the
scalar multiplication of the magnitudes of charges and inversely
proportional to the square of the distance between them
The force is along the straight line joining them. If the two charges have
the same sign, the electrostatic force between them is repulsive; if they
have different signs, the force between them is attractive.

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Coulomb's law can also be stated as a simple mathematical expression.
The scalar and vector forms of the mathematical equation are

and

respectively,

where is Coulomb's constant (

), and are the

signed magnitudes of the charges, the scalar is the distance between the
charges, the vector is the vectorial distance between the

charges, and (a unit vector pointing from to ). The

vector form of the equation calculates the force applied on by . If
is used instead, then the effect on can be found. It can be also calculated
using

Newton's third law: .

Units:

Electromagnetic theory is usually expressed using the standard SI units.

Force is measured in newtons, charge in coulombs, and distance in metres.

Coulomb's constant is given by . The constant is

the permittivity of free space in C2 m2 N1. And is the relative permittivity of
the material in which the charges are immersed, and is dimensionless.

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The SI derived units for the electric field are volts per meter, newtons per
coulomb, or tesla meters per second.

Coulomb's law and Coulomb's constant can also be interpreted in various terms:

Atomic units. In atomic units the force is expressed

in hartrees per Bohr radius, the charge in terms of the elementary
charge, and the distances in terms of the Bohr radius.

Electrostatic units or Gaussian units. In electrostatic units and

Gaussian units, the unit charge (esu or statcoulomb) is defined in such
a way that the Coulomb constant kdisappears because it has the value
of one and becomes dimensionless.

2.1 ELECTRIC FIELD

An electric field is a vector field that associates to each point in space the
Coulomb force experienced by a test charge. In the simplest case, the field is
considered to be generated solely by a single source point charge. The strength
and direction of the Coulomb force on a test charge depends on the electric
field that it finds itself in, such that . If the field is generated by a
positive source point charge , the direction of the electric field points along
lines directed radially outwards from it, i.e. in the direction that a positive point
test charge would move if placed in the field. For a negative point source
charge, the direction is radially inwards.

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FIG: If the two charges have the same sign, the electrostatic force between
them is repulsive; if they have different sign, the force between them is
attractive.

The magnitude of the electric field can be derived from Coulomb's law. By
choosing one of the point charges to be the source, and the other to be the test
charge, it follows from Coulomb's law that the magnitude of the electric field
created by a single source point charge at a certain distance from it in
vacuum is given by:

2.3 COULOMBS CONSTANT

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 Coulomb's constant is a proportionality factor that appears in
Coulomb's law as well as in other electric-related formulas. Denoted , it is
also called the electric force constant or electrostatic constant, hence the
subscript .

The exact value of Coulomb's constant is:

There are three conditions to be fulfilled for the validity of Coulombs law:

1. The charges considered must be point charges.

2. They should be stationary with respect to each other.

3. The two point charges should be placed in a single medium.

CHATER 3

GAUSS LAW

The net electric flux through any closed surface is equal to 1 times the
net electric charge enclosed within that closed surface.

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 Gauss's law has a close mathematical similarity with a number of laws in
other areas of physics, such as Gauss's law for magnetism and Gauss's law
for gravity. In fact, any "inverse-square law" can be formulated in a way
similar to Gauss's law: For example, Gauss's law itself is essentially
equivalent to the inverse-square Coulomb's law, and Gauss's law for gravity
is essentially equivalent to the inverse-square Newton's law of gravity.

Gauss's law is something of an electrical analogue of Ampre's law, which

deals with magnetism.

The law can be expressed mathematically using vector

calculus in integral form and differential form, both are equivalent since they
are related by the divergence theorem, also called Gauss's theorem. Each of
these forms in turn can also be expressed two ways: In terms of a relation
between the electric field E and the total electric charge, or in terms of
the electric displacement field D and the free electric charge

3.1 EQUATION INVOLVING E-FIELD

Gauss's law can be stated using either the electric field E or the electric
displacement field D. This section shows some of the forms with E; the form
with D is below, as are other forms with E.

Integral form

Gauss's law may be expressed as:

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 where E is the electric flux through a closed surface S enclosing any
volume V, Q is the total charge enclosed within S, and 0 is the electric
constant. The electric flux E is defined as a surface integral of the electric
field:

where E is the electric field, dA is a vector representing

an infinitesimal element of area,[note 1] and represents the dot product of
two vectors.

Since the flux is defined as an integral of the electric field, this

expression of Gauss's law is called the integral form.

Applying the integral form

If the electric field is known everywhere, Gauss's law makes it quite

easy, in principle, to find the distribution of electric charge: The charge in
any given region can be deduced by integrating the electric field to find
the flux.

However, much more often, it is the reverse problem that needs to be

solved: The electric charge distribution is known, and the electric field
needs to be computed. This is much more difficult, since if you know the
total flux through a given surface, that gives almost no information about
the electric field, which (for all you know) could go in and out of the
surface in arbitrarily complicated patterns.

An exception is if there is some symmetry in the situation, which

mandates that the electric field passes through the surface in a uniform
way. Then, if the total flux is known, the field itself can be deduced at

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 every point. Common examples of symmetries which lend themselves to
Gauss's law include cylindrical symmetry, planar symmetry, and
spherical symmetry. See the article Gaussian surface for examples where
these symmetries are exploited to compute electric fields.

Differential form

By the divergence theorem, Gauss's law can alternatively be written in

the differential form:

where E is the divergence of the electric field, 0 is the electric

constant, and is the total electric charge density (charge per unit
volume).

CHAPTER 4

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ELECTRIC FIELD AND ELECTRIC FIELD DENSITY

In electromagnetism, electric flux is the measure of flow of

the electric field through a given area. Electric flux is proportional to the
number of electric field lines going through a normally perpendicular surface. If
the electric field is uniform, the electric flux passing through a surface of vector
area S is

where E is the electric field (having units of V/m), E is its magnitude, S is

the area of the surface, and is the angle between the electric field lines and
the normal (perpendicular) to S.

For a non-uniform electric field, the electric flux dE through a small

surface area dS is given by

(the electric field, E, multiplied by the component of area perpendicular

to the field). The electric flux over a surface S is therefore given by
the surface integral:

where E is the electric field and dS is a differential area on the closed

surface S with an outward facing surface normal defining its direction.

For a closed Gaussian surface, electric flux is given by:

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where

E is the electric field,

S is any closed surface,
Q is the total electric charge inside the surface S,
0 is the electric constant (a universal constant, also called the
"permittivity of free space") (0 8.854 187 817... x
1012 farads per meter (Fm1)).

This relation is known as Gauss' law for electric field in its integral form and it
is one of the four Maxwell's equations.

While the electric flux is not affected by charges that are not within the closed
surface, the net electric field, E, in the Gauss' Law equation, can be affected by
charges that lie outside the closed surface. While Gauss' Law holds for all
situations, it is only useful for "by hand" calculations when high degrees of
symmetry exist in the electric field. Examples include spherical and cylindrical
symmetry.

Electrical flux has SI units of volt metres (V m), or, equivalently, newton metres
squared per coulomb (N m2 C1). Thus, the SI base units of electric flux
are kgm3s3A1.

Its dimensional formula is [L3MT3I1].

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4.1 MAGNETIC FLUX
The magnetic interaction is described in terms of a vector field, where each
point in space (and time) is associated with a vector that determines what force
a moving charge would experience at that point (see Lorentz force). Since a
vector field is quite difficult to visualize at first, in elementary physics one may
instead visualize this field with field lines. The magnetic flux through some
surface, in this simplified picture, is proportional to the number of field lines
passing through that surface (in some contexts, the flux may be defined to be
precisely the number of field lines passing through that surface; although
technically misleading, this distinction is not important). Note that the magnetic
flux is the net number of field lines passing through that surface; that is, the
number passing through in one direction minus the number passing through in
the other direction (see below for deciding in which direction the field lines
carry a positive sign and in which they carry a negative sign). In more advanced
physics, the field line analogy is dropped and the magnetic flux is properly
defined as the surface integral of the normal component of the magnetic field
passing through a surface. If the magnetic field is constant, the magnetic flux
passing through a surface of vector area S is

where B is the magnitude of the magnetic field (the magnetic flux density)
having the unit of Wb/m2 (tesla), S is the area of the surface, and is the
angle between the magnetic field lines and the normal (perpendicular) to S.
For a varying magnetic field, we first consider the magnetic flux through an

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 infinitesimal area element dS, where we may consider the field to be
constant:

A generic surface, S, can then be broken into infinitesimal elements and the
total magnetic flux through the surface is then thesurface integral

From the definition of the magnetic vector potential A and the fundamental
theorem of the curl the magnetic flux may also be defined as:

where the line integral is taken over the boundary of the surface S, which is
denoted S.

Magnetic flux through a closed surface

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FIG: Some examples of closed surfaces (left) and open surfaces(right). Left:
Surface of a sphere, surface of a torus, surface of a cube. Right: Disk
surface, square surface, surface of a hemisphere. (The surface is blue, the
boundary is red.)

Gauss's law for magnetism, which is one of the four Maxwell's equations, states
that the total magnetic flux through a closed surface is equal to zero. (A "closed
surface" is a surface that completely encloses a volume(s) with no holes.) This
law is a consequence of the empirical observation that magnetic
monopoles have never been found.

In other words, Gauss's law for magnetism is the statement:

for any closed surface S.

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Magnetic flux through an open surface

FIG: For an open surface , the electromotive force along the surface
boundary, , is a combination of the boundary's motion, with velocity v,
through a magnetic field B(illustrated by the generic F field in the diagram)
and the induced electric field caused by the changing magnetic field.

While the magnetic flux through a closed surface is always zero, the
magnetic flux through an open surface need not be zero and is an important
quantity in electromagnetism. For example, a change in the magnetic flux
passing through a loop of conductive wire will cause an electromotive force,
and therefore an electric current, in the loop. The relationship is given
by Faraday's law:

where

is the electromotive force (EMF),

B is the magnetic flux through the open surface ,

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 is the boundary of the open surface ; note that the surface, in general,
may be in motion and deforming, and so is generally a function of time.
The electromotive force is induced along this boundary.
d is an infinitesimal vector element of the contour ,
v is the velocity of the boundary ,
E is the electric field,
B is the magnetic field.

The two equations for the EMF are, firstly, the work per unit charge
done against the Lorentz force in moving a test charge around the (possibly
moving) surface boundary and, secondly, as the change of magnetic flux
through the open surface . This equation is the principle behind an electrical
generator.

Area defined by an electric coil with three turns.

COMPARISION OF ELECTRIC FLUX

By way of contrast, Gauss's law for electric fields, another of Maxwell's
equations, is

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where

E is the electric field,

S is any closed surface,
Q is the total electric charge inside the surface S,
0 is the electric constant (a universal constant, also called the
"permittivity of free space").

Note that the flux of E through a closed surface is not always zero; this indicates
the presence of "electric monopoles", that is, free positive or negative charges.

MAXWELL EQUATIONS:

Maxwell's equa tions are a set of partial differential equations that,

together with the Lorentz force law, form the foundation ofclassical
electrodynamics, classical optics, and electric circuits. These fields in turn
underlie modern electrical and communications technologies. Maxwell's
equations describe how electric and magnetic fields are generated and altered by
each other and bycharges and currents. They are named after the physicist and
mathematician James Clerk Maxwell, who published an early form of those
equations between 1861 and 1862.

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The equations have two major variants. The "microscopic" set of Maxwell's
equations uses total charge and total current, including the complicated charges
and currents in materials at the atomic scale; it has universal applicability but
may be infeasible to calculate. The "macroscopic" set of Maxwell's equations
defines two new auxiliary fields that describe large-scale behaviour without
having to consider these atomic scale details, but it requires the use of
parameters characterizing the electromagnetic properties of the relevant
materials.

The term "Maxwell's equations" is often used for other forms of Maxwell's
equations. For example, space-time formulations are commonly used in high
energy and gravitational physics. These formulations, defined on space-
time rather than space and time separately, are manifestly[note 1] compatible
with special and general relativity. In quantum mechanics and analytical
mechanics, versions of Maxwell's equations based on the electric and magnetic
potentials are preferred.

Since the mid-20th century, it has been understood that Maxwell's equations are
not exact but are a classical field theoryapproximation to the more accurate and
fundamental theory of quantum electrodynamics. In many situations, though,
deviations from Maxwell's equations are immeasurably small. Exceptions
include nonclassical light, photon-photon scattering, quantum optics, and many
other phenomena related to photons or virtual photons.

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 is a surface integral over the surface (the oval indicates the
surface is closed and not open),

is a volume integral over the volume ,

is a surface integral over the surface ,

is a line integral around the curve (the circle indicates the curve is
closed).

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Here "fixed" means the volume or surface do not change in time. Although it is
possible to formulate Maxwell's equations with time-dependent surfaces and
volumes, this is not actually necessary: the equations are correct and complete
with time-independent surfaces. The sources are correspondingly the total
amounts of charge and current within these volumes and surfaces, found by
integration.

The volume integral of the total charge density over any fixed
volume is the total electric charge contained in :

where dV is the differential volume element, and

the net electric current is the surface integral of the electric current
density J, passing through any open fixed surface :

MICROPROCESSOR AND MICRO

CONTROLLER
CHAPTER 1
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MICROPROCESSORS
1.1 Introduction
A microprocessor - also known as a CPU or centralprocessing unit - is a
complete computationengine that is fabricated on a single chip. The first
microprocessor was the Intel 4004, introduced in 1971. The 4004 was not very
powerful - all it could do was add and subtract, and it could only do that 4 bits
at a time. But it was amazing that everything was on one chip. Prior to the 4004,
engineers built computers either from collections of chips or from discrete
components (Transistors and such). The 4004 powered one of the first portable
electronic calculators. Microprocessor/Microcontroller . The first
microprocessor to make it into a home computer was the Intel 8080, a complete
8-bit computer on one chip, introduced in 1974. The first microprocessor to
make a real splash in the market was the Intel 8088, introduced in 1979 and
incorporated into the IBM PC (which first appeared around 1982). If you are
familiar with the PC market and its history, you know that the PC market moved
from the 8088 to the 80286 to the 80386 to the 80486 to the Pentium to the
Pentium II to the Pentium III to the Pentium 4. All of these microprocessors are
made by Intel and all of them are improvements on the basic design of the 8088.
The Pentium 4 can execute any piece of code that ran on This is about as simple
as a microprocessor gets. This

microprocessor has:

An address bus (that may be 8, 16 or 32 bits wide) that

sends an address to memory

A data bus (that may be 8, 16 or 32 bits wide) that can

send data to memory or receive data from memory

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 An RD (read) and WR (write) line to tell the memory

whether it wants to set or get the addressed location

A clock line that lets a clock pulse sequence the

processor

A reset line that resets the program counter to zero (or

whatever) and restarts execution

Let's assume that both the address and data buses are

8 bits wide in this example.Microprocessor/Microcontroller

Here are the components of this simple microprocessor:Registers A, B and C

are simply latches made outof flip-flops.The address latch is just like registers
A, B and C.The program counter is a latch with the extra ability to increment by
1 when told to do so, and also to reset to zero when told to do so.
Microprocessor/Microcontroller Microprocessor Instructions

Even the incredibly simple microprocessor shown in the previous example

will have a fairly large set of instructions that it can perform. The collection of
instructions is implemented as bit patterns, each one of which has a different
meaning when loaded into the instruction register. Humans are not particularly
good at remembering bit patterns, so a set of short words are defined to
represent the different bit patterns. This collection of words is called the
assembly language of the processor. An assembler can translate the words into
their bit patterns very easily, and then the output of the assembler is placed in
memory for the microprocessor to execute. Microprocessor/Microcontroller
Here's the set of assembly language instructions that the designer might create
for the simple microprocessor in

our example:
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 LOADA mem - Load register A from memory address

LOADB mem - Load register B from memory address

CONB con - Load a constant value into register B

SAVEB mem - Save register B to memory address

SAVEC mem - Save register C to memory address

ADD - Add A and B and store the result in C

SUB - Subtract A and B and store the result in C

MUL - Multiply A and B and store the result in C

DIV - Divide A and B and store the result in C

Microprocessor/Microcontroller

COM - Compare A and B and store the result in test

JUMP addr - Jump to an address

JEQ addr - Jump, if equal, to address

JNEQ addr - Jump, if not equal, to address

JG addr - Jump, if greater than, to address

JGE addr - Jump, if greater than or equal, to address

JL addr - Jump, if less than, to address

JLE addr - Jump, if less than or equal, to address

STOP - Stop execution

Microprocessor/Microcontroller

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 An opcode (operation code) is the portion of a

machine language instruction that specifies the operation to be performed. Their

specification and format are laid out in the instruction set architecture of the
processor in question (which may be a general CPU or a more specialized
processing unit). Apart from the opcode itself, an instruction normally also has
one or more specifiers for operands (i.e. data) on which the operation should
act, although some operations may have implicit operands, or none at all.

Microprocessor/Microcontroller

Assembly language, or just assembly, is a lowlevel programming language,

which uses mnemonics, instructions and operands to represent machine code.
This enhances the readability while still giving precise control over the machine
instructions. the original 8088, but it does it about 5,000 times faster!

CHAPTER 2

8086 MICROPROCESSOR

2.1 Introduction
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 In 1968, Intel Corporation was founded to exploit the
semiconductor memory market, which uniquely fulfilled these criteria. Early
semiconductor RAMs, ROMs, and shift registers were welcomed wherever
small memories were needed, especially in calculators and CRT terminals, In
1969, Intel engineers began to study ways of integrating and partitioning the
control logic functions of these systems into LSI chips.

At this time other companies (notably Texas Instruments) were

exploring ways to reduce the design time to develop custom integrated circuits
usable in a customer's application. Computer-aided design of custom ICs was a
hot issue then. Custom ICs are making a comeback today, this time in high-
volume applications which typify the low end of the microprocessor market.

An alternate approach was to think of a customer's application as a

computer system requiring a control program, I/O monitoring, and arithmetic
routines, rather than as a collection of special-purpose logic chips. Focusing on
its strength in memory, Intel partitioned systems into RAM, ROM, and a single
controller chip, the central processor unit (CPU).

Intel embarked on the design of two customer-sponsored

microprocessors, the 4004 for a calculator and the 8008 for a CRT terminal. The
4004, in particular, replaced what would otherwise have been six customized
chips, usable by only one customer, Because the first microcomputer
applications were known, tangible, and easy to understand, instruction sets and
architectures were defined in a matter of weeks. Since they were programmable
computers, their uses could be extended indefinitely.

Both of these first microprocessors were complete CPUs-on-a-chip and had

similar characteristics. But because the 4004 was designed for serial BCD

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arithmetic while the 8008 was made for 8-bit character handling, their
instruction sets were quite different.

2.2 Pin Configuration

PIN DIAGRAM OF 8086 MICROPROCESSORS

8086 pin diagram description8086 Pin diagram And Explanation The 8086 can
operate in two modes these are the minimum mode and maximum mode .For
minimum mode, a unique processor system with asingle 8086 and for
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Maximum mode a multiprocessor system with more than one 8086.MN/MX- is
an input pin used to select one of this mode .

when MN/MX is high the 8086 operates in minimum mode .In this mode
the 8086 is configured to support small single processor

System using a few devices that the system bus. when MN/MX is low 8086 is
configured to support multiprocessor system. The AD0-AD15 lines are a 16bit
multiplexed addressed or data bus. During the 1st clock cycle

AD0-AD15 are the low order 16Bit adders. The8086 has a total of 20 address
line ,the upper 4lines are multiplexed with the state signal that is A16/S3 ,
A17/S4 , A18/S5 , A19 /S6.Duringthe first clock period of a best cycle the entire
20bitaddress is available on these line. During all other clock cycles for memory
and i/o operations AD15-AD0 contain the 16 bit dataands3,S4,S5,S6 become
the status line .S3 and s4are decoded as follows

A17/S4 A16/S3 Function0 0 Extra Segment0 1 Stack Segment1 0 code or No

segment1 1 Data segment there for the 1st clock cycle of an instruction
execution the A17/S4 And A16/S3 pins Specify which Segment register
generate the segment portions of the 8086 address

BHE/S7 is used as best high enable during the1st click cycle of an instruction
execution .the bhe can be used in conjunction with AD0 to select the memory

RD is low when the data is read from memory ori/O location .

TEST is an input pin and is only used by the wait instruction .the 8086 enter a
wait state after execution of the wait instruction until a low is Sean on the test
pin.

INTR is a mask able interrupt input.

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NIM is the non mask able interrupt input.

RESET is the system set reset input signal it terminates all the activities it clear
PSW,IP,DS,SS,ES and the instruction queue.

DT/R(Data Transmit or receive ):is an o/p signal required in system that uses
the data bus transceiverale is an address latch enable . Is an o/p signal provided
by the 8086 and can be used to demultiplexed AD0 to AD15 in to A10 toA15
andD0 to D15.M/IO is an 8086 output signal to distinguish a memory access
and i/o access.

WR is used by the 8086 for performing write memory or write i/o operation .

INTA(interrupt acknowledgement signal )INTA is the interrupt

acknowledgment signal.

HOLD and HOLD a high on the HOLD pin indicates that another master is
required to take over the S/M bus.

CLK clock provides the basic timing signals for the8086 and bus controls

CHAPTER 3

ARCHITECTURE

3.1 Introduction

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The BIU handles all transactions of data and addresses on the buses for EU.

The BIU performs all bus operations such as instruction fetching, reading and
writing operands for memory and calculating the addresses of the memory
operands. The instruction bytes are transferred to the instruction queue.

EU executes instructions from the instruction system byte queue.

Both units operate asynchronously to give the 8086 an overlapping instruction

fetch and execution mechanism which is called as Pipelining. This results in
efficient use of the system bus and system performance.

BIU contains Instruction queue, Segment registers, Instruction pointer, Address

adder.

EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index

register, Flag register.

Pointer And Index Registers

used to keep offset addresses.

Used in various forms of memory addressing.

In the case of SP and BP the default reference to form a physical address is the
Stack Segment (SS-will be discussed under the BIU)

3.2 Architecture

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 Architectural Diagram of 8086 Microprocessor

8086 s two blocks BIU and EU.

The BIU handles all transactions of data and addresses on the buses for EU.

The BIU performs all bus operations such as instruction fetching, reading and
writing operands for memory and calculating the addresses of the memory
operands. The instruction bytes are transferred to the instruction queue.

EU executes instructions from the instruction system byte queue.

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Both units operate asynchronously to give the 8086 an overlapping instruction
fetch and execution mechanism which is called as Pipelining. This results in
efficient use of the system bus and system performance.

BIU contains Instruction queue, Segment registers, Instruction pointer, Address

adder.

EU contains :

Control circuitry,

Instruction decoder,

ALU,

Pointer and Index register,

Flag register.

Pointer And Index Registers

used to keep offset addresses.

Used in various forms of memory addressing.
In the case of SP and BP the default reference to form a physical address
is the Stack Segment (SS-will be discussed under the BIU)
The index registers (SI & DI) and the BX generally default to the Data
segment register (DS).

o SP: Stack pointer

Used with SS to access the stack segment
o BP: Base Pointer
Primarily used to access data on the stack
Can be used to access data in other segments
SI: Source Index register
is required for some string operations

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 When string operations are performed, the SI register
points to memory locations in the data segment which
is addressed by the DS register. Thus, SI is associated
with the DS in string operations.
DI: Destination Index register
is also required for some string operations.
When string operations are performed, the DI register
points to memory locations in the data segment which
is addressed by the ES register. Thus, DI is associated
with the ES in string operations.
The SI and the DI registers may also be used to access data stored in
array

Memory can be addressed as a special case by using register M.

The expanded I/O instructions permit transferring the contents of any one of
256 8-bit ports either to or from the accumulator. The port number is explicitly
contained in the instruction; hence, the instruction is two bytes long. The
equivalent 8008 instruction is only one byte long. This is the only instance in
which an 8080 instruction requires a different number of bytes than its 8008
counterpart. The motivation for doing this was more to free up 32 opcodes than
to increase the number of I/O ports.

The 8080 has the identical interrupt mechanism the 8008 has, but in addition, it
has instructions for enabling or disabling the interrupt mechanism. This feature,
along with the ability to push and pop the processor flags, made the interrupt
mechanism practical.

8085 Objectives and Constraints

In 1976, technology advances allowed Intel to consider enhancing its

8080. The objective was to come out with a processor set utilizing a single

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power supply and requiring fewer chips (the 8080 required a separate oscillator
chip and system controller chip to make it usable). The new processor, called
the 8085, was constrained to be compatible with the 8080 at the machine-code
level. This meant that the only extension to the instruction set could be in the
twelve unused opcodes of the 8080.

The 8085 turned out to be architecturally not much more than a

repackaging of the 8080. The major differences were in such areas as an on-chip
oscillator, power-on reset, vectored interrupts, decoded control lines, a serial I/O
port, and a single power supply. Two new instructions, RIM and SIM, were
added to handle the serial port and interrupt mask. Several other instructions
that had been contemplated were not made available because of the software
ramifications and the compatibility constraints they would place on the
forthcoming 8086.

Objectives and Constraints of 8086

The new Intel 8086 microprocessor was designed to provide an order

of magnitude increase in processing throughput over the older 8080. The
processor was to be assembly-language-level-compatible with the 8080 so that
existing 8080 software could be reassembled and correctly executed on the
8086. To allow for this, the 8080 register set and instruction set appear as
logical subsets of the 8086 registers and instructions. By utilizing a general-
register structure architecture, Intel could capitalize on its experience with the

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8080 to obtain a processor with a higher degree of sophistication. Strict 8080
compatibility, however, was not attempted, especially in areas where it would
compromise the final design.

The goals of the 8086 architectural design were to provide symmetric

extensions of existing 8080 features, and to add processing capabilities not
found in the 8080. These features included 16-bit arithmetic, signed 8- and 16-
bit arithmetic (including multiply and divide), efficient interruptible byte-string
operations, improved bit-manipulation facilities, and mechanisms to provide for
re-entrant code, position-independent code, and dynamically relocatable
programs.

By now memory had become very inexpensive and microprocessors

were being used in applications that required large amounts of code and/or data.
Thus another design goal was to be able to address directly more than 64k bytes
and support multiprocessor configurations.

The 8086 Instruction-Set Processor

The 8086 processor architecture is described in terms of its memory structure,

register structure, instruction set, and external interface. The 8086 memory
structure includes up to one megabyte of memory space and up to 64K
input/output ports. The register structure includes three files of registers. Four

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16-bit general registers can participate interchangeably in arithmetic and logic
operations, two 16-bit pointer and two 16-bit index registers are used for
address calculations, and four 16-bit segment registers allow extended
addressing capabilities. Nine flags record the processor state and control its
operation.

The instruction set supports a wide range of addressing modes and provides
operations for data transfer, signed and unsigned 8- and 16-bit arithmetic,
logicals, string manipulations, control transfer, and processor control. The
external interface includes a reset sequence, interrupts, and a multiprocessor-
synchronization and resource-sharing facility.

A. Memory Structure

The 8086 memory structure consists of two components-the memory space and
the input/output space. All instruction code and operands reside in the memory
space. Peripheral and I/O devices ordinarily reside in the I/O space, except in
the case of memory-mapped devices.

1. Memory Space. The 8086 memory is a sequence of up to 1 million 8-bit

bytes, a considerable increase over the 64K bytes in the 8080. Any two
consecutive bytes may be paired together to form a 16-bit word. Such words
may be located at odd or even byte addresses. The data bus of the 8086 is 16
bits wide, so, unlike the 8080, a word can be accessed in one memory cycle
(however, words located at odd byte addresses still require two memory cycles).

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As in the 8080, the most significant 8 bits of a word are located in the byte with
the higher memory address.

Since the 8086 processor performs 16-bit arithmetic, the address objects it
manipulates are 16 bits in length. Since a 16-bit quantity can address only 64K
bytes, additional mechanisms are required to build addresses in a megabyte
memory space. The 8086 memory may be conceived of as an arbitrary number
of segments, each at most 64K bytes in size. Each segment begins at an address
which is evenly divisible by 16 (i.e., the low-order 4 bits of a segment's address
are zero). At any given moment the contents of four of these segments are
immediately addressable. These four segments, called the current code segment,
the current data segment, the current stack segment, and the current extra
segment, need not be unique and may overlap. The high-order 16 bits of the
address of each current segment are held in a dedicated 16-bit segment register.
In the degenerate case where all four segments start at the same address, namely
address 0, we have an 8080 memory structure.

Bytes or words within a segment are addressed by using 16-bit offset addresses
within the 64K byte segment. A 20-bit physical address is constructed by adding
the 16-bit offset address to the contents of a 16-bit segment register with 4 low-
order zero bits appended, as illustrated in Figure 3.

Various alternatives for extending the 8080 address space were considered. One
such alternative consisted of appending 8 rather than 4 low-order zero bits to the
contents of a segment register, thereby providing a 24-bit physical address

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capable of addressing up to 16 megabytes of memory. This was rejected for the
following reasons:

Segments would be forced to start on 256-byte boundaries, resulting in

excessive memory fragmentation.

The 4 additional pins that would he required on the chip were not
available.

It was felt that a 1-megabyte address space was sufficient.

2. Input/Output Space. In contrast to the 256 I/O ports in the 8080, the 8086
provides 64K addressable input or output ports. Unlike the memory, the I/O
space is addressed as if it were a single segment, without the use of segment
registers. Input/output physical addresses are in fact 20 bits in length, but the
high-order 4 bits are always zero. The first 256 ports are directly addressable
(address in the instruction), whereas all 64K ports are indirectly addressable
(address in register). Such indirect addressing was provided to permit
consecutive ports to he accessed in a program loop. Ports may be 8 or 16 bits in
size, and 16-bit ports may he located at odd or even addresses.

B. Register Structure

The 8086 processor contains three files of four 16-bit registers and a file of nine
1-bit flags. The three files of registers are the general-register file, the pointer-

Mahaveer Inst of Science & Tech, ECE Department Page 66

and index-register file, and the segment-register file. There is a 16-bit
instruction pointer (called the program counter in the earlier processors) which
is not directly accessible to the programmer; rather, it is manipulated with
control transfer instructions. The 8086 register set is a superset of the 8080
registers, as shown in Figures 4 and 5. Corresponding registers in the 8080 and
8086 do not necessarily have the same names, thereby permitting the 8086 to
use a more meaningful set

Mahaveer Inst of Science & Tech, ECE Department Page 67

Mahaveer Inst of Science & Tech, ECE Department Page 68
1, General-Register File. The AX-BX-CX-DX register set is called the general-
register file, or HL group (for reasons that will be apparent below). The general
registers can participate interchangeably in the arithmetic and logical operations
of the 8086. Some of the other 8086 operations (such as the string operations)
dedicate certain of the general registers to specific uses. These uses are
indicated by the mnemonic phrases "accumulator," "base," "count," and "data"
in Figure 5. The general registers have a property that distinguishes them from
the other registers-their upper and lower halves are separately addressable.
Thus, the general registers can be thought of as two files of four 8-bit registers-
the H (high-order) file and the L (low-order) file.

2. Pointer- and Index-Register File. The SP-BP-SI-DI register set is called the
pointer- and index-register file, or the P and I groups. The registers in this file
generally contain offset addresses used for addressing within a segment. Like
the general registers, the pointer and index registers can participate
interchangeably in the 16-bit arithmetic and logical operations of the 8086,
thereby providing a means to perform address computations. These registers
play a major role in effective address computations, as described in the section
on Operand Addressing below (Sec. VIII. C. 1.).

There is one main difference between the registers in this file, which results in
dividing the file into two subfiles, the P or pointer group (SP,BP) and the I or
index group (SI,DI). The difference is that the pointers are by default assumed
to contain offset addresses within the current stack segment, and the indexes are
by default generally assumed to contain offset addresses within the current data
segment. The mnemonic phrases "stack pointer," "base pointer," "source index,"

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and "destination index" are mnemonics associated with these registers' names,
as shown in Figure 5.

3. Segment-Register File. The CS-DS-SS-ES register set is called the segment-

register file, or S group. The segment registers play an important role in the
memory addressing mechanism of the processor. These registers are similar in
that they are used in all memory address computations (see Sec. VIII. A. of this
chapter). The segment registers names have the associated mnemonic phrases
"code," "data," "stack," and "extra as shown in Figure 5.

The contents of the CS register define the current code segment. All instruction
fetches are taken to be relative to CS, using the instruction pointer (IP) as an
offset. The contents of the DS register define the current data segment.
Generally, all data references except those involving BP or SP are taken by
default to be relative to DS. The contents of the SS register define the current
stack segment. All data references which explicitly or implicitly involve SP or
BP are taken by default to be relative to SS. This includes all push and pop
operations, interrupts, and return operations. The contents of the ES register
define the current extra segment. The extra segment has no specific use,
although it is usually treated as an additional data segment which can be
specified in an instruction by using a special default-segment-override prefix.

In general, the default segment register for the two types of data references (DS
and SS) can be overriden. By preceding the instruction with a special one-byte
prefix, the reference can be forced to be relative to one of the other three

Mahaveer Inst of Science & Tech, ECE Department Page 70

segment registers. This prefix, as well as other prefixes described later, has a
unique encoding that permits it to be distinguished from the opcodes.

Programs which do not load or manipulate the segment registers are said to be
dynamically relocatable. Such a program may be interrupted, moved in memory
to a new location, and restarted with new segment-register values.

At first a set of eight segment registers was proposed along with a field in a
program-status word specifying which segment register was currently CS,
which was currently DS, and which was currently SS. The other five all served
as extra segment registers.

Such a scheme would have resulted in virtually no thrashing of segment register

contents; start addresses of all needed segments would be loaded initially into
one of the eight segment registers, and the roles of the various segment registers
would vary dynamically during program execution. Concern over the size of the
resulting processor chip forced the number of segment registers to be reduced to
the minimum number necessary, namely four. With this minimum number, each
segment register could be dedicated to a particular type of segment (code, data,
stack, extra), and the specifying field- in the program status word was no longer
needed.

4. Flag-Register File. The AF-CF-DF-IF-OF-PF-SF-TF-ZF register set is called

the flag-register file or F group. The flags in this group are all one bit in size and
are used to record processor status information and to control processor

Mahaveer Inst of Science & Tech, ECE Department Page 71

operation. The flag registers' names have the following associated mnemonic
phrases:

AF Auxiliary carry
CF Carry
DF Direction
IF Interrupt enable
OF Overflow
PF Parity
SF Sign
TF Trap
ZF Zero

The AF, CF, PE, SF, and ZF flags retain their familiar 8080 semantics, generally
reflecting the status of the latest arithmetic or logical operation. The OF flag
joins this group, reflecting the signed arithmetic overflow condition. The DF, IF,
and TF flags are used to control certain aspects of the processor. The DF flag
controls the direction of the string manipulations (auto-incrementing or auto-
decrementing). The IF flag enables or disables external interrupts. The TF flag
puts the processor into a single-step mode for program debugging. More detail
is given on each of these three flags later in the chapter.

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C. Instruction Set

The 8086 instruction set-while including most of the 8080 set as a subset-has
more ways to address operands and more power in every area. It is designed to
implement block-structured languages efficiently. Nearly all instructions operate
on either 8- or 16-bit operands. There are four classes of data transfer. All four
arithmetic operations are available. An additional logic instruction, test, is
included. Also new are byte- and word-string manipulations and intersegment
transfers.

1. Operand Addressing. The 8086 instruction set provides many more ways to
address

operands than were provided by the 8080. Two-operand operations generally

allow either a register or memory to serve as one operand (called the first
operand), and either a register or a constant within the instruction to serve as the
other (called the second operand). Typical formats for two-operand operations
are shown in Figure 6 (second operand is a register) and Figure 7 (second
operand is a constant). The result of a two-operand operation may be directed to
either of the source operands, with the exception, of course, of in-line
immediate constants. Single-operand operations generally allow either a register
or a memory to serve as the operand. A typical one- operand format is shown in
Figure 8. Virtually all 8086 operators may specify 8- or 16-bit operands.

Memory operands. An instruction may address an operand residing in memory

in one of four ways as determined by the mod and rim fields in the instruction
(see Table 2).

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 Direct 16-bit offset address

Indirect through a base register (BP or BX), optionally with an 8- or 16-

bit displacement

Indirect through an index register (SI or DI), optionally with an 8- or 16-

bit displacement

Indirect through the sum of a base register and an index register,

optionally with an 8- or 16-bit displacement

The general register, BX, and the pointer register, BP, may serve as base
registers. When the base register EX is used without an index register, the
operand by default resides in the current data segment. When the base register
BP is used without an index register, the operand by default resides in the
current stack segment. When both base and index registers are used, the operand
by default resides in the segment determined by the base register. When an
index register alone is used, the operand by default resides in the current data
segment.

Auto-incrementing and auto-decrementing address modes were not included in

general, since it was felt that their use is mainly oriented towards string
processing. These modes were included on the string primitive instructions.

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Register operands. The four 16-bit general registers and the four 16-bit pointer
and index registers may serve interchangeably as operands in 16-bit operations.
Three exceptions to note are multiply, divide, and the string operations, all of
which use the AX register implicitly. The eight 8-bit registers of the HL group
may serve interchangeably in 8-bit operations. Again, multiply, divide, and the
string operations use AL implicitly. Table 3 shows the register selection as
determined by the r/m field (first operand) or reg field (second operand) in the
instruction.

Immediate operands. All two-operand operations except multiply, divide, and

the string operations allow one source operand to appear within the instruction
as immediate data represented in 2's complement form. Sixteen-bit immediate
operands having a high-order byte which is the sign extension of the low-order
byte may be abbreviated to 8 bits.

Addressing mode usage. The addressing modes permit registers BX and BP to

serve as base registers and registers SI and DI as index registers. Possible use of
this for language implementation is discussed below.

Simple variables and arrays: A simple variable is accessed with the direct
address mode. An array element is accessed with the indirect address
mode utilizing the sum of the register SI (where SI contains the index into
the array) and displacement (where displacement is the offset of the array
in its segment).

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 Based variables: A based variable is located at a memory address pointed
at by some other variable. If the contents of the pointer variable were
placed in BX, the indirect addressing mode utilizing BX would access the
based variable. If the based variable were an array and the index into the
array were placed in SI, the indirect addressing mode utilizing the sum of
the register BX and register SI would access elements of the array.

Stack marker: Marking a stack permits efficient implementation of block-

structured languages and provides an efficient address mechanism for
reentrant procedures. Register BP can be used as a stack marker pointer to
the beginning of an activation record in the stack. The indirect address
mode utilizing the sums of the base register BP and a displacement
(where displacement is the offset of a local variable in the activation
record) will access the variable declared in the currently active block. The
indirect address mode utilizing the sum of the base register BP, index
register SI (where SI contains the index in an array), and displacement
(where displacement is the offset of the array in the activation record)
will access an element of the array. Register DI can be used in the same
manner as SI so that two array elements can be accessed concurrently.

Table 2 Determining 8086 Offset Address of a Memory Operand

(Use This Table When mod 11; Otherwise Use Table 3.)

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This table applies to the first operand only; the second operand can never be a
memory operand.

mod specifies how disp-lo and disp-hi are used to define a displacement as
follows:

mod = 00: DISP=0 (disp-lo and disp-hi are absent)

mod = 01: DISP=disp-lo sign extended (disp-hi is absent)

mod = 10: DISP = disp-hi,disp-lo

r/m specifies which base and index register contents are to be added to the
displacement to form the operand offset address as follows:

r/m = 000: OFFSET = (BX) + (SI) + DISP (indirect address mode)

r/m = 001: OFFSET = (BX) + (DI) + DISP (indirect address mode)

r/m = 010: OFFSET = (BP) + (SI) + DISP (indirect address mode)

r/m = 011: OFFSET = (BP) + (DI) + DISP (indirect address mode)

r/m = 100: OFFSET = (SI) + DISP (indirect address mode)

r/m = 101: OFFSET = (DI) + DISP (indirect address mode)

r/m = 110: OFFSET = (BP) + DISP (indirect address mode)

r/m = 111: OFFSET = (BX) + DISP (indirect address mode)

Mahaveer Inst of Science & Tech, ECE Department Page 77

The following special case is an exception to the above rules

If mod=00 and r/m=100 then

OFFSET = DISP-HI, DISP-LO (direct address mode)

interrupts. The 8080 interrupt mechanism was general enough to permit the
interrupting device to supply any operation to be executed out of sequence when
an interrupt occurs. However, the only operation that had any utility for
interrupt processing was the 1-byte subroutine call. This byte consists of 5 bits
of opcode and 3 bits identifying one of eight interrupt subroutines residing at
eight fixed locations in memory. If the unnecessary generalization was removed,
the interrupting device would not have to provide the opcode and all 8 bits
could be used to identify the interrupt subroutine. Furthermore, if the 8 bits
were used to index a table of subroutine addresses, the actual subroutine could
reside anywhere in memory. This is the evolutionary process that led to the
design of the 8086 interrupt mechanism.

Interrupts result in a transfer of control to a new location in a new code

segment. A 256-element table (interrupt transfer vector) containing pointers to
these interrupt service code locations resides at the beginning of memory. Each
element is four bytes in size, containing an offset address and the high-order 16-
bits of the start address of the service code segment. Each element of this table
corresponds to an interrupt type, these types being numbered 0 to 255. All
interrupts perform a transfer by pushing the current flag setting onto the stack
and then performing an indirect call (of the intersegment variety) through the
interrupt transfer vector.

Mahaveer Inst of Science & Tech, ECE Department Page 78

The 8086 processor recognizes two varieties of external interrupt-the non-
maskable interrupt and the maskable interrupt. A pin is provided for each
variety.

Mahaveer Inst of Science & Tech, ECE Department Page 79

Summary and Conclusions

"The 8008 begat the 8080, and the 8080 begat the 8085, and the 8085 begat the
8086."

During the six years in which the 8008 evolved into the 8086, the processor
underwent changes in many areas, as depicted by the conceptual diagram of
Figure 10. Comparisons in performance and technology are shown in Tables 5
and 6.

The era of the 8008 through the 8086 is architecturally notable for its role in
exploiting technology and capabilities, thereby lowering computing costs by
over three orders of magnitude. By removing a dominant hurdle that has
inhibited the computer industry the necessity to conserve expensive
processors the new era has permitted system designers to concentrate on
solving the fundamental problems of the applications themselves.

3.3 Applications

EXTERNAL HARDWARE YNCHRONIZATIONS

PROCESSOR CONTROL
ITERATION CONTROL
BIT MANIPULATION

Mahaveer Inst of Science & Tech, ECE Department Page 80

 References

Bylinsky, G., "Here Comes the Second Computer Revolution," Fortune,

November 1975.

Faggin, F., M. Shima, M. E. Hoff, Jr., H. Feeney, and S. Mazor, "The MCS-4:
An LSI Micro Computer System," IEEE Region 6 Conf. 1972, pp. 8-11.

Hoff, M. E., Jr., "The New LSI Components," 6th Annual IEEE Comp. Soc. Jut.
Conf, 1972.

Intel 8080 Microcomputer Systems User's Manual, September 1975.

Intel MCS-8 User's Manual, April 1975

Intel MCS-40 User's Manual, 3d ed., March 1976.

Intel MCS-85 User's Manual, March 1977.

Intel MCS-86 User's Manual, July 1978.

Morse, S. P: "The 8086 Primer," Hayden Book Co., New York, 1980.

Morse, S. P., W. B. Pohlman, and B. W. Ravenel, "The Intel 8086

Micropocessor A 16-Bit Evolution of the 8080," Computer, June 1978, pp. 18-
27.

Shima, M., F. Faggin, and S. Mazor, "An N-Channel 8-Bit Single Chip
Microprocessor," IEEE Int. Solid-State Circuits Conf, February 1974, pp. 56-57.

Vadasz, L. L., A. S. Grove, T. A. Rowe, and G. E. Moore, "Silicon Gate

Technology," IEEE Spectrum, October 1969, pp. 27-35.

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