PCIe Designguides PDF

Board Design Guidelines
for PCI Express Architecture

Zale Schoenborn
Co-Chair, PCI Express Electrical WG
Copyright 2004, PCI-SIG, All Rights Reserved 1

Agenda
Background
Layout considerations
System board requirements
Add-in card designs
Signal validations
Summary
PCI-SIG APAC Developers Conference Copyright 2004, PCI-SIG, All Rights Reserved 2
Background
T/s
Bus Topology Evolution 133
M
CONN
CONN
MCH
PCI common clock
Meet setup/hold timing CLK
Multi-drop parallel I/O T/s
M
533
AGP source synchronous
CONN
Single strobe, multiple data MCH
Match all data to strobes

T/s
PCI Express serial differential 2.5
+G
Embedded clock
CONN
MCH
Point-to-point, match per data pair only
Longer route, creative device placement
PCI
PCI Express
Express pt-to-pt
pt-to-pt routing
routing is
is straightforward
straightforward
Background
Serial Differential Diff pairs

System board Add-in card AC coupled
D+ Lane-to-lane
PCI Express
Connector
RX D- TX de-skew
AC caps Polarity
TX RX
RX inversion
Transmitter & Receiver & On-chip
package package equalization
(de-emphasis)
On-chip
TX Spec Interconnect RX terminations
Loss < 13.2 dB
Eye Jitter < 0.3 UI Spec 175 mV
800 mV
0.7 UI 0.4 UI
UI = Unit Interval = 400ps
(TX eye shown without de-emphasis)
Background
PCI Express Routing

Trace length matching between pairs
is not required
Embedded clock simplifies
routing rules
Longer motherboard traces
12+ inches possible
TX pairs usually route on top layer
AC coupling caps on TX traces on
system board
AC Coupling Caps
PCI Express x16 Connector

Trace Serpentines Not Required
Background
Interconnect Budget
Loss and jitter are key parameters
Target impedance not as critical
Maintain differential pair symmetry
Design tradeoffs: loss vs. trace length, etc.
Recommended Solution Space: Graphics Add-In Card
System board traces: Graphics

Engine
Via
Up to 12 inches Manufacturing
Probe Point
Add-in card traces: AC-Coupling

Caps
Up to 3.5 inches
GMCH
Chip-to-chip routes: Top
System board traces: Vcc

Gnd
Bottom
Up to 15 inches Manufacturing
Probe Point Via
X16 Connector
Manage
Manage loss
loss and
and jitter
jitter to
to meet
meet budget
budget
Stackup Design
No new PCB
technology
required
Standard 4-layer
stackup 0.062
thick PCB
T
Microstrip oz Cu
plated
-OR-
Stripline 1 oz Cu T = ~62 mils
(6+ layers)
Follow
Follow simple
simple layout
layout rules
rules &
& design
design tradeoffs
tradeoffs
Trace Geometry & Impedance

Wide pair-to-pair spacing minimize crosstalk
Close intra-pair spacing
Same geometry for interleaved/non-interleaved
Example impedance targets:
Single-end Zo of 60 15%
Differential Impedance of ~100 20%
Tx Tx
Tx w Tx Tx 5 7 5 20 mil
h
Non-interleaved topology example Microstrip
Tx Tx
Rx w Tx Rx 5 5 5 20 mil
h
Interleaved topology example
Stripline
FR4 Loss Considerations

Stackup: FR4 material Glass Material
Narrow traces loss Resin Material
Copper roughness loss
Dielectrics with more resin material
loss
Non-homogeneous dielectrics
Localized Zo variation due to
material weave loss FR4 cross-section
Wide differential impedance

variation on strip traces
Etching and plating process loss
Trace Length
Longer trace length loss
~0.25 to 0.35 dB inherent loss per inch for FR4
microstrip traces at 1.25GHz
Manage trace lengths to minimize loss
Example: 12 board, 3.5 add-in card lengths
1.25GHz
freq
-5.23dB
20-inch line
dB Example VNA measurements for

differential strip trace insertion loss
Trace Symmetry & Matching

No matching needed pair-to-pair
Match each differential pair per segment
Match overall length 5 mils (recommended)
Symmetric routing for each pair
Preferred
matching
Match
near 45 mils
mismatch
Alternative
matching
Bends and Small Serpentines

Avoid tight bends
No 90 bends; impact to loss
and jitter budgets
Keep angles >= 135 (a) C
A
Maintain adequate air gap
A >= 4x the trace width
B
Lengths of B, C >= 1.5x the
width of the trace >3w
w
Serpentines length is at least S S1 < 2 S

3w for jog
Package Pin Field Breakout

Use side-by-side breakout for package to maintain
symmetry
Avoid tight bends
Side-by-side Best
Adjacent w/ small
serpentine OK
Adjacent w/ bend Fair
Diagonal routing Fair
Reference Plane
Full GND plane reference Gnd stitching via
recommended
Stitching vias required for
layer transition
Plane Void
Keep clearance from
Long trace routes
plane voids
Avoid plane splits
Avoid trace over
anti-pad
AC Coupling Caps
Size: 0402 best, 0603 ok
No 0805 size or C-packs
Symmetric placement best
Cap size: 0.1uF best

Same sizes for both D+/D-
Cap location:
Along Tx pairs on system board
Along Tx pairs on add-in card
Test Points & Vias

Minimize via usage
Up to 0.25 dB loss per via
Use via pad size 25 mil, hole size 14 mil; standard
anti-pad size of 35 mil
Put test points or LAI pads in series (if used)
No stubs
Place symmetrically
Provide GND pads for single-ended probing
LAI pads
Probe pads
GND pads
Reference Clock
Clocks have no phase relationships
Length matching for clocks is NOT required!
Deliver diff clock to each device and connector
Use same trace geometries as other diff pairs
Clock driver requirements:
100MHz with SSC support (e.g. CK410)
System board (source) termination only
Rise/fall slew rate requirements need to be met
0.5 3.5
Clock Driver 22 - 33
Rs
5% 1 14PCI Express PCI Express Card
Connector
L1 L2 L4 L5
L1' L2' L4' L5'

Rs
0.5 00.2
max
L3' L3
0 0.2
Rt Rt 49.9 1%
Connector Layout
Side B: Side A:
Connector with standard PTH Tx Rx
Connector sizes: x1, x4, x8, x16
Pinout optimized for differential routing D+
D-
& crosstalk reduction D+
D-
Polarity inversion allowed
Gnd
Gnd
Loss & crosstalk part of system Gnd
Gnd
board budget
Gnd= Green
TX= Red
Rx= Blue
Improved
Improved PTH
PTH connector
connector for
for PCI
PCI Express
Express
Power Rails
Increased current capability for x16 connector
date Additional +12V pin; 1.1 Amp per pin capability
Up
Helpful grouping of power supply pins
Eases power delivery routing
ATX power supply connector
2x12 (recommended)
Power Rail x16 Connector Spec
+3.3V
Voltage Tolerance 9% (max)
Current 3.0 A (max)
+12V
Current 5.5A (max)
+3.3Vaux
Current: Wake 375 mA (max)
Non-Wake 20 mA (max)
Power Consumption
ate
Up
d PCI Express introduces a spec for 75W cards
Available for x16 connectors
Allows for performance graphics cards
75W can be fully drawn thru x16 connector
Note: 25W at initial power-up
(75W after configuration as a high power device)
Up to 25W allowed for x1,x4,x8 cards
Connector Size Power Consumption Allowances
X1 x4/x8 x16
Standard height 10 W 1 25 W 25 W (max) 25 W1 75 W
(max) (max) (max) (max)
Low profile card 10 W (max) 10 W (max) 25 W (max)
1. Max at initial power-up only.
PCI
PCI Express
Express spec
spec support
support for
for 75W
75W cards
cards
Power Delivery - 75W Support

Ensure +3.3V & +12V tolerances at add-in card
Max of 2%~3% MB +12V voltage drop (e.g. 360mV)
Typical power supply = 5% drop Example uATX +12V layout
Balance trace width vs. length
Example: 100 mils min trace width,
= 12 length for +12V with 1oz Cu
Proper power decoupling
Max current slew rate of 0.1A/s
Suppress high freq coupling noise
Tune capacitor type/location
to board needs 2x12 Power Supply Connector
Thermal & Acoustic Management

Platforms need to deliver cool air to x16 slot
Use side panel vents, ducting
75W card recommendation: 55 C air temp at graphics
o
card fan intake

Use larger fans for better acoustics
Cool Air
Source
Recommended PCI Express

PCI-SIG APAC Developers Conference
Side Panel Vent
Copyright 2004, PCI-SIG, All Rights Reserved 22
Add-in card requirements
Card Edge Fingers

Remove ref plane under edge
finger pads Outer Layer Differential Pair
Signal Traces
Better impedance match Layer 2
Ref Plane
PRSNT1#, PRSNT2# Pins Outer Layer

1mm shorter: last-mate, first Edge Fingers
Layer 3 Ref Plane
break Hot-Plug support
Multiple PRSNT2# pins
(x4,x8,x16 cards)
PRSNT1# to PRSNT2#
Cards must strap PRSNT1# Strapping Example
with furthest PRSNT2# signal
System board Hot-Plug support
optional
Card Retention
Card allows for chassis & system board-based retention
Fixed card height & keep outs
Hockey-stick near edge fingers
ate
PCI-SIG* design guideline for retention solution Up
d
Clip for system board, card hockey-stick

Supports up to 350g for 75W cards
OEMs free to innovate independent solutions
Requires two, 80-mil

diameter holes
Hockey-Stick Retention Mechanism

Card Physical Dimensions

End bracket Top edge keep out and fixed
height to enable chassis
level retention solutions
Hockey-stick to allow for

new retention solutions
Fixed height for I/O cards

(allowance for low profile compliance)
Gfx Thermal & Acoustic

Limit heat re-circulated thru Gfx card heat sink
Use shroud to separate fan intake and heat sink
exhaust
Place fan intake near air source- direct away the
exhaust
Reduce fan noise and low speed chatter
Use diode and/or thermister for fan speed control
cool air source (e.g. from chassis vent)
intake shroud
exhaust
exhaust
Signal validations
Lab Signal Measurements

PCI Express devices generate PCI Express connector
compliance pattern per spec
Use compliance boards for signal
validation
Compliance Base Board (CBB) for add-in
card measurements CBB Example
Compliance Load Board (CLB) for system
board measurements
Measure eye diagrams with real time
scope
6+ GHz analog bandwidth
20+ Gs sampling bandwidth
CLB Example
Scope vendor should have eye diagram
signal analysis SW tool
Signal validations
Acquiring & Interpreting Results

Example
Probe locations Transition Bit Eye
Tx Signals: measure at 50 loads

Rx Signals: measure at package input
pins
Scope post-processing software
Create transition bit eye
Create de-emphasized eye Example
De--emphasized Bit Eye
De
Determine:
Max jitter
Min eye voltage margin (high/low)
Max AC common mode voltage
Validate
Validate eye
eye diagrams
diagrams using
using real
real time
time scope
scope
Summary
Summary
PCI Express point-to-point layout is
straightforward
Manage loss and jitter from PCB to meet
interconnect budget
Follow basic layout rules and design tradeoffs to
implement typical topologies
Improved connector & add-in card features -
support for 75 Watt cards
Validate compliance eye diagrams using
compliance boards and real time scope
Collateral
For additional and updated information on PCI
Express Architecture, visit
http://www.pcisig.com
Thank you for attending the
2004 PCI-SIG Asia-Pacific
Developers Conference.
For more information please go to

www.pcisig.com

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What are the main considerations for PCI Express board layout?

What are the main considerations for PCI Express board layout?

What are the main signal integrity parameters that need to be managed for PCI Express?

What are the main signal integrity parameters that need to be managed for PCI Express?

Board Design Guidelines

for PCI Express Architecture

Copyright 2004, PCI-SIG, All Rights Reserved 1

Match all data to strobes

Serial Differential Diff pairs

PCI Express Routing

PCI Express x16 Connector

System board traces: Graphics

Add-in card traces: AC-Coupling

System board traces: Vcc

Trace Geometry & Impedance

FR4 Loss Considerations

Wide differential impedance

dB Example VNA measurements for

Trace Symmetry & Matching

Bends and Small Serpentines

Serpentines length is at least S S1 < 2 S

Package Pin Field Breakout

Diagonal routing Fair

Cap size: 0.1uF best

Test Points & Vias

L1' L2' L4' L5'

Power Delivery - 75W Support

Thermal & Acoustic Management

card fan intake

Recommended PCI Express

Card Edge Fingers

PRSNT1#, PRSNT2# Pins Outer Layer

Clip for system board, card hockey-stick

Requires two, 80-mil

Hockey-Stick Retention Mechanism

Card Physical Dimensions

Hockey-stick to allow for

Fixed height for I/O cards

Gfx Thermal & Acoustic

Lab Signal Measurements

Acquiring & Interpreting Results

Tx Signals: measure at 50 loads

For more information please go to

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