IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO.

4, APRIL 2014 1659

High Gain Soft-Switching Bidirectional DCDC

Converter for Eco-Friendly Vehicles
Minho Kwon, Secheol Oh, and Sewan Choi, Senior Member, IEEE

AbstractThis paper proposes a nonisolated soft-switching bidi- in the aforementioned systems. If the conventional half-bridge
rectional dcdc converter suitable for high step-up and step-down topology is used for high voltage gain, the boost diode must
applications. The proposed converter can achieve zero voltage sustain a short pulse current with high amplitude, resulting in
switching turn on of all switches and zero-current-switching turn
off of some switches in continuous conduction mode in both for- severe reverse recovery [1], [6] as well as high EMI problems.
ward and reverse modes. An optimized switching strategy is pre- Using an extreme duty cycle may also lead to poor dynamic
sented to minimize switch current rating and achieve soft switching responses to line and load variations. These make the conven-
in wider range. An intermediate switching pattern is introduced tional half-bridge topology inefficient in the applications where
to carry out seamless mode change. Experimental results from a high voltage gain is required.
5-kW prototype are provided to validate the proposed concept.
Also, high-frequency operation is required to achieve high
Index TermsBidirectional dcdc converter (BDC), continuous power density, improve dynamic characteristic, and reduce
conduction mode (CCM), high step-up, high voltage gain, noniso- acoustic noise. The switching frequency of the hard switching
lated, soft switched.
BDC is limited due to switching losses and EMI problem [7]. In
I. INTRODUCTION order to increase switching frequency of the BDC, several soft-
switching techniques have been applied to the half-bridge topol-
HE advantages of using a bidirectional dcdc converter
T (BDC) in hybrid electric vehicles (HEVs) are efficient
charge of regenerative energy as well as voltage boost and reg-
ogy that could achieve zero voltage switching (ZVS) or zero-
current-switching (ZCS) of main switches using an auxiliary cir-
cuit in both forward and reverse modes of operation [8], [9], [20].
ulation for efficient operation of inverters and motors. The con- The converter in [8] integrates an active clamp circuit into the
ventional half-bridge topology [1], [17] has been used as a BDC half-bridge topology to achieve soft-switching in CCM oper-
for HEV due to simple structure. The multiphase interleaved ation. The converter in [9] is based on a cascaded buck-boost
technique [2] can be employed to decrease the volume of passive structure with active snubber circuits in order to achieve zero-
component. However, the switch voltage rating of the converter voltage and zero-current transition, showing high efficiency de-
based on half-bridge topology is the same as the output voltage. spite of its circuit complexity. The converter is capable of being
The three-level converter in [3] has lower switch voltage stress operated with boost and buck operations in both forward and
(half compared to the half-bridge topology) and smaller passive reverse modes. However, they are not suitable for application
components even though the component count increases. where high-voltage conversion ratio in both boost and buck
In HEV, the input voltage of the inverter has a tendency to in- operations is required.
crease in order to use high-speed high-power motor and improve BDCs based on coupled or tapped inductors [10][13], [21]
the efficiency and power density of the inverter. For example, can provide high output voltage without extreme duty cycle and
the input voltage has increased from 500 to 650 V in fourth- yet reduce the switch voltage stress. In these coupled induc-
generation PCU of Toyota Prius HEV, where a Ni-MH battery of tor converters, in general, the effort to overcome the problem
nominal voltage of 201.6 V has been installed [4]. In the mean- associated with a leakage inductor of the coupling inductor is
time, the battery voltage is preferred to be low since parallel nontrivial, and the capacity of the magnetic core should substan-
strings of storage batteries not only enhance the redundancy of tially be increased as the required output power is increased.
the back-up system, but also alleviate the problems associated Therefore, these topologies incorporating the coupling induc-
with charge imbalance compared to series strings [5]. There- tor are not suitable for high-power applications. Also, the input
fore, high efficiency BDC with high voltage gain is preferred current ripple is considerable due to the operation of coupling
inductor.
Manuscript received December 21, 2012; revised April 28, 2013; accepted The BDC using switched-capacitor converter cells could have
June 10, 2013. Date of current version October 15, 2013. This work was sup- more modular structure and higher power handling capability,
ported in part by Seoul National University of Science and Technology and by but the required number of switches becomes high [14][16].
a National Research Foundation of Korea (NRF) grant funded by the Korea
Government (MEST) (No. 2012-000545). Recommended for publication by They are hard-switched, and high current pulse occurs since
Associate Editor M. Ferdowsi. two capacitors with different voltages are connected in parallel
M. Kwon and S. Choi are with the Department of Electrical and Information at each switching instant. A major drawback of the switched-
Engineering, Seoul National University of Science and Technology, Seoul 139-
743, Korea (e-mail: [email protected]; [email protected]). capacitor-based converter is that ESR drop of the active and
S. Oh is with the Vehicle Component Research and Development Group, LG passive devices is considerable due to high number of series
Electronics Co. Ltd., Pyeongtaek 451-713, Korea (e-mail: [email protected]). connected devices in the current path, resulting in reduced output
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. voltage. This may restrict the power level to which the switched-
Digital Object Identifier 10.1109/TPEL.2013.2271328 capacitor converter can be applied. So far, the nonisolated BDC
0885-8993 2013 IEEE
1660 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 4, APRIL 2014

Fig. 1. Proposed high step-up soft-switched bidirectional dcdc converter.

with high-voltage gain that can be applied to high power level

has rarely been proposed.
In this paper, a new nonisolated BDC for high step-up/step-
down and high-power applications is proposed. The optimized
PWM switching technique for boost and buck operations and
smooth mode transition is also presented. The proposed con-
verter has the following advantages:
1) high voltage gains for both boost and buck operations;
2) reduced (nearly half) voltage stresses of switches;
3) ZVS turn on and ZCS turn off of switches in CCM oper-
ation;
4) reduced energy volumes of passive components;
5) seamless mode transition.

II. PROPOSED CONVERTER

Fig. 1 shows the circuit diagram of the proposed BDC. The
proposed converter consists of a general half-bridge converter
as the main circuit and an auxiliary circuit that includes the
capacitor Ca , inductor La , and two high-voltage side (HVS)
switches S3 and S4 . The goal of control, in this paper, is assumed Fig. 2. Key waveforms of the proposed converter (boost operation).
to regulate the HVS voltage VH , while allowing bidirectional
power flow according to the direction of inductor current IL f . Mode II [t1 t2 ]: When the increasing current iL f becomes
greater than the decreasing current iL a , current flowing through
A. Operating Principle S1 is reversed, and the main channel of S1 conducts. This mode
Assume that capacitances C1 , C2 , and Ca are large enough ends when the decreasing current iL a reaches 0 A. Note that
so that voltages VC 1 , VC 2 , and VC a across them are constant switch S4 is also turned OFF under ZCS condition.
during the switching period TS . Mode III [t2 t3 ]: At t2 current iL a is reversed and the body
1) Boost Operation (Forward Mode): Figs. 2 and 3 show key diode of S3 is turned ON. For synchronous rectification the
waveforms and operation states of the boost operation, respec- gating signal for S3 can be applied after t2 . Note that S3 is
tively. In this mode, low-voltage side (LVS) switches S1 and S2 turned ON under ZVS condition. Inductor current iL a linearly
are operated with asymmetrical complementary switching with increases with the slope determined by the following equation:
duty cycles of D and 1D, respectively, as shown in Fig. 2. In
diL a VC a VC 1
the mean time, HVS switches S3 and S4 are turned ON with = . (3)
dt La
delay times of td3 and td4 , respectively. The operation of the
proposed converter can be divided into five modes, as shown in Both inductor currents iL f and iL a flow through switch S1 .
Fig. 3. Mode IV [t3 t4 ]: At t3 switches S1 and S3 are turned OFF,
Mode I [t0 t1 ]: This mode begins with turning OFF of S2 and then body diodes of S2 and S3 are turned ON. Both inductor
and S4 . Then, the body diodes of S1 and S4 are turned ON. currents iL f and iL a start to decrease with the slopes determined
The gating signal for S1 is applied with appropriate dead-time by the following equations:
during this mode, and then S1 could be turned ON under ZVS
condition. Inductor currents iL f and iL a start to increase and de- diL f VL VC 1
= (4)
crease, respectively, with the slopes determined by the following dt Lf
equations: diL a VC a
= . (5)
diL f VL dt La
= (1)
dt Lf The gating signal for S2 is applied with appropriate dead-time
diL a VC a VC 1 VC 2 during this mode, and then S2 could be turned ON under ZVS
= . (2) condition. This mode ends when the decreasing current iL a
dt La
KWON et al.: HIGH GAIN SOFT-SWITCHING BIDIRECTIONAL DCDC CONVERTER FOR ECO-FRIENDLY VEHICLES 1661

Fig. 3. Operation states of the proposed converter (boost operation).

2) Buck Operation (Reverse Mode): Figs. 4 and 5 show key

waveforms and operation states of the buck operation, respec-
tively. In this mode, HVS switches S3 and S4 are operated with
asymmetrical complementary switching with duty cycles of D
and 1D, respectively, as shown in Fig. 4. In the mean time,
LVS switch S2 is turned ON with delay time of td2 . The opera-
tion of the proposed converter can be divided into six modes, as
shown in Fig. 5.
Mode I [t0 t1 ]: This mode begins with turning OFF of
switches S2 and S4 . Then, the body diodes of S1 and S3 are
turned ON after the parasitic capacitors of S3 and S4 are com-
pletely discharged. Inductor current iL f starts to decrease with
the slope determined by (1).
Mode II [t1 t2 ]: At t1 inductor current iL a starts to decrease
with the slope determined by (3). After appropriate dead-time
switches S1 and S3 are turned ON. The gate signal for S3 should
be applied before reversal of current iL a for ZVS turn ON. Note
S1 is turned ON without any delay for synchronous rectification.
This mode ends when the decreasing current iL a reaches 0 A.
Mode III [t2 t3 ]: At t2 inductor current iL a is reversed and
starts increasing with slope determined by (3). From (3), the
positive peak value of iL a can be obtained as follows:


VC a VC 1 2 COSS
IL a+ = DTS VC 2 (7)
La La

Fig. 4. Key waveforms of the proposed converter (buck operation).

where COSS is the output capacitance of the switch.
Mode IV [t3 t4 ]: Switches S1 and S3 are turned OFF at t3 ,
reaches 0 A. Note that switch S3 is also turned OFF under ZCS and the n body diodes of S1 and S4 are turned ON. Inductor
condition. current iL a starts to decrease with the slope determined by (2).
Mode V [t4 t5 ]: This mode begins when current iL a is re- Note that S4 could be turned ON under ZVS condition if the
versed and the body diode of S4 is turned ON. For synchronous gate signal for S4 is applied with appropriate dead-time before
rectification, the gating signal for S4 can be applied after t4 . reversal of current iL a . This mode ends when the decreasing
Note that S4 is turned ON under ZVS condition. Inductor cur- current iL a reaches 0 A.
rent iL a linearly increases with the slope determined by the Mode V [t4 t5 ]: When the increasing current iL a becomes
following equation: greater than the decreasing current iL f , body diode of S1 is
turned OFF under ZCS condition. Then, after parasitic capac-
diL a VC a VC 2 itors of S1 and S2 are completely charged and discharged, re-
= . (6) spectively, the body diode of S2 is turned ON and inductor
dt La
currents iL a and iL f start to decrease and increase, respectively,
This is the end of one complete cycle. with slopes determined by (6) and (4), respectively. The negative
1662 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 4, APRIL 2014

Fig. 5. Operation states of the proposed converter (buck operation).

peak value of iL a is determined by the following equation:

IL f VC 1
IL a = IL f +  (8)
2 La /(2 COSS )
where IL f is current ripple of Lf . For ZVS turn on of S2 ,
the gate signal for S2 should be applied before the decreasing
current iL a becomes smaller than the increasing current iL f .
Mode VI [t5 t6 ]:At t5 switch current iS 2 is reversed. Inductor
currents iL a and iL f keep decreasing and increasing with slopes
determined by (6) and (4), respectively. At the end of this mode
S2 and S4 are turned OFF. This is the end of one complete cycle.

B. Voltage Conversion Ratio

The HVS voltage is given by the following equation [18], Fig. 6. Voltage gain of the proposed converter.
[19]:
2 Then, the positive and negative peak values of iL a can be ob-
VH = VL (9)
1 De tained as follows:
where the effective duty is defined as follows (see Fig. 2): 2 VH
IL a+ = (16)
1 D RH
De = D (d3 + d4 ) (10)
2 VH
where d3 +d4 means duty loss. The output voltage can also be IL a = . (17)
D RH
expressed as follows:
By applying volt-second principle to inductor La , we can obtain
2 the duty losses by the following equations:
VH = VL V (11)
1D
2 VH La
where V is the voltage drop caused by the duty loss. From (9), d3 = (18)
1 D R H TS VC 1
(10), and (11) the voltage drop V can be obtained as follows:
2 VH La
2VL (d3 + d4 ) d4 = (19)
V = . (12) D R H TS VC 1
(1 D)(1 D + d3 + d4 )
where VC 1 is the same as the output voltage of the general boost
Because the average current of both Ca and C2 is zero, the converter and can be expressed as follows:
average absolute currents of HVS switches can be expressed as
VL
follows: VC 1 = . (20)
 TS  TS 1D
1 1
|iS3 |dt = |iS4 |dt = IH (13) From (11), (12), (18), (19), and (20), the voltage gain can be
TS 0 TS 0
obtained as follows:
where IH =VH /RH . Assuming that the difference in duty losses 
VH 2 (1 D)2 + 4 (1 D)
d3 and d4 is much smaller than D, conduction times of HVS = (21)
switches in the boost operation can be approximated as follows: VL
where = DRH , = 4La fs and fs = 1/TS . Using (21), the
t4 t2 DTS (14)
voltage gain of the proposed converter is plotted as shown in
t6 t4 (1 D)TS . (15) Fig. 6.
KWON et al.: HIGH GAIN SOFT-SWITCHING BIDIRECTIONAL DCDC CONVERTER FOR ECO-FRIENDLY VEHICLES 1663

Fig. 8. Switching sequence for seamless mode change.

Fig. 7. Switching pattern for each operation. (a) Pattern 1 (boost operation). Fig. 9. Control block diagram of proposed converter for regulating HVS volt-
(b) Pattern 2 (intermediate operation). (c) Pattern 3 (buck operation). age under bidirectional operation.

C. Mode Change Strategy

In this section, a mode change strategy is proposed in order
to carry out seamless transfer during mode change. Fig. 7 shows
optimal switching patterns for each operation. The delay times
for S2 , S3 , and S4 are defined as td2 , td3 , and td4 , respectively.
The minimum delay time td2,m in for ZVS turn on of S2 is
determined by the peak values of iL f and iL a as follows:
La (1 D) Fig. 10. Circuit diagram of the two-phase interleaved prototype converter.
td2,m in = d2 TS = (IL a+ IL f ,m ax ) (22)
VL
where IL a+ is the peak value of iL a in the buck operation. in Fig. 8. If the band is too wide, ZVS may not be achieved
From (18), (19), and (20), the other minimum delay times are under the light load condition. Whereas, if the band is too nar-
determined as follows: row, there will be bumping at the mode transition caused by a
2La VH sudden change in switching pattern and be chattering problem
td3,m in = d3 TS = (23) under the light load condition. The maximum value of Iupp er
RH VL
is determined by load condition that the minimum delay time
1 D 2La VH of S3 or S4 becomes equal to dead-time Tdead . From (23) and
td4,m in = d4 TS = . (24)
D RH VL (24), the maximum value of Iupp er can be expressed as follows:
If delay times of each switch are chosen to be smaller than
VH Tdead
their minimum delay times, ZVS cannot be guaranteed and
2L , 0 < D 0.5
a
RMS current of switches will be increased. The delay times Iupp er,m ax = (25)

DVH Tdead
are usually chosen to be the minimum delay times in order to , 0.5 D 1.
(1 D)2La
minimize conduction time of a body diode of MOSFETs.
Although the switching patterns for boost and buck operations Similarly, the minimum value of Ilower is determined from (22)
are different, seamless mode transition can be achieved by in- and as follows:
troducing an intermediate switching pattern, as shown in Fig. 8. IL f VL Tdead
Ilower,m in = IL a+ (26)
The intermediate switching pattern is inserted between the two 2 La (1 D)
switching patterns for boost and buck operations. The switch-
where IL f is a current ripple of Lf , and IL a+ is the peak value
ing sequence for transfer from forward mode to reverse mode
of iL a in the buck operation.
is Pattern1 Pattern2 Pattern3. The switching sequence for
transfer from reverse mode to forward mode is Pattern3 Pat-
III. EXPERIMENTAL RESULTS
tern2 Pattern1. Figs. 8 and 9 show the switching sequence and
control block diagram for the proposed BDC, respectively. The The interleaving technique can be applied to reduce the size
moment at which the switching pattern is changed is determined of passive components and current stresses. A 5-kW proto-
by comparing the instantaneous average value IL f ,avg of the in- type of the two-phase interleaved version of the proposed con-
ductor current to the preset values Iupp er and Ilower , as shown verter shown in Fig. 10 was built according to the following
1664 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 4, APRIL 2014

Fig. 11. Experimental waveforms of proposed converter in boost operation.

(a) LVS bottom switch. (b) LVS top switch. (c) HVS bottom switch. (d) HVS
top switch.

Fig. 13. Experimental waveforms of mode change. (a) From forward mode to
reverse mode. (b) From reverse mode to forward mode.

Fig. 12. Experimental waveforms of proposed converter in buck operation.

(a) LVS bottom switch. (b) LVS top switch. (c) HVS bottom switch. (d) HVS
top switch.

specification: Po = 5 kW, fs = 30 kHz, VH = 400 V, VL =

72100 V, Lf = 130 H, La = 13 H, Ca = 30 F, C1 =C2 =
470 F.
Both LVS and HVS switches are implemented with
IXFN100N50P (500 V, 90 A, and 49 m) MOSFET, and the
filter and auxiliary inductor are implemented with powder cores
CH610125 and CM330060, respectively, from Changsung. The
nominal duty cycle of 0.64 was used to achieve voltage gain of
5.5 for the both buck and boost operations. The minimum delay
times were calculated using (22), (23), and (24) under full load
condition, the actual delay times td2 , td3 , and td4 were chosen
to be 3000, 3000, and 1200 ns, respectively, considering appro-
priate margin. The upper and lower values of the band for mode
change were calculated using (25) and (26) and chosen to be
Iupp er = 1.5 A and Ilower = 1 A, respectively. Experimental
waveforms of the proposed converter for boost and buck oper-
ations are shown in Figs. 11 and 12, respectively. Fig. 11(a) to
(d) shows voltage and current waveforms of switches S1 to S4
in boost operation. Fig. 12(a) to (d) shows voltage and current Fig. 14. Extended waveforms of the filter inductor current iL f in Fig. 13. (a)
waveforms of switches S1 to S4 in buck operation. It can be seen From forward mode to reverse mode. (b) From reverse mode to forward mode.
KWON et al.: HIGH GAIN SOFT-SWITCHING BIDIRECTIONAL DCDC CONVERTER FOR ECO-FRIENDLY VEHICLES 1665

proposed converter can achieve ZVS turn on of all switches and

ZCS turn off some switches in both boost and buck operations.
An optimized switching sequence has been presented along with
an intermediate switching pattern to carry out seamless mode
change. A 5-kW prototype of the proposed converter has been
built and tested to verify the validity of the proposed operation.
A nominal duty cycle of 0.64 was used to achieve voltage gain
of 5.5. The maximum efficiencies in forward and reverse modes
are 97.9% and 97.7%, respectively. It has also been shown in
the experiment that the mode change is seamless due to the
proposed switching sequence.

REFERENCES
[1] M. Gerber, J. A. Ferreira, N. Seliger, and I. W. Hofsajer, Design and
evaluation of an automotive integrated system module, in Proc IEEE2005
Ind. Appl. Conf., 2005, vol. 2, pp. 11441151.
[2] J. Zhang, R. Y. Kim, and J. S. Lai, High-Power density design of a
soft-switching high-power bidirectional DC-DC converter, in Proc IEEE
Power Electron. Spec. Conf., 2006, vol. 2, pp. 17.
Fig. 15. Measured efficiency according to the variation of LVS voltage. (a) [3] Y. Du, X. Zhou, S. Bai, S. Lukic, and A. Huang, Review of non-isolated
Forward mode. (b) Reverse mode. bi-directional DCDC converters for plug-in hybrid electric vehicle charge
station application at municipal parking decks, in Proc. 25th IEEE Appl.
Power Electron. Conf. Expo., 2010, pp. 11451151.
[4] Prius Battery Specifications. (2013). [Online]. Available:
http://www.toyotapriusbattery.com
[5] C. Pascual and P. T. Krein, Switched capacitor system for automatic
series battery equalization, in Proc IEEE Appl. Power Electron. Conf.,
1997, vol. 2, pp. 848852.
[6] W. Li, X. Lv, Y. Deng, J. Liu, and X. He, A review of non-isolated high
step-up DC/DC converters in renewable energy applications, in Proc.
24th Annu. IEEE Appl. Power Electron. Conf. Expo., Washington, DC,
USA, Feb. 1519, 2009, pp. 364369.
[7] D. Zhang, D. Y. Chen, and F. C. Lee, An experimental comparison of
conducted EMI emissions between a zero-voltage transition circuit and a
hard switching circuit, in Proc. IEEE Power Electron. Spec. Conf., 1996,
pp. 19921997.
[8] P. Das, B. Laan, S. A. Mousavi, and G. Moschopoulos, A nonisolated
bidirectional ZVS-PWM active clamped DCDC converter, IEEE Trans.
Power Electron., vol. 24, no. 2, pp. 553558, Feb. 2009.
[9] Y. Tsuruta, Y. Ito, and A. Kawamura, Snubber-assisted zero-voltage and
zero-current transition bilateral buck and boost chopper for EV drive
application and test evaluation at 25 kW, IEEE Trans. Ind. Electron.,
vol. 56, no. 1, pp. 411, Jan. 2009.
[10] P. Das, S.A. Mousavi, and G. Moschopoulos, Analysis and design of
Fig. 16. Photograph of the proposed converter prototype. a nonisolated bidirectional ZVS-PWM DCDC converter with coupled
inductors, IEEE Trans. Power Electron., vol. 25, no. 10, pp. 26302641,
Oct. 2010.
[11] B. L. Narasimharaju, S. P. Dubey, and S. P. Singh, Design and analysis of
that all switches are turned ON with ZVS in both operations. coupled inductor bidirectional DC-DC convertor for high-voltage diversity
Experimental waveforms of mode change are shown in Fig. 13. applications, IET. Power Electron., vol. 5, no. 7, pp. 9981007, Aug.
2012.
Fig. 14 is the extended waveforms of the filter inductor current [12] R. J. Wai and R. Y. Duan, High-efficiency bidirectional converter for
IL f in Fig. 13. It is seen that there are no transients caused power sources with great voltage diversity, IEEE Trans. Power Electron.,
by change of switching patterns during the mode change. The vol. 22, no. 5, pp. 19861996, Sep. 2007.
[13] L. S. Yang and T. J. Liang, Analysis and implementation of a novel
measured efficiencies under different LVS voltage conditions in bidirectional DCDC converter, IEEE Trans. Ind. Electron., vol. 59,
forward and reverse modes are shown in Fig. 15. The efficiency no. 1, pp. 422434, Jan. 2012.
was measured using Yokogawa WT3000. The maximum effi- [14] F. L. Luo, H. Ye, and M. H. Rashid, Switched capacitor four-quadrant
DC/DC Luo-converter, in Proc IEEE IAS. Ind. Appl. Conf., 1999, vol. 3,
ciencies in forward and reverse modes are 97.9% at 2 kW(VL = pp. 16531660.
100 V) and 97.7% at 3 kW(VL = 100 V), respectively. Fig. 16 [15] F. H. Khan, L. M. Tolbert, and W. E. Webb, Hybrid electric vehicle power
shows the photograph of the proposed converter. management solutions based on isolated and nonisolated configurations
of multilevel modular capacitor-clamped converter, IEEE Trans. Ind.
Electron., vol. 56, no. 8, pp. 30793095, Aug. 2009.
IV. CONCLUSION [16] W. Qian, D. Cao, J. G. Cintron-Rivera, M. Gebben, D. Wey, and F. Z. Peng,
A switched-capacitor DCDC converter with high voltage gain and re-
In this paper, a nonisolated soft switching BDC has been pro- duced component rating and count, IEEE Trans. Ind. Appl., vol. 48, no. 4,
posed for high-voltage gain and high-power applications. The pp. 13971406, Jul./Aug. 2012.
1666 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 4, APRIL 2014

[17] J. Cao and A. Emadi, A new battery/ultracapacitor hybrid energy storage Secheol Oh was born in Korea, in 1981. He received
system for electric, hybrid, and plug-in hybrid electric vehicles, IEEE the B.S. and M.S. degrees from the Department of
Trans. Power Electron., vol. 27, no. 1, pp. 122132, Jan. 2012. Control and Instrumentation Engineering from the
[18] S. Park and S. Choi, Soft-switched CCM boost converters with high Seoul National University of Science and Technol-
voltage gain for high-power applications, IEEE Trans. Power Electron., ogy, Seoul, Korea, in 2008 and 2012, respectively.
vol. 25, no. 5, pp. 12111217, May 2010. He is currently an Engineer of the Vehicle Compo-
[19] S. Park, Y. Park, S. Choi, W. Choi, and K. Lee, Soft-switched interleaved nent Research and Development Group, LG Electron-
boost converters for high step-up and high-power applications, IEEE ics, Pyeongtaek, Korea. His research interests include
Trans. Power Electron., vol. 26, no. 10, pp. 29062914, Oct. 2011. the dcdc converter and battery charger for electric
[20] I. Kim, J. Kim, E. Nho, and H. Kim, Analysis and design of a soft- vehicles.
switched PWM sepic DC-DC converter, J. Power Electron., vol. 10,
no. 5, pp. 461467, Sep. 2010.
[21] J. Lee, H. Cha, D. Shin, K. Lee, D. Yoo, and J. Yoo, Analysis and design
of coupled inductors for two-phase interleaved DC-DC converters, J.
Power Electron., vol. 13, no. 3, pp. 339348, May 2013.
Sewan Choi (S92M96SM04) received the B.S.
degree in electronic engineering from Inha Univer-
sity, Incheon, Korea, in 1985, and the M.S. and Ph.D.
degrees in electrical engineering from Texas A&M
University, College Station, TX, USA, in 1992 and
1995, respectively.
From 1985 to 1990, he was with Daewoo Heavy
Minho Kwon was born in Korea, in 1985. He re- Industries as a Research Engineer. From 1996 to
ceived the B.S. degrees in the Department of Con- 1997, he was a Principal Research Engineer at Sam-
trol and Instrumentation Engineering in 2012 from sung Electro-Mechanics Company, Korea. In 1997,
the Seoul National University of Science and Tech- he joined the Department of Electrical and Informa-
nology, Seoul, Korea, where he is currently working tion Engineering, Seoul National University of Science and Technology, Seoul,
toward the M.S. degree. Korea, where he is currently a Professor. His research interests include power
His research interests include the bidirectional dc conversion technologies for renewable energy systems and dcdc converters
dc converter for electric vehicles and renewable en- and battery chargers for electric vehicles.
ergy systems. Dr. Choi is an Associate Editor of the IEEE TRANSACTIONS ON POWER
ELECTRONICS and the IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS.