A Two-Step Prediction ADC Architecture For Integrated Low Power Image Sensors
A Two-Step Prediction ADC Architecture For Integrated Low Power Image Sensors
A Two-Step Prediction ADC Architecture For Integrated Low Power Image Sensors
1, JANUARY 2017
AbstractThis paper presents a two-step prediction method efforts to reduce power on each building block, or to modify the
for the design of low-power column-parallel analog-to-digital con- ADC structures or operations to achieve a system level power
verters (ADC) in CMOS image sensors. The proposed prediction saving.
method takes advantage of the spatial likelihood of natural scenes,
which shows strong correlations between neighboring pixels in Low-power ADC designs for CMOS image sensors have
the image. Based on this property, the proposed method predicts been prolific in literature. For instance, one popular way is
the MSBs of the selected pixel using quantization results of the reducing the power supply voltage of the whole image sensor or
neighboring pixels in the previous row, which enables a significant only the digital circuits of the image sensor [14]. If the power
power reduction of the A/D conversions. The simulation results supply voltage cannot be reduced, e.g., a specific fabrication
show that up to 2030% power saving can be achieved for most
natural scenes. A 384 256-pixel prototype chip was fabricated technology is applied or a high dynamic range (DR) is required,
using a 0.35 m CMOS technology with a pixel footprint of the switched power technique can be an alternative option,
15 m 15 m. The fill factor is 49%. 10-bit successive approxi- which powers off the components when they are not in use [5],
mation register (SAR) ADCs are used in the column-parallel ADC [15], [16]. Since digital circuits account for a large proportion
array. of the power dissipation, lowering the clock frequency can
Index TermsCMOS image sensor, column-parallel ADC, also be an efficient way to achieve a lower power consumption
common MSBs, low power, prediction. [16]. Also, reconfiguring the circuit operation may sometimes
decrease the power dissipation, e.g., in [6] and [17], only a
I. I NTRODUCTION
small portion of the total capacitor array is used to decide the
A. Algorithm Background
In images of natural scenes, the spatial frequency is often
limited because a group of pixels in the image can be occupied
by the same object. This means that most of the pixels in the
image could have similar values to their neighboring pixels. For
example, in a satellite image for remote sensing applications,
the differences between neighboring pixels can usually be very Fig. 2. 4-bit DAC voltages of different ADC architectures between two
small. In reality, in such cases, sometimes most of the pixel val- neighboring conversions. (a) Conventional SAR ADC; (b) conventional Single-
Slope ADC.
ues in the whole image have very small differences. Moreover,
the difference of neighboring pixel values could be reduced by
the limitation of the optical systems or the camera resolution. To the edge in order to start the next conversion. The operations
verify this, we studied hundreds of images and calculated the of the SAR ADC and the single-slope ADC are shown in
differences between neighboring pixels in these images using Fig. 2. Unfortunately, with such operations, when the neigh-
MATLAB. The result shows that there is a high percentage boring pixels in the same column have the similar values,
of pixels having similar values to their neighboring pixels. For the charging/discharging energy between the two consecutive
instance, the result of a Lena image with a resolution of 512 comparisons are wasted. This unnecessary discharge energy can
512 is shown in Fig. 1. Although the image contains a mixture be avoided if the consecutive conversion results share several
of detail, flat regions, shading and texture [24], Fig. 1 shows MSB values so the comparison energy of these MSBs can be
that most of the pixel value differences in the column-wised saved. Based on these considerations, we propose the two-step
direction distribute in the range between 50 to + 50 out prediction ADC algorithm for image sensors.
of the full range [ 255, + 255]. Therefore, the digital pixel
value differences in the image are mainly attributed to the LSBs.
B. Algorithm Description
However, conventional ADC structures in image sensors do
not consider the aforementioned image property. For example, The proposed two-step prediction ADC is based on predict-
in a conventional SAR ADC operation, the capacitor array of ing some MSB values of each conversion to reduce the number
the DAC needs to be reset (discharged) between every two of the conversion steps and avoid the unnecessary discharge
conversions. Similarly, in a conventional single-slope ADC between conversions. As illustrated in Fig. 3, the proposed two-
operation, after one conversion, the DAC also needs to be step conversion algorithm processes the pixel array by rows.
reset (charged or discharged depends on the specific design) to In Step 1, the pixel values of each row serve as references for
52 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 64, NO. 1, JANUARY 2017
the limited prediction number. In an imaging system, even taken conversion of Row 2, assume the prediction circuit picks up
from the same color, the pixels can also have different values the first three MSB values from Row 1 as the MSB prediction
because of non-uniformity and read noise, then the prediction values (in this case 110xx), the judgment is performed by
will fail. To avoid this, the prediction number is limited in the the following operations: 1) keep S4 S2 to 110; 2) switch
new design, so the failure rate due to the small pixel differences S1 S0 to GND to generate a lower boundary voltage at VDAC
can be removed. while obtain the first result of VCOMP ; 3) switch S2 to VREF to
generate a higher boundary voltage at VDAC while obtain the
second result of VCOMP ; 4) if VCOMP toggles, i.e., the first
C. Algorithm Implementation
result of VCOMP is 1 and the second result of VCOMP is
The proposed prediction ADC algorithm contains three key 0, then it means VIN is in the window between the higher
procedures: prediction, judgment, and final conversion. At the boundary and the lower boundary. And thus, the prediction is
beginning, the prediction circuit generates common MSBs from correct. So a partial conversion starts from the fourth bit, which
the data memories that store the digital results of the pixels means only S1 and S0 need to be adjusted to complete the A/D
in the previous row. Then the judgment circuit creates two conversion. After that, in the conversion of Row 3, the same
analog boundary voltages based on the predicted MSB values prediction and judgment processes are performed, however as
and check whether the current pixels analog value is between shown in Fig. 5(a), the judgment results are 0 and 0, which
the two boundary voltages based on (1). Finally, if the pre- means the prediction is failed. Thus, a complete conversion has
dicted MSB values are correct, the ADC only performs the to be performed. Although there are two extra switchings and
LSB conversions. Otherwise, the ADC performs a full A/D comparisons due to the failed prediction, the total energy can be
conversion. This algorithm can be implemented with various greatly saved in the whole image because of the limited spatial
ADC structures, e.g., single-slope ADCs, SAR ADCs, or cyclic frequency of the natural scene. Moreover, if a higher resolution
ADCs. Also, different data structures can be applied in the data ADC is required, power could be further reduced due to a higher
memory. number of successfully predicted MSBs.
There are two options for implementing the proposed al- Besides SAR ADCs, single-slope ADCs can also be used in
gorithm: the local DAC implementation and the global DAC the proposed two-step prediction architecture. In the example
implementation. When choosing the implementation options, illustrated in Fig. 5(b), a single-slope ADC is combined with
the circuit area, speed, and power consumptions are the main a global DAC. Similarly to the previous example, in Row 1
considerations. For the prediction circuit, since the input pixel a complete single-slope A/D conversion is performed. The
value varies column by column, the circuit should be imple- single-slope A/D conversion is divided into two parts: a coarse
mented locally. Another reason for doing this is that the predic- conversion and a fine conversion [23]. Both the coarse conver-
tion circuit is fully digital and does not occupy too much silicon sion and fine conversion use a linear search protocol. In the
area. The judgment circuit can be implemented either locally or coarse conversion, a global multi-reference generator generates
globally depending on the specific design requirements. In a a comparison reference VREF,C which contains 16 voltages
local implementation, the DAC is combined with the column coming sequentially. These voltages compare to the input signal
ADC, while in a global implementation, multiple reference one by one to obtain a coarse conversion result, which rep-
voltages are applied and broadcast to all column slices globally. resents the MSB values. After the coarse conversion, the fine
This can be achieved by using a voltage scaling DAC. conversion is performed by comparing a ramp signal VRAMP to
Examples of the implementation options with different ADC the input voltage. VRAMP is generated by a global ramp signal
types are shown in Fig. 5. In these examples, a 5-bit A/D generator. In our design, VRAMP is shifted to the input signal
conversion is applied using the same input signal with the same based on the result of the coarse conversion. In Fig. 5(b), VF F
scenario: 1) In Row 1, since there are no previous rows, the is a voltage following VREF . If the number of the MSBs of the
prediction is not available. So the conversion starts from the coarse conversion is n, then VF F is (2n 1)/(2n ) VREF . In
second step, which is a complete A/D conversion. 2) In Row 2, this example, VF F equals to 15/16 VREF . VP R is the analog
the first step prediction is successful. So in the second step, only value of the predicted MSBs for judgment. VP R is selected
a partial A/D conversion is performed. 3) In Row 3, the first from the global multiple references by the predicted MSBs.
step prediction is failed and thus a complete A/D conversion is The global ramp generator and multi-reference generator can
performed. be turned off after every A/D conversion in order to save power.
In the first example of Fig. 5(a), a local DAC is applied In addition to single-slope ADC, the global DAC solution
in the judgment circuit in the first step and an SAR ADC is can also be easily adopted into other ADC architectures without
used in the second step. In the A/D conversion of the pixels in much modification. For instance, Fig. 5(c) describes the DAC
Row 1, a full SAR A/D conversion is performed. A simplified voltages for a global DAC solution with local SAR ADC
schematic of the SAR ADC is shown in Fig. 6. At the beginning in column slices. The prediction result generation, judgment
of the conversion, the switch SR is turned ON and the switches process, and the coarse quantization are the same as that in the
S4 S0 are connected to GND to reset the capacitor array. example of the single-slope ADC, and the DAC voltage is gen-
Then SR is turned OFF, and S4 S0 are sequentially switched erated locally by the switched-capacitor array. Since the input
to VREF . During this process, if VCOMP is 1 then the switch voltage range of an SAR ADC is determined by the reference
remains at VREF , otherwise, it turns back to GND. The final voltage, the capacitor array can be connected to various refer-
positions of S4 S0 are the conversion results. Next, in the ence voltages depends on the coarse MSBs to perform a further
54 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 64, NO. 1, JANUARY 2017
Fig. 5. Three examples of the proposed algorithm implementations with different architectures. (a) Step 1: local DAC for coarse conversion and prediction
judgment, Step 2: local SAR ADC for fine conversion. (b) Step 1: global DAC for coarse conversion and prediction judgment, Step 2: local single-slope ADC for
fine conversion. (c) Step 1: global DAC for coarse conversion and prediction judgment, Step 2: local SAR ADC for fine conversion.
D. Algorithm Simulation
The power consumption of the proposed two-step prediction
ADC has been simulated using MATLAB based on our energy
model. According to the aforementioned discussion, we focus
on the local SAR ADC topology since it has a lower power
consumption. The power cost in this topology can be divided
into three parts: the switched-capacitor array, the comparator,
and the digital circuits. Since the comparator and the digital
circuits consume the same energy for different bits of the
ADC code, in the simulation we only study the power of the
switched-capacitor array.
Power analysis of the switched-capacitor array is based on Fig. 8. Block diagram of the prototype CMOS image sensor with the proposed
the charging and discharging energy during A/D conversions. two-step prediction ADC architecture.
Referring to Fig. 6, at the beginning of the conversion, the
capacitors are reset to GND. The conversion starts when SR to bottom, the five curves represent the switching energy with
is turned OFF. In the first bit conversion, the bottom plate of no prediction, 1-bit, 2-bit, 3-bit, and 4-bit MSB predictions.
capacitor C4 is switched to VREF , and VDAC is charged to 1/2 The simulation results show that the switching energy can be
VREF . This switching energy is 8CVREF 2 . At this moment, reduced with a higher number of the predicted MSBs.
if VIN > VDAC , then C4 is kept to VREF and C3 is switched
to VREF , so VDAC is charged to 3/4 VREF . In this case, the
switching energy of this step is 2CVREF 2 . Else if VIN < VDAC , III. I MAGE S ENSOR D ESIGN
C4 is switched back to GND and C3 is switched to VREF , so
A. Image Sensor Architecture
VDAC becomes 1/4VREF . In this case, the switching energy
of this step is 10CVREF 2 . Then the next step is to compare A prototype CMOS image sensor implementing the proposed
VDAC and VIN to decide the following bits. With this analysis, prediction algorithm using local SAR ADCs was designed
the switching energy of all the ADC output codes is simulated using a 0.35 m CMOS technology. Fig. 8 shows the image
with various numbers of the predicted MSBs. The simulation sensor block diagram. The circuits contain 6 main building
result of this 5-bit conversion is shown in Fig. 7. From top blocks. They are a 3 T-APS (3-transistor active pixel sensor)
56 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 64, NO. 1, JANUARY 2017
TABLE I
I MAGE S ENSOR P ERFORMANCE S UMMARY AND C OMPARISON W ITH S TATE - OF - THE -A RT W ORKS
C. Power Consumption
As shown in Fig. 12, the diagram of the consumed energy of
the prototype design is presented based on the measured result.
The red curve in the middle illustrates the energy consumed
by the typical A/D conversions, it increases with the ADC output
code because a larger ADC output code needs more registers
flipped and has a higher DAC voltage to be reset after the con-
version. The curves below the red one are the energy consumed
by the A/D conversions with successful MSB predictions. Simi-
larly, a larger ADC output code needs more energy for registers
flipping and DACs resetting, thus the saved energy would
increase with the ADC output values. Since the prediction judg-
ment also consumes energy, so the conversion with 1-bit right
prediction does not save much energy with small ADC codes.
The curves above the red one are the energy consumed by the
A/D conversions with failed prediction. In these cases, after
the prediction judgment, a whole conventional A/D conversion
would be carried out, so the energy differences come from
the prediction judgment operation, and are about 120160 pJ
more than the red one according to the predicted MSB quantity
and ADC code. From the diagram, it can be seen that if the
prediction succeeds, the ADC would need less power than the
conventional ADC. While, if the prediction fails, the ADC
would consume more energy than the conventional one. In the
view of the whole image, due to the limited spatial frequency of
nature scenes, the successful predictions are usually much more
than the failed ones, so the proposed design can save energy.
As discussed in Section II, the total saved power consumption
using the two-step prediction ADC depends on the specific
image, especially the spatial gradient distribution. Fig. 13(a) Fig. 13. (a) Sample image from the prototype chip. (b) Failed prediction pixels.
shows a sample image taken by the prototype chip. Since the (c) Prediction distribution.
YU et al.: A TWO-STEP PREDICTION ADC ARCHITECTURE FOR INTEGRATED LOW POWER IMAGE SENSORS 59
TABLE II V. C ONCLUSION
P REDICTION S TATISTIC OF THE S AMPLE I MAGE
This paper proposed a two-step prediction ADC architecture
for low-power column-parallel ADCs in the image sensor. By
finding the common MSBs of the neighboring pixels in the pre-
vious row, the MSB values of the current pixel can be predicted,
so the corresponding switching energy is saved. The prediction
judgment would introduce two more comparisons (3 clock
cycles in the proposed design) to decide if the prediction is
correct. But in the view of the whole system, the frame rate
is limited by the digital signal readout stage, which takes a
much longer time (384 clock cycles for 384 columns) after the
A/D conversion is completed. Since the A/D conversion and
the signal readout work in pipeline style, the proposed algo-
rithm will not delay to conversion. This method can be easily
integrated with most of the column-parallel ADCs by adding
simple extra digital circuits. But the prediction generation cir-
cuit will share the routing resources of the column slices. Thus
with limited column size, the prediction algorithm may not be
applied or only a few MSB bits can be utilized. Unlike a circuit
optimization, the improved power efficiency of the proposed
method is not consistent. The power saving depends on the
specific ADC architectures and image spatial frequencies. So
it is possible that in extreme cases where the spatial frequency
of the image is unusually high, applying the algorithm cannot
Fig. 14. Average energy consumption of one pixel of the sample image.
save energy but even waste more. A prototype CMOS image
sensor was designed and fabricated with column-parallel SAR
ADCs applying the proposed method. Both simulation results
FPN of the pixels is removed by the DDS circuit, some vertical
and measurement results show that the ADC power can be
lines in the image are mainly caused by the different types
significantly reduced using the proposed method.
of the polarizers and the FPN of the other readout circuits,
which will be discussed in another paper. Fig. 13(b) shows the
failed prediction pixels, they are mainly located in the object R EFERENCES
edges (with a high spatial gradient), in this image, the failure [1] T. Toyama, K. Mishina, H. Tsuchiya, T. Ichikawa, H. Iwaki, Y. Gendai,
prediction rate is 20.14%. To avoid the wrong prediction caused H. Murakami, K. Takamiya, H. Shiroshita, Y. Muramatsu, and
by small pixel difference and noise, the maximum bit number T. Furusawa, A 17.7 Mpixel 120 fps CMOS image sensor with
34.8 Gb/s readout, in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC),
of the prediction is set as 5. Fig. 13(c) shows the prediction Feb. 2011, pp. 420422.
distribution, a lighter color means more bit predictions are [2] M. Snoeij, A. Theuwissen, K. Makinwa, and J. Huijsing, A CMOS
successful. Table II gives its statistic summary. The result shows imager with column-level ADC using dynamic column fixed-pattern noise
reduction, IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 30073015,
that the number of the switching steps of MSBs is significantly Dec. 2006.
reduced, so the switching energy is also reduced proportionally. [3] M. Snoeij, A. Theuwissen, K. Makinwa, and J. Huijsing, Multiple-ramp
Fig. 14 shows the average energy statistic result of the column-parallel ADC architectures for CMOS image sensors, IEEE J.
Solid-State Circuits, vol. 42, no. 12, pp. 29682977, Dec. 2007.
sample image. The average energy of one pixel is 584.27 pJ [4] W. Lim, J. Hwang, D. Kim, S. Jeon, S. Son, and M. Song, A low noise
without the proposed prediction algorithm, and is 463.13 pJ CMOS image sensor with a 14-bit two-step single-slope ADC and a
with the proposed algorithm. The power with the proposed column self-calibration technique, in Proc. IEEE Int. Conf. Electron.,
Circuits, Syst. (ICECS), Dec. 2014, pp. 4851.
algorithm is saved by 26.13%. In other experiments of natural [5] M.-S. Shin, J.-B. Kim, M.-K. Kim, Y.-R. Jo, and O.-K. Kwon, A
scenes, the power saving is between 2030% by using the 1.92-megapixel CMOS image sensor with column-parallel low-power and
proposed method. With the algorithm, the energy is consumed area-efficient SA-ADCs, IEEE Trans. Electron Devices, vol. 59, no. 6,
pp. 16931700, Jun. 2012.
by seven operations/blocks: DAC switching, DAC resetting, [6] D. Chen, F. Tang, M.-K. Law, X. Zhong, and A. Bermak, A 64 fJ/step
the analog part of the prediction judgment, the digital part of 9-bit SAR ADC array with forward error correction and mixed-signal
the prediction judgment, SAR control logic, comparator and CDS for CMOS image sensors, IEEE Trans. Circuits Syst. I: Regular
Papers, vol. 61, no. 11, pp. 30853093, Nov. 2014.
memory. Without the algorithm, the energy is consumed by five [7] R. Xu, W. C. Ng, J. Yuan, S. Yin, and S. Wei, A 1/2.5 inch VGA 400 fps
operations/blocks: DAC switching, DAC resetting, SAR control CMOS image sensor with high sensitivity for machine vision, IEEE J.
logic, comparator and memory. It can be seen that except for Solid-State Circuits, vol. 49, no. 10, pp. 23422351, Oct. 2014.
[8] M. Dahoumane, J. Bouvier, D. Dzahini, L. G. Martel, E. Lagorio,
memory, every part consumes less power. Moreover, in the J. Y. Hostachy, and Y. Hu, A very low power and low signal 5 bit 50 M
prototype chip, all the circuits are powered by a 3.3 V supply, so samples/s double sampling pipelined adc for monolithic active pixel sen-
the digital components consumed a large portion of energy. If sors in high energy physics and biomedical imaging applications, in
Proc. IEEE Nucl. Sci. Symp. Conf. Rec., Oct. 2008, pp. 20912097.
the imager is fabricated by an advanced technology, the power [9] S. Lim, J. Cheon, Y. Chae, W. Jung, D.-H. Lee, M. Kwon, K. Yoo,
can be further reduced. S. Ham, and G. Han, A 240-frames/s 2.1-Mpixel CMOS image sensor
60 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 64, NO. 1, JANUARY 2017
with column-shared cyclic ADCs, IEEE J. Solid-State Circuits, vol. 46, Hang Yu (S12) received the B.S. degree in micro-
no. 9, pp. 20732083, Sep. 2011. electronics from Peking University, China, in 2007,
[10] T. Watabe, K. Kitamura, T. Hayashida, T. Kosugi, H. Ohtake, and the M.E. degree in computer science from In-
H. Shimamoto, and S. Kawahito, A digitally-calibrated 2-stage cyclic stitute of Computing Technology, Chinese Academy
ADC for a 33-Mpixel 120-fps super high-vision CMOS image sensor, in of Sciences in 2010. Currently he is working to-
Proc. IEEE SENSORS, Nov. 2014, pp. 6669. wards the Ph.D. degree in electrical and electronic
[11] J. Yeo, Y. Choi, J. Roh, G. Han, Y. Chae, and S. Ham, A current regulator engineering at Nanyang Technological University,
for inverter-based massively column-parallel ADCs, IEEE Trans. Singapore. His research interests are in smart vision
Circuits Syst. II, Express Briefs, vol. 61, no. 4, pp. 224228, Apr. 2014. sensors, time-delay-integration image sensors, and
[12] Y. Oike and A. El Gamal, CMOS image sensor with per-column motion detection sensors.
ADC and programmable compressed sensing, IEEE J. Solid-State
Circuits, vol. 48, no. 1, pp. 318328, Jan. 2013.
[13] M. Yue, D. Wu, and Z. Wang, Data compression for image sensor arrays
using a 15-bit two-step sigma-delta ADC, IEEE Sensors J., vol. 14,
no. 9, pp. 29892998, Sep. 2014.
[14] R. Ozgun, J. Lin, F. Tejada, P. Pouliquen, and A. Andreou, A low-power
8-bit SAR ADC for a QCIF image sensor, in Proc. IEEE Int. Symp.
Circuits Syst. (ISCAS), May 2011, pp. 841844.
[15] I. Ahmed and D. Johns, A high bandwidth power scalable sub-sampling
10-bit pipelined ADC with embedded sample and hold, IEEE J. Solid- Wei Tang (S06M12) received the B.S. degree in
State Circuits, vol. 43, no. 7, pp. 16381647, Jul. 2008. microelectronics from Peking University, China, in
[16] L. Zhang, F. Morel, C. Hu-Guo, and Y. Hu, A self-triggered column-level 2006, and the M.S. and Ph.D. degrees in electrical
ADC for CMOS pixel sensors in high energy physics, IEEE Trans. Nucl. engineering from Yale University, New Haven, CT,
Sci., vol. 61, no. 3, pp. 12691277, Jun. 2014. USA, in 2009 and 2012, respectively. In 2012, he
[17] D. Chen, F. Tang, and A. Bermak, A low-power pilot-DAC based column joined the Klipsch School of Electrical and Com-
parallel 8b SAR ADC with forward error correction for CMOS image puter Engineering at New Mexico State University,
sensors, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 60, no. 10, Las Cruces, NM, USA, as an Assistant Professor. His
pp. 25722583, Oct. 2013. research interests are analog/mixed-signal and low-
[18] K. Kitamura, T. Watabe, T. Sawamoto, T. Kosugi, T. Akahori, T. Iida, power circuit design, sigma delta systems, wireless
K. Isobe, T. Watanabe, H. Shimamoto, H. Ohtake, S. Aoyama, communication circuit design, and testing for bio-
S. Kawahito, and N. Egami, A 33-megapixel 120-frames-per-second medical applications.
2.5-Watt CMOS image sensor with column-parallel two-stage cyclic
analog-to-digital converters, IEEE Trans. Electron Devices, vol. 59,
no. 12, pp. 34263433, Dec. 2012.
[19] Y. Hwang, S. Lee, and M. Song, Design of a CMOS image sensor with a
10-bit two-step single-slope A/D converter and a hybrid correlated double
sampling, in Proc. Conf. Ph.D. Res. Microelectron. Electron. (PRIME),
Jun. 2014, pp. 14.
[20] N. Katic, M. Hosseini Kamal, M. Kilic, A. Schmid, P. Vandergheynst, and
Y. Leblebici, Column-separated compressive sampling scheme for low
power CMOS image sensors, in Proc. IEEE Int. New Circuits Syst. Conf. Menghan Guo received the B.S. degree in electronic
(NEWCAS), Jun. 2013, pp. 14. science and technology from Shandong Normal Uni-
[21] Y.-R. Jo, S.-K. Hong, and O.-K. Kwon, A low-noise and area-efficient versity, Jinan, China, in 2010 and the M.E. degree
PWM- ADC using a single-slope quantizer for CMOS image in circuits and system from the Southeast Univer-
sensors, IEEE Trans. Electron Devices, vol. 63, no. 1, pp. 168173, sity, Nanjing, China, in 2013. He joined Nanyang
Jan. 2016. Technological University, Singapore, as a Research
[22] L. Liu, H. Yu, and S. Chen, Low-power column-parallel ADC for CMOS Associate in 2013. His current research interests
image sensor by leveraging spatial likelihood in natural scene, in Proc. include smart vision sensors and low-power ADC
IEEE SENSORS, Nov. 2014, pp. 11961199. design.
[23] J. Lee, S. Lim, and G. Han, A 10b column-wise two-step single-slope
ADC for high-speed CMOS image sensor, in Proc. IEEE Int. Image
Sensor Workshop, 2007, pp. 196199.
[24] N. Xie and A. J. P. Theuwissen, Low-power high-accuracy micro-digital
sun sensor by means of a CMOS image sensor, J. Electron. Imag.,
vol. 22, no. 3, p. 033030, 2013.
[25] X. Liu, Y. Zhao, L. Liu, X. Jin, C. Wang, and Y. Zhao, The analyze
and design of low FPN double delta sampling circuit for CMOS image
sensor, in Proc. IEEE Int. Conf. Electron Devices Solid-State Circuits
(EDSSC), Jun. 2013, pp. 12. Shoushun Chen (M05SM13) received his B.S.
[26] Y. Zhu, C. H. Chan, U. F. Chio, S. W. Sin, S. P. U, R. P. Martins, and degree from Peking University, China, in 2000, the
F. Maloberti, A 10-Bit 100-MS/s reference-free SAR ADC in 90 nm M.E. degree from Chinese Academy of Sciences
CMOS, IEEE J. Solid-State Circuits, vol. 45, no. 6, pp. 11111121, in 2003, and the Ph.D. degree from Hong Kong
Jun. 2010. University of Science and Technology in 2007.
[27] H. Yu, V. Varghese, X. Qian, M. Guo, S. Chen, and K. S. Low, An He held a Postdoctoral Research Fellowship in
8-stage time delay integration CMOS image sensor with on-chip polariza- the Department of Electronic and Computer En-
tion pixels, in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2015, gineering, Hong Kong University of Science and
pp. 10981101. Technology, for one year after graduation. From
[28] Q. Gao and O. Yadid-Pecht, A low-power block-based CMOS image February 2008 to May 2009 he was a Postdoctoral
sensor with dual VDD, IEEE Sensors J., vol. 12, no. 4, pp. 747755, Research Associate in the Department of Electrical
Apr. 2012. Engineering, Yale University, New Haven, CT, USA. In July 2009, he joined
[29] J. B. Kim, S. K. Hong, and O. K. Kwon, A low-power CMOS image Nanyang Technological University, Singapore, as an Assistant Professor.
sensor with area-efficient 14-bit two-step SA ADCs using pseudomul- He serves as a technical committee member of Sensory Systems, IEEE
tiple sampling method, IEEE Trans. Circuits Syst. II, Express Briefs, Circuits and Systems Society (CASS); Associate Editor of IEEE Sensors
vol. 62, no. 5, pp. 451455, May 2015. Journal; Program Director (Smart Sensors) of VIRTUS, IC Design Centre
[30] J. Lee et al., High frame-rate VGA CMOS image sensor using non- of Excellence, NTU. His research interests include Smart image sensor and
memory capacitor two-step single-slope ADCs, IEEE Trans. Circuits imaging system, remote sensing imaging system, satellite engineering, mixed-
Syst. I, Reg. Papers, vol. 62, no. 9, pp. 21472155, Sep. 2015. signal integrated circuits.