A Resolution-Reconfigurable 5-To-10-Bit 0.4-To-1 V
A Resolution-Reconfigurable 5-To-10-Bit 0.4-To-1 V
A Resolution-Reconfigurable 5-To-10-Bit 0.4-To-1 V
Abstract—A power-scalable SAR ADC for sensor applications The analog-to-digital converter (ADC) is an indispensable
is presented. The ADC features a reconfigurable 5-to-10-bit DAC part of every sensor node, responsible for interfacing the phys-
whose power scales exponentially with resolution. At low resolu- ical world to the digital signal processing unit. In particular, for
tions where noise and linearity requirements are reduced, supply
voltage scaling is leveraged to further reduce the energy-per-con- energy-constrained systems powered off small batteries or en-
version. The ADC operates up to 2 MS/s at 1 V and 5 kS/s at 0.4 ergy harvesting, adapting the ADC performance to the signal of
V, and its power scales linearly with sample rate down to leakage interest to avoid consuming power on unnecessary bandwidth
levels of 53 nW at 1 V and 4 nW at 0.4 V. Leakage power-gating or accuracy can extend the device lifetime. Therefore, this paper
during a SLEEP mode in between conversions reduces total power presents a single reconfigurable ADC whose power scales with
by up to 14% at sample rates below 1 kS/s. Prototyped in a low-
power 65 nm CMOS process, the ADC in 10-bit mode achieves an
resolution and sample rate to maximize energy-efficiency for a
INL and DNL of 0.57 LSB and 0.58 LSB respectively at 0.6 V, and broad range of applications [4].
the Nyquist SNDR and SFDR are 55 dB and 69 dB respectively at The target resolution of the ADC is chosen to cover 5 to 10
0.55 V and 20 kS/s. The ADC achieves an optimal FOM of 22.4 bits of resolution in 1-bit increments which encompasses low
fJ/conversion-step at 0.55 V in 10-bit mode. The combined tech- resolution applications like neural spike sorting (up to 8 bits)
niques of DAC resolution and voltage scaling maximize efficiency
[5], as well as moderate resolution applications like ambulatory
at low resolutions, resulting in an FOM that increases by only 7x
over the 5-bit scaling range, improving upon a 32x degradation ECG monitoring (8 to 10 bits) [6]. The target sampling rate is
that would otherwise arise from truncation of bits from an ADC scalable from a maximum of 1 MS/s down to 10’s of samples
of fixed resolution and voltage. per second to accomodate high bandwidth modes and multi-
Index Terms—ADC, analog-to-digital converter, leakage reduc- channel applications where many channels are multiplexed into
tion, power-gating, power scaling, reconfigurable, resolution, scal- a single ADC, or low-power modes where the sensor node is
able, successive approximation, voltage scaling. highly duty cycled. For this performance range, the successive
approximation register (SAR) ADC is a good candidate [7].
Recent SAR ADCs have achieved exceptional energy-effi-
I. INTRODUCTION ciency but most lack the ability to reconfigure its resolution
Fig. 2. Conventional array segmented into a 5-bit main-DAC and a 5-bit sub-
DAC.
YIP AND CHANDRAKASAN: A RESOLUTION-RECONFIGURABLE 5-TO-10-BIT 0.4-TO-1 V POWER SCALABLE SAR ADC FOR SENSOR APPLICATIONS 3
Fig. 3. Split-capacitor array comprising the MSB sub-array and the main array, both segmented into a 5-bit main-DAC and a 4-bit sub-DAC.
Fig. 4. (a) Comparison of switching energy versus output code for a 10-bit DAC. (b) Average switching energy versus resolution.
main array. The choice of a 4-bit sub-DAC will be discussed large MSB capacitors, the required DAC energy is much larger
later in Section II.D. than necessary. For example, cycling the first 5 MSBs of a con-
In order to compare the energy-efficiency of the various ventional 10-bit array to achieve 5-bit resolution would require
switching schemes, Fig. 4(a) shows the switching energy of energy, which is 32 more energy required than
(normalized to units of ) versus the output code for a just cycling a small 5-bit array . The alternative is
differential 10-bit array. Assuming that the output codes are to start bit cycling in the middle of the array, and bit cycle to the
uniformly distributed, the split-capacitor array combined with LSB capacitor. However, in this case, the MSB capacitors atten-
a sub-DAC implemented in the proposed ADC consumes an uate the DAC output which increases the resolution requirement
average of , which is a 20 reduction from the of the comparator. Therefore, in the proposed ADC, two modi-
conventional array (1363 ). While the split-capacitor fications are made to the array shown in Fig. 3 to achieve resolu-
array with sub-DAC approach is very energy-efficient at 10 tion reconfigurability while avoiding the above issues. First, the
bits, Fig. 4(b) shows the average switching energy versus capacitors of the MSB sub-array and the main-array are inter-
resolution for each of the switching schemes, demonstrating leaved. Secondly, switches are inserted in between each pair of
that it remains quite energy-efficient down to around 5 bits. In MSB capacitors to decouple capacitors as resolution is scaled.
the comparison of Fig. 4(b), for arrays that use a sub-DAC, By interleaving the MSB sub-array and main array, it is pos-
the resolution of the sub-DAC is chosen to be equal to or one sible to decouple the same number of capacitors from both ar-
greater than the main-DAC resolution to minimize switching rays, maintaining an identical structure between the two arrays
energy. as resolution is scaled. In this prototype, the switches are con-
trolled by the thermometer coded bits [4:0], and are driven off
C. Resolution Reconfigurability a fixed 1.2 V supply with negligible current draw. The resulting
In addition to optimizing the energy-efficiency of the capac- capacitor array reconfigured in the 10-bit, 8-bit, and 5-bit modes
itor array, further energy savings can be achieved by scaling its are shown in Figs. 5(a)-(c) respectively.
resolution. With a fixed-resolution DAC, resolution scaling can
traditionally be done in two ways. First, it is possible to bit cycle D. Resolution Scaling Trade-Offs
starting at the MSB capacitor, and stop at the desired resolution As resolution is scaled, in order to minimize area and
[13]. However, this approach is avoided because by cycling the switching energy, the optimal distribution of bits between the
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YIP AND CHANDRAKASAN: A RESOLUTION-RECONFIGURABLE 5-TO-10-BIT 0.4-TO-1 V POWER SCALABLE SAR ADC FOR SENSOR APPLICATIONS 5
TABLE I
ENERGY SAVINGS ACROSS RESOLUTION OF THE PROPOSED ARRAY COMPARED TO THE CONVENTIONAL ARRAY
A. Energy-Per-Conversion and Minimum Energy Point where is the effective capacitance being switched,
This section discusses the energy-per-conversion of the con- and is a function of the resolution. Finally, the leakage energy-
stituent blocks of the ADC. It can be shown that the average per-conversion is given by
switching energy of the DAC is
(4)
(1)
where is the leakage current, and is the minimum
conversion time at a given . As is scaled into the
where is the resolution and is dependent on the switching sub-threshold, the speed of CMOS devices decreases exponen-
scheme, and is equal to 1 for the conventional array [17] and tially, thereby increasing exponentially. The net result is that
0.049 in the proposed ADC. In [20], the energy of a dynamic actually increases as the supply voltage is reduced. The
regenerative comparator is derived. When applied to an -bit energy-per-conversion versus supply voltage for each compo-
matching-limited SAR ADC that requires comparisons per nent of the ADC is illustrated in Fig. 8. The plotted data is based
conversion, the comparator energy-per-conversion can be de- on measurements of dynamic power at 1 V and leakage mea-
rived as surements over all voltages, and extrapolated based on the en-
ergy models above. As voltage is scaled down from 1 V, the
(2) total energy is reduced because the dynamic energy of
where is the load capacitance, and is the transistor the active blocks dominate. However, the opposing trends of
overdrive. For the digital circuits and clock network, the energy- dynamic energy reduction and increased leakage energy at low
per-conversion is given by voltages lead to a minimum energy point (MEP) for the ADC.
For low-bandwidth applications that are not throughput limited,
(3) it is beneficial to operate at the MEP.
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C. Linearity Requirements
In addition to noise, the degraded “on” resistance of analog
switches at low voltages can introduce distortion and limit the
Fig. 10. (a) Schematic of the DAC during the sampling phase, bottom-plate
bandwidth. To address this, a bootstrap circuit is used to increase sampling switch, and bootstrap circuit. (b) Simulated THD versus input fre-
the gate-source voltage of the sampling switches. Fig. 10(a) quency.
shows the schematic of the differential DAC during the sam-
pling phase and the bootstrap circuit [10] applied to the NMOS
device of the complementary bottom-plate sampling switches. the THD requirement at various resolution modes. For example,
The same bootstrap circuit is applied to the NMOS top-plate in order to achieve 8-bit linearity, the required THD is below
sampling switches. Node acts as the supply of the output dB, where an extra 6 dB is
inverter, and charge is stored across capacitor so that added for margin. To illustrate how linearity requirements vary
swings to when is driven high. The bootstrap can with supply voltage, first consider sampling a 100 kHz signal
be bypassed when operating at the nominal voltage with 10-bit linearity. Fig. 10(b) suggests that should be
of the process in order to avoid reliability concerns. approximately 0.72 V or greater to achieve 10-bit linearity.
Fig. 10(b) shows the simulated total harmonic distortion However, to sample the same 100 kHz signal with only 5-bit
(THD) of the sampling network versus the input frequency for linearity, it is possible to reduce the supply down to 0.5 V.
supply voltages from 0.5 V to 0.8 V. The dotted lines indicate Therefore, as with noise requirements, it is possible to leverage
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YIP AND CHANDRAKASAN: A RESOLUTION-RECONFIGURABLE 5-TO-10-BIT 0.4-TO-1 V POWER SCALABLE SAR ADC FOR SENSOR APPLICATIONS 7
Fig. 11. (a) Schematic of the dynamic comparator. (b) Degradation in the
ENOB due to comparator noise.
TABLE II
SUMMARY TABLE OF THE MEASURED ADC PERFORMANCE
(8)
V. MEASUREMENT RESULTS
A prototype ADC was fabricated in a low-leakage 65 nm dig-
ital CMOS process, and the die micrograph is shown in Fig. 14.
The ADC core occupies an area of 0.212 mm . This section
presents the measured results, and a summary of the perfor-
mance is provided in Table II.
A. Static Linearity
Fig. 15 shows the measured static linearity using the code
Fig. 14. Die micrograph of the ADC prototype.
density test with full-swing, low-frequency sinusoids at 0.6 V
and a sampling rate of 100 kS/s in the 5-bit, 8-bit, and 10-bit
modes. 10 samples were measured and the mean results are pre-
per conversion, where is the capacitance at the virtual sented. In the 10-bit mode, the peak DNL and INL are
ground node. Therefore, in order for leakage power-gating to LSB and LSB respectively. The 32-code
be beneficial, the overhead energy must be less than the leakage sawtooth pattern in the INL arises from parasitic capacitance
energy savings which is summarized by on the top-plate of the sub-DAC, resulting in a systematic mis-
match with the main-DAC. The sawtooth can be corrected by
(7) properly adjusting the capacitor in the DAC array using
post-layout extraction. Alternatively, since this linearity error
This condition sets a minimum on which corresponds is systematic, it can also be calibrated out in the digital domain.
to a maximum sampling rate defined as , the break-even No sawtooth pattern is present in the 5-bit mode because only
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YIP AND CHANDRAKASAN: A RESOLUTION-RECONFIGURABLE 5-TO-10-BIT 0.4-TO-1 V POWER SCALABLE SAR ADC FOR SENSOR APPLICATIONS 9
Fig. 15. Measured DNL and INL at 0.6 V in (a) 5-bit mode, (b) 8-bit mode,
and (c) 10-bit mode.
Fig. 17. Measured effect of voltage scaling (with respect to 0.7 V) and DAC
resolution scaling on the ADC FOM at 200 kS/s. In the case of the fixed reso-
lution DAC, the FOM at each resolution is calculated by truncating bits from
10-bit data.
(9)
Fig. 20. Measured total ADC power at 200 kS/s, and breakdown by block as a percentage of the total power.
VI. CONCLUSION
This paper presents a power-scalable SAR ADC with recon-
figurable resolution from 5 to 10 bits. The voltage-scalable ar-
chitecture features an energy-efficient DAC that combines the
split-capacitor switching scheme with the use of a sub-DAC to
reduce energy and input capacitance. Switches are used to de-
Fig. 19. Measured (a) energy-per-conversion , (b) maximum
couple capacitors as resolution is scaled, leading to exponential
sampling frequency, and (c) figure-of-merit, versus the supply voltage. DAC power savings with resolution. As noise and linearity re-
quirements are reduced at lower resolutions, voltage scaling is
leveraged to further improve the ADC energy-per-conversion.
Fig. 18(b) shows the total ADC power versus the sampling Finally, leakage power-gating is applied to minimize leakage at
frequency at 1 V and 0.6 V without leakage power-gating, and low sample rates.
at 0.6 V with leakage power-gating enabled. At high frequen- The combined techniques of DAC resolution and voltage
cies, the power scales linearly with frequency because active scaling maximize efficiency at low resolutions, resulting in an
power dominates. Leakage becomes significant at sample rates FOM that increases by only 7 over the 5-bit scaling range
below 2 kS/s and limits the energy-efficiency. When leakage from 10 bits to 5 bits, improving upon a 32 degradation that
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YIP AND CHANDRAKASAN: A RESOLUTION-RECONFIGURABLE 5-TO-10-BIT 0.4-TO-1 V POWER SCALABLE SAR ADC FOR SENSOR APPLICATIONS 11
Marcus Yip received the B.A.Sc. degree in en- 2011. Since July 2011, he is the Head of the MIT EECS Department. His
gineering science from the University of Toronto, research interests include micro-power digital and mixed-signal integrated
Toronto, ON, Canada, in 2007, and the M.S. degree circuit design, wireless microsensor system design, portable multimedia
from the Massachusetts Institute of Technology, devices, energy efficient radios and emerging technologies. He is a co-author
Cambridge, MA, USA, in 2009, where he is cur- of Low Power Digital CMOS Design (Kluwer Academic Publishers, 1995),
rently pursuing the doctoral degree. Digital Integrated Circuits (Pearson Prentice-Hall, 2003, 2nd edition), and
He has held internships at Actel Corporation, Sub-threshold Design for Ultra-Low Power Systems (Springer 2006). He is
Snowbush Microelectronics, Texas Instruments, and also a co-editor of Low Power CMOS Design (IEEE Press, 1998), Design of
OnChip Power Corporation. His research interests High-Performance Microprocessor Circuits (IEEE Press, 2000), and Leakage
include low-power sensor front-ends, reconfigurable in Nanometer CMOS Technologies (Springer, 2005).
analog-to-digital converters, and signal processing Dr. Chandrakasan was a co-recipient of several awards including the 1993
circuits for wearable and implantable medical applications. IEEE Communications Society’s Best Tutorial Paper Award, the IEEE Electron
Mr. Yip received the Natural Sciences and Engineering Council of Canada Devices Society’s 1997 Paul Rappaport Award for the Best Paper in an EDS
(NSERC) postgraduate fellowship from 2007 to 2011. publication during 1997, the 1999 DAC Design Contest Award, the 2004 DAC/
ISSCC Student Design Contest Award, the 2007 ISSCC Beatrice Winner Award
for Editorial Excellence and the ISSCC Jack Kilby Award for Outstanding Stu-
dent Paper (2007, 2008, 2009). He received the 2009 Semiconductor Industry
Anantha P. Chandrakasan received the B.S., M.S. Association (SIA) University Researcher Award. He has served as a technical
and Ph.D. degrees in electrical engineering and program co-chair for the 1997 International Symposium on Low Power Elec-
computer sciences from the University of California, tronics and Design (ISLPED), VLSI Design’98, and the 1998 IEEE Workshop
Berkeley, CA, USA, in 1989, 1990, and 1994, on Signal Processing Systems. He was the Signal Processing Sub-committee
respectively. Chair for ISSCC 1999–2001, the Program Vice-Chair for ISSCC 2002, the Pro-
Since September 1994, he has been with the gram Chair for ISSCC 2003, the Technology Directions Sub-committee Chair
Massachusetts Institute of Technology, Cambridge, for ISSCC 2004–2009, and the Conference Chair for ISSCC 2010–2012. He
MA, USA, where he is currently the Joseph F. is the Conference Chair for ISSCC 2013. He was an Associate Editor for the
and Nancy P. Keithley Professor of Electrical IEEE JOURNAL OF SOLID-STATE CIRCUITS from 1998 to 2001. He served on
Engineering. He was the Director of the MIT Mi- SSCS AdCom from 2000 to 2007 and he was the meetings committee chair
crosystems Technology Laboratories from 2006 to from 2004 to 2007.