Laporan Prak - Sisdig Modul 1
Laporan Prak - Sisdig Modul 1
Laporan Prak - Sisdig Modul 1
Figure 2.3
Figure 3.4
In experiment we use voltage 5V. From figure 3.3 we
found:
In CH 1: 1V
In CH 2: 1V
Time : 500 ns
Figure 3.1 In the second experiment there was a slight problem so the
image or the resulting data did not match what was expected.
The problem may be caused by the lack of good work from
The experiment result data is obtained as follows:
the practicum tool.
A. Voltage transfer characteristic and noise margin ic
C. Delay Propagation
On the third experiment conducted experiments to
determine the effect of room temperature and not. But on the
third practicum there is no datashet so no comparison will be
done.
Figure 3.2
Based on the picture above can be analyzed that when the
input signal in the form of a triangle signal is inserted into the
IC then the signal is converted into the opposite signal from
inputnya.Ketika input signal given a low signal, then the
output is converted into high signal and otherwise, when the
input signal given is a high signal then the resulting output is
low signal.
Figure 3.5
= 200
Based on the practicum should be obtained the value of tplh Figure 3.6
and tphl but because the tool is not optimal when the process
so that no found.
IV. CONCLUSION
D. Verificate Function of Gate
On the third practicum is done to know that when inserted 1. Real logic gates have certain limitations of having
into a voltage of 5V then the lamp will flame but if one only propagation time so gate feeding must be limited so
breaks (0) then the lamp will not live (0), but if all is as not to exceed the delay time of the circuit.
connected then the light is on (1). 2. The noise margin is the tolerance for the input on the
gate to be within the logical range HIGH "1" or LOW
Input 1 Input 2 Input 3 Output
"0".
0 0 0 0
3. We can determine the function of a gate by creating a
0 0 1 0
truth table and verifying its function.
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0 REFERENS
1 1 1 1
1. Vahid Frank, Digital Design, Page. 73 76,
Wiley, Australia, 2007
In the above truth table is the same as the AND Gate truth
2. Pandapotan Siagian, Petunjuk Praktikum Sistem
table because life (1) when everything is alive (1) nothing is
Digital, Laboratorium Sistem Digital,
not lit (0). And the next experiment from of this experiment,
Sitoluama, 2015
we dont finish because time has been done, so the experiment
3. Teknikeletronika.com, logic gate,
finish only one in this experiment.
http://teknikelektronika.com/pengertian-gerbang-
In experiment we know gate given to us even the gate we
logika-dasar-simbol/ (accessed on October 9th,
dont know.
2017)
Lampiran
1. Picture of calibration