Tn2906 Nand Flash Controller
Tn2906 Nand Flash Controller
Tn2906 Nand Flash Controller
Overview
Technical Note
Micron NAND Flash Controller via Xilinx Spartan-3 FPGA
Overview
As mobile product capabilities continue to expand, so does the demand for high-density
static memory storage. NAND Flash memory is moving to the forefront, evolving rapidly
to meet this ever-growing demand. Micron offers designers a complete solution that
includes industry-standard NAND features, Micron enhancements, plus software and
support options.
NAND Flash architecture differs from that of traditional memory sources, so accessing a
NAND Flash device from a host presents challenges for systems designers. The most
direct approach for a host interface is using a NAND Flash controller. The NAND Flash
controller can be an internal device, built into the application processor or host, or
designs can incorporate an external, stand-alone chip.
This technical note describes the Micron NAND Flash controller, techniques for inter-
facing the NAND Flash device with a processor (using Xilinx Spartan-3 as an exam-
ple), and use of the Micron glueless interface to interface a processor with NAND Flash
memory.
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Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by
Micron without notice. Products are only warranted by Micron to meet Microns production data sheet specifications. All
information discussed herein is provided on an as is basis, without warranties of any kind.
TN-29-06: NAND Flash Controller on Spartan-3
Overview
Interface Options
In situations where the processor lacks a native NAND Flash controller, it is possible to
design a simple memory-mapped interface providing a hardware interface to the NAND
Flash device. This gives NAND Flash the appearance of an SRAM when interfaced to a
processor, microcontroller, or any other host device.
ECC Requirement
To protect against bit errors, error correction code (ECC) is an essential part of the
NAND Flash interface. The Micron ECC module technical note (TN-29-05) provides a
thorough review of error correction for NAND Flash.
The Micron NAND Flash controller is designed to work in series, with the optional
Micron NAND Flash ECC module placed between the NAND Flash controller and the
NAND Flash device. Throughout this document, the presence of an ECC module is
assumed.
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TN-29-06: NAND Flash Controller on Spartan-3
NAND Flash Controller Design and Implementation
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TN-29-06: NAND Flash Controller on Spartan-3
Micron NAND Flash Controller Features
ADDRESS[11:0] CE#
Registers
CE# ALE#
Standard SRAM Interface
WE# WE#
OE# RE#
Control Logic
CLK WP#
RESET# PRE
errINT
Architectural Description
The Micron NAND Flash controller comprises a control logic module with two data buf-
fers. The control logic module contains two control logics:
Timing control logic
Control signals control logic
The architecture is structured so that the timing control logic uses two 5-bit registers to
toggle the signals to the NAND Flash device. These two 5-bit registers are each mapped
to CE#, CLE, ALE, WE#, and RE#. These registers are set by the main control logic that
controls the timing control logic.
Memory-Mapped Interface
The Micron NAND Flash controller implements a memory-mapped interface. This
interface is implemented with internal registers for the various pieces of data. When the
host writes to the internal register addresses, the VHDL code writes to the specific regis-
ters. Some registers have only some bits used. The unused bits on these registers are not
implemented in hardware. For example, there are only 4 bits implemented for the part
type and ECC register 0xFF7.
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TN-29-06: NAND Flash Controller on Spartan-3
Micron NAND Flash Controller Features
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TN-29-06: NAND Flash Controller on Spartan-3
Micron NAND Flash Controller Features
Register
Address READ/WRITE Name Register Function
0xFF0 Read ID register 0 The registers the host should read following a READ ID operation.
0xFF1 Read ID register 1
0xFF2 Read ID register 2
0xFF3 Read ID register 3
0xFF4 R/W Block address [7:0] Used to address the blocks and pages of the NAND Flash. This is the row
0xFF5 R/W Block address address described in the Micron NAND Flash data sheet. This Micron
[15:8] NAND Flash controller supports all NAND Flash devices. During ERASE
0xFF6 R/W Block address operations, the page address is ignored and the block address is used to
[24:16] erase the specified block.
0xFF7 Read Part type and ECC Bit [0]0 = x8 device
1 = x16 device
Bit [2:1] 00 = 2Gb
01 = 4Gb
10 = 8Gb
Bit [6] 0 = No ECC
1 = ECC module connected
0xFF8 R/W Buffer number Bit [0] 0 = Host controls Buffer 1
1 = Host controls Buffer 2
0xFF9 Read Status register Used for reading the status from the NAND Flash. The format of the
status read is the same as with the NAND Flash, with the exception of bits
2, 3, and 4. These bits are used for ECC information
Status 000 = No errors
001 = First 512-byte section of 2K page erroneous
010 = Second 512-byte section of 2K page erroneous
011 = Third 512-byte section of 2K page erroneous
100 = Fourth 512-byte section or 2K page erroneous
0xFFA Write Command register Bit [0] Determines whether the target buffer is specified in the READ
command bit [1]. If this bit is 0,the host does nothing with
regard to the target and source buffers.
Bit [1] Target buffer; READ operation data is written into this buffer;
this buffer is the data source for WRITE operation data to be
written to the Flash.
Bit [7:4] Holds the command the controller is to execute. Executing a
command clears this register.
0h = PAGE READ
6h =BLOCK ERASE
7h = READ STATUS
8h = PROGRAM PAGE
9h = READ ID
Fh = RESET (NAND Flash)
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TN-29-06: NAND Flash Controller on Spartan-3
READ Operations
READ Operations
PAGE READ Operation
To execute a PAGE READ command, the host writes the block and page address to regis-
ters 0xFF4, 0xFF5, and 0xFF6. The part descriptions for these registers are provided in
Table 3.
After loading the address, the host must write 0x00 to register 0xFFA to execute the READ
command. This causes the control logic to read the page specified by the address in the
registers and to put it in the buffer. The control logic initiates an interrupt and switches
buffer control to the other buffer.
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TN-29-06: NAND Flash Controller on Spartan-3
Micron NAND Flash Controller Design Details
40ns
RE#
Data[7:0]
5ns
60ns
Buffer Management
The Micron NAND Flash controller includes two buffers so the host does not have to
wait for the controller to finish an operation to use a buffer. While the controller uses
one buffer, the host has control of the other buffer.
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TN-29-06: NAND Flash Controller on Spartan-3
Micron NAND Flash Controller Design Details
When the host issues a WRITE command, the buffer that the host controls is taken over
by the controller, and the host then takes control of the other buffer. At this point, the
controller reads from the host-controlled buffer and writes to NAND Flash memory; at
the same time, the user can employ the other buffer.
When the host issues a READ command, the controller reads the data into the buffer the
user is not accessing. At the end of the READ operation, the controller automatically
switches host control to the buffer containing the data read from NAND Flash. This
switch is implemented so that the user can choose to not engage the double buffering
feature. However, if the host contains some valuable data in the other buffer, it is pre-
served; the user can continue to use that buffer by changing buffer control to the desired
buffer. Changing buffer control is carried out by reading and writing to the register at
address 0xFF8.
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TN-29-06: NAND Flash Controller on Spartan-3
Micron NAND Flash Controller Design Details
Input Interface
The Micron NAND Flash controller input interface is managed with three control lines:
CE#, OE#, and WE#. These are all active LOW signals. Descriptions of the command sig-
nals are provided in Table 4.
enableTOGGLE = 0
toggleWAIT toggleDONE
enableTOGGLE = 0
toggle 0 toggle1
Starting state
Repetitive states
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TN-29-06: NAND Flash Controller on Spartan-3
Micron NAND Flash Controller Design Details
The address toggle control logic starts in the toggle WAIT state. When the ENABLE TOG-
GLE signal is issued, it toggles the CNTupto lines. The CNTupto register is set by the
main control logic so that the toggle control logic knows the number of times it must
toggle the signals.
RESET NAND
States
READ ID
States STATUS READ
States
FETCH ERROR
States PROGRAM PAGE
States
READ PAGE
States
Each state sequence has nearly the same functionality, and the following functions in
common:
Sets the outputVEC1 and outputVEC2 registers. The toggle control logic uses these
registers to drive the NAND bus.
Sets the cntUPTO register. This indicates the number of times the toggle control logic
must repeat the set of outputVEC1 and outputVEC2.
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TN-29-06: NAND Flash Controller on Spartan-3
Micron NAND Flash Controller Design Details
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TN-29-06: NAND Flash Controller on Spartan-3
Micron NAND Flash Controller Design Details
STreadpage STreadpageCORREDTaddr
STreadpageADDlatch00
FetchErrorStates
enableTOGO
STreadpageADDlatch3cycles
STreadpageCORRECT
STreadpageCMDfinal30h
STwaitforRB0 STreadpageSWAPbuf
STwaitforRB1
STreadpageREADS STreadpageCORwaitforRB
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TN-29-06: NAND Flash Controller on Spartan-3
Micron NAND Flash Controller Design Details
State Definition
STreadpage Beginning of the page read process.
STreadpageADDlatch00 Waits for the first command 00h, which starts the NAND Flash PAGE READ operation.
STreadpageADDlatch3cycles Waits for the 3 address cycles that indicate the page and block to be read. Since the
Micron NAND controller can read only whole pages, it does not require all 5 address
cycles.
STreadpageCMDfinal30h Accepts the final command of the PAGE READ operation, 30h.
STwaitforRB0 Waits for R/B# to go LOW, indicating that the control logic is loading the page from the
memory array to the cache register.
STwaitforRB1 Checks for R/B# to go HIGH, indicating that the control logic is finished loading the
page from the memory array.
STreadpagesREADS Reads the page data.
STreadpageCORwaitforRB Waits for completion of the comparison between what was read and what ECC
indicates should be present (assuming an ECC module is in place).
STreadpagesSWAPbuf Swaps address buffers so new address can be entered by user.
STreadpageCORRECT Checks for errors during the read (assuming an ECC module is in place).
No error: Exits READ PAGE STATE.
Error: Goes to the FETCH ERROR STATES command.
STreadpageCORRECTaddr Provides the error location (assuming an ECC module is in place) and the correct data
for error correction.
STfetchERRORs
enableTOGO
STfetchERRORseightReads
State Definition
STfetchERRORs Writes a 23h command on the NAND I/O bus.
STfetchERRORseightReads Performs 8 READs to collect error information for the page.
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TN-29-06: NAND Flash Controller on Spartan-3
Micron NAND Flash Controller Design Details
STprotgrampageCHbuf
STprogrampage
STprogrampageADDlatch00
enableTOGO
STprogrampageADDlatch3cycles
STprogrampageWRITES
STprogrampageCMDfinal10h
STwaitforRB0
STwaitforRB1
STprogrampageSWstatusRB
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TN-29-06: NAND Flash Controller on Spartan-3
Micron NAND Flash Controller Design Details
State Definition
STprogrampageCHbuf Programs the page data buffer.
STprogrampage Controller takes control of data buffer to move data to NAND Flash cache register.
StprogrampageADDlatch00 Waits for the 00h command to be issued to start a PROGRAM PAGE operation.
STprogrampageADDlatch3cycles Waits for the 3 address cycles that indicate the page and block to be programmed.
Since the Micron NAND controller can read only whole pages, it does not require all 5
address cycles.
STprogrampageWRITES Takes data in the I/O bus and programs it to the bytes of the cache register.
STprogrampageCMDfinal10h Waits for the 10h command to be issued to initiate main array programming.
STwaitforRB0 Waits for R/B# to go LOW, indicating that main array programming is under way.
STwairforRB1 Waits for R/B# to go HIGH, indicating that programming is complete.
STprogrampageSWstatusRB Checks the status of the last program to see if it was successful.
STeraseblock
STeraseblockADDcycles
enableTOGO
STeraseblockCMDd0
STwaitforRB0
STwaitforRB1
State Definition
STeraseblock First command (60h); starts the two-step BLOCK ERASE operation in the NAND device.
STeraseblockADDcycles Waits for 3 address cycles to determine which block to erase.
STeraseblockCMDd0 Second command (D0h); begins the actual BLOCK ERASE operation.
STwaitforRB0 Waits for R/B# line to go LOW, indicating the BLOCK ERASE operation is under way.
STwaitforRB1 Waits for R/B# to go HIGH, indicating the BLOCK ERASE operation is complete.
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TN-29-06: NAND Flash Controller on Spartan-3
Micron NAND Flash Controller Design Details
STresetNAND
STwaitforRB0
STwaitforRB1
State Definition
STresetNAND Waits for the FFh command to initiate a RESET operation.
STwaitforRB0 Waits for R/B# to go LOW, indicating the RESET operation is under way.
STwairforRB1 Waits for R/B# line to go HIGH, indicating the RESET operation is complete.
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TN-29-06: NAND Flash Controller on Spartan-3
Micron NAND Flash Controller Design Details
STreadID
enableTOGO
STreadIDadd00
STreadIDfourReads
State Definition
STreadID Starts the READ ID sequence when the 90h command is issued.
STreadIDadd00 Waits for the 00h address on the I/O bus, which is part of the READ ID command
sequence.
STreadIDfourReads Reads out the 4 bytes of data containing device identification information.
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TN-29-06: NAND Flash Controller on Spartan-3
Micron NAND Flash Controller Design Details
STreadstatusCMD
enableTOGO
STreadstatusRead
State Definition
STreadstatusCMD Waits for the 70h READ STATUS command.
STreadstatusRead Outputs the value of the status register in the NAND Flash device.
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TN-29-06: NAND Flash Controller on Spartan-3
Limitations *************
Limitations *************
Paging and Partial-Page WRITEs
The Micron NAND Flash ECC controller does not support partial-page WRITEs. When
the PROGRAM command is issued, the controller takes whatever is in the buffer and
writes it to the NAND Flash. Therefore, the host should fill in 1 at each location where
no data is to be written to the page.
Bad-Block Management
The Micron NAND Flash controller does not perform bad-block management in hard-
ware, as this is a software function. The Micron NAND Flash specification requires that a
bad block be marked bad at the factory, by writing a byte other than 0xFF into byte
2,048 (the first byte of the extra space) of page 0 or page 1 of the bad block. Precautions
should be taken to ensure that bad blocks are not inadvertently left unmarked by
removal of the bad marking. When the bad-block mark is lost (for example, by erasing
a bad block without a mechanism for recording its location), its location cannot be
retrieved again, and a malfunction may result.
ECC Module
Using the Micron NAND Flash Controller with the Micron ECC Module
The Micron ECC module uses the standard NAND Flash interface, with interrupt and
enable lines added on the host side. This interface plugs directly into the Micron NAND
Flash controller and can also be used to easily make a glueless interface with built-in
ECC.
If the controller is being used with the ECC module, it gives the host the ECC debug fea-
ture of reading the 8 bytes of error information from the ECC module. These 8 bytes of
error information can be used for testing purposes, to calculate ECC statistics. For
detailed information on the format of the 8 bytes of error information, refer to Micron
NAND Flash ECC module documentation at download.micron.com/pdf/technotes/
nand/tn2905.pdf.
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TN-29-06: NAND Flash Controller on Spartan-3
Revisions History
Revisions History
Rev. C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7/14
Removed obsolete URLs.
Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/07
Overview on page 1: Revised description.
Micron NAND Flash Controller Features on page 3: Revised description.
Architectural Description and Memory-Mapped Interface on page 4: Revised
description.
Table 1 on page 5: Revised descriptions.
Table 2 on page 6: Revised function descriptions.
Double Data Buffering on page 9: Revised description.
The enableTOG0 State on page 11: Revised description.
Program Page States on page 15: Revised description.
NAND Flash ECC Module Partial-Page WRITEs on page 20: Revised description.
Updated Web links.
Rev. A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4/05
Initial release.
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