Control Instructions

Opcode Operand Explanation of Description

Instruction

NOP none No operation No operation is

performed. The
instruction is fetched
and decoded.
However no
operation is executed.

Example: NOP

HLT none Halt and enter The CPU finishes

wait state executing the current
instruction and halts
any further execution.
An interrupt or reset
is necessary to exit
from the halt state.

Example: HLT

DI none Disable interrupts The interrupt enable

flip-flop is reset and
all the interrupts
except the TRAP are
disabled. No flags are
affected.

Example: DI

EI none Enable interrupts The interrupt enable

flip-flop is set and all
interrupts are
enabled. No flags are
affected. After a
system reset or the
acknowledgement of
an interrupt, the
interrupt enable
 flipflop is reset, thus
disabling the
interrupts. This
instruction is
necessary to reenable
the interrupts (except
TRAP).

Example: EI

RIM none Read interrupt This is a multipurpose

mas instruction used to
read the status of
interrupts 7.5, 6.5, 5.5
and read serial data
input bit. The
instruction loads
eight bits in the
accumulator with the
following
interpretations.

Example: RIM

SIM none Set interrupt This is a multipurpose

mask instruction and used
to implement the
8085 interrupts 7.5,
6.5, 5.5, and serial
data output. The
instruction interprets
the accumulator
contents as follows.

Example: SIM

LOGICAL INSTRUCTIONS
Opcode Operand Explanation of Description
Instruction

CMP R Compare The contents of the operand (register or

register or memory) are M compared with the contents
M memory with of the accumulator. Both contents are
accumulator preserved . The result of the comparison is
shown by setting the flags of the PSW as
follows:

if (A) < (reg/mem): carry flag is set

if (A) = (reg/mem): zero flag is set
if (A) > (reg/mem): carry and zero flags are
reset

Example: CMP B or CMP M

CPI 8-bit Compare The second byte (8-bit data) is compared

data immediate with with the contents of the accumulator. The
accumulator values being compared remain unchanged.
The result of the comparison is shown by
setting the flags of the PSW as follows:

if (A) < data: carry flag is set

if (A) = data: zero flag is set
if (A) > data: carry and zero flags are reset

Example: CPI 89H

ANA R Logical AND The contents of the accumulator are logically

register or ANDed with M the contents of the operand
M memory with (register or memory), and the result is placed
accumulator in the accumulator. If the operand is a
memory location, its address is specified by
the contents of HL registers. S, Z, P are
modified to reflect the result of the
operation. CY is reset. AC is set.

Example: ANA B or ANA M

ANI 8-bit Logical AND The contents of the accumulator are logically
data immediate with ANDed with the
accumulator 8-bit data (operand) and the result is placed
in the
accumulator. S, Z, P are modified to reflect
 the result of the
operation. CY is reset. AC is set.

Example: ANI 86H

XRA R Exclusive OR The contents of the accumulator are Exclusive

register or ORed with M the contents of the operand
M memory with (register or memory), and the result is placed
accumulator in the accumulator. If the operand is a
memory location, its address is specified by
the contents of HL registers. S, Z, P are
modified to reflect the result of the
operation. CY and AC are reset.

Example: XRA B or XRA M

XRI 8-bit Exclusive OR The contents of the accumulator are Exclusive

data immediate with ORed with the 8-bit data (operand) and the
accumulator result is placed in the accumulator. S, Z, P are
modified to reflect the result of the
operation. CY and AC are reset.

Example: XRI 86H

ORA R Logical OR The contents of the accumulator are logically

register or ORed with M the contents of the operand
M memory with (register or memory), and the result is placed
accumulator in the accumulator. If the operand is a
memory location, its address is specified by
the contents of HL registers. S, Z, P are
modified to reflect the result of the
operation. CY and AC are reset.

Example: ORA B or ORA M

ORI 8-bit Logical OR The contents of the accumulator are logically

data immediate with ORed with the 8-bit data (operand) and the
accumulator result is placed in the accumulator. S, Z, P are
modified to reflect the result of the
operation. CY and AC are reset.

Example: ORI 86H

RLC none Rotate Each binary bit of the accumulator is rotated

accumulator left left by one position. Bit D7 is placed in the
position of D0 as well as in the Carry flag. CY
 is modified according to bit D7. S, Z, P, AC are
not affected.

Example: RLC

RRC none Rotate Each binary bit of the accumulator is rotated

accumulator right by one position. Bit D0 is placed in the
right position of D7 as well as in the Carry flag. CY
is modified according to bit D0. S, Z, P, AC are
not affected.

Example: RRC

RAL none Rotate Each binary bit of the accumulator is rotated

accumulator left left by one position through the Carry flag.
through carry Bit D7 is placed in the Carry flag, and the
Carry flag is placed in the least significant
position D0. CY is modified according to bit
D7. S, Z, P, AC are not affected.

Example: RAL

RAR none Rotate Each binary bit of the accumulator is rotated

accumulator right by one position through the Carry flag.
right through Bit D0 is placed in the Carry flag, and the
carry Carry flag is placed in the most significant
position D7. CY is modified according to bit
D0. S, Z, P, AC are not affected.

Example: RAR

CMA none Complement The contents of the accumulator are

accumulator complemented. No flags are affected.

Example: CMA

CMC none Complement The Carry flag is complemented. No other

carry flags are affected.

Example: CMC

STC none Set Carry Set Carry

Example: STC
BRANCHING INSTRUCTIONS

Opcode Operand Explanation of Description

Instruction

JMP 16-bit Jump The program sequence is tra

address unconditionally to the memory location spe
the 16-bit address given
operand.

Example: JMP 2034H or J

Flag 16-bit Jump The program sequence is tra

Opcode Description
Status address conditionally to the memory location spe
JC Jump on Carry CY = 1 the 16-bit address given
operand based on the spec
JNC Jump on no Carry CY = 0
of the PSW as described belo
JP Jump on positive S=0
Example: JZ 2034H or J
JM Jump on minus S=1
JZ Jump on zero Z=1
JNZ Jump on no zero Z=0
Jump on parity
JPE P=1
even
Jump on parity
JPO P=0
odd

Flag 16-bit Unconditional The program sequence is tra

Opcode Description
Status address subroutine call to the memory location spe
CC Call on Carry CY = 1 the 16-bit address given
operand. Before the trans
CNC Call on no Carry CY = 0
address of the next instruct
CP Call on positive S=0 CALL (the contents of the
CM Call on minus S=1 counter) is pushed onto the
CZ Call on zero Z=1 Example: CALL 2034H or C
CNZ Call on no zero Z=0
 Call on parity
CPE P=1
even
CPO Call on parity odd P = 0

RET none Return from The program sequence is tra

subroutine from the subroutine to th
unconditionally program. The two bytes f
top of the stack are copied
program counter,and
execution begins at th
address.

Example: RET

Flag none Return from The program sequence is tra

Opcode Description
Status subroutine from the subroutine to th
RC Return on Carry CY = 1 conditionally program based on the spec
of the PSW as described be
Return on no
RNC CY = 0 two bytes from the top of t
Carry
are copied into the
RP Return on positive S=0 counter, and program e
RM Return on minus S=1 begins at the new address.
RZ Return on zero Z=1
Example: RZ
RNZ Return on no zero Z=0
Return on parity
RPE P=1
even
Return on parity
RPO P=0
odd

PCHL none Load program The contents of registers

counter with HL are copied into the
contents counter. The contents of
placed as the high-order b
the contents of L as the lo
byte.

Example: PCHL

RST 0-7 Restart The RST instruction is equiv

a 1-byte call instruction to
eight memory locations de
upon the number. The ins
are generally used in con
 with interrupts and inserte
external hardware. Howeve
can be used as software ins
in a program to transfer
execution to one of th
locations. The addresses are

Restart
Instruction
Address
RST 0 0000H
RST1 0008H
RST 2 0010H
RST 3 0018H
RST 4 0020H
RST 5 0028H
RST 6 0030H
RST 7 0038H

The 8085 has four a

interrupts and these in
generate RST instructions i
and thus do not require any
hardware. These instructio
their Restart addresses are:

Restart
Interrupt
Address
TRAP 0024H
RST 5.5 002CH
RST 6.5 0034H
RST 7.5 003CH

Arithmetic Instructions
Opcode Operand Explanation of Description
Instruction

ADD R Add register or The contents of the operand (register or

memory, to memory) are added to the contents of the
M accumulator accumulator and the result is stored in the
accumulator. If the operand is a memory
location, its location is specified by the
contents of the HL registers. All flags are
modified to reflect the result of the addition.

Example: ADD B or ADD M

ADC R Add register to The contents of the operand (register or

accumulator memory) and M the Carry flag are added to
M with carry the contents of the accumulator and the
result is stored in the accumulator. If the
operand is a memory location, its location is
specified by the contents of the HL registers.
All flags are modified to reflect the result of
the addition.

Example: ADC B or ADC M

ADI 8-bit data Add immediate The 8-bit data (operand) is added to the
to accumulator contents of the accumulator and the result is
stored in the accumulator. All flags are
modified to reflect the result of the addition.

Example: ADI 45H

ACI 8-bit data Add immediate The 8-bit data (operand) and the Carry flag
to accumulator are added to the contents of the
with carry accumulator and the result is stored in the
accumulator. All flags are modified to reflect
the result of the addition.

Example: ACI 45H

LXI Reg. pair, Load register The instruction loads 16-bit data in the
16-bit pair immediate register pair designated in the operand.
data
Example: LXI H, 2034H or LXI H, XYZ

DAD Reg. pair Add register The 16-bit contents of the specified register
pair to H and L pair are added to the contents of the HL
 registers register and the sum is stored in the HL
register. The contents of the source register
pair are not altered. If the result is larger
than 16 bits, the CY flag is set. No other
flags are affected.

Example: DAD H

SUB R Subtract register The contents of the operand (register or

or memory from memory ) are subtracted from the contents
M accumulator of the accumulator, and the result is stored
in the accumulator. If the operand is a
memory location, its location is specified by
the contents of the HL registers. All flags are
modified to reflect the result of the
subtraction.

Example: SUB B or SUB M

SBB R Subtract source The contents of the operand (register or

and borrow memory ) and M the Borrow flag are
M from subtracted from the contents of the
accumulator accumulator and the result is placed in the
accumulator. If the operand is a memory
location, its location is specified by the
contents of the HL registers. All flags are
modified to reflect the result of the
subtraction.

Example: SBB B or SBB M

SUI 8-bit data Subtract The 8-bit data (operand) is subtracted from
immediate from the contents of the accumulator and the
accumulator result is stored in the accumulator. All flags
are modified to reflect the result of the
subtraction.

Example: SUI 45H

SBI 8-bit data Subtract The contents of register H are exchanged

immediate from with the contents of register D, and the
accumulator contents of register L are exchanged with
with borrow the contents of register E.

Example: XCHG
INR R Increment The contents of the designated register or
register or memory) are incremented by 1 and the
M memory by 1 result is stored in the same place. If the
operand is a memory location, its location is
specified by the contents of the HL registers.

Example: INR B or INR M

INX R Increment The contents of the designated register pair

register pair by are incremented by 1 and the result is
1 stored in the same place.

Example: INX H

DCR R Decrement The contents of the designated register or

register or memory are M decremented by 1 and the
M memory by 1 result is stored in the same place. If the
operand is a memory location, its location is
specified by the contents of the HL registers.

Example: DCR B or DCR M

DCX R Decrement The contents of the designated register pair

register pair by are decremented by 1 and the result is
1 stored in the same place.

Example: DCX H

DAA none Decimal adjust The contents of the accumulator are

accumulator changed from a binary value to two 4-bit
binary coded decimal (BCD) digits. This is
the only instruction that uses the auxiliary
flag to perform the binary to BCD
conversion, and the conversion procedure is
described below. S, Z, AC, P, CY flags are
altered to reflect the results of the
operation.

If the value of the low-order 4-bits in the

accumulator is greater than 9 or if AC flag is
set, the instruction adds 6 to the low-order
four bits.

If the value of the high-order 4-bits in the

accumulator is greater than 9 or if the Carry
flag is set, the instruction adds 6 to the
 high-order four bits.

Example: DAA

Data Transfer Instructions

Opcode Operand Explanation of Description

Instruction

MOV Rd, Rs Copy from This instruction copies the contents of

source(Rs) to the source register into the destination
M, Rs destination(Rd) register; the contents of the source
register are not altered. If one of the
Rd, M operands is a memory location, its
location is specified by the contents of
the HL registers.

Example: MOV B, C or MOV B, M

MVI Rd, data Move immediate The 8-bit data is stored in the destination
8-bit register or memory. If the operand is a
M, data memory location, its location is specified
by the contents of the HL registers.

Example: MVI B, 57H or MVI M, 57H

LDA 16-bit Load accumulator The contents of a memory location,

address specified by a 16-bit address in the
operand, are copied to the accumulator.
The contents of the source are not
altered.

Example: LDA 2034H

LDAX B/D Reg. Load accumulator The contents of the designated register
pair indirect pair point to a memory location. This
instruction copies the contents of that
memory location into the accumulator.
 The contents of either the register pair or
the memory location are not altered.

Example: LDAX B

LXI Reg. pair, Load register pair The instruction loads 16-bit data in the
16-bit immediate register pair designated in the operand.
data
Example: LXI H, 2034H or LXI H, XYZ

LHLD 16-bit Load H and L The instruction copies the contents of

address registers direct the memory location pointed out by the
16-bit address into register L and copies
the contents of the next memory location
into register H. The contents of source
memory locations are not altered.

Example: LHLD 2040H

STA 16-bit 16-bit address The contents of the accumulator are

address copied into the memory location
specified by the operand. This is a 3-byte
instruction, the second byte specifies the
low-order address and the third byte
specifies the high-order address.

Example: STA 4350H

STAX Reg. pair Store accumulator The contents of the accumulator are
indirect copied into the memory location
specified by the contents of the operand
(register pair). The contents of the
accumulator are not altered.

Example: STAX B

SHLD 16-bit Store H and L The contents of register L are stored into
address registers direct the memory location specified by the 16-
bit address in the operand and the
contents of H register are stored into the
next memory location by incrementing
the operand. The contents of registers HL
are not altered. This is a 3-byte
instruction, the second byte specifies the
low-order address and the third byte
 specifies the high-order address.

Example: SHLD 2470H

XCHG none Exchange H and L The contents of register H are exchanged

with D and E with the contents of register D, and the
contents of register L are exchanged with
the contents of register E.

Example: XCHG

SPHL none Copy H and L The instruction loads the contents of the
registers to the H and L registers into
stack pointer the stack pointer register, the contents of
the H register provide the high-order
address and the contents of the L register
provide the low-order address. The
contents of the H
and L registers are not altered.

Example: SPHL

XTHL none Exchange H and L The contents of the L register are

with top of stack exchanged with the stack location
pointed out by the contents of the stack
pointer register. The contents of the H
register are exchanged with the next
stack location (SP+1); however, the
contents of the stack pointer register are
not altered.

Example: XTHL

PUSH Reg. pair Push register pair The contents of the register pair
onto stack designated in the operand are copied
onto the stack in the following sequence.
The stack pointer register is decremented
and the contents of the highorder
register (B, D, H, A) are copied into that
location. The stack pointer register is
decremented again and the contents of
the low-order register (C, E, L, flags) are
copied to that location.

Example: PUSH B or PUSH A

POP Reg. pair Pop off stack to The contents of the memory location
register pair pointed out by the stack pointer register
are copied to the low-order register (C, E,
L, status flags) of the operand. The stack
pointer is incremented by 1 and the
contents of that memory location are
copied to the high-order register (B, D, H,
A) of the operand. The stack pointer
register is again incremented by 1.

Example: POP H or POP A

OUT 8-bit port Output data from The contents of the accumulator are
address accumulator to a copied into the I/O port specified by the
port with 8-bit operand.
address
Example: OUT F8H

IN 8-bit port Input data to The contents of the input port designated
address accumulator from in the operand are read and loaded into
a port with 8-bit the accumulator.
address
Example: IN 8CH