NRF51 Series Reference Manual v3.0
NRF51 Series Reference Manual v3.0
NRF51 Series Reference Manual v3.0
Version 3.0
Contents
1 Revision history................................................................................... 8
3 System overview................................................................................ 11
3.1 Summary............................................................................................................................... 11
3.2 Block diagram....................................................................................................................... 11
3.3 System blocks....................................................................................................................... 12
3.3.1 ARM® Cortex™-M0................................................................................................. 12
3.3.2 2.4 GHz radio..........................................................................................................13
3.3.3 Power management................................................................................................ 13
3.3.4 PPI system.............................................................................................................. 13
3.3.5 Debugger support....................................................................................................13
4 CPU......................................................................................................14
5 Memory................................................................................................15
5.1 Functional description........................................................................................................... 15
5.1.1 Memory categories.................................................................................................. 15
5.1.2 Memory types.......................................................................................................... 15
5.1.3 Code memory.......................................................................................................... 16
5.1.4 Random Access Memory........................................................................................ 16
5.1.5 Peripheral registers................................................................................................. 16
5.2 Instantiation........................................................................................................................... 17
Page 2
Contents
10 Peripheral interface..........................................................................37
10.1 Functional description......................................................................................................... 37
10.1.1 Peripheral ID......................................................................................................... 37
10.1.2 Bit set and clear.................................................................................................... 38
10.1.3 Tasks..................................................................................................................... 38
10.1.4 Events....................................................................................................................38
10.1.5 Shortcuts................................................................................................................38
10.1.6 Interrupts................................................................................................................38
Page 3
Contents
18 Timer/counter (TIMER).....................................................................99
18.1 Functional description......................................................................................................... 99
Page 4
Contents
Page 5
Contents
24.1.2 Decryption............................................................................................................122
24.1.3 AES CCM and RADIO concurrent operation...................................................... 122
24.1.4 Encrypting packets on-the-fly in radio transmit mode......................................... 122
24.1.5 Decrypting packets on-the-fly in radio receive mode.......................................... 123
24.1.6 CCM data structure............................................................................................. 124
24.1.7 EasyDMA and ERROR event............................................................................. 125
24.1.8 Shared resources................................................................................................ 125
24.2 Register Overview............................................................................................................. 125
24.3 Register Details................................................................................................................. 126
2
28 I C compatible Two Wire Interface (TWI).....................................144
28.1 Functional description....................................................................................................... 144
28.2 Master mode pin configuration......................................................................................... 144
28.3 Shared resources.............................................................................................................. 145
28.4 Master write sequence......................................................................................................145
28.5 Master read sequence...................................................................................................... 146
28.6 Master repeated start sequence....................................................................................... 146
28.7 Register Overview............................................................................................................. 147
28.8 Register Details................................................................................................................. 148
Page 6
Contents
Page 7
1 Revision history
1 Revision history
Date Version Description
September 2014 3.0b Added content:
• Software Interrupts chapter
Updated content:
• Power chapter
November 2013 2.1 Updated content:
• Table 6 on page 19.
• Figure 72 on page 181
• Section31.4.5 on page 185
Page 8
2 About this document
Page 9
2 About this document
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A A
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
Ren 0 Read only access
Wen 1 Write Enabled
Een 2 Erase enabled
Page 10
3 System overview
3 System overview
3.1 Summary
The nRF51 series of System on Chip (SoC) devices embed a powerful yet low power ARM® Cortex™-M0
processor with our industry leading 2.4 GHz RF transceivers. In combination with the very flexible orthogonal
power management system and a Programmable Peripheral Interconnect (PPI) event system, the nRF51
series enables you to make ultra-low power wireless solutions.
The nRF51 series offers pin compatible device options for Bluetooth low energy, proprietary 2.4 GHz, and
ANT™ solutions giving you the freedom to develop your wireless system using the technology that suits your
application the best. Our unique memory and hardware resource protection system allows you to develop
applications on devices with embedded protocol stacks running on the same processor without any need to
link in the stack or strenuous testing to avoid application and stack from interfering with each other.
Page 11
3 System overview
nRF51
SWCLK
SW-DP
SWDIO
slave
slave
slave
slave
slave
AHB
Multi-Layer
master
slave
slave
slave
slave
DAP
NVIC NVMC
RNG
nRESET POWER
RTC [0..n]
TEMP
PPI
XC1 ECB
XC2
CLOCK master EasyDMA
XL1
XL2
CCM
ma s
ter
EasyDMA master master EasyDMA
GPIOTE SCL
TWI [0..n]
SDA
LPCOMP RTS
CTS
UART [0..n]
AIN0 – AIN7 TXD
AREF0 – AREF1 ADC
RXD
CSN
LED MISO
SPIS [0..n]
MOSI
A QDEC
B SCK
master EasyDMA
MISO
SPI [0..n]
MOSI
SCK
Page 12
3 System overview
The ARM® Cortex Microcontroller Software Interface Standard (CMSIS) hardware abstraction layer for the
ARM® Cortex-M processor series is implemented and available for M0 CPU. Code is forward compatible
with ARM® Cortex-M3 and ARM® Cortex-M4 based devices.
Page 13
4 CPU
4 CPU
A low power ARM® Cortex™-M0 32 bit CPU is embedded in all nRF51 series devices. The ARM® Cortex™-
M0 has a 16 bit instruction set with 32 bit extensions (Thumb-2® technology) that delivers high density
code with a small memory footprint. By using a single-cycle 32 bit multiplier, a 3-stage pipeline, and a Nested
Vector Interrupt Controller (NVIC), the ARM® Cortex™-M0 CPU makes program execution simple and highly
efficient.
The data alignment in nRF51 implementation is Little Endian.
The ARM® Cortex Microcontroller Software Interface Standard (CMSIS) hardware abstraction layer for the
ARM® Cortex-M processor series is implemented and available for M0 CPU. Code is forward compatible
with ARM® Cortex-M3 based devices.
For further information on the embedded ARM® Cortex™-M0 CPU, see ARM Cortex M0.
Page 14
5 Memory
5 Memory
Device
0xC000 0000
Device
0xA000 0000
RAM
0x8000 0000
RAM
AHB peripherals 0x5000 0000
0x6000 0000
0x2000 0000
UICR 0x1000 1000
Code
FICR 0x1000 0000
0x0000 0000
Code FLASH
0x0000 0000
1
See product specification for more information
Page 15
5 Memory
Data RAM
System
RAM7
Section 0
AHB slave
Block 3
0x2000 7000
RAM6
Section 0
AHB slave
0x2000 6000
RAM5
Section 0
AHB slave
Block 2
0x2000 5000
RAM4
Section 0
AHB slave
0x2000 4000
RAM3
Section 0
AHB slave
Block 1
0x2000 3000
RAM2
Section 0
AHB slave
0x2000 2000
RAM1
Section 0
AHB slave
Block 0
0x2000 1000
RAM0
Section 0
AHB slave
0x2000 0000
See product specification for more information about how many blocks and RAM AHB slaves are
implemented.
Page 16
5 Memory
When switching from one peripheral to another sharing the same base address (see Instantiation below
to find for which peripherals this is the case), one shall disable the other peripheral currently using the base
address, configure the new settings, and then enable the new peripheral.
Note that tasks and events cannot be used prior to enabling the peripheral.
Some peripherals feature a POWER register. This register is not required to be used unless specifically
required by a PAN (Product Anomaly Notice).
5.2 Instantiation
Table 2: Instantiation table
ID Base address Peripheral Instance Description
0 0x40000000 CLOCK CLOCK Clock control
0 0x40000000 POWER POWER Power Control
0 0x40000000 MPU MPU Memory Protection Unit
1 0x40001000 RADIO RADIO 2.4 GHz radio
2 0x40002000 UART UART0 Universal Asynchronous Receiver/Transmitter
3 0x40003000 SPI SPI0 SPI master 0
3 0x40003000 TWI TWI0 Two-wire interface master 0
4 0x40004000 SPI SPI1 SPI master 1
4 0x40004000 SPIS SPIS1 SPI slave 1
4 0x40004000 TWI TWI1 Two-wire interface master 1
6 0x40006000 GPIOTE GPIOTE GPIO tasks and events
7 0x40007000 ADC ADC Analog to digital converter
8 0x40008000 TIMER TIMER0 Timer 0
9 0x40009000 TIMER TIMER1 Timer 1
10 0x4000A000 TIMER TIMER2 Timer 2
11 0x4000B000 RTC RTC0 Real time counter 0
12 0x4000C000 TEMP TEMP Temperature Sensor
13 0x4000D000 RNG RNG Random Number Generator
14 0x4000E000 ECB ECB AES ECB Mode Encryption
15 0x4000F000 AAR AAR Accelerated Address Resolver
15 0x4000F000 CCM CCM AES CCM Mode Encryption
16 0x40010000 WDT WDT Watchdog Timer
17 0x40011000 RTC RTC1 Real time counter 1
18 0x40012000 QDEC QDEC Quadrature decoder
19 0x40013000 LPCOMP LPCOMP Low power comparator
20 0x40014000 SWI SWI0 Software interrupt 0
21 0x40015000 SWI SWI1 Software interrupt 1
22 0x40016000 SWI SWI2 Software interrupt 2
23 0x40017000 SWI SWI3 Software interrupt 3
24 0x40018000 SWI SWI4 Software interrupt 4
25 0x40019000 SWI SWI5 Software interrupt 5
30 0x4001E000 NVMC NVMC Non Volatile Memory Controller
31 0x4001F000 PPI PPI PPI controller
N/A 0x10000000 FICR FICR Factory Information Configuration
N/A 0x10001000 UICR UICR User Information Configuration
N/A 0x40024000 RTC RTC2 Real time counter 2.
N/A 0x50000000 GPIO GPIO General purpose input and output
Page 17
6 Non-Volatile Memory Controller (NVMC)
Page 18
6 Non-Volatile Memory Controller (NVMC)
Table 6: CONFIG
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A A
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW WEN Program memory access mode. It is strongly recommended
to only activate erase and write modes when they are actively
used.
Ren 0 Read only access
Wen 1 Write Enabled
Een 2 Erase enabled
Table 7: ERASEPAGE
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW ERASEPAGE Register for starting erase of a page in Code region 1
The value is the address to the page to be erased. (Addresses
of first word in page). Note that code erase has to be enabled
by CONFIG.EEN before the page can be erased. See product
specification for information about the total code size of the
device you are using. Attempts to erase pages that are outside
the code area may result in undesirable behaviour, e.g. the
wrong page may be erased.
Table 8: ERASEPCR1
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW ERASEPCR1 Register for erasing a page in Code region 1. Equivalent to
ERASEPAGE.
Table 9: ERASEALL
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A RW ERASEALL Erase all non-volatile memory including UICR registers. Note
that code erase has to be enabled by CONFIG.EEN before the
UICR can be erased.
NoOperation 0 No operation
Erase 1 Start chip erase
Page 19
6 Non-Volatile Memory Controller (NVMC)
Page 20
7 Factory Information Configuration Registers
(FICR)
Page 21
7 Factory Information Configuration Registers
(FICR)
Page 22
7 Factory Information Configuration Registers
(FICR)
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id B B B B B B B B B B B B B B B B A A A A A A A A A A A A A A A A
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id RW Field Value Id Value Description
B R FWID Identification number for the FW that is pre-loaded into the Deprecated
chip
Page 23
7 Factory Information Configuration Registers
(FICR)
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Id RW Field Value Id Value Description
Value to be written to RADIO.OVERRIDE[n] register if
OVERRIDEEN is set. If override values are enabled for more
than one mode the RADIO.OVERRIDE[n] registers has to be
updated every time RADIO.MODE is changed.
Page 24
8 User Information Configuration Registers
(UICR)
Page 25
8 User Information Configuration Registers
(UICR)
Page 26
8 User Information Configuration Registers
(UICR)
Page 27
9 Memory Protection Unit (MPU)
Configuration
Requester
MPU Decision
information
(FA, LA,
NA0 or NA1)
Request target
information
9.1.1 Inputs
The MPU has three classes of inputs. These are:
• Configuration
• Readback protection configuration from UICR and FICR.
Page 28
9 Memory Protection Unit (MPU)
9.1.2 Output
The MPU outputs the level of memory access that shall be given to a memory access request. The access
levels the MPU can give are as follows:
• Full access (FA)
• Full read write access to the requested memory.
• Limited access (LA)
• Full read access.
• No write access. Write will generate hard fault exception.
• No access 0 (NA0)
• No read or write access.
• Read will return 0.
• Write will have no effect.
• No access 1 (NA1)
• No read or write access.
• Read or write will generate hard fault exception.
Table 40: MPU output decision table based on the MPU inputs and the ICR configuration
Request target
Request source UICR.RBPCONF.PALL UICR.RBPCONF.PRO or Code R0 Code R1 RAM R0 RAM R1 PER R0 PER R1
(Readback protect entire code FICR.PPFC (Readback
memory) protect code region 0)
SWD 0xFF 0xFF FA FA FA FA FA FA
0xFF 0x00 NA0 FA FA FA FA FA
0x00 X NA0 NA0 NA0 NA0 NA0 NA0
Code R0 X X FA FA FA FA FA FA
Code R1 X 0xFF LA FA LA FA LA FA
X 0x00 NA1 FA LA FA LA FA
RAM R0/R1 0xFF 0xFF FA FA FA FA FA FA
0xFF 0x00 NA1 FA FA FA FA FA
0x00 X NA1 NA1 FA FA FA FA
Key:
• X: Don't care
• LA: limited access
• NA0: no access 0
• NA1: no access 1
• FA: full access
Page 29
9 Memory Protection Unit (MPU)
Program Memory
63
62
61
31 PROTENSET[1] 0
...
2
1
0
0x00000000
31 PROTENSET[0] 0
Page 30
9 Memory Protection Unit (MPU)
Page 31
9 Memory Protection Unit (MPU)
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id U T S R Q P O N M L K J I H G F E D C B A
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
InRegion0 1 Peripheral configured in region 0
InRegion1 0 Peripheral configured in region 1
R RW QDEC Classify QDEC as region 0 or region 1 peripheral
InRegion0 1 Peripheral configured in region 0
InRegion1 0 Peripheral configured in region 1
S RW LPCOMP Classify LPCOMP as region 0 or region 1 peripheral
InRegion0 1 Peripheral configured in region 0
InRegion1 0 Peripheral configured in region 1
T RW NVMC Classify NVMC as region 0 or region 1 peripheral
InRegion0 1 Peripheral configured in region 0
InRegion1 0 Peripheral configured in region 1
U RW PPI Classify PPI as region 0 or region 1 peripheral
InRegion0 1 Peripheral configured in region 0
InRegion1 0 Peripheral configured in region 1
Page 32
9 Memory Protection Unit (MPU)
Page 33
9 Memory Protection Unit (MPU)
Page 34
9 Memory Protection Unit (MPU)
Page 35
9 Memory Protection Unit (MPU)
Page 36
10 Peripheral interface
10 Peripheral interface
Peripheral
write
TASK
k SHORTS
OR
task
Peripheral
core
event
INTEN m
EVENT m
IRQ signal to NVIC
10.1.1 Peripheral ID
Every peripheral is assigned a fixed block of 0x1000 bytes, which is equal to 1024 x 32 bit registers. This
pattern is applied to all peripherals located on the APB bus and on the AHB bus. See Instantiation on page
17 for more information about which peripherals are available and where they are located in the address
map.
For peripherals on the APB bus there is a direct relationship between its ID and its base address. A
peripheral with base address 0x40000000 is therefore assigned ID=0, and a peripheral with base address
0x40001000 is assigned ID=1. The peripheral with base address 0x4001F000 is assigned ID=31.
Peripherals may share the same ID, which may impose one or more of the following limitations:
• Peripherals do not share any registers or common resources, but the total number of registers available
for each peripheral is reduced compared to a peripheral that has a dedicated ID.
• Peripherals share some registers or other common resources.
• Only one of the peripherals can be used at a time.
• Both peripherals are optional in the series, and only one of them is instantiated in any given chip.
• Switching from one peripheral to another must follow a specific pattern (disable the first, then enable the
second peripheral).
Page 37
10 Peripheral interface
10.1.3 Tasks
Tasks are used to trigger actions in a peripheral, for example, to start a particular behavior. A peripheral can
implement multiple tasks with each task having a separate register in that peripheral's task register group.
A task is triggered when firmware writes a '1' to the task register or when the peripheral itself, or another
peripheral, toggles the corresponding task signal. Figure 6: Tasks, events, shortcuts, and interrupts on page
37
10.1.4 Events
Events are used to notify peripherals and the CPU about events that have happened, for example, a state
change in a peripheral. A peripheral may generate multiple events with each event having a separate
register in that peripheral’s event register group.
An event is generated when the peripheral itself toggles the corresponding event signal, whereupon
the event register is updated to reflect that the event has been generated. See Figure 6: Tasks, events,
shortcuts, and interrupts on page 37. An event register is only cleared when firmware writes a '0' to it.
Events can be generated by the peripheral even when the event register is set to '1'.
10.1.5 Shortcuts
A shortcut is a direct connection between an event and a task within the same peripheral. If a shortcut is
enabled, its associated task is automatically triggered when its associated event is generated.
Using a shortcut is the equivalent to making the same connection outside the peripheral and through the
PPI. However, the propagation delay through the shortcut is usually shorter than the propagation delay
through the PPI.
Shortcuts are predefined, which means their connections cannot be configured by firmware. Each shortcut
can be individually enabled or disabled through the shortcut register, one bit per shortcut, giving a maximum
of 32 shortcuts for each peripheral.
10.1.6 Interrupts
An interrupt is an exception that is generated by an event and can interrupt the program flow of the CPU.
All peripherals on the APB bus support interrupts. A peripheral only occupies one interrupt, and the interrupt
number follows the peripheral ID, for example, the peripheral with ID=4 is connected to interrupt number 4 in
the Nested Vector Interrupt Controller (NVIC).
Using the INTEN, INTENSET and INTENCLR registers, you can configure every event in a peripheral to
generate that peripheral’s interrupt. You can enable multiple events to generate interrupts simultaneously. To
resolve the correct interrupt’s source, firmware can query the event registers found in the event group in the
peripherals register map.
Some peripherals implement only INTENSET and INTENCLR, the INTEN register is not available on those
peripherals. Refer to the individual chapters for details. In all cases, however, reading back the INTENSET or
INTENCLR register returns the same information as in INTEN.
Page 38
10 Peripheral interface
Each event implemented in the peripheral is associated with a specific bit position in the INTEN, INTENSET
and INTENCLR registers. The correct bit position can be derived from the event's address. The event on
address 0x100 is associated with bit 0 in the INTEN register, the event at address 0x104 is associated with
bit 1, and so on. The event at address 0x17C is identified with bit 31 in the INTEN register. This pattern
effectively limits the maximum number of events in a peripheral to 32.
The relationship between tasks, events, shortcuts, and interrupts is shown in Figure 6: Tasks, events,
shortcuts, and interrupts on page 37.
Page 39
11 Debugger Interface (DIF)
SWDCLK SWDCLK
DAP
DIF
SWDIO / nRESET SWDIO ARM CoreSightTM DAP
nRESET
POWER
Page 40
11 Debugger Interface (DIF)
Page 41
12 Power management (POWER)
‘1’ - Always ON
VDD
EN
Regulator
Request 1V2
DCDCEN
EN System and Peripheral
Power
1.2V LDO
VOUT
VDD
VIN
Regulator
EN EN EN Flash
Radio Power Power
Switch mode Radio LDO 1.7V LDO
VOUT
VOUT
VOUT
VIN
VIN
VIN
C C
Page 42
12 Power management (POWER)
‘1’ - Always ON
VDD
EN
1.2V ULP
VOUT
VIN
Regulator
Request 1V2
DCDCEN
EN System and Peripheral
Power
1.2V LDO
VOUT
VDD
VIN
Regulator
EN EN EN
Flash
Radio Power
Switch mode VOUT Radio LDO 1.7V LDO Power
VOUT
VOUT
VIN
VIN
VIN
DC/DC Converter Regulator Regulator
DCC
C C C
The DC/DC converter requires an external LC filter and is enabled through the DCDCEN register. See the
reference circuitry chapter in the product specification for more information about component values.
The DC/DC converter only reduces the power consumption used by the radio, it does not affect the power
used by the Flash, System, and Peripheral.
Enabling the DC/DC converter will not turn it on, but set it in a state where it automatically gets turned on
when the radio is enabled and goes off again when the radio gets disabled. This is done to avoid wasting
power running the DC/DC in between the radio events where current consumption is too low.
DC/DC efficiency
The conversion factor (FDCDC) is the ratio between the power used by the radio and the DC/DC converter
when the DC/DC is active (IDD,DCDC) and the power used by the radio when the DC/DC is disabled (IDD). As
shown in below:
IDD,DCDC=FDCDC * IDD
Page 43
12 Power management (POWER)
DC/DC converter must be disabled. Additional requirements may apply to the accuracy and stability of the
supply voltage in low voltage mode. See the product specification for more information.
‘1’ - Always ON
VDD
EN
1.2V ULP
VOUT
VIN
Regulator
Request 1V2
DCDCEN
EN System and Peripheral
Power
1.2V LDO
VOUT
VDD
VIN
Regulator
EN EN EN
Flash
Radio Power
Switch mode Radio LDO 1.7V LDO Power
VOUT
VOUT
VOUT
VIN
VIN
VIN
DC/DC Converter Regulator Regulator
DCC
C C
Page 44
12 Power management (POWER)
interrupt request if the associated interrupt is enabled in the NVIC. In WFE sleep the CPU will wake up as a
result of an interrupt request regardless of the associated interrupt being enabled in the NVIC or not.
The system implements mechanisms to automatically switch on and off the appropriate power sources
depending on how many peripherals are active, and how much power is needed at any given time. The
power requirement of a peripheral is directly related to its activity level. The activity level is usually raised
and lowered when specific tasks are triggered or events generated, see individual chapters describing the
different peripherals for more information on how to optimize power consumption in System ON mode.
VDD
C
Power on reset
1.7V
Brown-out reset
POFCON VSS
2.1V
2.3V
MUX
2.5V
POFWARN
THRESHOLD
2.7V
Page 45
12 Power management (POWER)
The comparator features a hysteresis of VHYST (refer to the Product Specification for the exact value), as
illustrated in Figure 12: Power failure comparator (BOR = Brown-out reset) on page 46. The threshold
VPOF is set in the POFCON register.
VDD
VPOF+VHYST
VPOF
1.7V
t
POFWARN
POFWARN
MCU
BOR
12.1.11 Reset
There are multiple reset sources that may trigger a reset of the system. After a reset the CPU can query the
RESETREAS (reset reason register) to find out which source generated the reset.
Page 46
12 Power management (POWER)
Note: The RAM is never reset, but depending on reset source, RAM content may be corrupted.
2
Reset from CPU lockup is disabled if the device is in debug interface mode. CPU lockup is not possible in System
OFF.
3
The DAP will not be reset if the device is in debug interface mode.
4
RAM is not reset on wakeup from OFF mode, but depending on settings in the RAMON register parts, or the
whole RAM, may not be retained after the device has entered System OFF mode.
5
Watchdog reset is not available in System OFF.
Page 47
12 Power management (POWER)
Page 48
12 Power management (POWER)
Page 49
12 Power management (POWER)
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id D C B A
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Id RW Field Value Id Value Description
D RW OFFRAM3 Keep retention on RAM block 3 when RAM block is switched off
RAM3Off 0 Off
RAM3On 1 On
Page 50
13 Clock management (CLOCK)
CLOCK
HFCLKSRC
PCLK1M
XC1
PCLK16M
XC2
HCLK
HFCLK
HFCLK LFCLK
CAL SYNT
RC oscillator RC oscillator
LFCLK LFCLK
XL1
XL2
LFCLKSRC
HFCLKSTARTED LFCLKSTARTED
Page 51
13 Clock management (CLOCK)
A HFCLKSTOP task will stop the HFCLK oscillator. However the HFCLKSTOP task can only be sent after
the STATE field in the HFCLKSTAT register indicates a 'HFCLK running' state.
The HFCLK RC oscillator is automatically switched off when the HFCLK crystal oscillators is running; it will
be switched back on automatically when the HFCLK crystal oscillator is stopped.
If the system does not require any of the clocks provided by the HFCLK clock controller, the HFCLK
controller may enter a power saving mode automatically and switch off the selected clock source. This
occurs if all peripherals that require either PCLK1M, PCLK16M are appropriately stopped or disabled, and
the CPU is sleeping and thereby no longer requesting HCLK.
When one or more of the clocks PCLK1M, PCLK16M or HFCLK are requested again, the HFCLK clock
controller will resume normal operation mode. There will be transition time from power saving mode to
normal operation mode that may be different depending on the configuration of the HFCLKSRC register, see
product specification for more information.
To use the RADIO and the calibration mechanism associated with the 32.768 kHz RC oscillator, the HFCLK
clock controller must be configured to use HFCLK crystal oscillator via the HFCLKSRC register, and the
HFCLK crystal oscillator must be running.
The HFCLK crystal oscillators utilize amplitude regulated architecture to achieve low current consumption
and fast start-up. The HFCLK crystal oscillators are also designed to work with one of the following
alternative external sources:
• A 16 MHz rail-to-rail clock signal applied to the XC1 pin. The XC2 pin shall then be left unconnected.
• A 16 MHz low swing clock signal applied to the XC1 pin. The XC2 pin shall then be left unconnected.
Page 52
13 Clock management (CLOCK)
• A low swing clock signal applied to the XL1 pin. The XL2 pin shall then be left unconnected.
• A rail-to-rail clock signal applied to the XL1 pin. The XL2 pin shall then be left unconnected.
The synthesized 32.768 kHz clock depends on the HFCLK to run. If 250 ppm accuracy is required for the
LFCLK running off the synthesized 32.768 kHz clock, the HFCLK must be generated from the HFCLK crystal
oscillator.
CTSTART
Calibration
CTSTOP CTIV
timer
CTTO
Due to limitations in the calibration timer, only one task related to calibration, that is, CAL, CTSTART and
CTSTOP, can be triggered for every period of LFCLK.
Page 53
13 Clock management (CLOCK)
Page 54
13 Clock management (CLOCK)
Page 55
14 General-Purpose Input/Output (GPIO)
PIN0
ANAEN
GPIO Port
DIR_OVERRIDE
OUT_OVERRIDE PIN_CNF[0].DRIVE
PIN0 PIN0
OUT
OUT.0
O
IN.0
OUT.0 PIN_CNF[0]
PIN_CNF[0].DIR
DETECT Sense
..
PIN0_CNF.SENSE PIN_CNF[0].PULL
PIN_CNF[0].INPUT
IN.0 I
PIN31 PIN31
IN OUT.31
IN.31
PIN_CNF[31]
INPUT_OVERRIDE
ANAIN
Figure 15: GPIO Port and the GPIO pin details on page 56 illustrates the GPIO port containing 32
individual pins, where PIN0 is illustrated in more detail as a reference. All the signals on the left side of the
illustration are used by other peripherals in the system, and therefore, are not directly available to the CPU.
Page 56
14 General-Purpose Input/Output (GPIO)
Other peripherals in the system can attach themselves to GPIO pins and override their output value and
configuration, or read their analog or digital input value, see Figure 15: GPIO Port and the GPIO pin details
on page 56.
Selected PINs also support analog input signals, see ANAIN in Figure 15: GPIO Port and the GPIO pin
details on page 56. Pins that support analog input signals vary between devices, see the product
specification for your device for more details.
Page 57
14 General-Purpose Input/Output (GPIO)
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AF AE ADAC AB AA Z Y X W V U T S R Q P O N M L K J I H G F E D C B A
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
C RW PIN2 Pin 2
Low 0 Pin driver is low
High 1 Pin driver is high
D RW PIN3 Pin 3
Low 0 Pin driver is low
High 1 Pin driver is high
E RW PIN4 Pin 4
Low 0 Pin driver is low
High 1 Pin driver is high
F RW PIN5 Pin 5
Low 0 Pin driver is low
High 1 Pin driver is high
G RW PIN6 Pin 6
Low 0 Pin driver is low
High 1 Pin driver is high
H RW PIN7 Pin 7
Low 0 Pin driver is low
High 1 Pin driver is high
I RW PIN8 Pin 8
Low 0 Pin driver is low
High 1 Pin driver is high
J RW PIN9 Pin 9
Low 0 Pin driver is low
High 1 Pin driver is high
K RW PIN10 Pin 10
Low 0 Pin driver is low
High 1 Pin driver is high
L RW PIN11 Pin 11
Low 0 Pin driver is low
High 1 Pin driver is high
M RW PIN12 Pin 12
Low 0 Pin driver is low
High 1 Pin driver is high
N RW PIN13 Pin 13
Low 0 Pin driver is low
High 1 Pin driver is high
O RW PIN14 Pin 14
Low 0 Pin driver is low
High 1 Pin driver is high
P RW PIN15 Pin 15
Low 0 Pin driver is low
High 1 Pin driver is high
Q RW PIN16 Pin 16
Low 0 Pin driver is low
High 1 Pin driver is high
R RW PIN17 Pin 17
Low 0 Pin driver is low
High 1 Pin driver is high
S RW PIN18 Pin 18
Low 0 Pin driver is low
High 1 Pin driver is high
T RW PIN19 Pin 19
Low 0 Pin driver is low
High 1 Pin driver is high
U RW PIN20 Pin 20
Low 0 Pin driver is low
High 1 Pin driver is high
V RW PIN21 Pin 21
Low 0 Pin driver is low
High 1 Pin driver is high
W RW PIN22 Pin 22
Low 0 Pin driver is low
High 1 Pin driver is high
X RW PIN23 Pin 23
Low 0 Pin driver is low
High 1 Pin driver is high
Y RW PIN24 Pin 24
Low 0 Pin driver is low
High 1 Pin driver is high
Z RW PIN25 Pin 25
Low 0 Pin driver is low
High 1 Pin driver is high
AA RW PIN26 Pin 26
Low 0 Pin driver is low
High 1 Pin driver is high
AB RW PIN27 Pin 27
Low 0 Pin driver is low
High 1 Pin driver is high
AC RW PIN28 Pin 28
Low 0 Pin driver is low
Page 58
14 General-Purpose Input/Output (GPIO)
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AF AE ADAC AB AA Z Y X W V U T S R Q P O N M L K J I H G F E D C B A
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
High 1 Pin driver is high
AD RW PIN29 Pin 29
Low 0 Pin driver is low
High 1 Pin driver is high
AE RW PIN30 Pin 30
Low 0 Pin driver is low
High 1 Pin driver is high
AF RW PIN31 Pin 31
Low 0 Pin driver is low
High 1 Pin driver is high
Page 59
14 General-Purpose Input/Output (GPIO)
Page 60
14 General-Purpose Input/Output (GPIO)
Page 61
14 General-Purpose Input/Output (GPIO)
Table 79: IN
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AF AE ADAC AB AA Z Y X W V U T S R Q P O N M L K J I H G F E D C B A
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
A R PIN0 Pin 0
Low 0 Pin input is low
High 1 Pin input is high
B R PIN1 Pin 1
Low 0 Pin input is low
High 1 Pin input is high
C R PIN2 Pin 2
Low 0 Pin input is low
High 1 Pin input is high
D R PIN3 Pin 3
Low 0 Pin input is low
High 1 Pin input is high
E R PIN4 Pin 4
Low 0 Pin input is low
High 1 Pin input is high
F R PIN5 Pin 5
Low 0 Pin input is low
Page 62
14 General-Purpose Input/Output (GPIO)
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AF AE ADAC AB AA Z Y X W V U T S R Q P O N M L K J I H G F E D C B A
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
High 1 Pin input is high
G R PIN6 Pin 6
Low 0 Pin input is low
High 1 Pin input is high
H R PIN7 Pin 7
Low 0 Pin input is low
High 1 Pin input is high
I R PIN8 Pin 8
Low 0 Pin input is low
High 1 Pin input is high
J R PIN9 Pin 9
Low 0 Pin input is low
High 1 Pin input is high
K R PIN10 Pin 10
Low 0 Pin input is low
High 1 Pin input is high
L R PIN11 Pin 11
Low 0 Pin input is low
High 1 Pin input is high
M R PIN12 Pin 12
Low 0 Pin input is low
High 1 Pin input is high
N R PIN13 Pin 13
Low 0 Pin input is low
High 1 Pin input is high
O R PIN14 Pin 14
Low 0 Pin input is low
High 1 Pin input is high
P R PIN15 Pin 15
Low 0 Pin input is low
High 1 Pin input is high
Q R PIN16 Pin 16
Low 0 Pin input is low
High 1 Pin input is high
R R PIN17 Pin 17
Low 0 Pin input is low
High 1 Pin input is high
S R PIN18 Pin 18
Low 0 Pin input is low
High 1 Pin input is high
T R PIN19 Pin 19
Low 0 Pin input is low
High 1 Pin input is high
U R PIN20 Pin 20
Low 0 Pin input is low
High 1 Pin input is high
V R PIN21 Pin 21
Low 0 Pin input is low
High 1 Pin input is high
W R PIN22 Pin 22
Low 0 Pin input is low
High 1 Pin input is high
X R PIN23 Pin 23
Low 0 Pin input is low
High 1 Pin input is high
Y R PIN24 Pin 24
Low 0 Pin input is low
High 1 Pin input is high
Z R PIN25 Pin 25
Low 0 Pin input is low
High 1 Pin input is high
AA R PIN26 Pin 26
Low 0 Pin input is low
High 1 Pin input is high
AB R PIN27 Pin 27
Low 0 Pin input is low
High 1 Pin input is high
AC R PIN28 Pin 28
Low 0 Pin input is low
High 1 Pin input is high
AD R PIN29 Pin 29
Low 0 Pin input is low
High 1 Pin input is high
AE R PIN30 Pin 30
Low 0 Pin input is low
High 1 Pin input is high
AF R PIN31 Pin 31
Low 0 Pin input is low
High 1 Pin input is high
Page 63
14 General-Purpose Input/Output (GPIO)
Page 64
14 General-Purpose Input/Output (GPIO)
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AF AE ADAC AB AA Z Y X W V U T S R Q P O N M L K J I H G F E D C B A
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
Output 1 Pin set as output
AA RW PIN26 Pin 26
Input 0 Pin set as input
Output 1 Pin set as output
AB RW PIN27 Pin 27
Input 0 Pin set as input
Output 1 Pin set as output
AC RW PIN28 Pin 28
Input 0 Pin set as input
Output 1 Pin set as output
AD RW PIN29 Pin 29
Input 0 Pin set as input
Output 1 Pin set as output
AE RW PIN30 Pin 30
Input 0 Pin set as input
Output 1 Pin set as output
AF RW PIN31 Pin 31
Input 0 Pin set as input
Output 1 Pin set as output
Page 65
14 General-Purpose Input/Output (GPIO)
Page 66
14 General-Purpose Input/Output (GPIO)
Page 67
14 General-Purpose Input/Output (GPIO)
Page 68
14 General-Purpose Input/Output (GPIO)
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id E E D D D C C B A
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Id RW Field Value Id Value Description
S0D1 6 Standard '0'. disconnect '1'
H0D1 7 High drive '0', disconnect '1'
E RW SENSE Pin sensing mechanism
Disabled 0 Disabled
High 2 Sense for high level
Low 3 Sense for low level
Page 69
15 GPIO tasks and events (GPIOTE)
Page 70
15 GPIO tasks and events (GPIOTE)
Only one GPIOTE channel can be assigned to one physical pin. Failing to do so may result in unpredictable
behavior.
Page 71
15 GPIO tasks and events (GPIOTE)
Note: Write '0' has no effect. When read this register will return the value of INTEN.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id I D C B A
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
D RW IN3 Write '1' to Enable interrupt on IN[3] event.
Enabled 1 Enable
I RW PORT Write '1' to Enable interrupt on PORT event.
Enabled 1 Enable
Page 72
16 Programmable Peripheral Interconnect (PPI)
CHEN
n 10
CH[0].EEP CH[0].TEP
CH[1].EEP CH[1].TEP
CH[n].EEP CH[n].TEP
CHG[0]
n 10 CHG[0].EN
CHG[0].DIS
CHG[m]
n 10 CHG[m].EN
CHG[m].DIS
n: number of channels
m: number of channel groups
Page 73
16 Programmable Peripheral Interconnect (PPI)
Page 74
16 Programmable Peripheral Interconnect (PPI)
Page 75
16 Programmable Peripheral Interconnect (PPI)
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AF AE ADAC AB AA Z Y X W V U P O N M L K J I H G F E D C B A
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
AA RW CH26 Enable or disable channel 26
Disabled 0 Disable channel
Enabled 1 Enable channel
AB RW CH27 Enable or disable channel 27
Disabled 0 Disable channel
Enabled 1 Enable channel
AC RW CH28 Enable or disable channel 28
Disabled 0 Disable channel
Enabled 1 Enable channel
AD RW CH29 Enable or disable channel 29
Disabled 0 Disable channel
Enabled 1 Enable channel
AE RW CH30 Enable or disable channel 30
Disabled 0 Disable channel
Enabled 1 Enable channel
AF RW CH31 Enable or disable channel 31
Disabled 0 Disable channel
Enabled 1 Enable channel
Page 76
16 Programmable Peripheral Interconnect (PPI)
Page 77
16 Programmable Peripheral Interconnect (PPI)
Page 78
16 Programmable Peripheral Interconnect (PPI)
Page 79
16 Programmable Peripheral Interconnect (PPI)
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id AF AE ADAC AB AA Z Y X W V U P O N M L K J I H G F E D C B A
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
I RW CH8 Include or exclude channel 8
Excluded 0 Exclude
Included 1 Include
J RW CH9 Include or exclude channel 9
Excluded 0 Exclude
Included 1 Include
K RW CH10 Include or exclude channel 10
Excluded 0 Exclude
Included 1 Include
L RW CH11 Include or exclude channel 11
Excluded 0 Exclude
Included 1 Include
M RW CH12 Include or exclude channel 12
Excluded 0 Exclude
Included 1 Include
N RW CH13 Include or exclude channel 13
Excluded 0 Exclude
Included 1 Include
O RW CH14 Include or exclude channel 14
Excluded 0 Exclude
Included 1 Include
P RW CH15 Include or exclude channel 15
Excluded 0 Exclude
Included 1 Include
U RW CH20 Include or exclude channel 20
Excluded 0 Exclude
Included 1 Include
V RW CH21 Include or exclude channel 21
Excluded 0 Exclude
Included 1 Include
W RW CH22 Include or exclude channel 22
Excluded 0 Exclude
Included 1 Include
X RW CH23 Include or exclude channel 23
Excluded 0 Exclude
Included 1 Include
Y RW CH24 Include or exclude channel 24
Excluded 0 Exclude
Included 1 Include
Z RW CH25 Include or exclude channel 25
Excluded 0 Exclude
Included 1 Include
AA RW CH26 Include or exclude channel 26
Excluded 0 Exclude
Included 1 Include
AB RW CH27 Include or exclude channel 27
Excluded 0 Exclude
Included 1 Include
AC RW CH28 Include or exclude channel 28
Excluded 0 Exclude
Included 1 Include
AD RW CH29 Include or exclude channel 29
Excluded 0 Exclude
Included 1 Include
AE RW CH30 Include or exclude channel 30
Excluded 0 Exclude
Included 1 Include
AF RW CH31 Include or exclude channel 31
Excluded 0 Exclude
Included 1 Include
Page 80
17 2.4 GHz Radio (RADIO)
RAM RADIO
S0 2.4 GHz
CRC Dewhitening
Packet Receiver
L
disassembler
S1
EasyDMA
Payload
IFS
Bit counter
control unit
S0 ANT0, ANT1
L Packet
assembler 2.4 GHz
S1 CRC Whitening
Transmitter
Payload MAXLEN
The RADIO includes a Device Address Match unit and an interframe spacing control unit that can be utilized
to simplify address white listing and interframe spacing respectively, in Bluetooth low energy and similar
applications.
The RADIO also includes a Received Signal Strength Indicator (RSSI) and a bit counter. The bit counter
generates events when a preconfigured number of bits have been sent or received by the RADIO.
Page 81
17 2.4 GHz Radio (RADIO)
If the PACKETPTR is not pointing to the Data RAM region, an EasyDMA transfer will result in a HardFault.
See Memory on page 15 for more information about the different memory regions.
The EasyDMA will have finished accessing the RAM when the DISABLED event is generated.
MSBit
LSBit
LSBit
LSBit
For all modes that can be specified in the MODE register, the PREAMBLE is always one byte long. If the first
bit of the ADDRESS is 0 the preamble will be set to 0xAA otherwise the PREAMBLE will be set to 0x55.
Radio packets are stored in memory inside instances of a radio packet data structure as illustrated in
Figure 19: In-RAM representation of radio packet, S0, LENGTH and S1 are optional on page 82. The
PREAMBLE, ADDRESS and CRC fields are omitted in this data structure.
S0 LENGTH S1 PAYLOAD
0 LSByte n
Figure 19: In-RAM representation of radio packet, S0, LENGTH and S1 are optional
The byte ordering on air is always Least Significant Byte First for the ADDRESS and PAYLOAD fields and
Most Significant Byte First for the CRC field. The ADDRESS fields are always transmitted and received least
significant bit first on-air. The CRC field is always transmitted and received Most Significant Bit first. The bit-
endian, i.e. which order the bits are sent and received in, of the S0, LENGTH, S1 and PAYLOAD fields can
be configured via the ENDIAN in PCNF1.
The sizes, in number of bits, of the S0, LENGTH and S1 fields can be individually configured via S0S, LS
and S1S in PCNF0 respectively. If any of these fields are configured to be less than 8 bit long the, the least
significant bits of the fields, as seen from the RAM representation, are used.
If S0, LENGTH or S1 are specified with zero length their fields will be omitted in memory, otherwise each
field will be represented as a separate byte, regardless of the number of bits in their on-air counterpart.
Page 82
17 2.4 GHz Radio (RADIO)
TXADDRESS, RXADDRESSES and RXMATCH registers, logical radio addresses ranging from 0 to 7 are
being used. The relationship between the on-air radio addresses and the logical addresses is described in
Table 99: Definition of logical addresses on page 83.
D0 D4 D7 Data out
+ +
Position 0 1 2 3 4 5 6
Data in
Whitening and de-whitening will be performed over the whole packet, except for the preamble, and the
address field.
The linear feedback shift register, illustrated in Figure 20: Data whitening and de-whitening on page 83
can be initialised via the DATAWHITEIV register.
Page 83
17 2.4 GHz Radio (RADIO)
17.1.7 CRC
The CRC generator in the RADIO calculates the CRC over the whole packet excluding the preamble. If
desirable the address field can be excluded from the CRC calculation as well, see CRCCNF register for
more information.
The CRC polynomial is configurable as illustrated in Figure 21: CRC generation of an n bit CRC on page
0 1
84 where bit 0 in the CRCPOLY register corresponds to X and bit 1 corresponds to X etc. See
CRCPOLY for more information.
Xn Xn-1 X2 X1 X0
Packet
(Clocked in serially)
+ + + + +
bn b0
As illustrated in Figure 21: CRC generation of an n bit CRC on page 84, the CRC is calculated by feeding
the packet serially through the CRC generator. Before the packet is clocked through the CRC generator, the
CRC generator's latches b0 through bn will be initialized with a predefined value specified in the CRCINIT
register. When the whole packet is clocked through the CRC generator, latches b0 through bn will hold the
resulting CRC. This value will be used by the RADIO during both transmission and reception but it is not
available to be read by the CPU at any time. A received CRC can however be read by the CPU via the
RXCRC register independent of whether or not it has passed the CRC check.
The length (n) of the CRC is configurable, see CRCCNF for more information.
The status of the CRC check can be read from the CRCSTATUS register after a packet has been received.
Page 84
17 2.4 GHz Radio (RADIO)
DISABLE
Address sent / ADDRESS
START
DISABLED
RXEN
Address received [Address match]
Packet received / END
/ DISABLED / ADDRESS
Ramp-up
complete START
/ READY
RXDISABLE RXRU RXIDLE RX
STOP / END
Page 85
17 2.4 GHz Radio (RADIO)
State
Transmitter TXRU TXIDLE TX TXIDLE TXDISABLE
DISABLED
READY
ADDRESS
PAYLOAD
END
Lifeline
1 2 3
DISABLE
START
TXEN
A slightly modified version of the transmit sequence from Figure 23: Transmit sequence on page 86 is
illustrated in Figure 24: Transmit sequence using shortcuts to avoid delays on page 86 where the RADIO
is configured to use shortcuts between READY and START, and between END and DISABLE, which means
that no delay is introduced.
State
TXRU TX TXDISABLE
Transmitter
PAYLOAD
READY
END
Lifeline
1 2
DISABLE
START
TXEN
The RADIO is able to send multiple packets one after the other without having to disable and re-enable the
RADIO between packets, this is illustrated in Figure 25: Transmission of multiple packets on page 87.
Page 86
17 2.4 GHz Radio (RADIO)
State
Transmitter TXRU TX TXIDLE TX TXDISABLE
DISABLED
ADDRESS
ADDRESS
PAYLOAD
PAYLOAD
END
READY
END
Lifeline
1 2 3
DISABLE
START
START
TXEN
ADDRESS
PAYLOAD
END
Lifeline
1 2 3
DISABLE
START
RXEN
A slightly modified version of the receive sequence from Figure 26: Receive sequence on page 87 is
illustrated in Figure 27: Receive sequence using shortcuts to avoid delays on page 88 where the the
RADIO is configured to use shortcuts between READY and START, and between END and DISABLE, which
means that no delay is introduced.
Page 87
17 2.4 GHz Radio (RADIO)
State
Reception RXRU RX RXDISABLE
DISABLED
READY
ADDRESS
PAYLOAD
END
Lifeline
1 2
START
DISABLE
RXEN
The RADIO is able to receive multiple packets one after the other without having to disable and re-enable
the RADIO between packets, this is illustrated Figure 28: Reception of multiple packets on page 88.
State
DISABLED
ADDRESS
ADDRESS
PAYLOAD
PAYLOAD
END
READY
END
Lifeline
1 2 3
DISABLE
START
START
RXEN
6
See product specification for more information on the timing value tTXEN.
Page 88
17 2.4 GHz Radio (RADIO)
The Device Address match unit assumes that the 48 first bits of the payload is the device address and that
bit number 6 in S0 is the TxAdd bit. See the Bluetooth Core Specification for more information about device
addresses, TxAdd and white listing.
The RADIO is able to listen for 8 different device addresses at the same time. These addresses are specified
in a DAB/DAP register pair, one pair per address, in addition to a TxAdd bit configured in the DACNF
register. The DAB register specifies the 32 least significant bits of the device address, while the DAP register
specifies the 16 most significant bits of the device address.
Each of the device addresses can be individually included or excluded from the matching mechanism. This is
configured in the DACNF register.
RXRU RX RXDISABLE
0 1 2
Reception
This example
assumes that the
combined length
BCMATCH
BCMATCH
and S1 is 12
DISABLED
ADDRESS
PAYLOAD
bits.
END
Lifeline
1 2 3
BCC = 12
DISABLE
BCC = 12 + 16
START
BCSTART
RXEN
BCSTOP
Page 89
17 2.4 GHz Radio (RADIO)
To enable the trim values to be overridden the override mechanism must be enabled via the ENABLE field in
the OVERRIDE4 register. After override is enabled the new trim values will be used next time the RADIO is
enabled in TX or RX mode.
To go back to standard trim values, for example when switching between BLE_1MBIT and another RADIO
MODE, the override mechanism must be disabled via the ENABLE field in the OVERRIDE4 register.
Page 90
17 2.4 GHz Radio (RADIO)
Page 91
17 2.4 GHz Radio (RADIO)
Page 92
17 2.4 GHz Radio (RADIO)
Page 93
17 2.4 GHz Radio (RADIO)
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id E D C C C B B B B B B B B A A A A A A A A
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
Enabled 1 Enable
Page 94
17 2.4 GHz Radio (RADIO)
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id H G F E D C B A
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
Enable or disable reception on logical address 4. Decision point
START task.
Disabled 0 Disable
Enabled 1 Enable
F RW ADDR5 Enable or disable reception on logical address 5. Decision point
START task.
Disabled 0 Disable
Enabled 1 Enable
G RW ADDR6 Enable or disable reception on logical address 6. Decision point
START task.
Disabled 0 Disable
Enabled 1 Enable
H RW ADDR7 Enable or disable reception on logical address 7. Decision point
START task.
Disabled 0 Disable
Enabled 1 Enable
Page 95
17 2.4 GHz Radio (RADIO)
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A A A A A A A A
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
Inter frame space is the time interval between two consecutive
packets. It is defined as the time, in micro seconds, from the
end of the last bit of the previous packet to the start of the first
bit of the subsequent packet. Decision point: START task.
Page 96
17 2.4 GHz Radio (RADIO)
Page 97
17 2.4 GHz Radio (RADIO)
Page 98
18 Timer/counter (TIMER)
18 Timer/counter (TIMER)
CAPTURE[0..n]
SHUTDOWN
COUNT
START
CLEAR
STOP
TIMER
TIMER Core
Increment BITMODE
PCLK1M Counter
Prescaler
PCLK16M fTIMER
CC[0..n]
When fTIMER <= 1 MHz the TIMER will use PCLK1M instead of PCLK16M for reduced power consumption.
Page 99
18 Timer/counter (TIMER)
In counter mode, the TIMER's internal Counter register is incremented by one each time the COUNT task
is triggered, that is, the timer frequency and the prescaler are not utilized in counter mode. Similarly, the
COUNT task has no effect in Timer mode.
The TIMER's maximum value is configured by changing the bit-width of the timer in the BITMODE register.
For details on which bitmodes are supporting which timers see the device product specification.
The PRESCALER register and the BITMODE register must only be updated when the timer is stopped. If
these registers are updated while the TIMER is started then this may result in unpredictable behavior.
When the timer is incremented beyond its maximum value the Counter register will overflow and the TIMER
will automatically start over from zero.
The Counter register can be cleared, that is, its internal value set to zero explicitly, by triggering the CLEAR
task.
The TIMER implements multiple capture/compare registers, see the product specification for more
information on how many capture/compare registers that are supported in the chip.
18.1.1 Capture
The TIMER implements one capture task for every available capture/compare register. Every time the
CAPTURE[n] task is triggered the Counter value is copied to the CC[n] register.
18.1.2 Compare
The TIMER implements one COMPARE event for every available capture/compare register. A COMPARE
event is generated when the Counter is incremented and then becomes equal to the value specified in
one of the capture compare registers. When the Counter value becomes equal to the value specified in a
capture compare register CC[n], the corresponding compare event COMPARE[n] is generated. The amount
of compare registers per TIMER instantiation is defined in the Product Specification.
BITMODE specifies how many bits of the Counter register and the capture/compare register that are used
when the comparison is performed. Other bits will be ignored.
Page 100
18 Timer/counter (TIMER)
Page 101
18 Timer/counter (TIMER)
Note: Write '0' has no effect. When read this register will return the value of INTEN.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id D C B A
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
B RW COMPARE1 Write '1' to Clear interrupt on COMPARE[1] event.
Disabled 1 Disable
C RW COMPARE2 Write '1' to Clear interrupt on COMPARE[2] event.
Disabled 1 Disable
D RW COMPARE3 Write '1' to Clear interrupt on COMPARE[3] event.
Disabled 1 Disable
Page 102
19 Real Time Counter (RTC)
32.768 kHz
COUNTER
STOP task
event
OVRFLW
RTC
CLEAR task
The PRESCALER register is read/write when the RTC is stopped. The RESCALER register is read-only
once the RTC is STARTed. Writing to the RESCALER register when the RTC is started has no effect.
The PRESCALER is restarted on START, CLEAR and TRIGOVRFLW, that is, the prescaler value is latched
to an internal register (<<PRESC>>) on these tasks.
Examples:
1. Desired COUNTER frequency 100 Hz (10 ms counter period)
PRESCALER = round(32.768 kHz / 100 Hz) - 1 = 327
fRTC = 99.9 Hz
10009.576 µs counter period
2. Desired COUNTER frequency 8 Hz (125 ms counter period)
PRESCALER = round (32.768 kHz / 8 Hz) – 1 = 4095
fRTC = 8 Hz
125 ms counter period
Page 103
19 Real Time Counter (RTC)
Page 104
19 Real Time Counter (RTC)
This means that the RTC implements a slightly different task and event system compared to the standard
system described in Figure 6: Tasks, events, shortcuts, and interrupts on page 37. The RTC's task and event
system is illustrated in Figure 34: Tasks, events and interrupts in the RTC on page 105.
RTC
write
TASK
OR
task
RTC
core
event
EVTEN m INTEN m
EVENT m
IRQ signal to NVIC
Page 105
19 Real Time Counter (RTC)
Page 106
19 Real Time Counter (RTC)
1. CLEAR and STOP (and TRIGOVRFLW; not shown) will be delayed as long as it takes for the peripheral
to clock a falling edge and rising of the LFCLK. This is between 15.2585 µs and 45.7755 µs – rounded to
15 µs and 46 µs for the remainder of the section.
7
Assumes RTC runs continuously between these events.
Note: 32.768 kHz clock jitter is additional to the above provided numbers.
Page 107
19 Real Time Counter (RTC)
Page 108
19 Real Time Counter (RTC)
Page 109
19 Real Time Counter (RTC)
Note: Write '0' has no effect. When read this register will return the value of INTEN.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id F E D C B A
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
B RW OVRFLW Write '1' to Enable interrupt on OVRFLW event.
Enabled 1 Enable
C RW COMPARE0 Write '1' to Enable interrupt on COMPARE[0] event.
Enabled 1 Enable
D RW COMPARE1 Write '1' to Enable interrupt on COMPARE[1] event.
Enabled 1 Enable
E RW COMPARE2 Write '1' to Enable interrupt on COMPARE[2] event.
Enabled 1 Enable
F RW COMPARE3 Write '1' to Enable interrupt on COMPARE[3] event.
Enabled 1 Enable
Page 110
19 Real Time Counter (RTC)
Page 111
20 Watchdog timer (WDT)
When started, the watchdog will automatically force the 32.768 kHz RC oscillator on as long as no other
32.768 kHz clock source is running and generating the 32.768 kHz system clock, see CLOCK chapter.
Page 112
20 Watchdog timer (WDT)
Page 113
20 Watchdog timer (WDT)
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id H G F E D C B A
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Id RW Field Value Id Value Description
F R RR5 Request status for RR[5] register
DisabledOrRequested 0 RR[5] register is not enabled, or are already requesting reload
EnabledAndUnrequested 1 RR[5] register is enabled, and are not yet requesting reload
G R RR6 Request status for RR[6] register
DisabledOrRequested 0 RR[6] register is not enabled, or are already requesting reload
EnabledAndUnrequested 1 RR[6] register is enabled, and are not yet requesting reload
H R RR7 Request status for RR[7] register
DisabledOrRequested 0 RR[7] register is not enabled, or are already requesting reload
EnabledAndUnrequested 1 RR[7] register is enabled, and are not yet requesting reload
Page 114
21 Random Number Generator (RNG)
21.1.2 Speed
The time needed to generate one random byte of data is unpredictable, and may vary from one byte to the
next, see product specification for more information. This is especially true when digital error correction is
enabled.
Page 115
21 Random Number Generator (RNG)
Page 116
22 Temperature sensor (TEMP)
Page 117
22 Temperature sensor (TEMP)
Page 118
23 AES Electronic Codebook mode encryption
(ECB)
23.1.1 EasyDMA
The ECB implements an EasyDMA mechanism for reading and writing to the RAM. This DMA cannot access
the program memory or any other parts of the memory area except RAM.
If the ECBDATAPTR is not pointing to the Data RAM region, an EasyDMA transfer will result in a HardFault.
See Memory on page 15 for more information about the different memory regions.
The EasyDMA will have finished accessing the RAM when the ENDECB or ERRORECB is generated.
Page 119
23 AES Electronic Codebook mode encryption
(ECB)
Page 120
24 AES CCM Mode Encryption (CCM)
SHORTCUT
Figure 47: Key-stream generation followed by encryption or decryption. The shortcut is optional.
Key-stream generation, packet encryption, and packet decryption operations utilize the configuration
specified in the data structure pointed to by the CNFPTR pointer. It is necessary to configure this pointer and
its underlying data structure, and the MODE register before the KSGEN task is triggered. It is also necessary
to configure the INPTR pointer and the OUTPTR pointer before the CRYPT task is triggered.
If a shortcut is used between ENDKSGEN event and CRYPT task, the INPTR pointer and the OUTPTR
pointer must be configured before the KSGEN task is triggered.
24.1.1 Encryption
During packet encryption the AES CCM will read the unencrypted packet located in RAM at the address
specified in the INPTR pointer, encrypt the packet and append a four byte long Message Integrity Check
(MIC) field to the packet. The AES CCM will also modify the length field of the packet to adjust for the
appended MIC field, that is, add four bytes to the length, and store the resulting packet back into RAM at the
address specified in the OUTPTR pointer, see Figure 48: Encryption on page 122.
Empty packets (length field is set to 0) will not be encrypted but instead moved unmodified through the AES
CCM.
The AES CCM is limited to read maximum 27 bytes of the unencrypted payload (PL) regardless of what is
specified in the length field of the unencrypted packet.
8
Bluetooth AES CCM 128 bit block encryption, see Bluetooth Core specification Version 4.0.
Page 121
24 AES CCM Mode Encryption (CCM)
SCRATCHPTR
INPTR
Unencrypted packet
H: Header (S0)
L: Length
H L RFU PL Scratch area
RFU: reserved for future use (S1)
OUTPTR PL: unencrypted payload
Encrypted packet MODE = ENCRYPTION AES CCM EPL: encrypted payload
CCM data
H L+4 RFU EPL MIC
structure
CNFPTR
24.1.2 Decryption
During packet decryption the AES CCM will read the encrypted packet located in RAM at the address
specified in the INPTR pointer, decrypt the packet, authenticate the packet’s MIC field and generate the
appropriate MIC status. The AES CCM will also modify the length field of the packet to adjust for the MIC
field, that is, subtract four bytes from the length, and then store the decrypted packet back into RAM at the
address pointed to by the OUTPTR pointer, see Figure 49: Decryption on page 122.
The CCM is only able to decrypt packets that are at least 5 bytes long, that is, 1 byte encrypted payload
(EPL) and 4 bytes of MIC. The CCM will therefore generate a MIC error for packets where the length field is
set to 1, 2, 3 or 4.
Empty packets (length field is set to 0) will not be decrypted but instead moved unmodified through the AES
CCM, these packets will always pass the MIC check.
The AES CCM is limited to read maximum 27 bytes of the encrypted payload and four bytes of the MIC
regardless of what is specified in the length field of the encrypted packet.
SCRATCHPTR
OUTPTR
Unencrypted packet
H: Header (S0)
L: Length
H L RFU PL Scratch area
RFU: reserved for future use (S1)
INPTR PL: unencrypted payload
Encrypted packet MODE = DECRYPTION AES CCM EPL: encrypted payload
CCM data
H L+4 RFU EPL MIC
structure
CNFPTR
Page 122
24 AES CCM Mode Encryption (CCM)
OUTPTR pointer in the AES CCM must therefore point to the same memory location as the PACKETPTR
pointer in the RADIO, see Figure 50: Configuration of on-the-fly encryption on page 123.
SCRATCHPTR
INPTR
Unencrypted packet
H: Header (S0)
L: Length
OUTPTR H L RFU PL Scratch area
RFU: reserved for future use (S1)
& PL: unencrypted payload
PACKETPTR MODE = ENCRYPTION AES CCM EPL: encrypted payload
Encrypted packet
CCM data
H L+4 RFU EPL MIC
structure
CNFPTR
To remote
receiver
RADIO
TXEN
In order to match the RADIO’s timing, the KSGEN task must be triggered no later than when the START task
in the RADIO is triggered, in addition the shortcut between the ENDKSGEN event and the CRYPT task must
be enabled. This use-case is illustrated in Figure 51: On-the-fly encryption using a PPI connection on page
123 using a PPI connection between the READY event in the RADIO and the KSGEN task in the AES
CCM.
SHORTCUT
ENDKSGEN CRYPT
key-stream
AES CCM encryption
generation
KSGEN ENDCRYPT
PPI
READY
TXEN END
READY START
Page 123
24 AES CCM Mode Encryption (CCM)
SCRATCHPTR
OUTPTR
Unencrypted packet
H: Header (S0)
L: Length
INPTR H L RFU PL Scratch area
RFU: reserved for future use (S1)
& PL: unencrypted payload
PACKETPTR MODE = DECRYPTION AES CCM EPL: encrypted payload
Encrypted packet
CCM data
H L+4 RFU EPL MIC
structure
CNFPTR
From remote
transmitter
RADIO
RXEN
In order to match the RADIO’s timing, the KSGEN task must be triggered no later than when the START task
in the RADIO is triggered. In addition, the CRYPT task must be triggered no earlier than when the ADDRESS
event is generated by the RADIO.
If the CRYPT task is triggered exactly at the same time as the ADDRESS event is generated by the RADIO,
the AES CCM will guarantee that the decryption is completed no later than when the END event in the
RADIO is generated.
This use-case is illustrated in Figure 53: On-the-fly decryption using a PPI connection between the READY
event in the RADIO and the KSGEN task in the AES CCM on page 124 using a PPI connection between
the ADDRESS event in the RADIO and the CRYPT task in the AES CCM. The KSGEN task is triggered from
the READY event in the RADIO through a PPI connection.
key-stream
AES CCM decryption
generation
PPI PPI
READY ADDRESS
RXEN END
READY START
SHORTCUT
RU: Ramp-up of RADIO H: Header (S0) EPL: encrypted payload
P: Preamble L: Length : RADIO receiving noise
A: Address RFU: reserved for future use (S1)
Figure 53: On-the-fly decryption using a PPI connection between the READY event in the RADIO and
the KSGEN task in the AES CCM
Page 124
24 AES CCM Mode Encryption (CCM)
The NONCE vector (as specified by the Bluetooth Core Specification) will be generated by hardware based
on the information specified in the CNFPTR data structure from Table 194: CCM data structure overview on
page 124.
Page 125
24 AES CCM Mode Encryption (CCM)
Page 126
24 AES CCM Mode Encryption (CCM)
Page 127
25 Accelerated Address Resolver (AAR)
LSB MSB
random 10
hash prand
(24-bit) (24-bit)
To resolve an address the ADDRPTR pointer must point to the least significant byte (LSB) of the resolvable
address offset by 3 bytes to accommodate the packet header. The resolver is started by triggering the
START task. A RESOLVED event is generated when and if the AAR manages to resolve the address using
one of the Identity Resolving Keys (IRK) found in the IRK data structure. The AAR will use the IRK specified
in the register IRK0 to IRK15 starting from IRK0. How many to be used is specified by the NIRK register. The
AAR module will generate a NOTRESOLVED event if it is not able to resolve the address using the specified
list of IRKs.
The AAR will go through the list of available IRKs in the IRK data structure and for each IRK try to resolve
the address according to the Resolvable Private Address Resolution Procedure described in the Bluetooth
9
Specification . The time it takes to resolve an address may vary depending on where in the list the
resolvable address is located. The resolution time will also be affected by RAM accesses performed by other
peripherals and the CPU. See product specification for more information about resolution time.
The AAR will not distinguish between public and random addresses. The AAR will also not distinguish
between static and private addresses, or between private resolvable and private non-resolvable addresses.
The AAR will stop as soon as it has managed to resolve the address, or after trying to resolve the address
using NIRK number of IRKs from the IRK data structure. The AAR will generate an END event after it has
stopped.
SCRATCHPTR
IRK data
S0 L S1 ADDR
structure
IRKPTR
25.1.2 Use case example for chaining RADIO packet reception with resolving
addresses with the AAR
The AAR may be started as soon as the 6 bytes required by the AAR has been received by the RADIO and
stored in RAM. The ADDRPTR pointer must point to the least significant byte of the resolvable address
within the received packet offset by 3 bytes to accommodate the packet header.
9
Bluetooth Specification Version 4.0 [Vol 3] chapter 10.8.2.3.
Page 128
25 Accelerated Address Resolver (AAR)
SCRATCHPTR
IRK data
S0 L S1 ADDR
structure
IRKPTR
From remote
transmitter
RADIO
RXEN
Figure 56: Address resolution with packet loaded into RAM by the RADIO
25.1.4 EasyDMA
The AAR implements EasyDMA for reading and writing to the RAM. The EasyDMA will have finished
accessing the RAM when the END, RESOLVED, and NOTRESOLVED events are generated.
If the IRKPTR, ADDRPTR and the SCRATCHPTR is not pointing to the Data RAM region, an EasyDMA
transfer will result in a HardFault. See Memory on page 15 for more information about the different memory
regions.
Page 129
25 Accelerated Address Resolver (AAR)
Page 130
25 Accelerated Address Resolver (AAR)
Page 131
26 Serial Peripheral Interface (SPI) Master
RXD-1 TXD+1
MISO MOSI
RXD TXD
READY
Note: RXD-1 and TXD+1 illustrate the double buffered version of RXD and TXD respectively.
Page 132
26 Serial Peripheral Interface (SPI) Master
Only one peripheral can be assigned to drive a particular GPIO pin at a time, failing to do so may result in
unpredictable behavior.
Page 133
26 Serial Peripheral Interface (SPI) Master
CSN
SCK
READY
READY
READY
READY
READY
CPU 1 2 3 4 5 6 7
TXD = n-2
TXD = n-1
m-2 = RXD
m-1 = RXD
C = RXD
A = RXD
B = RXD
TXD = 0
TXD = 1
TXD = 2
TXD = n
m = RXD
Figure 58: SPI master transaction
The READY event of the third byte transaction is delayed until B is extracted from RXD in occurrence
number 3 on the horizontal lifeline. The reason for this is that the third event is generated first when C is
moved from RXD-1 to RXD after B is read.
The SPI master will move the incoming byte to the RXD register after a short delay following the SCK clock
period of the last bit in the byte. This also means that the READY event will be delayed accordingly, see
Figure 59: SPI master transaction on page 134. Therefore, it is important that you always clear the READY
event, even if the RXD register and the data that is being received is not used.
CSN
CSN
SCK
(CPHA=0)
SCK
MOSI (CPHA=1)
MOSIMISO
MISO
READY
READY
Lifeline
Lifeline
1 1
Page 134
26 Serial Peripheral Interface (SPI) Master
Page 135
26 Serial Peripheral Interface (SPI) Master
Page 136
27 SPI Slave (SPIS)
SPIS
CSN MISO MOSI
ACQUIRE
ACQUIRED
END
DEF
OVERREAD
RAM
TXD RXD
TXD+1 RXD+1
TXD+2 RXD+2
TXD+n RXD+n
Page 137
27 SPI Slave (SPIS)
27.3 EasyDMA
The SPI Slave implements EasyDMA for reading and writing to and from the RAM. The EasyDMA will have
finished accessing the RAM when the END event is generated.
If the TXDPTR and the RXDPTR are not pointing to the Data RAM region, an EasyDMA transfer will result in
a HardFault. See Memory on page 15 for more information about the different memory regions.
Page 138
27 SPI Slave (SPIS)
same TX data will be clocked out and the RX buffers will be overwritten. To prevent this from happening,
the END_ACQUIRE shortcut can be used. With this shortcut enabled the semaphore will be handed over to
the CPU automatically after the granted transaction has completed, giving the CPU the ability to update the
TXPTR and RXPTR between every granted transaction.
If the CPU tries to acquire the semaphore while it is assigned to the SPI slave, an immediate handover
will not be granted. However, the semaphore will be handed over to the CPU as soon as the SPI slave
has released the semaphore after the granted transaction is completed. If the END_ACQUIRE shortcut is
enabled and the CPU has triggered the ACQUIRE task during a granted transaction, only one ACQUIRE
request will be served following the END event.
The MAXRX register specifies the maximum number of bytes the SPI slave can receive in one granted
transaction. If the SPI slave receives more than MAXRX number of bytes, an OVERFLOW will be indicated
in the STATUS register and the incoming bytes will be discarded.
The MAXTX parameter specifies the maximum number of bytes the SPI slave can transmit in one granted
transaction. If the SPI slave is forced to transmit more than MAXTX number of bytes, an OVERREAD will be
indicated in the STATUS register and the ORC character will be clocked out.
The AMOUNTRX and AMOUNTTX registers are updated when a granted transaction is completed. The
AMOUNTTX register indicates how many bytes were read from the TX buffer in the last transaction, that is,
ORC (over-read) characters are not included in this number. Similarly, the AMOUNTRX register indicates
how many bytes were written into the RX buffer in the last transaction.
0 0 1 2 0 1 2
MISO
ACQUIRED
END
&
Lifeline
1 2 3 4
RELEASE
RELEASE
ACQUIRE
ACQUIRE
ACQUIRE
Figure 61: SPI transaction when shortcut between END and ACQUIRE is enabled
Page 139
27 SPI Slave (SPIS)
Page 140
27 SPI Slave (SPIS)
Page 141
27 SPI Slave (SPIS)
Page 142
27 SPI Slave (SPIS)
Page 143
2
28 I C compatible Two Wire Interface (TWI)
2
28 I C compatible Two Wire Interface (TWI)
STARTRX RXDRDY
STARTTX TXDSENT
SUSPEND RXD TXD BB
RXD TXD
RESUME SUSPENDED
(signal) (signal)
ERROR
STOP
STOPPED
VDD VDD
TWI slave TWI slave TWI slave
(EEPROM) (Sensor)
TWI master
Address = b1011001 Address = b1011000 Address = b1011011
R R
SDA SCL SCL SDA SCL SDA SCL SDA
Figure 63: A typical TWI setup comprising one master and three slaves
This TWI master supports clock stretching performed by the slaves. The TWI master is started by triggering
the STARTTX or STARTRX tasks, and stopped by triggering the STOP task.
If a NACK is clocked in from the slave, the TWI master will generate an ERROR event.
Page 144
2
28 I C compatible Two Wire Interface (TWI)
To secure correct signal levels on the pins used by the TWI master when the system is in OFF mode, and
when the TWI master is disabled, these pins must be configured in the GPIO peripheral as described in
Table 258: GPIO configuration on page 145.
Only one peripheral can be assigned to drive a particular GPIO pin at a time, failing to do so may result in
unpredictable behavior.
WRITE
STOP
ACK
ACK
ACK
ACK
ACK
ACK
TWI
ADDR 0 1 2 N-1 N
STOPPED
TXDSENT
TXDSENT
TXDSENT
TXDSENT
CPU Lifeline
1 2 3 4 6 7
STARTTX
TXD = N
TXD = 0
TXD = 1
TXD = 2
STOP
Page 145
2
28 I C compatible Two Wire Interface (TWI)
The TWI master write sequence is stopped when the STOP task is triggered whereupon the TWI master will
generate a stop condition on the TWI bus.
READ
NACK
STOP
ACK
ACK
ACK
ACK
TWI
ADDR A B M-1 M
BB
BB
BB
BB
TWI Lifeline
SHORT
SHORT
SHORT
SHORT
SUSPEND
SUSPEND
SUSPEND
STOP
SUSPENDED
STOPPED
RXDRDY
SUSPENDED
SUSPENDED
RXDRDY
RXDRDY
RXDRDY
CPU Lifeline
1 2 3 4 5
RESUME
M-1 = RXD
STARTRX
RESUME
M = RXD
A = RXD
Page 146
2
28 I C compatible Two Wire Interface (TWI)
START
START
WRITE
READ
NACK
STOP
ACK
ACK
ACK
ACK
ACK
TWI
ADDR 0 ADDR A M-1 M
BB
BB
BB
2-W Lifeline
SHORT
SHORT
SHORT
SUSPEND
SUSPEND
STOP
SUSPENDED
STOPPED
RXDRDY
TXDSENT
RXDRDY
CPU Lifeline
1 2 3 4 5
M-1 = RXD
STARTRX
STARTTX
RESUME
M = RXD
TXD = 0
Figure 66: A repeated start sequence, where the TWI master writes one byte, followed by reading M
bytes from the slave without performing a stop in-between
To generate a repeated start after a read sequence, a second start task must be triggered instead of
the STOP task, that is, STARTRX or STARTTX. This start task must be triggered before the last byte is
extracted from RXD to ensure that the TWI master sends a NACK back to the slave before generating the
repeated start condition.
Page 147
2
28 I C compatible Two Wire Interface (TWI)
Page 148
2
28 I C compatible Two Wire Interface (TWI)
Page 149
2
28 I C compatible Two Wire Interface (TWI)
Page 150
29 Universal Asynchronous Receiver/Transmitter
(UART)
STARTTX
STARTRX
RXD-5
RXD TXD STOPTX
STOPRX RXD-4 TXD
(signal)
RXD-3 (signal)
RXD-2
RXD-1
RXTO
RXD
RXDRDY TXDRDY
Page 151
29 Universal Asynchronous Receiver/Transmitter
(UART)
configured and used. Disabling a peripheral that has the same ID as the UART will not reset any of the
registers that are shared with the UART. It is therefore important to configure all relevant UART registers
explicitly to ensure that it operates correctly.
See the Instantiation table in Instantiation on page 17 for details on peripherals and their IDs.
29.4 Transmission
A UART transmission sequence is started by triggering the STARTTX task. Bytes are transmitted by writing
to the TXD register. When a byte has been successfully transmitted the UART will generate a TXDRDY
event after which a new byte can be written to the TXD register. A UART transmission sequence is stopped
immediately by triggering the STOPTX task.
If flow control is enabled a transmission will be automatically suspended when CTS is deactivated and
resumed when CTS is activated again, as illustrated in Figure 68: UART transmission on page 152. A
byte that is in transmission when CTS is deactivated will be fully transmitted before the transmission is
suspended.
CTS
TXD
0 1 2 N-2 N-1 N
TXDRDY
TXDRDY
TXDRDY
TXDRDY
TXDRDY
Lifeline
1 2 3 5 5 6
TXD = N-1
STARTTX
STOPTX
TXD = N
TXD = 0
TXD = 1
TXD = 2
29.5 Reception
A UART reception sequence is started by triggering the STARTRX task. The UART receiver chain
implements a FIFO capable of storing six incoming RXD bytes before data is overwritten. Bytes are extracted
from this FIFO by reading the RXD register. When a byte is extracted from the FIFO a new byte pending in
the FIFO will be moved to the RXD register. The UART will generate an RXDRDY event every time a new
byte is moved to the RXD register.
When flow control is enabled, the UART will deactivate the RTS signal when there is only space for four
more bytes in the receiver FIFO. The counterpart transmitter is therefore able to send up to four bytes after
the RTS signal is deactivated before data is being overwritten. To prevent overwriting data in the FIFO, the
counterpart UART transmitter must therefore make sure to stop transmitting data within four bytes after the
RTS line is deactivated.
The RTS signal will first be activated again when the FIFO has been emptied, that is, when all bytes in the
FIFO have been read by the CPU, see Figure 69: UART reception on page 153.
The RTS signal will also be deactivated when the receiver is stopped through the STOPRX task as illustrated
in Figure 69: UART reception on page 153. The UART will be able to receive up to four bytes if they are
sent in succession immediately after the RTS signal has been deactivated. This is possible because the
UART is, even after the STOPRX task is triggered, able to receive bytes for an extended period equal to the
Page 152
29 Universal Asynchronous Receiver/Transmitter
(UART)
time it takes to send four bytes on the configured baud rate. The UART will generate a receiver timeout event
(RXTO) when this period has elapsed.
To prevent loss of incoming data the RXD register must only be read one time following every RXDRDY
event.
To secure that the CPU can detect all incoming RXDRDY events through the RXDRDY event register, the
RXDRDY event register must be cleared before the RXD register is read. The reason for this is that the
UART is allowed to write a new byte to the RXD register, and therefore can also generate a new event,
immediately after the RXD register is read (emptied) by the CPU.
RTS
RXD
A B C F M-2 M-1 M
RXDRDY
RXDRDY
RXDRDY
RXDRDY
RXDRDY
RXDRDY
RXDRDY
RXDRDY
RXDRDY
RXTO
Lifeline
1 2 3 4 5 6 7 5 6 7
M-2 = RXD
M-1 = RXD
STARTRX
STOPRX
M = RXD
C = RXD
D = RXD
A = RXD
B = RXD
E = RXD
F = RXD
As indicated in occurrence 2 in Figure 69: UART reception on page 153, the RXDRDY event associated
with byte B is generated first after byte A has been extracted from RXD.
Page 153
29 Universal Asynchronous Receiver/Transmitter
(UART)
Page 154
29 Universal Asynchronous Receiver/Transmitter
(UART)
Note: Write '0' has no effect. When read this register will return the value of INTEN.
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id F E D C B A
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
Enabled 1 Enable
C RW RXDRDY Write '1' to Enable interrupt on RXDRDY event.
Enabled 1 Enable
D RW TXDRDY Write '1' to Enable interrupt on TXDRDY event.
Enabled 1 Enable
E RW ERROR Write '1' to Enable interrupt on ERROR event.
Enabled 1 Enable
F RW RXTO Write '1' to Enable interrupt on RXTO event.
Enabled 1 Enable
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29 Universal Asynchronous Receiver/Transmitter
(UART)
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29 Universal Asynchronous Receiver/Transmitter
(UART)
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30 Quadrature Decoder (QDEC)
ACCREAD ACCDBLREAD
ACC ACCDBL
+ +
SAMPLE
Quadrature decoder
IO router
On-chip
Off-chip Phase A Phase B LED
Mechanical to electrical
Mechanical
device
Quadrature Encoder
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30 Quadrature Decoder (QDEC)
Only one peripheral can be assigned to drive a particular GPIO pin at a time, failing to do so may result in
unpredictable behavior.
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30 Quadrature Decoder (QDEC)
always be suppressed by the filter. (This is assumed that the frequency during the debounce period never
exceeds 500 kHz (as required by the Nyquist theorem when using a 1 MHz sample frequency).
Note: The LED will always be ON when the debounce filters are enabled, as the inputs in this case
will be sampled continuously.
30.1.5 Accumulators
The quadrature decoder contains two accumulator registers, ACC and ACCDBL, that accumulate
respectively valid motion sample values and the number of detected invalid samples (double transitions).
The ACC register will accumulate all valid values (1/-1) written to the SAMPLE register. This can be useful
for preventing hard real-time requirements from being enforced on the application. When using the ACC
register the application does not need to read every single sample from the SAMPLE register, but can
instead fetch the ACC register whenever it fits the application. The ACC register will always hold the relative
movement of the external mechanical device since the previous clearing of the ACC register. Sample values
indicating a double transition (2) will not be accumulated in the ACC register.
An ACCOF event will be generated if the ACC receives a SAMPLE value that would cause the register to
overflow or underflow. Any SAMPLE value that would cause an ACC overflow or underflow will be discarded,
but any samples not causing the ACC to overflow or underflow will still be accepted.
The accumulator ACCDBL accumulates the number of detected double transitions since the previous
clearing of the ACCDBL register.
The ACC and ACCDBL registers can be cleared by the READCLRACC and subsequently read using the
ACCREAD and ACCDBLREAD registers.
The REPORTPER register allows automating the capture of several samples before sending out
a REPORTRDY event in case a non-null displacement has been captured and accumulated. The
REPORTPER field in this register selects after how many samples the accumulator content is evaluated to
send (or not) a REPORTRDY event.
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30 Quadrature Decoder (QDEC)
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30 Quadrature Decoder (QDEC)
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30 Quadrature Decoder (QDEC)
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
Register accumulating all valid samples (not double transition)
read from the RENC (in the SAMPLE register)
Double transitions ( SAMPLE = 2 ) will not be accumulated in
this register. The value is a 32 bit 2's complement value. If a
sample that would cause this register to overflow or underflow
is received, the sample will be ignored and an overflow event
( ACCOF ) will be generated. The ACC register is cleared by
triggering the READCLRACC task.
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30 Quadrature Decoder (QDEC)
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id A A A A
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Id RW Field Value Id Value Description
When this register has reached its maximum value the
accumulation of double / illegal transitions will stop. An
overflow event ( ACCOF ) will be generated if any double or
illegal transitions are detected after the maximum value was
reached. This field is cleared by triggering the READCLRACC
task.
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31 Analog to Digital Converter (ADC)
VDD 1/3
1/3 VDD
2/3
Input Reference M 1/2
M ADC
U
AIN7 U X MUX AREF1
1/3 1
AIN6 AREF0
X
AIN5
AIN4 VBG
AIN3
MUX 2/3 1
AIN2
AIN1
1
AIN0
SAMPLE
Voltage divider
There are two rules to follow to find the maximum input voltage allowed on the AIN pins:
1. The ADC should not be exposed to higher voltage than 2.4 V on an AIN pin after prescaling: Input voltage
x prescaling = max. 2.4 V.
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31 Analog to Digital Converter (ADC)
2. A GPIO pin must not be exposed to higher voltage than VDD + 0.3 V, according to the Absolute
maximum ratings from the nRF51x22 Product Specification.
For example, when using 2/3 prescaling, you can expose 2.4 V / (2/3) = 3.6 V to an AIN pin. To not violate
rule 2, VDD must be 3.3 V or higher.
Table 2 shows examples on maximum voltages that can be exposed to an ADC AIN pin, depending on the
supply voltage and your prescaling settings
If the signal you want to measure is above the maximum allowed AIN voltage, a voltage divider must be
used. See Section 2.4 “Using a voltage divider to lower the voltage” on page 6.
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31 Analog to Digital Converter (ADC)
Figure 4 shows the nRF51 ADC input model when the ADC is sampling and Table 5 shows the value of
RAIN for different prescaling settings. The internal VBG reference voltage is 1.2 V so the ADC internal
voltage source is VBG/2 = 0.6 V.
When the ADC is not sampling the AIN input pin has very high impedance and can be regarded as open
circuit. Table 5 shows the statistics for the internal impedance for different prescaling settings. 99.7% of
devices (+- 3 sigma) are expected to be within 6.3%, for example for 1/1 prescaling => [121.5, 137.9]k#.
31.1.4 Configuration
All parameters such as input selection, reference selection, resolution, pre-scaling etc. are configured using
the CONFIG register.
Note: It is not allowed to configure the ADC during an on-going ADC conversion (ADC busy).
31.1.5 Usage
An ADC conversion is started by using the START task, either by writing the task register directly from the
CPU or by triggering the task through the PPI.
During sampling the ADC will enter a busy state. The ADC busy/ready state can be monitored via the BUSY
register.
When the ADC conversion is completed, an END event will be generated and the result of the conversion
can be read from the RESULT register.
When the ADC conversion is completed, the ADC analog electronics power down to save power.
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31 Analog to Digital Converter (ADC)
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31 Analog to Digital Converter (ADC)
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32 Low Power Comparator (LPCOMP)
AREF0
SAMPLE
START AREF
STOP
MUX
VDD*1/8 AREF1
VDD*2/8
VDD*3/8
VIN+ VIN-
+ - MUX
VDD*4/8
ANADETECT Comparator
(signal to POWER module) core VDD*5/8
RESULT VDD*6/8
VDD*7/8
READY
DOWN
CROSS
UP
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32 Low Power Comparator (LPCOMP)
See the RESETREAS register in the POWER module (Table 53: RESETREAS on page 48) for more
information on how to detect a wakeup from LPCOMP.
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32 Low Power Comparator (LPCOMP)
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32 Low Power Comparator (LPCOMP)
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33 Software Interrupts (SWI)
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