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Fault Trees: Probability of A Particular Failure Condition

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Ranabhat Bikash

Fault trees are used to evaluate the probability of failures in standby and sequential systems. The evaluation process involves deducing the fault tree from the top event down to basic events and their logic gates. Probability of failure can be calculated directly, using Boolean algebra which is complex for large systems, or the minimal cutset method which simplifies the calculation and finds critical combinations of basic events leading to failure. Multi-failure mode components require considering the probability of different failure types and their effect on system success.

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Fault Trees: Probability of A Particular Failure Condition

Uploaded by

Ranabhat Bikash
19 views4 pages
Fault trees are used to evaluate the probability of failures in standby and sequential systems. The evaluation process involves deducing the fault tree from the top event down to basic events and their logic gates. Probability of failure can be calculated directly, using Boolean algebra which is complex for large systems, or the minimal cutset method which simplifies the calculation and finds critical combinations of basic events leading to failure. Multi-failure mode components require considering the probability of different failure types and their effect on system success.

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Fault trees are used to evaluate the probability of failures in standby and sequential systems. The evaluation process involves deducing the fault tree from the top event down to basic events and their logic gates. Probability of failure can be calculated directly, using Boolean algebra which is complex for large systems, or the minimal cutset method which simplifies the calculation and finds critical combinations of basic events leading to failure. Multi-failure mode components require considering the probability of different failure types and their effect on system success.

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Download as pdf or txt
19 views4 pages

Fault Trees: Probability of A Particular Failure Condition

Uploaded by

Ranabhat Bikash
Fault trees are used to evaluate the probability of failures in standby and sequential systems. The evaluation process involves deducing the fault tree from the top event down to basic events and their logic gates. Probability of failure can be calculated directly, using Boolean algebra which is complex for large systems, or the minimal cutset method which simplifies the calculation and finds critical combinations of basic events leading to failure. Multi-failure mode components require considering the probability of different failure types and their effect on system success.

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Fault Trees

- widely used in standby & sequential logic systems


- to evaluate the probability of a particular failure condition of a system
Evaluation process:
 Deduce the fault tree (top-down approach)
- start from the Top Event (system failure condition of interest)
- identify immediate events that cause the top event,
and how they interact(represented by logic gates) to cause the top event
- identify further events that cause the events above,
and proceed downwards until Basic Events are reached
 Calculate the failure probability
- Direct numerical approach (bottom-up approach)
(applicable when all events are independent: no duplicate basic events)
- Boolean algebra approach (top-down) - complex for large systems
- Minimal cutset method (top-down)
approximation can be used to simplify evaluation

Fault Trees
T : loss of electric power

I : loss of a.c. power E3: loss of d.c. power

E1: loss of onsite power E2: loss of offsite power

I
E3

E1 E2

1
Direct Numerical Approach

T Evaluate the probability of ‘loss of electric


power’. If,

P(E1) = 0.067
P(E2) = 0.075
P(E3) = 0.005
I
E3
P(I) = P(E1). P(E2)
= (0.067) x (0.075) = 0.005025

E1 E2
P(T) = P(I) + P(E3) - P(I). P(E3)
= 0.005025 + 0.005 –(0.005025).(0.005)
= 0.01

Boolean Algebra Approach: Duplicated basic events


(Top-down approach)

T = I1 + I2
T = (E1. I3) + (E2 + I4)
= [E1.(E3. E4)] + [E2 + (E5 + E3)]
= E1.E3. E4 + E2 + E5 + E3
= E3 (E1. E4 + 1) + E2 + E5
I1 I2

From the Rules of Boolean Algebra,


(E1. E4 + 1) = 1

E I3 E I4
T = E3 + E2 + E5
1 2

E E E E
3 4 5 3

2
Minimal Cut Set Method
Start from the top logic gate

Replace the gate by its inputs (i.e. gates or basic events)

 if OR gate - take the events below as separate items


 if AND gate - take the events below as a combined item

Continue from top to bottom gates until the basic events are reached

Separate or combined items finally obtained


include only the basic events – these are the cutsets

Determine the minimal cutsets from the cutsets above

Minimal Cut Set Method: Duplicated basic events

G0
T
G1 G2

E1 G3 E2 G4
I1 I2
E1 E3 E4 E2 E5 E3

Cut Sets: Minimal Cut sets:


I3 E I4 E2 E2
E
1 2 E5 E5
E3 E3
E1 E3 E4

E E E E P(T) ≈ P(E2)+ P(E5) + P(E3)


3 4 5 3

3
Multi-failure modes

1 Derive the expression for success probability if


success is defined as a unidirectional path
X Y existing between X and Y. Assume that both
diodes have the same failure probabilities, and
2 Pn = probability of normal operation
Po = probability of failure due to open circuit
Ps = probability of failure due to short circuit

State enumeration method:


Binomial Distribution (p+q)n extended for 3-state component,

(Pn + Po + Ps)2 = Pn2 + Po2 + Ps2 + 2 Pn Po + 2 Pn Ps + 2 Po Ps


G B B G B B

Rs = Pn2 + 2 Pn Po

Multi-failure modes: Conditional Probability Method

Rs = P(sys success | 1 is normal).P(1 is normal)


+ P(sys success | 1 is open).P(1 is open)
1 + P(sys success | 1 is shorted).P(1 is shorted)

X Y Given 1 is normal, P(sys success) = Pn + Po


Given 1 is open, P(sys success) = Pn
2 Given 1 is shorted, P(sys success) = 0

Rs = (Pn + Po) (Pn) + (Pn) (Po) + (0) (Ps)


= Pn2 + 2 Pn Po

If Pn = 0.98, Po = Ps = 0.01 then Rs = 0.98

If Pn = 0.98, Po = 0.02, Ps = 0 then Rs = 0.9996

If Pn = 0.98, Po =0, Ps = 0.02 then Rs = 0.9604

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