EC6601 VLSI DESIGN

UNIT I- MOS TRANSISTOR PRINCIPLE

PART A
1. Define body bias effect. [Nov /Dec-2016]
2. Draw the stick diagram and layout for CMOS inverter[Nov /Dec-2016]
3. Define any two layout design rules [Nov /Dec-2015,reg8]
4. Determine the drain current of short channel NMOS transistor for the following
measurements VDS = 1.5 V, VGS = 2V, VBS = 0V,VTO = 0.43V.Assume VDSAT = 0.6VG,
Kn =110µA/V2 , λ = 0.1V-1, γ = 0.4 and W/L = 0.4/0.25[Nov /Dec-2015, reg8]
5. State channel-length modulation. Write down the equation for describing the channel
length modulation effect in NMOS transistors.[May/June-2016]
6. What is Latch-up? How to prevent latch up?.[May/June-2016]
7. Draw the DC transfer characteristics of CMOS inverter.[May/June-2015,reg8]
8. Define lambda based design rules for layout.[May/June-2015,reg8]
9. List the various issues in technology -CAD.[May/June-2013,reg8]
10. What is stick diagram? Give the various colour coding used in stick diagram.
[Nov /Dec-2010, reg8]
11. What is instances? What is instancing? [Nov /Dec-2010, reg8]
12. What is the need for design rule ? [Nov /Dec-2014, reg8]
13. What are the advantages of CMOS over NMOS technology
14. What are the advantages of CMOS technology ?
15. What is micron design rule?
16. Compare NMOS and PMOS ?
17. What is threshold voltage ?
18. What are different operating modes of MOS transistor ?
19. What are three operating regions of MOS transistor ?
20. Define Scaling?
21. What are the different generations of integrated circuits ?
22. What are the major advantages of IC ?
23. What is the objective of layout rules ?
24. What is accumulation mode?
25. What is depletion mode ?

PART B
1.(i)Describe the Equation for source to drain current in the three regions of operation
of MOS transistor and draw the VI characteristics.[May/June -2016]
[Nov/Dec-2014,reg8] (8)
(ii)Explain in detail about the body effect and its effect in MOS device
[May/June -2016] (8)

2.(i)Explain the DC transfer characteristics of a CMOS Inverter with necessary

conditions for the different regions of operation. [May/June -2016] (8)
(ii)Discuss the principles of constant field and lateral scaling. Write the effects of the
above scaling methods on the device characteristics[May/June -2016] (8)

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3.(i)Explain the different steps involved in n-well CMOS fabrication process with neat
Diagrams. [Nov/Dec-2014,reg8] ,[Nov /Dec-2016] (8)
(ii)Derive the noise margins for a CMOS inverter. [Nov /Dec-2016] (8)

4.(i)Discuss in detail with a neat layout, the design rules for a CMOS inverter.
[Nov /Dec-2016] (8)
(ii)Discuss the mathematical equations that be used to model the drain current and
diffusion capacitance of MOS transistors. [Nov /Dec-2016] (8)

5.Explain in detail about the ideal I-V characteristics and Non ideal I-V characteristics of a
NMOS and PMOS devices. [May/June -2013,reg8] (16)

6.(i)Explain in detail about the body effect and its effect in NMOS and PMOS device (8)
(ii)Derive the expression for DC transfer characteristics of CMOS inverter (8)
[May/June -2013,reg8]

7. Explain the DC transfer characteristics of CMOS inverter. (16)

[May/June -2015,reg8] [Nov /Dec-2015,reg8]

8. Explain in detail with neat diagram the steps involved in the fabrications of nwell process.
[May/June -2015,reg8] (16)

9.(i)Explain in detail of C-V Characteristics of MOSFET. [Nov /Dec-2015,reg8] (8)

(ii)Explain any one process enhancement method and one manufacturing issue in detail.
[Nov /Dec-2015,reg8] , [Nov/Dec-2014,reg8] (8)

10. Design the layout for NAND gate and discuss about layout design rules.
[Nov/Dec-2010,reg8] (16)
11.(i) Draw the stick diagram & layout diagram for 3-input NOR gate. (8)
(ii) Draw the stick diagram & layout diagram for 3-input NAND gate. (8)

12.Explain different fabrication process of Cmos transistor.[April/May 2015](R2008)

13.Device an expression for the rise timer tall timer & propagation delay of a Cmos
inverter. [May/June 2013](R2008)

14.Explain in detail about small signal AC characteristics of mos transistor.

[ May/June2013](R2008)

UNIT II-COMBINATIONAL LOGIC CIRCUITS

PART A
1. Give Elmore Delay expression for propagation delay of an inverter. [May/June-2016]
2. Why single phase dynamic logic structure cannot be cascaded? Justify. [May/June-2016]
3. What is the value of Vout for the figure shown below, where Vtn is threshold voltage of
transistor? [Nov /Dec-2016]

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4.List out the sources of static and dynamic power consumption. [Nov /Dec-2016]
5.Give the expression for Elmore delay and state the various parameters associated with it.
[Nov /Dec-2014, reg8]
6.Draw the small signal model of a MOSFET. [Nov /Dec-2015, reg8]
7.How can a CMOS inverter act as an amplifier? [Nov /Dec-2010, reg8]
8. State the types of power dissipation. [May/June-2015,reg8]
9. What is meant by design margin? [May/June-2013,reg8]
10. List the various power losses in CMOS circuits. [May/June-2013,reg8]
11. Implement a 2:1 Mux using pass transistor. [May/June-2014,reg8]
12. What is static power dissipation?
13. What are the methods to reduce dynamic power dissipation?
14. What are the methods to reduce static power dissipation?
15. Write the applications of transmission gate?
16. What is pass transistor?
17. why low power has become an important issue in the present day VLSI circuit realization
18. What are the various ways to reduce the delay time of a CMOS inverter?
19. What makes dynamic CMOS circuits faster than static CMOS circuits?
20. List various sources of leakage currents?
21. What is glitching power dissipation?
22. What is Dynamic power dissipation?
23. What is transmission gate?

PART B
1.Write short notes on
(i) Ratioed Circuits [Nov /Dec-2016] (8)
(ii)Dynamic CMOS Circuits. [Nov /Dec-2016] (8)

2.(i)Estimate least delay and determine input capacitance of each stages for the logic
network shown in figure, which may represent the critical path of a more complex
logic block. The output of the network is loaded with a capacitance which is 5 times
larger than the input capacitance of the first gate, which is a minimum-sized inverter. .
[Nov /Dec-2016] (8)

(ii)Explain the dynamic power dissipation in CMOS circuits with necessary diagrams and
Expressions. [Nov /Dec-2016] (8)

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3. What are the sources of power dissipation in CMOS and discuss various designs
techniques to reduce power dissipation in CMOS? [May/June-2016] (16)

4.(i)Draw the static CMOS logic circuit for the following expression
(a)Y = (A.B.C.D)’ (b)Y = (D(A+BC))’ [May/June-2016] (8)
(ii) Discuss in detail the characteristics of CMOS transmission gate? [May/June-2016](8)

5. Derive expressions for effective resistance and capacitance estimation using RC

delay models. [Nov /Dec-2014,reg8] (8)

6. (i)Explain the power dissipation of static CMOS design in detail. [N /D-2014,reg8] (8)
(ii)Define logic Effort and reason –out why mostly NAND gates are used to realize the
Combinational circuits rather than NOR gates. [Nov /Dec-2014,reg8] (8)

7. Discuss in detail about the resistive and capacitive delay estimation of a CMOS inverter
circuit. [May/June -2013] (16)
8.(i) Construct a 4 input pseudo nMOS NAND and NOR gates (8)
(ii)Write the expression for minimum possible delay of multistage logic networks. (8)

9.(i)Explain in detail about static and dynamic power dissipation. [A/M2015](R2008)(8)

(ii) Implement a XOR gate using Cmos logic. (8)
10(i) Explain in detail about low power design principles. May/June 2014(R2008) (8)
(ii)Comparison of CMOS families [May/June 2014](R2008) (8)
11. Illustrate the operation of dynamic CMOS Domino and NP Domino logic with necessary
diagrams. (16)

UNIT III- SEQUENTIAL LOGIC CIRCUITS

PART A
1. List out the sources of static and dynamic power consumption.[Nov/Dec-2016]
2. What is meant by pipelining? [Nov/Dec-2016]
3. Why single phase dynamic logic structure cannot be cascaded? Justify.[May/June-2016]
4. Draw the switch level schematic of multiplexer based nMOS latch using nMOS only pass
transistors for multiplexers.[May/June-2016]
5. Enumerate the features of synchronizers .[May/June-2013,reg8]
6. Differentiate between latch and flip flop Nov/Dec-2015,reg8]
7. List the advantages of differential flip flops.
8. Draw the characteristic curve of meta stable state in static latch.
9. What are synchronizers?
10. Summarize the operation modes of NORA logic.
11. Determine the property of clock overlap in the registers.
12. List the methods of sequencing static circuit.
13. Compare SRAM and DRAM.
14. Justify the advantages and applications of self-time pipelined circuits.
15. Design a 1-transistor DRAM cell.
16. Explain the concept of clock skew in transparent latches.
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17. What is clock skew?

18. Define propagation delay and contamination delay?
19. What is MTBF
20. What do you meant by Max delay constraint and Min delay constraint?
21. What is the classification of CMOS circuit families?
22. What are the characteristics of Static CMOS design?
23. List the important properties of Static CMOS design?
24. What are the properties of Dynamic logic?

PART B
1. Explain the operation of Master-slave based edge trigged register.[May/June-2016] (16)

2. Discuss in detail various pipelining approaches to optimize sequential circuits.

[May/June-2016] (16)

3. Discuss in detail various static latches and registers. [Nov/Dec-2016] (16)

4.Write short notes on:

(i) True single-phase clocked register [Nov/Dec-2016] (8)
(ii)NORA-CMOS latches. [Nov/Dec-2016] (8)

5.(i) What are the Klass semi dynamic flip flops and differential Flip flops?
[Nov/Dec-2015,reg8] (8)
(ii)Discuss on Skew tolerant Domino circuits. [Nov/Dec-2015,reg8] (8)

6.(i)Compare Static and dynamic logic circuit with example. [Nov/Dec-2015,reg8] (8)
(ii) Explain briefly the concept of NORA CMOS pipelined structures. (8)

7.(i) Design a 2 input CVSL AND/NAND gate and a 3 input CVSL OR/NOR gate . (8)
(ii) Describe in detail about memory architectures and its building blocks. (8)

8.(i)Draw and explain the operation of conventional CMOS pulsed and resettable latches. (8)
ii) Write a brief note on sequencing dynamic circuits. (8)

9. Explain in detail about static & Dynamic Latches. [ May/June 2014](R2008)

10. What are the different memory architecture and explain them.
[May/June 2014](R2008)
11.Explain any one of the low power memory circuits. Nov/Dec 2013(R2008)
12.Explain issues related to timing and pipelines for VLSI design.
[May/June2013](R2008)

UNIT IV - DESIGNING ARITHMETIC BUILDING BLOCKS

PART A
1. What is meant by bit-sliced data path organization? [May/June-2016]
2. Determine propagation delay of n-bit carry select adder. [May/June-2016]
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3. Why is barrel shifter very useful in the designing of arithmetic circuits? [Nov/Dec-2016]
4. Write the principle of any one fast multiplier. [Nov/Dec-2016]
5. 5 .How path can be implemented in VLSI system?

6. Comment on performance of ripple carry adder.

7. What is the logic of adder for increasing its performance?
8. What is multiplier circuit?
9. Which factors dominate the performance of programmable shifter?
10. What is meant by data path?
11. Write down the expression for worst-case delay for RCA.
12. Define Braun multiplier.
13. Why we go to Booth’s algorithm?
14. List the different types of shifters?
15. Design a logic to reduce the number of generated partial products by half for
Multiplication.
16. Give a note on barrel Shifters.
17. List the uses of Clock gating?
18. Compare DVS & DTS.
19. Explain Bit sliced data path organization.
20. Explain the inverting property of full adder
21. Define Clustered voltage scaling technique.
22. Give a neat sketch on Manchester carry gates.
23. Explain the Concept of logarithmic look ahead adder.
24. Create a partial product selection table using modified booth’s recoding.

PART B
1. Design a 16 bit carry bypass and carry select adder and discuss their features.
[May/June-2016]. (16)

2. Design a 4x4 array multiplier and write down the equation for delay.
[May/June-2016] (16)

3. Explain the operation of a basic 4 bit adder, Describe the different approaches of
improving the speed of the adder. [Nov/Dec-2016] (16)

4. Explain the operation of booth multiplication with suitable examples? Justify how booths
algorithm speed up the multiplication process. [Nov/Dec-2016] (16)

5. Explain in detail about ripple carry adder? [May/June-2014,reg8] (10)

6. Draw the architecture of carry look ahead adders & Explain.[May/June-2014,reg8](16)

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7. What are the types of high speed multiplier? Explain any two.
[Nov/Dec-2014,reg8] (16)

8. Explain in detail about barrel shifters. [Nov/Dec-2014,reg8] (12)

9. Explain the structure of booth multiplier and list its advantages.

10. List the logic design considerations of binary adder and explain
(i) Carry skip adder (8)
(ii) Carry save adder (8)
11. (i) Give a note on linear carry select adder. (10)
(ii) Discuss the data paths in digital processor architectures. (6)
12. (i) Design the arithmetic logic unit (ALU) of 64 bit high end microprocessor and
Arithmetic operators involved in design (12)
(ii) Give a short note on Logarithmic shifter. (4)

UNIT V- IMPLEMENTATION STRATEGIES

PART A
1. What are feed-through cells? State their uses. [May/June-2016]
2. State the features of full custom design. [May/June-2016]
3. What is the standard cell-based ASIC design?[ Nov/Dec-2016]
4. What is an antifuse? State its merits and demerits. [Nov/Dec-2016]
5. Differentiate between channeled and channel less gate array.
6. What are the different levels of design abstraction at physical design.
7. What are macros.
8. What are programmable Interconnects ?
9. What are the types of ASICs ?
10. What are the types of programmable devices ?
11. What are the characteristics of FPGA ?
12. What is programmable logic array ?
13. Give the application of PLA.
14. Give the different types of ASIC.
15. What is the full custom ASIC design ?
16. What is FPGA?
17. What are the different methods of programming of PALs?
18. Give the steps in ASIC design flow?
19. Demonstrate Programmable logic array.
20. Design a primitive gate array cell.
21. Explain configurable logic block.
22. Define Control module of DSP processor.
23. Classify the implementation approaches for digital integrated circuits.
24. Compare semi-custom and full custom design

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PART B
1. With neat sketch explain the CLB,IOB and programmable interconnects of an FPGA
a. Device. [May/June-2016]
(16)
2. Write brief notes on:
3. Full custom ASIC [May/June-2016] (8)
4. Semi-custom ASIC[May/June-2016] (8

5. Discuss the different types of programming technology used in FPGA design.

a. [Nov/Dec-2016] (16)

6. Briefly explain the semi-custom ASIC with its classification. [Nov/Dec-2016] (16)

7. (i)Describe the FPGA architectures. (8)

a. (ii)Explain ASIC design process.
(8)

8. Write notes on (i) SEMI custom ASIC. (ii) PLDs (8+8)

9. Explain in detail about different types of Asic’s. [ Nov/Dec 2009](R2008)
10. Explain in detail about building block architectures of FPGA?
a. [May/June 2013](R2008) (10)
11. Explain in detail about various routing procedures involved in FPGA
interconnect? [May/June2014,reg8] (10)
12. Explain Asic’s standard cell design & cell Libraries.[ May/June 2014,reg8] (8)
13. (i)Describe the Steps involved in semicustom design flow. (8)
(ii)Explain the concepts of programmable interconnect. (8)
14. (i)Describe the FPGA block structure and its components. (8)
(ii)Describe the techniques involved in Switch box programmable wiring. (8)

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