002-00649 S25FL064P 64 Mbit 3.0 V Spi Flash Memory
002-00649 S25FL064P 64 Mbit 3.0 V Spi Flash Memory
002-00649 S25FL064P 64 Mbit 3.0 V Spi Flash Memory
This product family has been retired and is not recommended for designs. For new and current designs, S25FL064L supersede
S25FL064P. These are the factory-recommended migration paths. Please refer to the S25FL-L Family data sheets for specifications
and ordering information.
Distinctive Characteristics
CFI (Common Flash Interface) compliant: allows host system
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 002-00649 Rev. *J Revised May 22, 2017
S25FL064P
General Description
The S25FL064P is a 3.0 Volt (2.7V to 3.6V), single-power-supply flash memory device. The device consists of 128 uniform 64 kB
sectors with the two (Top or Bottom) 64 kB sectors further split up into thirty-two 4 kB sub sectors. The S25FL064P device is fully
backward compatible with the S25FL064A device.
The device accepts data written to SI (Serial Input) and outputs data on SO (Serial Output). The devices are designed to be
programmed in-system with the standard system 3.0-volt VCC supply.
The S25FL064P device adds the following high-performance features using 5 new instructions:
Contents
Distinctive Characteristics .................................................. 1 11. Power-up and Power-down........................................ 48
General Description ............................................................. 2 12. Initial Delivery State.................................................... 49
1. Block Diagram.............................................................. 4 13. Program Acceleration via W#/ACC Pin..................... 49
2. Connection Diagrams.................................................. 5 14. Electrical Specifications............................................. 50
3. Input/Output Descriptions........................................... 7 14.1 Absolute Maximum Ratings .......................................... 50
15. Operating Ranges ....................................................... 50
1. Block Diagram
SRAM PS
RD DATA PATH
IO
CS#
SCK
SI / IO0
SO / IO1
GND
VCC
HOLD# / IO3
W# / ACC / IO2
2. Connection Diagrams
Figure 2.1 16-pin Plastic Small Outline Package (SO)
HOLD#/IO3 1 16 SCK
VCC 2 15 SI/IO0
DNC 4 13 DNC
DNC 5 12 DNC
DNC 6 11 DNC
CS# 7 10 GND
SO/IO1 8 9 W#/ACC/IO2
Note
DNC = Do Not Connect (Reserved for future use)
CS# 1 8 VCC
SO/IO1 2 7 HOLD#/IO3
WSON
W#/ACC/IO2 3 6 SCK
GND 4 5 SI/IO0
Note
There is an exposed central pad on the underside of the USON package. This should not be connected to any voltage or signal line on the PCB. Connecting the central
pad to GND (VSS) is possible, provided PCB routing ensures 0 mV difference between voltage at the USON GND (VSS) lead and the central exposed pad.
A
NC NC NC NC
B
NC SCK GND VCC NC
C
NC CS# NC W#/ACC/IO2 NC
D
NC SO/IO1 SI/IO0 HOLD#/IO3 NC
E
NC NC NC NC NC
A1 A2 A3 A4
NC NC NC NC
B1 B2 B3 B4
NC CS# NC W#/ACC/IO2
D1 D2 D3 D4
E1 E2 E3 E4
NC NC NC NC
F1 F2 F3 F4
NC NC NC NC
3. Input/Output Descriptions
Signal I/O Description
Serial Data Output: Transfers data serially out of the device on the falling edge of SCK.
SO/IO1 I/O
Functions as an input pin in Dual and Quad I/O, and Quad Page Program modes.
Serial Data Input: Transfers data serially into the device. Device latches commands,
SI/IO0 I/O addresses, and program data on SI on the rising edge of SCK. Functions as an output pin in
Dual and Quad I/O mode.
Serial Clock: Provides serial interface timing. Latches commands, addresses, and data on SI
4. Logic Symbol
VCC
SI/IO0 SO/IO1
SCK
CS#
W#/ACC/IO2
HOLD#/IO3
GND
5. Ordering Information
The ordering part number is formed by a valid combination of the following:
S25FL 064 P 0X M F I 00 1
Packing Type
0 = Tray
1 = Tube
3 = 13” Tape and Reel
Model Number (Additional Ordering Options)
03 = 6 x 4 pin configuration BGA package
6. SPI Modes
A microcontroller can use either of its two SPI modes to control SPI flash memory devices:
CPOL = 0, CPHA = 0 (Mode 0)
CPOL = 1, CPHA = 1 (Mode 3)
Input data is latched in on the rising edge of SCK, and output data is available from the falling edge of SCK for both modes.
When the bus master is in standby mode, SCK is as shown in Figure 6.2 for each of the two modes:
SCK remains at 0 for (CPOL = 0, CPHA = 0 Mode 0)
Figure 6.1 Bus Master and Memory Devices on the SPI Bus
SO
SPI Interface with SI
(CPOL, CPHA) =
(0, 0) or (1, 1) SCK
Note
The Write Protect/Accelerated Programming (W#/ACC) and Hold (HOLD#) signals should be driven high (logic level 1) or low (logic level 0) as appropriate.
CS#
CPOL CPHA
Mode 0 0 0 SCK
Mode 3 1 1 SCK
SI MSB
SO MSB
7. Device Operations
All Cypress SPI devices accept and output data in bytes (8 bits at a time). The SPI device is a slave device that supports an inactive
clock while CS# is held low.
Note
(Default) indicates the value of each Configuration Register bit set upon initial factory shipment.
SCK
HOLD#
Hold Hold
Condition Condition
9. Command Definitions
The host system must shift all commands, addresses, and data in and out of the device, beginning with the most significant bit. On
the first rising edge of SCK after CS# is driven low, the device accepts the one-byte command on SI (all commands are one byte
long), most significant bit first. Each successive bit is latched on the rising edge of SCK. Table 9.1 lists the complete set of
commands.
Every command sequence begins with a one-byte command code. The command may be followed by address, data, both, or
nothing, depending on the command. CS# must be driven high after the last bit of the command sequence has been written.
The Read Data Bytes (READ), Read Data Bytes at Higher Speed (FAST_READ), Dual Output Read (DOR), Quad Output Read
CS#
Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
SCK Mode 0
SI 23 22 21 3 2 1 0
MSB
Data Out 1 Data Out 2
Hi-Z
SO 7 6 5 4 3 2 1 0 7
MSB
Figure 9.2 Read Data Bytes at Higher Speed (FAST_READ) Command Sequence
CS#
Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK Mode 0
23 22 21 3 2 1 0 7 6 5 4 3 2 1 0
SI
Hi-Z
SO 7 6 5 4 3 2 1 0 7
MSB MSB
DATA OUT 1 DATA OUT 2
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
SI/IO0 23 22 21 3 2 1 0 7 6 5 4 3 2 1 0 6 4 2 0 6 4 2 0 6
* *
Hi-Z
SO/IO1 7 5 3 1 7 5 3 1 7
* *
Byte 1 Byte 2
*MSB
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
SI/IO0 23 22 21 3 2 1 0 7 6 5 4 3 2 1 0 4 0 4 0 4 0 4 0 4
Hi-Z * *
SO/IO1 5 1 5 1 5 1 5 1 5
Hi-Z
W#/ACC/IO2 6 2 6 2 6 2 6 2 6
Hi-Z
HOLD#/IO3 7 3 7 3 7 3 7 3 7
* * * * *
DATA DATA DATA DATA
OUT 1 OUT 2 OUT 3 OUT 4 *MSB
CS#
0 1 2 3 4 5 6 7 8 9 10 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction 24 Bit
Address IO0 & IO1 Switches from Input to Output
SI/IO0 22 20 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6
Hi-Z
SO/IO1 23 21 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7
* * * * *
Mode Bits Byte 1 Byte 2
*MSB
Figure 9.6 Continuous Dual I/O High Performance Read Instruction Sequence
CS#
0 1 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
24 Bit
Address IO0 & IO1 Switches from Input to Output
SO/IO1 23 21 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7
* * * * *
Mode Bits Byte 1 Byte 2 *MSB
CS#
0 1 2 3 4 5 6 7 8 9 13 14 15 16 17 18 19 20 21 22 23 24 25 26
SCK
Instruction 24 Bit
Address IO’s Switches from Input to Output
SI/IO0 20 16 0 4 0 4 0 4 0 4
CS#
0 1 4 5 6 7 8 9 10 11 12 13 14 15 16
SCK
SI/IO0 20 16 0 4 0 4 0 0 4
4
SO/IO1 21 17 1 5 1 5 1 5 1 5
W#/ACC/IO2 22 18 2 6 2 6 2 6 2 6
HOLD#/IO3 23 19 3 7 3 7 3 7 3 7
* * Bits DUMMY * * *
Mode DUMMY Byte 1 Byte 2
*MSB
Figure 9.9 Read Identification (RDID) Command Sequence and Data-Out Sequence
CS#
Instruction
SI
Notes
1. Byte 0 is Manufacturer ID of Cypress.
2. Byte 1 & 2 is Device Id.
3. Byte 3 is Extended Device Information String Length, to indicate how many Extended Device Information bytes will follow.
4. Bytes 4, 5 and 6 are Cypress reserved (do not use).
5. For Bytes 07h-0Fh and 3Dh-3Fh, the data will be read as 0xFF.
6. Bytes 10h-50h are factory programmed per JEDEC standard.
1Bh 27h VCC Min. (erase/program): (D7-D4: Volt, D3-D0: 100 mV)
1Ch 36h VCC Max. (erase/program): (D7-D4: Volt, D3-D0: 100 mV)
1Dh 00h VPP Min. voltage (00h = no VPP pin present)
1Eh 00h VPP Max. voltage (00h = no VPP pin present)
1Fh 0Bh Typical timeout per single byte program 2N µs
Typical timeout for Min. size Page program 2N µs
20h 0Bh
(00h = not supported)
21h 09h Typical timeout per individual sector erase 2N ms
22h 10h Typical timeout for full chip erase 2N ms (00h = not supported)
23h 01h Max. timeout for byte program 2N times typical
24h 01h Max. timeout for page program 2N times typical
25h 02h Max. timeout per individual sector erase 2N times typical
Max. timeout for full chip erase 2N times typical
26h 01h
(00h = not supported)
Note
CFI data related to VCC and time-outs may differ from actual VCC and time-outs of the product. Please consult the Ordering Information tables to obtain the VCC range for
particular part numbers. Please consult the AC Characteristics on page 53 for typical timeout specifications.
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
SI 23 22 21 3 2 1 0
High Impedance
SO 7 6 5 4 3 2 1 0
Mode 3 0 1 2 3 4 5 6 7
SCK Mode 0
Command
SI
Hi-Z
SO
CS#
Mode 3 0 1 2 3 4 5 6 7
SCK Mode 0
Command
SI
Hi-Z
SO
CS#
Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK Mode 0
Command
SI
Hi-Z
SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
MSB MSB
Status Register Out Status Register Out
The following describes the status and control bits of the Status Register.
Write In Progress (WIP) bit: Indicates whether the device is busy performing a Write Registers, program, or erase operation. This
bit is read-only, and is controlled internally by the device. If WIP is 1, one of these operations is in progress; if WIP is 0, no such
operation is in progress. This bit is a Read-only bit.
Write Enable Latch (WEL) bit: Determines whether the device will accept and execute a Write Registers, program, or erase
command. When set to 1, the device accepts these commands; when set to 0, the device rejects the commands. This bit is set to 1
by writing the WREN command, and set to 0 by the WRDI command, and is also automatically reset to 0 after the completion of a
Write Registers, program, or erase operation, and after a power down/power up sequence. WEL cannot be directly set by the WRR
command.
Block Protect (BP2, BP1, BP0) bits: Define the portion of the memory area that will be protected against any changes to the stored
data. The Block Protection (BP2, BP1, BP0) bits are either volatile or non-volatile, depending on the state of the non-volatile bit
BPNV in the Configuration register. The Block Protection (BP2, BP1, BP0) bits are written with the Write Registers (WRR)
instruction. When one or more of the Block Protect (BP2, BP1, BP0) bits is set to 1’s, the relevant memory area is protected against
Page Program (PP), Parameter Sector Erase (P4E, P8E), Sector Erase (SE), Quad Page Programming (QPP) and Bulk Erase (BE)
instructions. If the Hardware Protected mode is enabled, BP2:BP0 cannot be changed.
The Bulk Erase (BE) instruction can be executed only when the Block Protection (BP2, BP1, BP0) bits are set to 0’s.
The default condition of the BP2-0 bits is binary 000 (all 0’s).
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
In st r u ct i o n
SI
Configuration Register Out Configuration Register Out
High Impedance
SO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
CS#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK
In st r u ct i o n St at u s Regi st er In
SI 7 6 5 4 3 2 1 0
MSB
High Impedance
SO
CS
S#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
MSB MSB
High Impedance
SO
Note
As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 7.3 on page 14.
Table 9.9 shows that neither W#/ACC or SRWD bit by themselves can enable HPM. The device can enter HPM either by setting the
SRWD bit after driving W#/ACC low, or by driving W#/ACC low after setting the SRWD bit. However, the device disables HPM only
when W#/ACC is driven high.
Note that HPM only protects against changes to the status register. Since BP2:BP0 cannot be changed in HPM, the size of the
protected area of the memory array cannot be changed. Note that HPM provides no protection to the memory array area outside that
specified by BP2:BP0 (Software Protected Mode, or SPM).
If W#/ACC is permanently tied high, HPM can never be activated, and only the SPM (BP2:BP0 bits of the Status Register) can be
used.
The Status and Configuration registers originally default to 00h, when the device is first shipped from the factory to the customer.
Note: HPM is disabled when the Quad I/O Mode is enabled (Quad bit = 1 in the Configuration Register). W# becomes IO2; therefore,
HPM cannot be utilized.
CS#
Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
SCK Mode 0
23 22 21 3 2 1 0 7 6 5 4 3 2 1 0
SI
MSB MSB
CS#
2072
2075
2074
2076
2073
2078
2077
2079
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCK
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
SI
MSB MSB MSB
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
SCK
Instruction 24 Bit
Address
SI/IO0 23 22 21 3 2 1 0 4 0 4 0 4 0 4 0
*
SO/IO1 5 1 5 1 5 1 5 1
W#/ACC/IO2 6 2 6 2 6 2 6 2
HOLD#/IO3 7 3 7 3 7 3 7 3
* * * *
Byte 1 Byte 2 Byte 3 Byte 4
CS#
536
537
538
539
540
541
542
543
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCK
SI/IO0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 0
4
SO/IO1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1
W#/ACC/IO2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2
HOLD#/IO3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3
* * * * * * * * * * * *
Byte 5 Byte 6 Byte 7 Byte 8 Byte 9 Byte 10 Byte 11 Byte 12 Byte 253 Byte 254 Byte 255 Byte 256
*MSB
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
SCK
SI 23 22 21 3 2 1 0
MSB
CS#
Mode 3 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
SCK Mode 0
SI 23 22 21 3 2 1 0
MSB
Hi-Z
SO
CS#
Mode 3 0 1 2 3 4 5 6 7
SCK
Mode 0
Command
SI
Hi-Z
SO
CS#
tDP
Mode 3 0 1 2 3 4 5 6 7
SCK
Mode 0
Command
SI
Hi-Z
SO
CS#
Mode 3 0 1 2 3 4 5 6 7
SCK Mode 0
Command tRES
SI
Hi-Z
SO
9.20.1 Release from Deep Power-Down and Read Electronic Signature (RES)
The device features an 8-bit Electronic Signature, which can be read using the RES command. See Figure 9.24 and Table 9.1
on page 18 for the command sequence and signature value. The Electronic Signature is not to be confused with the identification
data obtained using the RDID command. The device offers the Electronic Signature so that it can be used with previous devices that
offered it; however, the Electronic Signature should not be used for new designs, which should read the RDID data instead.
After the host system drives CS# low, it must write the RES command followed by 3 dummy bytes to SI (each bit is latched on SI
during the rising edge of SCK). The Electronic Signature is then output on SO; each bit is shifted out on the falling edge of SCK. The
RES operation is terminated by driving CS# high after the Electronic Signature is read at least once. Additional clock cycles on SCK
with CS# low cause the device to output the Electronic Signature repeatedly.
Figure 9.24 Release from Deep Power-Down and RES Command Sequence
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
SCK
3 Dummy t RES
Instruction
Bytes
SI 23 22 21 3 2 1 0
MSB
Electonic ID
High Impedance
SO 7 6 5 4 3 2 1 0
MSB
CS
S#
0 1 2 3 4 5 6 7
SCK
Instruction
SI
CS#
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
SCK
24 Bit
Instruction Data Byte 1
Address
SI 23 22 21 3 2 1 0 7 6 5 4 3 2 1 0
MSB MSB
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
24 Bit
Instruction Address Dummy Byte
SI 23 22 21 3 2 1 0 7 6 5 4 3 2 1 0
The thirty 16-byte and one 10-byte OTP regions are open for the customer usage.
The thirty 16-byte, one 10-byte, and upper 8-byte ESN OTP regions can be individually locked by the end user. Once
locked, the data cannot changed. The locking process is permanent and cannot be undone.
The following general conditions should be noted with respect to the OTP Regions:
On power-up, or following a hardware reset, or at the end of an OTPP or an OTPR command, the device reverts to sending
commands to the normal address space.
Reads or Programs outside of the OTP Regions will be ignored
The OTP Region is not accessible when the device is executing an Embedded Program or Embedded Erase algorithm.
The ACC function is not available when accessing the OTP Regions.
The thirty 16-byte and one 10-byte OTP regions are left open for customer usage, but special care of the OTP locking must
be maintained, or else a malevolent user can permanently lock the OTP regions. This is not a concern, if the OTP regions
are not used.
ADDRESS OT P R EGION
0x213h
16 bytes (OTP16)
0x204h
0x203h
16 bytes (OTP15)
0x1F4h
0x1F3h
16 bytes (OTP14)
Notes
1. Bit 0 at address 0x100h locks ESN1 region.
2. Bit 1 at address 0x100h locks ESN2 region.
3. Bits 2-7 (“X”) are NOT programmable and will be ignored.
ADDRESS OT P R EGION
0x2FFh
10 bytes (OTP31)
0x2F6h
0x2F5h
16 bytes (OTP30)
0x2E6h
0x2E5
16 bytes (OTP29)
Note
1. Bit 7 (“X”) at address 0x215h is NOT programmable and will be ignored.
Vcc
(max)
Vcc
(min)
Vcc
Time
VHH
ACC
tWC tWC
VIL or VIH VIL or VIH
tVHH Command OK
tVHH
Note
Only Read Status Register (RDSR) and Page Program (PP) operation are allow when ACC is at (VHH).
The W#/ACC pin is disabled during Quad I/O mode.
+0.8V
–0.5V
–2.0V
20 ns
VCC
+2.0V
VCC
+0.5V
2.0V
20 ns 20 ns
Note
Operating ranges define those limits between which functionality of the device is guaranteed.
16. DC Characteristics
This section summarizes the DC Characteristics of the device. Designers should check that the operating conditions in their circuit
match the measurement conditions specified in the Test Specifications in Table 17.1 on page 52, when relying on the quoted
parameters.
VOL Output Low Voltage IOL = 1.6 mA, VCC = VCC min. 0.4 V
VOH Output High Voltage IOH = -0.1 mA VCC-0.6 V
VCC = VCC Max,
ILI Input Leakage Current ±2 µA
VIN = VCC or GND
VCC = VCC Max,
ILO Output Leakage Current ±2 µA
VIN = VCC or GND
At 80 MHz
38
Active Power Supply Current - (Dual or Quad)
ICC1 READ mA
At 104 MHz (Serial) 26
(SO = Open)
At 40 MHz (Serial) 15
Active Power Supply Current
ICC2 CS# = VCC 26 mA
(Page Program)
Active Power Supply Current
ICC3 CS# = VCC 15 mA
(WRR)
Active Power Supply Current
ICC4 CS# = VCC 26 mA
(SE)
Active Power Supply Current
ICC5 CS# = VCC 26 mA
(BE)
CS# = VCC;
ISB1 Standby Current 80 200 µA
VIN = GND or VCC
CS# = VCC;
IPD Deep Power-down Current 3 10 µA
VIN = GND or VCC
0.8 VCC
0.7 VCC
Input Levels 0.5 VCC
0.3 VCC
0.2 VCC
18. AC Characteristics
Figure 18.1 AC Characteristics
Symbol Parameter Min. Typ Max
(Notes) (Notes) (Notes) (Notes) (Notes) Unit
SCK Clock Frequency for READ command DC 40 MHz
fR
SCK Clock Frequency for RDID command DC 50
SCK Clock Frequency for all others:
104 (serial)
fC FAST_READ, PP, QPP, P4E, P8E, SE, BE, DP, DC MHz
Notes
1. Typical program and erase times assume the following conditions: 25°C, VCC = 3.0V; 10,000 cycles; checkerboard data pattern
2. Under worst-case conditions of 85°C; VCC = 2.7V; 100,000 cycles.
3. Acceleration mode (9V ACC) only in Program mode, not Erase.
4. Only applicable as a constraint for WRR instruction when SRWD is set to a 1.
5. tWH + tWL must be less than or equal to 1/fC.
18.1 Capacitance
Symbol Parameter Test Conditions Min Typ Max Unit
Input Capacitance
CIN VOUT = 0V 9.0 12.0 pF
(applies to SCK, PO7-PO0, SI, CS#)
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
3. For more information on pin capacitance, please consult the IBIS models.
Hi-Z
SO
CS#
tWH
SCK
tV tWL
tV tDIS
tHO tHO
SO LSB OUT
CS#
SCK
tCHHH
SO
SI
HOLD#
Figure 18.5 Write Protect Setup and Hold Timing during WRR when SRWD = 1
W#
tWPS tWPH
CS#
SCK
SI
SO Hi-Z
Note:
1. Each write command to a non-volatile register causes a PE cycle on the entire non-volatile register array. OTP bits and registers internally reside in a separate array
that is not cycled.
Contact Cypress Sales and FAE for further information on the data integrity. An application note is available at
http://www.cypress.com/appnotes.
0.20 C A-B
0.25 M C A-B D
0.10 C
0.10 C
DIMENSIONS NOTES:
SYMBOL
MIN. NOM. MAX. 1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994.
A 2.35 - 2.65
3. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
A1 0.10 - 0.30 MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm PER
END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.
A2 2.05 - 2.55 INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 mm PER SIDE.
D AND E1 DIMENSIONS ARE DETERMINED AT DATUM H.
b 0.31 - 0.51
4. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. DIMENSIONS
b1 0.27 - 0.48 D AND E1 ARE DETERMINED AT THE OUTMOST EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD
c 0.20 - 0.33 FLASH, BUT INCLUSIVE OF ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF
THE PLASTIC BODY.
c1 0.20 - 0.30 5. DATUMS A AND B TO BE DETERMINED AT DATUM H.
D 10.30 BSC 6. "N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR THE SPECIFIED
PACKAGE LENGTH.
E 10.30 BSC 7. THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 TO
0.25 mm FROM THE LEAD TIP.
E1 7.50 BSC
8. DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR
e 1.27 BSC PROTRUSION SHALL BE 0.10 mm TOTAL IN EXCESS OF THE "b" DIMENSION AT
h 0.25 - 0.75
0 0° - 8°
01 5° - 15°
02 0° - -
CYPRESS
Company Confidential
TITLE
PACKAGE OUTLINE, 16 LEAD SOIC
DRAWN BY DATE 10.30X7.50X2.65 MM SO3016/SL3016/SS3016
THIS DRAWING CONTAINS INFORMATION WHICH IS THE PROPRIETARY PROPERTY OF CYPRESS
KOTA 24-OCT-16 SPEC NO. REV
PACKAGE
SEMICONDUCTOR CORPORATION. THIS DRAWING IS RECEIVED IN CONFIDENCE AND ITS CONTENTS
CODE(S) SO3016 SL3016 SS3016 APPROVED BY DATE
002-15547 *A
MAY NOT BE DISCLOSED WITHOUT WRITTEN CONSENT OF CYPRESS SEMICONDUCTOR CORPORATION.
BESY 24-OCT-16 SCALE : TO FIT SHEET 1 OF 2
CYPRESS
Company Confidential
TITLE PACKAGE OUTLINE, 8 LEAD DFN
DRAWN BY DATE
6.0X8.0X0.8 MM WNF008 4.8X5.8 MM EPAD (SAWN)
THIS DRAWING CONTAINS INFORMATION WHICH IS THE PROPRIETARY PROPERTY OF CYPRESS
KOTA 23-FEB-17 SPEC NO. REV
PACKAGE
SEMICONDUCTOR CORPORATION. THIS DRAWING IS RECEIVED IN CONFIDENCE AND ITS CONTENTS
CODE(S) WNF008 APPROVED BY DATE
002-18902 **
MAY NOT BE DISCLOSED WITHOUT WRITTEN CONSENT OF CYPRESS SEMICONDUCTOR CORPORATION.
LKSU 23-FEB-17 SCALE : TO FIT SHEET 1 OF 2
D1 4.00 BSC 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
E1 4.00 BSC SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
MD 5 N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME.
ME 5
6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE
N 24
PARALLEL TO DATUM C.
b 0.35 0.40 0.45
eE 1.00 BSC 7 "SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE
eD 1.00 BSC POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
SD 0.00 BSC WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" OR "SE" = 0.
SE 0.00 BSC
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" = eD/2 AND
"SE" = eE/2.
CYPRESS
Company Confidential
TITLE
PACKAGE OUTLINE, 24 BALL FBGA
DRAWN BY DATE 8.0X6.0X1.2 MM FAB024
THIS DRAWING CONTAINS INFORMATION WHICH IS THE PROPRIETARY PROPERTY OF CYPRESS
KOTA 18-JUL-16 SPEC NO. REV
PACKAGE
SEMICONDUCTOR CORPORATION. THIS DRAWING IS RECEIVED IN CONFIDENCE AND ITS CONTENTS
CODE(S) FAB024 APPROVED BY DATE
002-15534 **
MAY NOT BE DISCLOSED WITHOUT WRITTEN CONSENT OF CYPRESS SEMICONDUCTOR CORPORATION.
BESY 18-JUL-16 SCALE : TO FIT SHEET 1 OF 2
E1 3.00 BSC SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
MD 6 N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME.
ME 4 6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE
N 24
PARALLEL TO DATUM C.
b 0.35 0.40 0.45
7 "SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE
eE 1.00 BSC
eD POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
1.00 BSC
SD 0.50 BSC WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" OR "SE" = 0.
SE 0.50 BSC WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, "SD" = eD/2 AND
"SE" = eE/2.
CYPRESS
Company Confidential
TITLE
PACKAGE OUTLINE, 24 BALL FBGA
DRAWN BY DATE 8.0X6.0X1.2 MM FAC024
THIS DRAWING CONTAINS INFORMATION WHICH IS THE PROPRIETARY PROPERTY OF CYPRESS
KOTA 18-JUL-16 SPEC NO. REV
PACKAGE
SEMICONDUCTOR CORPORATION. THIS DRAWING IS RECEIVED IN CONFIDENCE AND ITS CONTENTS
CODE(S) FAC024 APPROVED BY DATE
002-15535 **
MAY NOT BE DISCLOSED WITHOUT WRITTEN CONSENT OF CYPRESS SEMICONDUCTOR CORPORATION.
BESY 18-JUL-16 SCALE : TO FIT SHEET 1 OF 2
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