HW

SW

Hardware/Software Codesign
EEE G626

Dr. A. Amalin Prince

BITS - Pilani K.K. Birla Goa Campus
Department of Electrical and Electronics Engineering

‹#›
 HW

SW

Lecture – 4
Xilinx vivado: Overview, Lab1, Lab2

EEE G626 2
 VIVADO DESIGN SUITE
DSP Design Software Development Hardware Design VIVADO HLS
VIVADO IP INTEGRATOR C Functional Verification
System Generator for DSP Software Development Kit (SDK)
DSP Specific IP Zynq and Embedded Specific IP

HW/SW Co-Verification &

C/RTL Cosimulation
Debugging

Power
Estimation
On-Chip Debug STA
XPower Analyzer Vivado Logic Analyzer
Timing Analyzer
& Virtual I/O

RTL Design I/O Planning Functional Verification RTL Synthesis Floorplanning Place & Route Power Analysis

Vivado Flow Vivado I/O Pin Vivado Simulator / Vivado Synthesis Vivado Vivado Xpower Analyzer
Navigator Planning 3rd Party Simulator Implementation Implementation
Introduction to Embedded System
Design using Zynq

Zynq
Vivado 2014.2 Version

This material exempt per Department of Commerce license exception TSU © Copyright 2014 Xilinx
Objectives

After completing this module, you will be able to:

– Define a Zynq All Programmable SoC (AP SoC) processor component
– Enumerate the key aspects of the Zynq AP SoC processing system
– Describe the embedded design flow
– Understand the function of the IP Integrator tool
– Indicate how the hardware design is linked to the software development environment

Embedded Overview 11-5 © Copyright 2014 Xilinx

Outline

Embedded Processor Component

Overview of Vivado for Embedded System Design
Embedded System Development Flow
Hardware Platform Creation
SDK Software Platform
Summary

Embedded Overview 11-6 © Copyright 2014 Xilinx

Embedded Design Architecture in Zynq

Embedded design with Zynq is based on:

– Processor and peripherals
• Dual ARM® Cortex™ -A9 processors of Zynq-7000 AP SoC
• AXI interconnect
• AXI component peripherals
• Reset, clocking, debug ports
– Software platform for processing system
• Bare Metal Applications or OS’s (e.g. Linux, FreeRTOS)
• C language support
• Processor services
• C drivers for hardware
– User application
• Interrupt service routines (optional)

Embedded Overview 11-7 © Copyright 2014 Xilinx

The PS and the PL

The Zynq-7000 AP SoC architecture consists of two major sections

– PS: Processing system
• Dual ARM Cortex-A9 processor based
• Multiple peripherals
• Hard silicon core
– PL: Programmable logic
• Uses the same 7 series programmable logic
 Artix™-based devices: Z-7010, Z-7015 and Z-7020 (high-range I/O banks only)
 Kintex™-based devices: Z-7030, Z-7045, and Z-7100 (mix of high-range and high-performance I/O
banks)

Embedded Overview 11-8 © Copyright 2014 Xilinx

PS Components

The Zynq AP SoC processing system

consists of the following blocks
– Application processing unit (APU)
– I/O peripherals (IOP)
• Multiplexed I/O (MIO), extended multiplexed
I/O (EMIO)
– Memory interfaces
– PS interconnect
– DMA
– Timers
• Public and private
– General interrupt controller (GIC)
– On-chip memory (OCM): ROM and RAM
– Debug controller: CoreSight

Embedded Overview 11-9 © Copyright 2014 Xilinx

Zynq Architecture Built-in Peripherals

Two USB 2.0 OTG/Device/Host

Two Tri- Mode GigE (10/100/1000)
Two SD/SDIO interfaces
– Memory, I/O and combo cards
Two CAN 2.0Bs, SPIs , I2Cs, UARTs
Four GPIO 32bit Blocks
– 54 available through MIO; other available through EMIO
Multiplexed Input/Output (MIO)
– Multiplexed pinout of peripherals and static memories
Extended MIO
– Maps PS peripheral ports to the PL

Embedded Overview 11-10 © Copyright 2014 Xilinx

Outline

Embedded Processor Component

Overview of Vivado for Embedded Design
Embedded System Development Flow
Hardware Platform Creation
SDK Software Platform
Summary

Embedded Overview 11-11 © Copyright 2014 Xilinx

Vivado

What are Vivado, IP Integrator and SDK?

– Vivado is the tool suite for Xilinx FPGA design and includes capability for embedded system design
• IP Integrator, is part of Vivado and allows system level design of the hardware part of an Embedded system
• Integrated into Vivado
• Vivado includes all the tools, IP, and documentation that are required for designing systems with the Zynq-7000
AP SoC hard core and/or Xilinx MicroBlaze soft core processor
• Vivado + IPI replaces ISE/EDK
– SDK is an Eclipse-based software design environment
• Enables the integration of hardware and software components
• Links from Vivado

Vivado is the overall project manager and is used for developing non-embedded
hardware and instantiating embedded systems
– Vivado/IP Integrator flow is recommended for developing Zynq embedded systems using 2013.2 and
later

Embedded Overview 11-12 © Copyright 2014 Xilinx

Vivado Components

Vivado/IP Integrator Software Development Kit (SDK)

– Design environment for configuration of – Project workspace
PS, and hardware design for PL – Hardware platform definition
– Hardware Platform (xml) – Board Support Package (BSP)
– Platform, software, and peripheral – Software application
simulation – Software debugging
– Vivado logic analyzer integration

HW/SW Simulation

Hardware Software
Design Design

HW/SW Debug

Embedded Overview 11-13 © Copyright 2014 Xilinx

Embedded System Tools: Hardware

Hardware and software development tools

– IP Integrator
– IP Packager
– Hardware netlist generation
– Simulation model generation
– Xilinx Microprocessor Debugger (XMD)
– Hardware debugging using Vivado analyzer

Embedded Overview 11-14 © Copyright 2014 Xilinx

Embedded System Tools: Software

Eclipse IDE-based Software Development Kit (SDK)

– Board support package creation
– GNU software development tools
– C/C++ compiler for the MicroBlaze and ARM Cortex-A9 processors (gcc)
– Debugger for the MicroBlaze and ARM Cortex-A9 processors (gdb)
– TCF framework – multicore debug
Board support packages (BSPs)
– Stand-alone BSP
• Free basic device drivers and utilities from Xilinx
• NOT an RTOS

Embedded Overview 11-15 © Copyright 2014 Xilinx

Vivado View
D

A
Customizable panels

B E
A: Project Management
B: IP Integrator
C
C: FPGA Flow
D: Layout Selection
E: Project view/Preview Panel
F: Console, Messages, Logs

Embedded Overview 11-16 © Copyright 2014 Xilinx

Zynq Customization Processing System

Block Configuration
PS-PL Interface
Configuration
MIO Configuration/Table
View
Clock Configuration
DDR
SMC Timing Calculation
Interrupt Configuration

Embedded Overview 11-17 © Copyright 2014 Xilinx

MIO Configuration

Embedded Overview 11-18 © Copyright 2014 Xilinx

MIO Configuration…

Embedded Overview 11-19 © Copyright 2014 Xilinx

Project Files

Top level Directory

– .xpr Vivado Project File (xml file), log files, journal
.srcs
– Project source files, IP Integrator files
.data
– Vivado database, internal data
.runs
– Synthesis, Implementation runs
.sdk
– SDK Export directory, Hardware Platform (xml)
.cache
– Temporary Files

Embedded Overview 11-20 © Copyright 2014 Xilinx

Outline

Embedded Processor Component

Overview of Vivado
Embedded System Development Flow
Hardware Platform Creation
SDK Software Platform
Summary

Embedded Overview 11-21 © Copyright 2014 Xilinx

Embedded System Design Flow for Zynq-7000 AP SoC

Embedded Overview 11-22 © Copyright 2014 Xilinx

Embedded System Design using Vivado

Create a new Vivado project, or open an existing project

Invoke IP Integrator
Construct(modify) the hardware portion of the embedded design
Create (Update) top level HDL wrapper
[optional] Synthesize any non-embedded components and implement in Vivado
Export the hardware description, and launch SDK
Create a new software board support package and application projects in the SDK
Compile the software with the GNU cross-compiler in SDK
[optional] Download the programmable logic’s completed bitstream using iMPACT
[optional] Use SDK to download the program (the ELF file)

Embedded Overview 11-23 © Copyright 2014 Xilinx

Embedded System Design using Vivado

1. Launch Vivado

2. Invoke IP Integrator to
3. Configure PS settings create Block Diagram
4. Add IP & configure 5. Generate Top-Level HDL 9. Specify hardware
(close Block Diagram, 6. Add Constraints description from Vivado
return to Vivado) 7. Generate Bitstream => .bit 10. Add Software
8. Export hardware to SDK Project & Build => .elf
Hardware Configuration
IP Integrator

Vivado SDK
11. Program bitstream & .elf into Zynq

ZYBO

Vivado Overview 11-24 © Copyright 2014 Xilinx

Add IP Integrator Block Diagram

IP Integrator Block Diagram opens a

blank canvas
IP can be added from the IP catalog
Drag and drop interface
Intelligent Design environment
– Design Assistance
– Connection automation
– Highlights valid connections
– Group, create hierarchal blocks
Can create and import custom IP using
IP Packager

Embedded Overview 11-25 © Copyright 2014 Xilinx

Configuring Hardware in IP Integrator

Double click blocks to access

configuration options
Drag pointer to make connections
– Highlights valid connections
Connection Automation
– Automatically connect recognised
interfaces
Automatically Redraw system

Embedded Overview 11-26 © Copyright 2014 Xilinx

Exporting to SDK

Software development is performed

with the Xilinx Software Development
Kit tool (SDK)
– Hardware configuration in Vivado
An XML description of the hardware is
exported to SDK
– The hardware platform is built on this
description
– Only one hardware platform for each SDK
project
– (Optionally export bitstream)
The SDK tool will then associate user
software projects to hardware

Embedded Overview 11-27 © Copyright 2014 Xilinx

Software Development Flow

Create hardware platform project

– Automatically performed when SDK tool is
launched from Vivado project
Create BSP
– System software, board support package
Create software application
Create linker script
Build project
– compile, assemble, link output file
<app_project>.elf

Embedded Overview 11-28 © Copyright 2014 Xilinx

Configuring FPGA and Downloading Application

Download the bitstream

– Only if PL is used
– Input file <top_name>.bit
The Vivado Hardware Manager (or Xilinx iMPACT tool) download the bitstream to the
target
The bitstream can be downloaded from either
– Vivado
– SDK
Requires that the download cable is connected

Embedded Overview 11-29 © Copyright 2014 Xilinx

Outline

Embedded Processor Component

Overview of Vivado
Embedded System Development Flow
Hardware Platform
SDK Software Platform
Summary

Embedded Overview 11-30 © Copyright 2014 Xilinx

Zynq Configuration GUI

Provides a graphical view of the PS to

configure
– ARM cores
– I/O peripherals
– DDR controller
– Memory systems
I/O partitioning between dedicated PS
pins and programmable logic I/O
Zynq-7000 AP SoC PS is configured via
a set of memory-mapped configuration
registers

Embedded Overview 11-31 © Copyright 2014 Xilinx

Clock configuration

Clock Configuration
– Input frequency can be set
• Processor, DDR
– All IOP clock frequencies can be set
– Clock to PL configuration
– Set Timers

Embedded Overview 11-32 © Copyright 2014 Xilinx

Project Settings

Accessed from flow navigator

Default settings are typically used
Set/change target device
– Architecture, Device size, Package, Speed
grade
Simulation, Synthesis, Implementation,
Bitstream options
IP repository directory
– Provide path to custom IP not present in
the current project directory structure

Embedded Overview 11-33 © Copyright 2014 Xilinx

Outline

Embedded Processor Component

Overview of Vivado
Embedded System Development Flow
Hardware Platform Creation
SDK Software Platform
Summary

Embedded Overview 11-34 © Copyright 2014 Xilinx

Software Development Kit (SDK)

Full-featured software design environment

Separate tool from Vivado – can install standalone for SW teams
Based on popular Eclipse open-source IDE
Used for software applications only; hardware design and modifications are done in
Vivado
Well-integrated environment for seamless debugging of embedded targets
Sophisticated software design environment with many options and features with
support for
– Multiple processors
– Multiple software platforms
– Multiple software applications
Fully Featured C/C++ code editor and error navigator

Embedded Overview 11-35 © Copyright 2014 Xilinx

SDK Workbench Views

1. C/C++ project outline displays the

elements of a project with file
decorators (icons) for easy
identification
2. C/C++ editor for integrated software
creation
3. Code outline displays elements of
the software file under development
with file decorators (icons) for easy
identification
4. Problems, Console, Properties views
list output information associated
with the software development flow

Embedded Overview 11-36 © Copyright 2014 Xilinx

Software Management Settings

Software is managed in three major

areas
– Compiler/Linker Options
• Application program
– Software Platform Settings
• Board support package
– Linker Script Generation
• Assigning software to memory resources
Covered in more detail later

Embedded Overview 11-37 © Copyright 2014 Xilinx

Outline

Embedded Processor Component

Overview of Vivado
Embedded System Development Flow
Hardware Platform Creation
SDK Software Platform
Summary

Embedded Overview 11-38 © Copyright 2014 Xilinx

Summary

Vivado includes all the tools, documentation, and IP necessary for building embedded
systems
IPI is a System Level design tool that increases productivity, allowing designs to be
completed faster
The Software Development Kit (SDK) is a comprehensive software development
environment for software applications
An embedded processing system component is built with IP provided in the IP Catalog.
Designers can also add their own custom IP to this catalog
The PS Configuration wizard permits access to several configurable features of PS

Embedded Overview 11-39 © Copyright 2014 Xilinx

Lab1 Intro
Create a Processor System with Zynq

Zynq
Vivado 2014.2 Version

This material exempt per Department of Commerce license exception TSU © Copyright 2014 Xilinx
ARM Cortex-A9 based Embedded System Design
Lab1 through Lab5

DDR3 PL
Memory Memory
Controller

Timer

RS232 UART

ARM AXI4
Cortex-A9 AXI-BRAM Controller BRAM

AXI4-Lite
AXI LED_IP LED
M_AXI_GP0 Interconnect
Block AXI4-Lite
GPIO Push-Buttons

AXI4-Lite
PS GPIO DIP Switches

Lab1 Lab2 Lab3 Lab5

Lab4 uses hardware built in Lab3
Lab1 Intro 11a- 41 © Copyright 2014 Xilinx
Introduction

This lab guides you through the process of using Vivado and IP Integrator to create a
simple ARM Cortex-A9 based processor system
Targeting the Zedboard or ZYBO board.
– Very similar steps, differences pointed out in the instructions
– Follow the instructions for the board you are using
You will use Vivado to create the system and generate a software application from one
of the standard project templates in SDK to verify the hardware functionality

Lab1 Intro 11a- 42 © Copyright 2014 Xilinx

ARM Cortex-A9 based Embedded System Design
Lab1: Use Vivado to Create a System

DDR3
Memory Memory
Controller

RS232 UART

ARM
Cortex-A9

PS

Lab1 Intro 11a- 43 © Copyright 2014 Xilinx

Procedure

Create a project using Vivado

Invoke IP Integrator from Vivado and build basic system
Generate top-level HDL in Vivado and Export to SDK
Generate a simple memory test application in SDK
Verify the functionality in hardware

Lab1 Intro 11a- 44 © Copyright 2014 Xilinx

Summary

Vivado software allows creating or adding an embedded processor source and invoking
IP Integrator.
A block diagram, representing the hardware design, provides hardware system
parameters information.
After the system has been defined and configured, the hardware can be exported and
SDK can be invoked from Vivado.
Software development is done in SDK which provides several application templates
including memory tests.
You verified the hardware operation by downloading the test application, executing on
the processor, and observing the output in the serial terminal window.

Lab1 Intro 11a- 45 © Copyright 2014 Xilinx

Lab2 Intro
Adding IP in PL

Zynq
Vivado 2014.2 Version

This material exempt per Department of Commerce license exception TSU © Copyright 2014 Xilinx
Introduction

This lab guides you through the process of extending the processing system you
created in the previous lab by adding two GPIO IPs in PL

Lab2 Intro 13a- 47 © Copyright 2014 Xilinx

ARM Cortex-A9 based Embedded System Design
Lab2: Adding IPs in PL

DDR3 PL
Memory Memory
Controller

RS232 UART

ARM
Cortex-A9

AXI
M_AXI_GP0 Interconnect
Block AXI4-Lite
GPIO Push-Buttons

AXI4-Lite
PS GPIO DIP Switches

Lab2 Intro 13a- 48 © Copyright 2014 Xilinx

Procedure

Open the project in Vivado

Add and configure GPIO peripherals in the system in the IP Integrator
Add external ports
Generate the bitstream and export to SDK
Create a TestApp application in SDK
Verify the functionality in hardware

Lab2 Intro 13a- 49 © Copyright 2014 Xilinx

Summary

The GP Master interface of the PS was enabled. GPIO peripherals were added from the
IP catalog and connected to the Processing System through the 32b Master GP
interface.
The peripherals were configured and external FPGA connections were established. Pin
location constraints were made using IP Integrator Automation, and also manually, to
connect the peripherals to push buttons and DIP switches.
A TestApp application project was created and the functionality was verified after
downloading the bitstream and executing the program.

Lab2 Intro 13a- 50 © Copyright 2014 Xilinx

 HW

The End SW

 Questions ?

 Thank you for your attention

EEE G626 51