Nec 78k0 Kb2

Preliminary Product Information
MOS Integrated Circuit
78K0/KB2
8-BIT SINGLE-CHIP MICROCONTROLLER
The 78K0/KB2 products are 8-bit single-chip microcontrollers of the 78K0 series.
These microcontrollers feature Single-voltage Self-programming Flash memory and many peripherals.
FEATURES
• 78K0 CPU core, 8-bit CISC architecture
• Flash EEPROM and RAM sizes
Item Program memory Data memory
Product name (Flash ROM) (RAM)
µPD78F0503 32K bytes (Flash) 1K bytes
µPD78F0502 24K bytes (Flash) 1K bytes
µPD78F0501 16K bytes (Flash) 768 bytes
µPD78F0500 8K bytes (Flash) 512 byte
Minimum instruction cycle • AD CONVERTER

0.1µs ([email protected] to 5.5V) - 10-bit resolution A/D converter 4 ch
0.2µs ([email protected] to 5.5V) • I/O PORT
0.4µs ( [email protected] to 5.5V) Total : 23
Clock CMOS I/O : 21
• MAIN CLOCK N-ch O.D I/O: 2
- Internal Ring-oscillator 8MHz (Typ.) • Other
- Ceramic/Crystal Oscillator/External CLK (2MHz to 20MHz) - Self programming
(Instruction execution time = 100ns(min.) @20MHz) - On-chip debug function (product name undecided)
Interrupt
• WDT CLOCK
- Internal 16ch
- Internal Ring-oscillator 240KHz (Typ.)
- External 6ch
Peripherals.
Operation Voltage
• On-Chip Power-On-Clear (POC) Circuit
1.8V to 5.5V
• Low-Voltage Detector (LVI) Circuit
Package
• Timer
30-pin SSOP (7.62mm(300))
- 16bit Timer 1ch
- 8bit Timer 4ch
- Watchdog Timer (Operable with 240KHz Ring-OSC)
• Serial Interface
- UART/CSI 1ch
- UART (with LIN-bus) 1ch
- IIC 1ch
This information contained in this document is being issued in advance of the production cycle for the product. The
parameters for the product may change before final production or NEC Electronics Corporation, at its own discretion,,
may withdraw the product prior to its production. Not all products and/ or types are available in every country. Please
check with an NEC Electronics sales representative for availability and additional information.
ZUD-CC-04-0125-E
Data Published Oct 2004 N CP(K) ©NEC Electronics Corporation 2004
78K0/KB2
1. Block Diagram
Fig. 78K0/KB2
Port0 P00 -P01

TI000
TI010 16bit Timer
(TM00)
TO00
Port1 P10 -P17
8bit Timer
TOH0
(TMH0) Port2 P20 -P23
8bit Timer
TOH1
(TMH1) Port3 P30 -P33
TO50 8bit Timer

TI50 (TM50) Port6 P60 -P61
78K0
TO51 8bit Timer CPU CORE
Port12 P120 -P122
TI51 (TM51)
SCL0 Multi master

SDA0 IIC
(IIC0)
RxD6 Flash
UART-LIN RAM EEPROM
TxD6 (UART6)
RxD0 UART
TxD0 (UART0)
Watchdog
SI10 Timer
3wire
SO10 Serial I/F
SCK10 (CSI10) Reset CTL
RESET
Power On
ANI0 - FLMD0
Clear
ANI3 System
10bit AD (POC) REGC
Control
AVREF converter
AVSS VDD
VSS
Low voltage
EXLVI Indicator Internal High-speed High-speed system X1
(LVI) Ring-OSC clock OSC
(8MHz typ.) X2/ EXCLK
INTP0 - External Internal Low-speed

INTP5 Interrupt Ring-OSC
(240kHz typ.)
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2. Pin Lay Out

78K0/KB2
30-pin plastic SSOP (7.62mm(300))
µPD78F0500MC-5A4, µPD78F0501MC-5A4
µPD78F0502MC-5A4, µPD78F0503MC-5A4
P21/ANI1 1 30 P22/ANI2
P20/ANI0 2 29 P23/ANI3
P01/TI010/TO00 3 28 AVSS
P00/TI000 4 27 AVREF
P120/INTP0/EXLVI 5 26 P10/SCK10/TXD0
RESET 6 25 P11/SI10/RXD0
IC/FLMD0 7 24 P12/SO10
P122/X2/EXCLK 8 30pin SSOP 23 P13/TXD6
P121/X1 9 22 P14/RXD6
REGC 10 21 P15/TOH0
VSS 11 20 P16/TOH1/INTP5
VDD 12 19 P17/TI50/TO50
P60/SCL0 13 18 P30/INTP1
P61/SDA0 14 17 P31/INTP2
P33/TI51/TO51/INTP4 15 16 P32/INTP3
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3. Pin Function
Table (1/2)
PIN NAME Function
VDD Positive power supply except for ports (except P20-P23) and AD converter
VSS Ground potential except for ports (except P20-P23) and AD converter
RESET System reset input
FLMD0 Flash EEPROM programming mode setting
REGC Connecting regulator output stabilization capacitor. Connect to GND via a
capacitor (0.47µF)
AVREF A/D converter analog power supply and power supply for P20-P23
AVSS Ground potential for A/D converter and P20 - P23.
P00 I/O port
/TI000 External count clock input to 16-bit timer/event counter 00
Capture trigger input to capture registers (CR000, CR010) of16-bit
timer/event counter 00 (TM00)
P01 I/O port
/TI010 Capture trigger input to capture register (CR000) of 16-bit timer/event
/TO00 counter 00 (TM00)
16-bit timer/event counter 00 output (TM00)
P10 I/O port
/SCK10 Clock input/ output for serial interface (CSI10)
/TXD0 Serial data output from asynchronous serial interface (UART0)
P11 I/O port
/SI10 Serial data input to serial interface (CSI10)
/RXD0 Serial data input to asynchronous serial interface (UART0)
P12 I/O port
/SO10 Serial data output form serial interface (CSI10)
P13 I/O port
/TXD6 Serial data output from asynchronous serial interface (UART6)
P14 I/O port
/RXD6 Serial data input to asynchronous serial interface (UART6)
P15 I/O port
/TOH0 8-bit timer H0 output (TMH0)
P16 I/O port
/TOH1 8-bit timer H1 output (TMH1)
/INTP5 External interrupt request input with specifiable valid edges
P17 I/O port
/TI50 External count clock input to 8-bit timer/event counter 50 (TM50)
/TO50 8-bit timer/event counter 50 output (TM50)
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Table(2/2)
PIN NAME Function
P20- P23 I/O ports
/ ANI0- ANI3 A/D converter analog input
P30/INTP1 I/O port
P31/INTP2 External interrupt request input with specifiable valid edges
P32/INTP3
P33 I/O port
/TI51 External count clock input to 8-bit timer/event counter 51(TM51)
/TO51 8-bit timer/event counter 51output (TM51)
P60 I/O port (N-ch Open drain)
/SCL0 Clock input/ output for serial interface (IIC0)
P61 I/O port (N-ch Open drain)
/SDA0 Serial data input/ output for serial interface (IIC0)
P120 I/O port
/EXLVI Reference voltage input for Low voltage Indicator
P121 I/O port (An external oscillation circuit is not used)
/X1 Connecting resonator for main system clock oscillation
P122 I/O port (An external oscillation circuit is not used)
/X2 Connecting resonator for main system clock oscillation
/EXCLK External clock input for main system clock
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4. Memory space
78K0/KB2 have 64kB linear address area.
Common ROM Bank ROM

Products ROM size Number of
Address Address
Bank
0000H-7FFFH
µPD78F0503 32KB - -
(32KB)
0000H-5FFFH
µPD78F0502 24KB - -
(24KB)
0000H-3FFFH
µPD78F0501 16KB - -
(16KB)
0000H-1FFFH
µPD78F0500 8KB - -
(8KB)
5. Clock
78K0/KB2 have 2 type internal Ring-OSC and 2 type external resonator oscillation circuit.
78K0/KB2 can be operated high-speed internal Ring-OSC only. Low-speed Ring-OSC can connect to
Watch dog timer and 8bit timer (TMH1) only for high secure.
Fig. Clock connecting block image
Low-speed
Ring-OSC Watchdog timer
(240kHz typ)
8bit timer (TMH1)
High-speed
Ring-OSC
(8MHz typ)
MPX CPU
High-speed
External resonator system clock
or oscillation circuit
External clock
(2-20MHz)
MPX Peripheral
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6. Outline of Functions of KB2
µ PD78F0500 µ PD78F0501 µ PD78F0502 µ PD78F0503

Internal Flash Memory 8K 16K 24K 32 K
Memory
(Byte) Bank - - - -
High Speed RAM 512 768 1K

Extend RAM -
Main System Ceramic/Crystal - 2 to 20 MHz: VDD = 4.0 to 5.5 V
Clock - 2 to 10 MHz: VDD = 2.7 to 5.5 V
- 2 to 5 MHz: VDD = 1.8 to 5.5 V
Internal Ring-OSC - 8 MHz(TYP.)
Sub System Clock -
Internal Low Speed Ring-OSC - 240 kHz(TYP.)

(For TMH1, WDT)
Minimum Instruction Cycle - 0.1 µ s (Ceramic/ Crystal Operation fXH = 20 MHz VDD = 4.0 to 5.5 V)
I/O Total :23
- CMOS I/O :21
- N-ch O.D. :2
Timer - 16 Bit Timer/Event Counter:1ch

- 8 Bit Timer/Event Counter:2ch
- 8 bit Timer:2ch
- Watch Dog Timer:1ch
Timer Output -5(PWM:3)
PCL output -
Buzzer Output -
A/D Converter - 10bit x 4ch
Serial Interface - UART (with LIN-bus):1ch
- CSI/ UART:1ch
2
- I C:1ch
Multiplier/Divider
-
Interrupt Internal 16
External 6
Key Return -
On Chip Debug Function Product name undecided
Voltage Range VDD = 1.8 to 5.5 V
Operation temperature Ta = -40°C to +85°C
Package - 30pin SSOP(7.62mm(300))
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7. Electrical specification of KB2 (Target)
Caution These specifications show target values, which may change after device evaluation. The operating
voltage range may also change.
Absolute Maximum Ratings(TA = 25°C) (1/2)

Parameter Symbol Conditions Ratings Unit
Supply voltage VDD -0.5 to +6.5 V

VSS -0.5 to +0.3 V
AVREF -0.5 to +6.5 V
AVSS -0.5 to +0.3 V
Note
Input voltage VI1 -0.3 to VDD+0.3 V
VI2 P60-P61(N-ch open drain) -0.3 to +6.5 V
Note
Output voltage VO -0.3 to VDD+0.3 V
Note
Analog input voltage VAN -0.3 to AVREF+0.3 V
Output current, high IOH Per pin -10 mA
Total of P00-P01, P120-P122 -25 mA
all pins P10-P17,P30-P33, -55 mA
-80 mA P60-P61
Note Must be 6.5 V or lower.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the
product is on the verge of suffering physical damage, and therefore the product must be
used under conditions that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as
those of port pins.
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Absolute Maximum Ratings(TA = 25°C) (2/2)

Parameter Symbol Conditions Ratings Unit
Output current, low IOL Per pin 30 mA

Total of all P00-P01, P120-P122 60 mA
pins P10-P17,P30-P33, 140 mA
200 mA P60-P61
Operating TA In normal operation mode -40 to +85 °C
Ambient temperature In flash memory programming mode
Storage temperature Tstg -65 to +150 °C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the
product is on the verge of suffering physical damage, and therefore the product must be
used under conditions that ensure that the absolute maximum ratings are not exceeded.
those of port pins.
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78K0/KB2
High-Speed System Clock (Crystal/Ceramic) Oscillator Characteristics

(TA = -40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, 2.3 V ≤ AVREF ≤ VDD, VSS = AVSS = 0 V)
Resonator Recommended Parameter Conditions MIN. TYP. MAX. Unit
Circuit
Ceramic VSS X1 X2 Oscillation 4.0 V ≤ VDD ≤ 5.5 V 2.0 20.0 MHz

Note
resonator frequency(fXH) 2.7 V ≤ VDD < 4.0 V 2.0 10.0
1.8 V ≤ VDD < 2.7 V 2.0 5.0
C1 C2
Crystal resonator Oscillation 4.0 V ≤ VDD ≤ 5.5 V 2.0 20.0 MHz

VSS X1 X2 Note
frequency(fXH) 2.7 V ≤ VDD < 4.0 V 2.0 10.0
1.8 V ≤ VDD < 2.7 V 2.0 5.0
C1 C2
Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution
time.
Cautions 1. When using the high-speed system clock oscillator, wire as follows in the area enclosed
by the broken lines in the above figures to avoid an adverse effect from wiring
capacitance.
• Keep the wiring length as short as possible.

• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. Since the CPU is started by the Ring-OSC after reset is released, check the oscillation
stabilization time of the high-speed system clock using the oscillation stabilization time
status register (OSTC). Determine the oscillation stabilization time of the OSTC
register and oscillation stabilization time select register (OSTS) after sufficiently
evaluating the oscillation stabilization time with the resonator to be used.
Remark For the resonator selection and oscillator constant, customers are requested to either
evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
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Ring-OSC Oscillator Characteristics

Resonator Parameter Conditions MIN. TYP. MAX. Unit
8 MHz Ring-OSC oscillator High-speed Ring-OSC 2.7 V ≤ VDD ≤ 5.5 V 7.6 Note2
8.0 Note2
8.4 Note2
MHz
Oscillation
1.8 V ≤ VDD ≤ 5.5 V T.B.D 8.0 Note2 T.B.D MHz
frequency(fRH)Note1
240 kHz Ring-OSC oscillator Low-speed Ring-OSC 2.7 V ≤ VDD ≤ 5.5 V 216 240 264 kHz
Oscillation frequency(fRL)
1.8 V ≤ VDD ≤ 5.5 V T.B.D 240 T.B.D
Note 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction
execution time.
2. This is the frequency in the case of RSTS(RCM.7)=1. This is 5 MHz(TYP.) in the case of
RSTS=0.
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DC Characteristics (1/4)
(TA = -40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Output current, high IOH1 Per pin of P00-P01, P10-P17, 4.0V ≤ VDD ≤ 5.5V -3.0 mA
P30-P33, P120 2.7 V ≤ VDD < 4.0V -2.5
1.8 V ≤ VDD < 2.7V -1.0
Total of P00-P01, P120 4.0V ≤ VDD ≤ 5.5V -20.0 mA
2.7 V ≤ VDD < 4.0V -10.0
1.8 V ≤ VDD < 2.7V -5.0
Total of P10-P17, P30-P33 4.0V ≤ VDD ≤ 5.5V -30.0 mA
2.7 V ≤ VDD < 4.0V -19.0
1.8 V ≤ VDD < 2.7V -10.0
Total of all pins 4.0V ≤ VDD ≤ 5.5V -50.0 mA
2.7 V ≤ VDD < 4.0V -29.0
1.8 V ≤ VDD < 2.7V -15.0
IOH2 Per pin of P20-P23,P121-P122 Note
1.8V ≤ VDD ≤ 5.5V -100 µA
Output current, low IOL1 Per pin of P00-P01, P10-P17, 4.0V ≤ VDD ≤ 5.5V 8.5 mA
P30-P33, P120 2.7 V ≤ VDD < 4.0V 5.0
1.8 V ≤ VDD < 2.7V 2.0

Per pin of P60-P61 4.0V ≤ VDD ≤ 5.5V 15.0 mA
2.7 V ≤ VDD < 4.0V 5.0
1.8 V ≤ VDD < 2.7V 2.0
Total of P00-P01, P120 4.0V ≤ VDD ≤ 5.5V 20.0 mA
2.7 V ≤ VDD < 4.0V 15.0
1.8 V ≤ VDD < 2.7V 9.0
Total of P10-P17, P30-P33 4.0V ≤ VDD ≤ 5.5V 45.0 mA
2.7 V ≤ VDD < 4.0V 35.0
1.8 V ≤ VDD < 2.7V 20.0
Total of all pins 4.0V ≤ VDD ≤ 5.5V 65.0 mA
2.7 V ≤ VDD < 4.0V 50.0
1.8 V ≤ VDD < 2.7V 29.0
IOL2 Per pin of P20-P23,P121-P122 Note
1.8V ≤ VDD ≤ 5.5V 400 µA
Note When used as digital input ports, set AVREF = VDD
Caution This specification is Duty = 70% condition of IOH and IOL.

those of port pins.
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Input voltage, high VIH1 P12, P13, P15, P60-P61, P121-P122 0.7VDD VDD V
VIH2 P00, P01, P10-P11, P14, P16-P17, P30-P33, P120, 0.8VDD VDD V
RESET
VIH3 P20-P23 Note 0.7AVREF AVREF V
Input voltage, low VIL1 P12, P13, P15, P60-P61, P121-P122 0 0.3VDD V
VIL2 P00, P01, P10-P11, P14, P16-P17, P30-P33, P120, 0 0.2VDD V

RESET
VIL3 P20-P23 Note 0 0.3AVREF V
Note When used as digital input ports, set AVREF = VDD.
those of port pins.
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Output voltage, high VOH1 IOH = -3.0 mA P00-P01, P10-P17, 4.0V ≤ VDD ≤ 5.5V VDD-0.7 V
P30-P33, P120
IOH = -2.5 mA 2.7 V ≤ VDD ≤ 5.5V VDD-0.5 V
IOH = -1.0 mA 1.8 V ≤ VDD ≤ 5.5V VDD-0.5 V
VOH2 IOH = -100 µA P20-P23 1.8 V ≤ VDD ≤ 5.5 V VDD-0.5 V

AVREF = VDD
Output voltage, low VOL1 IOL = 8.5 mA P00-P01, P10-P17, 4.0V ≤ VDD ≤ 5.5V 0.7 V
P30-P33, P120,
IOL = 1.0 mA 2.7 V ≤ VDD ≤ 5.5V 0.5 V
IOL = 0.5 mA 1.8 V ≤ VDD ≤ 5.5V 0.4 V
VOL2 IOL = 400 µA P20-P23 1.8 V ≤ VDD ≤ 5.5 V 0.4 V

AVREF = VDD
VOL3 IOL = 15.0 mA P60-P61 4.0V ≤ VDD ≤ 5.5V 2.0 V
IOL = 5.0 mA 0.4 V
IOL = 3.0 mA 2.7 V ≤ VDD ≤ 5.5V 0.4 V
IOL = 2.0 mA 1.8 V ≤ VDD ≤ 5.5V 0.4 V

Input leakage ILIH1 VI = VDD P00-P01, P10-P17, P30-P33, 1 µA
P120-P122
current, high
ILIH2 VI = AVREF P20-P23 1 µA
ILIH3 VI = VDD X1, X2 20 µA
(When use External oscillator)
Input leakage ILIL1 VI = VSS P00-P01, P10-P17, P30-P33, -1 µA
current, low P120-P122
ILIL2 VI = AVREF P20-P23 -1 µA

ILIL3 VI = VSS X1, X2 -20 µA
(When use External oscillator)
Pull-up resistance RU VI = VDD 10 20 100 kΩ
value
FLMD0 supply VIL In normal operation mode 0 0.2VDD V
voltage VIH In flash memory programming mode 0.8VDD VDD V
those of port pins.
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Note2
Supply IDD1 Operation mode fXH = 20 MHz , VDD = 5.0 V 4.7 5.8 mA
Note1 Note2 Note3
current fXH = 10 MHz , VDD = 5.0 V 2.5 3.5 mA
Note2 Note3
fXH = 5 MHz , VDD = 3.0 V 1.5 2.2 mA
Note2
fRH = 8 MHz , VDD = 5.0 V 1.9 2.7 mA
Note2
IDD2 HALT mode fXH = 20 MHz , VDD = 5.0 V 2.2 2.6 mA
Note2 Note3
fXH = 10 MHz , VDD = 5.0 V 1.0 1.2 mA
Note2 Note3
fXH = 5 MHz , VDD = 3.0 V 0.55 0.65 mA
Note2
fRH = 8 MHz , VDD = 5.0 V 0.6 0.65 mA
IDD3 STOP mode VDD = 5.0 V 1 20 µA
IADC A/D converter A/D converter operating 0.57 1.3 mA
operating current A/D converter not operating T.B.D. T.B.D. mA
IWDT Watchdog Time 240 kHz Ring-OSC operating 5 10 µA
operating current
ILVI LVI operating 9 T.B.D. µA
current
Notes 1. Total current flowing through the internal power supply (VDD).
2. Input square-wave
3. When AMPH(OSCCTL.0) = 0.
Remark 1. fXH: High-Speed System Clock oscillation frequency (X1 clock oscillation frequency or
External main system clock frequency).
2. fRH: High-speed Ring-OSC oscillation frequency.
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AC Characteristics
(1)Basic operation
Instruction cycle (minimum TCY Main High-speed 4.0 V ≤ VDD ≤5.5 V 0.1 16 µs
instruction execution time) system system 2.7 V ≤ VDD < 4.0 V 0.2 16 µs
clock(fXP) clock(fXH) 1.8 V ≤ VDD < 2.7 V 0.4 16 µs
operation
High-speed 2.7 V ≤ VDD < 5.5 V 0.25 4 µs
Ring-OSC 1.8 V ≤ VDD < 2.7 V 0.5 4 µs
clock(fRH)
External main system clock fEXCLK 4.0 V ≤ VDD ≤ 5.5 V 2.0 20.0 MHz
frequency 2.7 V ≤ VDD < 4.0 V 2.0 10.0 MHz
1.8 V ≤ VDD < 2.7 V 2.0 5.0 MHz
External main system clock tEXCLKH, (1/ fEXCLK ns
input high-/low-level width tEXCLKL x 1/2) - 1
TI000, TI010 input high-level tTIH0, 4.0 V ≤ VDD ≤ 5.5 V 2/fsam + µs
Note1
width, low-level width tTIL0 0.1
2.7 V ≤ VDD < 4.0 V 2/fsam + µs
0.2 Note1
TI50, TI51 input frequency fTI5 4.0 V ≤ VDD ≤ 5.5 V 10 MHz
2.7 V ≤ VDD < 4.0 V 10 MHz
1.8 V ≤ VDD < 2.7 V 5 MHz
TI50, TI51 input high-level tTIH5, 4.0 V ≤ VDD ≤ 5.5 V 50 ns
width, low-level width tTIL5 2.7 V ≤ VDD < 4.0 V 50 ns
1.8 V ≤ VDD < 2.7 V 100 ns

Interrupt input high-level tINTH, 1 µs
width, low-level width tINTL
RESET low-level width tRSL 10 Note2 µs

Notes 1. Selection of fsam = fPRS, fPRS /4, fPRS /256 is possible using bits 0 and 1 (PRM000, PRM001) of
prescaler mode register (PRM00). Note that when selecting the TI000 valid edge as the
count clock, fsam = fPRS.
2. Input low level signal into RESET pin until power supply voltage is stabilized in the case of
the power supply voltage rise time is slowly (more than 3.4ms).
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TCY vs VDD (main system clock operation)

[µs]
Guaranteed
operation range
Supply voltage VDD [V]
Remark The values indicated by the shaded section are only when the High-speed Ring-OSC clock
is selected.
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AC Timing Test Points (Excluding X1 Input)
0.8VDD 0.8VDD
Test points
0.2VDD 0.2VDD
Clock Timing
1/fXP
tXPL tXPH
VIH6 (MIN.)
X1 input
VIL6 (MAX.)
1/fXT
tXTL tXTH
VIH6 (MIN.)
XT1 input
VIL6 (MAX.)
TI Timing
tTIL0 tTIH0
TI00, TI010, TI001, TI011
1/fTI5
tTIL5 tTIH5
TI50, TI51
Interrupt Request Input Timing
tINTL tINTH
INTP0 to INTP75
RESET Input Timing
tRSL
RESET
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(2) Serial interface

(a)UART mode (UART6, dedicated baud rate generator output)

Transfer rate 312.5 kbps
(b) UART mode (UART0, dedicated baud rate generator output)

Transfer rate 312.5 kbps
(c) IIC0 mode

Parameter Symbol Normal mode High speed mode Unit
MIN. . MAX MIN. . MAX
SCL0 clock frequency fCLK 0 100 0 400 kHz

Start/restart condition setup timeNote1 tSU: STA 4.8 - 0.7 - µs
hold time tHD: STA 4.1 - 0.7 - µs
Hold time in SCL = ”L” tLOW 5.0 - 1.25 - µs
Hold time in SCL = ”H” tHIGH 5.0 - 1.25 - µs
Data setup time (reception) tSU: DAT 0 - 0 - µs
Data hold time (sending) Note2
tHD: DAT 0.47 4.0 0.23 1.00 µs
Notes 1. The first clock pulse is generated after this period in the case of the start/restart condition.
2. The MAX of tHD:DAT is normal transition value. Wait is occurred in the term of
ACK(acknowledge) .
Caution Specification at 1.8 V ≤ VDD < 2.7V is not fixed.
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(d) 3-wire serial I/O mode (CSI10 master mode, SCK1n…internal clock output)
SCK1n cycle time tKCY1 4.0 V ≤ VDD ≤ 5.5 V 100 ns
2.7 V ≤ VDD < 4.0 V 200 ns

Not1
SCK1n high-/low-level width tKH1, tKCY1/2 - 10 ns
tKL1
SI1n setup time (to SCK1n↑) tSIK1 30 ns
SI1n hold time (to SCK1n↑) tKSI1 30 ns
Note2
Delay time from SCK1n↓ to SO1n tKSO1 C = 50 pF 40 ns
output
Notes 1. This is the value when the high-speed system clock (fXH) is operating.
2. C is the load capacitance of the SCK1n and SO1n output lines.
(e) 3-wire serial I/O mode (CSI10 slave mode, SCK1n…external clock input)
SCK1n cycle time tKCY2 400 ns

SCK1n high-/low-level width tKH2, T.B.D ns
tKL2
SI1n setup time (to SCK1n↑) tSIK2 80 ns
SI1n hold time (to SCK1n↑) tKSI2 50 ns
Note
Delay time from SCK1n↓ to SO1n tKSO2 C = 50 pF 120 ns
output
Note C is the load capacitance of the SO1n output lines.
Remark n = 0
Caution Specification at 1.8 V ≤ VDD < 2.7V is not fixed.
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Serial Transfer Timing
3-wire serial I/O mode:
tKCYm
tKLm tKHm
SCK1n
tSIKm tKSIm
SI1n Input data
tKSOm
SO1n Output data
Remark m = 1, 2
n=0
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A/D Converter Characteristics

(TA = -40 to +85°C，1.8 V ≤ VDD ≤ 5.5 V, 2.3 V ≤ AVREF ≤ VDD, VSS = AVSS = 0 V)
Resolution RES 10 bit

Overall error Note1,2
AINL 4.0 V ≤ AVREF ≤ 5.5 V ±0.4 %FSR
2.7 V ≤ AVREF ≤ 5.5 V ±0.6 %FSR
AVREF < 2.7 V T.B.D. %FSR

Conversion time tCONV 4.0 V ≤ AVREF ≤ 5.5 V 6.6 30 µs
2.7 V ≤ AVREF ≤ 5.5 V 6.6 30 µs
AVREF < 2.7 V 11 T.B.D. µs
Zero-scale error Note1,2 EZS 4.0 V ≤ AVREF ≤ 5.5 V ±0.4 %FSR
2.7 V ≤ AVREF ≤ 5.5 V ±0.6 %FSR
Full-scale error Note1,2

EFS 4.0 V ≤ AVREF ≤ 5.5 V ±0.4 %FSR
2.7 V ≤ AVREF ≤ 5.5 V ±0.6 %FSR
AVREF <2.7 V T.B.D. %FSR

Integral linearity error Note1
ILE 4.0 V ≤ AVREF ≤ 5.5 V ±2.5 LSB
2.7 V ≤ AVREF ≤ 5.5 V ±4.5 LSB
AVREF < 2.7 V T.B.D. LSB
Differential linearity error Note1

DLE 4.0 V ≤ AVREF ≤ 5.5 V ±1.5 LSB
2.7 V ≤ AVREF ≤ 5.5 V ±2.0 LSB

Analog input voltage VAIN AVSS AVREF V
Notes 1. Excludes quantization error (±1/2 LSB).

2. This value is indicated as a ratio (%FSR) to the full-scale value.
POC Circuit Characteristics (TA = -40 to +85°C)

Detection voltage VPOC 1.3 1.5 1.7 V

Power supply rise time tPTH VDD : VPOC →1.8 V (MIN. value of VDD) 75 T.B.D mV/ms
Minimum pulse width tPW T.B.D. 50 µs
Notes 1. When voltage rises, time required from detection to reset release
2. When voltage drops, time required from detection to reset occur.
POC Circuit Timing
Supply voltage
(VDD)
Detection voltage (MAX.)

Detection voltage (TYP.)
Detection voltage (MIN.)
tPW
tPTH tPTHD tPD
Time
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LVI Circuit Characteristics (TA = -40 to +85°C)

Detection Supply voltage VLVI0 4.10 4.20 4.30 V

voltage level VLVI1 3.95 4.05 4.15 V
VLVI2 3.81 3.91 4.01 V
VLVI3 3.66 3.76 3.86 V
VLVI4 3.51 3.61 3.71 V
VLVI5 3.37 3.47 3.57 V
VLVI6 3.22 3.32 3.42 V
VLVI7 3.07 3.17 3.27 V
VLVI8 2.93 3.03 3.13 V
VLVI9 2.78 2.88 2.98 V
VLVI10 2.63 2.73 2.83 V
VLVI11 2.49 2.59 2.69 V
VLVI12 2.34 2.44 2.54 V
VLVI13 2.19 2.29 2.39 V
VLVI14 2.05 2.15 2.25 V
VLVI15 1.90 2.00 2.10 V
External input pin EXLVI EXLVI < VDD 1.21 V

Note1
Minimum pulse width tLW T.B.D. 50 µs

Operation stabilization wait TLWAIT1 10 T.B.D µs
Note2
time
Note 1. Using EXLVI/P120/INTP0 pin
2. Time required from setting LVION to 1 to operation stabilization
Remark VLVI(n−1) > VLVIn : n = 1-15
LVI Circuit Timing
Supply voltage
(VDD)
Detection voltage (MAX.)

Detection voltage (TYP.)
Detection voltage (MIN.)
tLW
tWAIT tLD
LVION ← 1 Time
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Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85°C)
Note
Data retention supply voltage VDDDR 1.3 5.5 V
Note Dependence on POC detection voltage. The data is held before POC reset, but is not held after
POC reset when voltage drops.
STOP mode Operation mode

Data retention mode
STOP instruction
Standby release signal
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Flash Memory Programming Characteristics

(1) Basic characteristics

VDD supply voltage IDD fXP = 10 MHz (TYP.), 20 MHz (MAX.) 4.5 11.0 mA
Note1
Erase time Chip unit Teraca 20 T.B.D ms
Sector unit Terasa 20 T.B.D ms
Write time Twrwa 50. T.B.D. µs
Number of rewrites per chip Cerwr 1 erase + 1 write after erase = 1 100 time
rewriteNote2
Notes 1. The prewrite time before erasure and the erase verify time (writeback time) are not included.
2. When a product is first written after shipment, “erase → write” and “write only” are both
taken as one rewrite.
(2) Serial write operation characteristics

Time from RESET↑ to FLMD0 count TRFCF T.B.D 10 T.B.D ms

start
Count execution time TCOUNT T.B.D 10 T.B.D ms
FLMD0 counter high-/low-level width TCH/TCL Tc x 0.45 µs
FLMD0 counter rise/fall time TR/TF 12.5 µs
Remark These values may change after evaluation.
Serial Write Operation
VDD
RESET
0V TCOUNT
TCH
VDD
FLMD0
0V
TF TR
TRFCF TCL
TC
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NOTES FOR CMOS DEVICES
1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
VIH (MIN).
2 HANDLING OF UNUSED INPUT PINS

Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3 PRECAUTION AGAINST ESD

A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4 STATUS BEFORE INITIALIZATION

Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5 POWER ON/OFF SEQUENCE

In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6 INPUT OF SIGNAL DURING POWER OFF STATE

Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in
the United States and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
SuperFlash® is a registered trademark of Silicon Storage Technology, Inc. in several
countries including the United States and Japan.
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78K0/KB2
Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.
• The information contained in this document is being issued in advance of the production cycle for the
product. The parameters for the product may change before final production or NEC Electronics
Corporation, at its own discretion, may withdraw the product prior to its production.
• No part of this document may be copied or reproduced in any form or by any means without the prior written consent
of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document.
• NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC Electronics or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative purposes
in semiconductor product operation and application examples. The incorporation of these circuits, software and
information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC
Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of
these circuits, software and information.
• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products,
customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and
anti-failure features.
• NEC Electronics products are classified into the following three quality grades: "Standard", "Special", and "Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-designated
"quality assurance program" for a specific application. The recommended applications of an NEC Electronics
product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC
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systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life
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"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support
systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M5 02. 11-1
ZUD-CC-04-0125-E

Nec 78k0 Kb2

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Nec 78k0 Kb2

Uploaded by

Preliminary Product Information

MOS Integrated Circuit

Product name (Flash ROM) (RAM)

µPD78F0503 32K bytes (Flash) 1K bytes

µPD78F0502 24K bytes (Flash) 1K bytes

µPD78F0501 16K bytes (Flash) 768 bytes

µPD78F0500 8K bytes (Flash) 512 byte

Minimum instruction cycle • AD CONVERTER

Port0 P00 -P01

TO50 8bit Timer

SCL0 Multi master

INTP0 - External Internal Low-speed

2. Pin Lay Out

78K0/KB2 have 64kB linear address area.

Common ROM Bank ROM

Fig. Clock connecting block image

6. Outline of Functions of KB2

µ PD78F0500 µ PD78F0501 µ PD78F0502 µ PD78F0503

High Speed RAM 512 768 1K

Sub System Clock -

Internal Low Speed Ring-OSC - 240 kHz(TYP.)

Timer - 16 Bit Timer/Event Counter:1ch

7. Electrical specification of KB2 (Target)

Absolute Maximum Ratings(TA = 25°C) (1/2)

Supply voltage VDD -0.5 to +6.5 V

Absolute Maximum Ratings(TA = 25°C) (2/2)

Output current, low IOL Per pin 30 mA

High-Speed System Clock (Crystal/Ceramic) Oscillator Characteristics

Ceramic VSS X1 X2 Oscillation 4.0 V ≤ VDD ≤ 5.5 V 2.0 20.0 MHz

Crystal resonator Oscillation 4.0 V ≤ VDD ≤ 5.5 V 2.0 20.0 MHz

• Keep the wiring length as short as possible.

Ring-OSC Oscillator Characteristics

1.8 V ≤ VDD < 2.7V 2.0

Caution This specification is Duty = 70% condition of IOH and IOL.

VIL2 P00, P01, P10-P11, P14, P16-P17, P30-P33, P120, 0 0.2VDD V

IOH = -2.5 mA 2.7 V ≤ VDD ≤ 5.5V VDD-0.5 V

IOH = -1.0 mA 1.8 V ≤ VDD ≤ 5.5V VDD-0.5 V

VOH2 IOH = -100 µA P20-P23 1.8 V ≤ VDD ≤ 5.5 V VDD-0.5 V

IOL = 0.5 mA 1.8 V ≤ VDD ≤ 5.5V 0.4 V

VOL2 IOL = 400 µA P20-P23 1.8 V ≤ VDD ≤ 5.5 V 0.4 V

VOL3 IOL = 15.0 mA P60-P61 4.0V ≤ VDD ≤ 5.5V 2.0 V

IOL = 5.0 mA 0.4 V

IOL = 3.0 mA 2.7 V ≤ VDD ≤ 5.5V 0.4 V

IOL = 2.0 mA 1.8 V ≤ VDD ≤ 5.5V 0.4 V

ILIL2 VI = AVREF P20-P23 -1 µA

1.8 V ≤ VDD < 2.7 V 100 ns

RESET low-level width tRSL 10 Note2 µs

TCY vs VDD (main system clock operation)

Supply voltage VDD [V]

AC Timing Test Points (Excluding X1 Input)

TI00, TI010, TI001, TI011

Interrupt Request Input Timing

RESET Input Timing

(2) Serial interface

(a)UART mode (UART6, dedicated baud rate generator output)

Transfer rate 312.5 kbps

(b) UART mode (UART0, dedicated baud rate generator output)

Transfer rate 312.5 kbps

(c) IIC0 mode

SCL0 clock frequency fCLK 0 100 0 400 kHz

Caution Specification at 1.8 V ≤ VDD < 2.7V is not fixed.

SCK1n cycle time tKCY1 4.0 V ≤ VDD ≤ 5.5 V 100 ns

2.7 V ≤ VDD < 4.0 V 200 ns

SCK1n cycle time tKCY2 400 ns

Caution Specification at 1.8 V ≤ VDD < 2.7V is not fixed.

Serial Transfer Timing

3-wire serial I/O mode:

SI1n Input data

SO1n Output data

A/D Converter Characteristics

Resolution RES 10 bit

2.7 V ≤ AVREF ≤ 5.5 V ±0.6 %FSR

AVREF < 2.7 V T.B.D. %FSR

Zero-scale error Note1,2 EZS 4.0 V ≤ AVREF ≤ 5.5 V ±0.4 %FSR

2.7 V ≤ AVREF ≤ 5.5 V ±0.6 %FSR

AVREF < 2.7 V T.B.D. %FSR