PrimeTime ECO

PrimeTime® Version M-2016.12-SP3

© 2016 Synopsys, Inc. 1

 CONFIDENTIAL INFORMATION
The following material is confidential information of Synopsys and is being
disclosed to you pursuant to a non-disclosure agreement between you or your
employer and Synopsys. The material being disclosed may only be used as
permitted under such non-disclosure agreement.

IMPORTANT NOTICE
In the event information in this presentation reflects Synopsys’ future plans,
such plans are as of the date of this presentation and are subject to
change. Synopsys is not obligated to develop the software with the features
and functionality discussed in these materials. In any event, Synopsys’
products may be offered and purchased only pursuant to an authorized quote
and purchase order or a mutually agreed upon written contract.

© 2016 Synopsys, Inc. 2

 Topics

Clock ECO

IC Compiler II NDM support

Estimation of ECO Unfixable Reasons

Side-Load Cell Sizing ECO Method

© 2016 Synopsys, Inc. 3

 Topics

Clock ECO

IC Compiler II NDM support

Estimation of ECO Unfixable Reasons

Side-Load Cell Sizing ECO Method

© 2016 Synopsys, Inc. 4

 PrimeTime Clock Skew and DRC Fixing

…
Setup Violation Fixing by Useful Skew

• Fixing Target on Clock Network

– Max transition & max capacitance violations
– Adjusting useful skew for setup & hold
violations

• Available Fixing Methods

– Sizing and buffer insertion at pins on leaf and
branch levels in a clock network

© 2016 Synopsys, Inc. 5

 Feature Description Clock ECO
Overview

• Clock ECO feature available in the PrimeTime 2016.12-SP3 release

– DRC violations (max_transition, max_cap, max_fanout) can be fixed on clock network
– Feature provides ability to fix setup and hold violations by changing clock arrival
– Supported in Physically-Aware ECO only

• Benefits of Clock ECO

– Ability to now fix DRC violations in clock network
– Timing violations can be resolved which could not be fixed in data path
– Fixing more timing violations with fewer changes

© 2016 Synopsys, Inc. 6

 Clock ECO DRC Fixing Techniques

Q
max tran
max cap violation CLK
violation
DRC violation on a clock net Buf2X Buf2X

max tran Q
max cap violation
violation fixed
fixed CLK
DRC violation fixed by upsizing Buf4X Buf2X

max cap max tran Q

violation violation
fixed
fixed
CLK
DRC violation fixed by buffering Buf2X Buf4X Buf2X

© 2016 Synopsys, Inc. 7

 Clock ECO DRC Fixing Techniques

ECO
• Clock Net with large fanout all has max transition violations Buffer

– No opportunity for up sizing on network to fix violation

– On route buffering splits nets to help isolate loading on fanout

– Clock max_tran can be fixed by resolving route topology on Driver

overloaded net

© 2016 Synopsys, Inc. 8

 Clock ECO Setup Fixing Techniques
Setup slack =
110ps -10 ps

Launch
D Q D Q

CK CK
Capture

C2 C3

C1 Clock
ECO Slower Capture Clock path allows
more time for setup path
Faster Launch on Launch Flop
Setup slack =
allows more time for setup path 110ps +1 ps

D Q D Q Launch
Upsizing for
faster launch CK CK
Capture
C2 C3

C1 Downsizing for
Buffer insertion for delayed capture
delayed capture
© 2016 Synopsys, Inc. 9
 Clock ECO Hold Fixing Techniques
Hold slack =
-10 ps
10ps

D Q D Q Launch
CK CK
Capture
C2 C3

C1
Clock
ECO
Slower Launch on Launch Flop Hold slack =
+2 ps
10ps
improves hold Launch
D Q D Q

Buffer insertion for CK CK

delayed launch Capture

C2 C3 Faster Capture Clock path

improves hold path
C1
C1
Upsizing for
Down sizing for faster capture
delayed launch
© 2016 Synopsys, Inc. 10
 Buffer Count Reduction with Clock ECO
Hold Fixing Example

• Data path hold fixing requires 16 buffer insertions • Clock path hold fixing requires only 1 buffer insertion

Q0 D0 Q0 D0

Q1 D1 Q1 D1

Q2 D2 Q2 D2
… … ..... …..

…. ….
Q15 D15 Q15 D15

CK CK CK CK

C1 C2 C1 C2

© 2016 Synopsys, Inc. 11

 User Interface for Clock ECO

• Option in set_eco_options for Clock ECO to enable loading of Clock Data

– set_eco_options –physical_enable_clock_data
– By Default PT does not read clock routing data from DEF. This option will enable reading of
physical data for clock network
– Used for both DRC and Timing based Clock ECO

• For DRC fixing new option for cell_type “clock_network”

– fix_eco_drc –cell_type clock_network
– clock_network enables drc fixing on clock network
– When –cell_type clock_network is specified, fixing is only performed on clock network

© 2016 Synopsys, Inc. 12

 User Interface for Clock ECO (2)

• For Timing based fixing new option for cell_type “clock_network”

– fix_eco_timing –cell_type clock_network
– When –cell_type clock_network is specified, timing fixing is only done on clock network
– Clock fixing and Data path fixing cannot be done within a single command
– All other options of fix_eco_timing are supported for custom based timing fixing

• Two other options are available to control timing based fixing fix_eco_timing
– clock_fixes_per_change
– controls the minimum number of violations to be fixed per one change, either sizing or buffer insertion
– clock_max_level_from_reg
– specifies the highest level of a clock network tree in which timing fixes can occur

© 2016 Synopsys, Inc. 13

 Explanation of -clock_max_level_from_reg
• fix_eco_timing –cell_type clock_network -clock_max_level_from_reg <Value>
• Defualt is “0” meaning changes can occur anywhere in the clock tree
• User has ability to control where ECO can occur relative to the register clock pins

-clock_max_level_from_reg 1

Changes can only occur 1 level B4 B3 B2 B1

back from clock pin

-clock_max_level_from_reg 3

Changes can only occur 3 levels

B4 B3 B2 B1
back from clock pin

© 2016 Synopsys, Inc. 14

 Logfile: Timing Fixing on Clock Network
fix_eco_timing -physical_mode open_site -cell_type clock_network -type setup -methods size_cell -verbose
Information: Starting physically aware fixing in open_site mode...
Information: Starting to load physical information at [ Date ]... (PTECO-039)
Information: Loading physical data and creating output log in ./lef_def.log... (PTECO-040)
Information: Starting timing fix iteration 1 at [ Date ]...
Information: Analyzing sizing candidates in capture clocks... -cell_type clock_network
Information: 2799 violating endpoints located. specified to perform Clock
Information: Updating timing...
……
ECO
Final ECO Summary:
--------------------------------------------------------
Number of size_cell commands 553 Analyzing Clock Network
Total number of commands 553
for Candidates for sizing
Area increased by cell sizing 15.68
Total area increased 15.68 and buffering

Fixing Summary:
--------------------------------------------------------
Total violating endpoints found 2799
Analyzing Clock Network
ECO Summary for Clock
Total violating endpoints fixed 1944 for Candidates for sizing
ECO timing based fixing
Total violating endpoints remaining 855 and buffering
Total percentage of violations fixed 69.5%

© 2016 Synopsys, Inc. 15

 Logfile: DRC Fixing on Clock Network
fix_eco_drc -physical_mode open_site -cell_type clock_network -type max_tran -buffer_list $clock_buff -verbose
Information: Starting physically aware fixing in open_site mode...
Information: Starting to load physical information at [ Date ]... (PTECO-039)
Information: Loading physical data and creating output log in ./lef_def.log... (PTECO-040)
Information: Starting DRC fix iteration 1 at [ Date ]...

Available buffers:
Lib_cell Area
-------------------------------------------------------- -cell_type clock_network
CBUF1 4.95
…… specified to perform Clock
Information: Detected 1320 max transition violations in clock network. ECO for max transition fixing
……
Inserted buffers:
Count Lib_cell Area Total_area
--------------------------------------------------------
……… Analyzing Clock Network
417 CBUFXYZ 1.52 635.55
…… for DRC violations for fixing
--------------------------------------------------------
1466 TOTAL 2365.78

Final ECO Summary:

--------------------------------------------------------
Number of size_cell commands 52 ECO Summary for Clock
Number of insert_buffer commands 1466 ECO
ECOtiming
DRC based
based fixing
fixing
Total number of commands 1518
Area increased by cell sizing 60.01
Area increased by buffer insertion 2365.78
Total area increased 2425.79

© 2016 Synopsys, Inc. 16

 Controlling Cells used in Clock ECO
• For many designs only certain lib cells can be used in the clock network
– User should remove dont_use or dont_touch attributes for lib cells or clock leaf cells
– set_dont_use [get_lib_cells $valid_clock_buffers] false
– set_dont_touch [get_lib_cells $valid_clock_buffers] false
– set_dont_touch [get_cells $clock_leaf_cells] false

• PrimeTime ECO has the ability to control which lib cells can be used for buffering and sizing
– Buffering: User provide usable Clock buffer buffer list : –buffer_list $valid_clk_buffers
– Sizing: Use set_user_attribute & eco_alternative_cell_attribute_restrictions for clock lib cell
selection
– For Example :

define_user_attribute –type boolean –class lib_cell is_clk_cell

set clk_lcells [get_lib_cell */*CLK*]  Restrict lib cells to these
set_user_attribute $clk_lcells is_clk_cell true
set eco_alternative_cell_attribute_restrictions is_clk_cell

© 2016 Synopsys, Inc. 17

 Clock ECO fixing
Results

• PrimeTime ECO enhancement enables better fixing results

Design Instance Count Fixing Results

D1 73K Setup fix rate from 47% to 73%
D2 2.7M 17% hold buffer reduction
D3 11M 20% hold buffer reduction
D4 1M 20% less area added, 13% hold buffer reduction
D5 4.5M 96% max transition violations fixed on clock network
D6 2.2M 94% max transition violations fixed on clock network

© 2016 Synopsys, Inc. 18

 Topics

Clock ECO

IC Compiler II NDM support

Estimation of ECO Unfixable Reasons

Side-Load Cell Sizing ECO Method

© 2016 Synopsys, Inc. 19

 NDM Support for PrimeTime ECO

• PrimeTime 2016.12-SP3 supports reading IC Compiler II NDM physical data for Physically-Aware
ECO

• For Top Level and Hier NDM preparation, please refer to the IC Compiler II application note:
– https://solvnet.synopsys.com/retrieve/customer/application_notes/attached_files/2258100/ICCII_TopLeve
lSolution_L-201603-SP5.pdf
– Please reference app note for details on creating and using frame views
– For PrimeTime hierarchical ECO, the frame view for all sub-blocks are required

© 2016 Synopsys, Inc. 20

 User Interface for NDM Reading in PrimeTime ECO

• Two new options have been implemented to support reading NDM physical data
• NDM data is read at the same time in flow as LEF/DEF
• check_eco and fix_eco_* commands invoke NDM reading for Physically-Aware ECO

set_eco_options Specify physical information

-physical_icc2_lib Specifies path to NDM library, the value of this option mirrors the input
that you would provide to open_lib command in ICC2:
<library_name >
Library name in simple, relative, or absolute path

-physical_icc2_blocks Specifies the block to use from NDM lib, this value of this option mirrors
the input you would provide open_block command in ICC2:
<name of the block to open>

*Note in PrimeTime 2016.12-SP3 labels are not supported, just the name of the block should be supplied
to this option (see next slide for example)
© 2016 Synopsys, Inc. 21
 NDM Example for Opening Block
• For a using a block from NDM, nlib reference and associated block need to be supplied
• Physical data is utilized from this nlib and block for Physically-Aware ECO

icc2_shell> open_lib design.nlib

Information: Loading library file '<lib_loc>/design.nlib' (FILE-007)
ICC2 commands
Information: Loading library file '<lib_loc>/ref_lib1.nlib' (FILE-007)
example for opening ………
up block {design.nlib}
icc2_shell> open_block design_post_route
Information: User units loaded from library 'lib_xyz' (LNK-040)
Opening block 'design.nlib:design_post_route.design' in edit mode
{design.nlib:design_post_route.design}
icc2_shell> NDM library, same input
as user would supply to
open_lib in ICC2 :
Corresponding
PrimeTime set_eco_options \
set_eco_options -physical_icc2_lib design.nlib \ Block name, same
command -physical_icc2_blocks design_post_route \ input as user would
-log_file ./ndm_read.log supply to open_block
in ICC2D:N
*Note if more than one block is inside a library, users can reference multiple blocks
by -physical_icc2_blocks {block1 block2}

© 2016 Synopsys, Inc. 22

 NDM Example for Mixed LEF/DEF and Hier NDM
• For Hier Designs with mixed LEF/DEF and NDM
– Supply set_eco_option for LEF and DEF for blocks represented, same as in prior releases
– NDM is supplied in supplemental set_eco_options commands for block and top

LEF supplied for library information as well as

LEF supplied for library information as well as
set_eco_option -log ndm_eco_option.log -physical_lib_path \ block lefs by -physical_lib_path for Blocks
block LEFs by -physical_lib_path
“ <lef_location>/library.lef \ being represented in DEF
<lef_location>/BLOCK_A.lef \
<lef_location>/BLOCK_B.lef “ \
-physical_design_path “ \ DEF files provided by -physical_design_path
<def_location>/BLOCK_A.def.gz \ for those blocks represented in DEF
<def_location>/BLOCK_B.def.gz “

NDM used
NDMfor block
used for :
BLOCK_C
block BLOCK_C
set_eco_options -physical_icc2_lib <NDM_lib_loc>/BLOCK_C.nlib -physical_icc2_blocks BLOCK_C

set_eco_options -physical_icc2_lib <NDM_lib_loc>/TOP_DES.nlib -physical_icc2_blocks TOP_DES

NDM
NDMused top :DMC_TOP_B
usedforforblock TOP_DES

* Note : NDM reading automatically determines the top and blocks as before
© 2016 Synopsys, Inc. 23
 report_eco_options with NDM Provided
• New columns in report_eco_options specify NDM parameters supplied for Physically-Aware ECO
• If LEF and DEF are provided, these are also denoted as in prior releases

****************************************
Report : eco_options
Design : TOP_DES
Version: M-2016.12-SP3 NDM library and associated block to
Date : DATE
**************************************** be read in for Physically-Aware ECO
….
Cell LEF files
------------------------------
<lef_location>/library.lef
<lef_location>/BLOCK_A.lef
<lef_location>/BLOCK_B.lef
….
Physical ICC2 lib Physical ICC2 blocks
------------------------------ --------------------------
<NDM_lib_location>/BLOCK_C.nlib BLOCK_C
<NDM_lib_location>/TOP_DES.nlib TOP_DES

DEF files Physical constraint files

------------------------------ --------------------------
<def_location>/BLOCK_A.def.gz
<def_location>/BLOCK_B.def.gz
……

© 2016 Synopsys, Inc. 24

 Topics

Clock ECO

IC Compiler II NDM support

Estimation of ECO Unfixable Reasons

Side-Load Cell Sizing ECO Method

© 2016 Synopsys, Inc. 25

 Estimate Unfixable Reasons Feature Description
• Ability to estimate unfixable reasons with the fix_eco_timing command
– Generates an estimate of unfixable reasons report without changing the design
– Significantly faster than actual fixing

• Useful to regenerate unfixable reasons after initial ECO without doing actual fixing

• User can select specific paths from large unfixable reasons report
– Quickly evaluate alternative solutions like new buffer list/area threshold/margins, remove don’t_touch
– Can also use pre-ECO to identify reasons early in design flow, like lack of open_site “O”, UPF “U”,
dont_touch “V”

• Honors all options of fix_eco_timing: –from/-to, -physical_mode, -pba, –group,

-methods, -ignore_drc, etc

• User Interface: New option  fix_eco_timing –estimate_unfixable_reasons

© 2016 Synopsys, Inc. 26

 Example of Feature for Estimating Hold Fixing

u1
u1 u1

fix_eco_timing -type hold -buffer_list {BUFX12} fix_eco_timing -type hold -buffer_list {DELBUFX1 }
-estimate_unfixable_reasons -estimate_unfixable_reasons
Unfixable Violations: Unfixable Violations:
I: buffer_list with given lib_cells cannot fix violation Violation Reasons Prio/Slk
Violation Reasons Prio/slk
S: r1/Q I P9
E: o1 -0.1

© 2016 Synopsys, Inc. 27

 Details on Usage in ECO Flow
• To enable feature, set eco_report_unfixed_reason_max_endpoints > 0 (default = 0)
– For DMSA flow, you need to set this variable at the master

• Example: set eco_report_unfixed_reason_max_endpoints 10

fix_eco_timing -type hold -estimate_unfixable_reasons
– This generates an unfixable reasons report with maximum number of violating endpoints = 10
– If its set to the default or a negative integer, this generates an unfixable reasons report containing no violating
endpoints

fix_eco_timing -type setup -estimate_unfixable_reasons

# Identify unfixable reasons such as lack of open_site “O”, UPF “U”, dont_touch “V” that can lower fix rate

fix_eco_timing -type setup -verbose

# Does actual fixing based on appropriate changes
# Some unfixable reasons from estimation and actual ECO fixing are not expected to be identical

© 2016 Synopsys, Inc. 28

 Example Snippet of Estimate Run
fix_eco_timing -type hold -estimate_unfixable_reasons -buffer_list $buff_list
Information: Using option -estimate_unfixable_reasons. Estimation started at [ Thu Oct 13 15:16:05 2016 ] ...
Information: The design will not be changed.

Available buffers:
Lib_cell Area
--------------------------------------------------------
BUF_NO_D12_L 0.4
BUF_NO_D6_L 0.2
BUF_SK_D8_UL 0.3

Information: 115930 violating endpoints located... (PTECO-022)

Information: 115930 endpoints are being considered for fixing... (PTECO-027)
Information: Fixing violations...
Unfixable violations:
S:core/fdx/MMU_P_FF1/q_reg[68]/Q P5
core/fdx/U213/ZN P9
core/U8638/Z W P9
core/PORT_OUTPUT_1/ZN V P9
l2e/iso/iso_rgt/Y U P9
E:l2e/misc/q_reg[11:4]/D7 -373.824
E:l2e/misc/q_reg[11:4]/D8 -364.750

© 2016 Synopsys, Inc. 29

 Topics

Clock ECO

IC Compiler II NDM support

Estimation of ECO Unfixable Reasons

Side-Load Cell Sizing ECO Method

© 2016 Synopsys, Inc. 30

 Improve Setup Fixing by Downsizing Side Loads
• For setup fixing with this feature, fix_eco_timing downsizes side-loads of violating paths
• This reduces the pin capacitance of multi-fanout stages in a violating path, makes it easier to
fix the setup violation

• Illustration below shows an example of a critical path going through u1 and u2 (figure a)
– Downsizing side loads u3 and u4 improves the slack of critical path by reducing the capacitive loading
seen by u1 (figure b)

3X u3 1X

3X u4 1X

© 2016 Synopsys, Inc. 31

 Details on Usage
• This feature is enabled by using –methods {size_cell_side_load} during setup fixing
– Usage: fix_eco_timing -type setup –methods {size_cell_side_load} -cell_type
combinational
– When this feature is enabled, informational messages are output to the logfile:
– Information: Starting pre-processing at [ Mon Oct 20 12:43:17 2016 ]...
– Information: 811 violating endpoints located... (PTECO-022)
– Information: 50 cells have been down-sized.

• This feature can be used for GBA, PBA, physical/non-physical ECO

• The method size_cell_side_load only works with combinational cell fixing, and generates
an error when other cell types are specified
– fix_eco_timing -type setup –methods {size_cell_side_load} -cell_type sequential
– Error: The option -cell_type must be combinational if the option -methods has size_cell_side_load.

© 2016 Synopsys, Inc. 32

 Thank You

© 2016 Synopsys, Inc. 33