Manual
Manual
Manual
Introduction
Vi Microsystems Xilinx Spartan-6 Trainer Kit (VPTB – 20) is a demonstration platform intended
for you to become familiar with the new features and availability of the Spartan-6 FPGA family.
This Kit provides a low-cost, easy to use development and evaluation platform for Spartan-6
FPGA designs.
Features
Block Diagram
CHAPTER 2
CLOCK SOURCE
Spartan-6 FPGA works in different clock frequencies. User can use any frequencies for their
applications as given below,
Table-1
3.6864 25.175
1Mhz Mhz 4Mhz 20Mhz 24Mhz Mhz 48Mhz 66Mhz 80Mhz 100Mhz
S2 0 0 0 0 1 1 0 0 0 0
S1 0 0 0 1 0 1 0 0 0 0
S0 0 0 0 0 0 1 1 1 1 1
R6 0 0 0 0 0 1 0 0 0 0
R5 1 1 0 0 0 0 0 0 0 0
R4 0 1 0 0 0 0 0 0 0 0
R3 1 0 1 0 0 1 0 1 0 0
R2 1 0 0 0 0 0 0 0 0 0
R1 1 0 1 0 1 1 1 0 0 0
R0 0 1 0 1 0 0 1 0 1 1
V8 0 0 0 0 0 1 0 0 0 0
V7 0 0 0 0 0 0 0 0 0 0
V6 0 0 0 0 0 0 0 0 0 0
V5 0 1 0 0 0 0 0 0 0 0
V4 0 0 0 0 0 1 0 1 0 0
V3 0 0 0 0 0 0 0 1 0 0
V2 1 1 1 1 1 1 1 0 1 1
V1 0 1 1 0 0 1 0 0 0 1
V0 0 1 0 0 0 1 0 1 0 1
For any other frequency use the online ICS252 calculator at
http://www.idt.com//app=calculator & device=525_01 or alternatively, the output of the
ICS252 output frequency in between 1Mhz to 100Mhz use the following formula.
( + 8)
= ×2
( + 2)( )
Where,
Reference Divider Word (RDW) = 1 to 127 (0 is not permitted)
VCO Divider Word (VDW) = 4 to 511 (0,1,2,3 are not permitted)
Output Divider(OD) = Values below
EXAMPLE
To generate 12 MHz, assume Crystal frequency or Input frequency is 20MHz.
In general,
( )
= ×2 ( )( )
(4 + 8)
= 20 ×2 = 12
(18 + 2)(2)
ICS525-01 Output Divider and Maximum Output Frequency Table
Table:2
0 0 0 10 26 23 18 16
0 1 0 8 40 36 25 22
0 1 1 4 80 72 50 45
1 0 0 5 50 45 34 30
1 0 1 7 40 36 26 23
1 1 0 9 33.3 30 20 18
1 1 1 6 53 47 27 24
On-board 20MHz oscillator (Y4) is used to give one more clock input to FPGA device. When
using this clock input set the Jumper J15 in upward direction. When using external clock from
P13 second pin / P10 second pin short the jumper J15 in downward direction.
The Spartan-6 Trainer Kit has a slide power switch. Moving the power switch Up for Power ON,
the LED L1 will glow and down for power OFF, the LED L1 will off.
The Spartan-6 Trainer Kit has a push button Switch (named as CONFIG) to Configure the FPGA
from Xilinx Serial Flash PROM. During configuration process of the FPGA the LED L2 will be
off and after successful configuration the LED L2 will glow.
The Spartan-6 Trainer kit has a push button switch (named as RESET) which can be configured
as input by assigning the corresponding FPGA pin location.
Name FPGA
RESET (SW34) P175
Name SW21
FPGA Pin R7
The Spartan-6 Trainer Kit has 16 nos of slide switches with led indication for giving inputs to the
FPGA I/O lines. The slide switches are located in the bottom corner of the board and are labeled
as SW22 through SW37. Switch SW22 is the left-most switch, and SW37 is the right-most
switch. When in the UP or ON position, a switch connects the FPGA pin to 3.3V, a logic High.
When DOWN or in the OFF position, the switch connects the FPGA pin to ground, a logic Low.
The switches typically exhibit about 2 ms of mechanical bounce. There is no active de-bouncing
circuitry, although such circuitry could easily be added to the FPGA design programmed on the
board.
Slide Switch connections with FPGA
There are 16 The VPTB-10 board has 16 momentary-contact push button switches are arranged
in 4 x 4 matrix format, and multiplexed by 8 IO pins to FPGA. There are 4 output lines named a3
to a0 (row) and 4 input lines are available named as b3 to b0 (column).
Output LEDs
The Spartan-6 Trainer Kit board has sixteen individual surface-mount LEDs located immediately
above the slide switches. The LEDs are labeled L40 through L55. L40 is the left-most LED, L55
the right-most LED.
Each LED has one side connected to ground and the other side connected to a pin on the Spartan-
6 device via a 270Ω current limiting resistor. To light an individual LED, drive the associated
FPGA control signal High.
The VPTB-20 board has a four-character, seven segment LED display controlled by FPGA user-
I/O pins. Each individual character has a separate common pin, and this pin is connected to J10
3-pin jumper. When using common cathode control input seven segment display short this
jumper to ground and when using common anode control input seven segment display short this
jumper to +3.3V. The LED control signals are connected to the individual line of the FPGA I/O.
Character a b c d e f g
1 0 1 1 0 0 0 0
2 1 1 0 1 1 0 1
3 1 1 1 1 0 0 1
4 0 1 1 0 0 1 1
5 1 0 1 1 0 1 1
6 1 0 1 1 1 1 1
7 1 1 1 0 0 0 0
8 1 1 1 1 1 1 1
9 1 1 1 0 0 1 1
A 1 1 1 0 1 1 1
B 0 0 1 1 1 1 1
C 1 0 0 1 1 1 0
D 0 1 1 1 1 0 1
E 1 0 0 1 1 1 1
F 1 0 0 0 1 1 1
Disp1
FPGA Pin T7 P7 N5 P1 P2 L8 N8 N4
Disp3
FPGA Pin P5 P4 L4 L5 L7 R1 R2 L3
Disp2
FPGA Pin P6 N6 M6 N1 N3 T6 M7 M5
Disp4
FPGA Pin T4 T3 M2 M3 M4 T5 R5 M1
CHAPTER-5
The VPTB-20 contains Buzzer & Relay circuit, and both works in 5V DC Voltage. A buzzer or
beeper is a signaling device, usually electronic, typically used in automobiles, household
appliances such as a microwave oven, or game shows. Buzzer generates different tone Generator.
Relay is used as On/Off switch depending upon user needs.
The VPTB-20 Contains Stepper Motor Interface Connector to Control the Stepper Motor Speed
and it also controls the Step Angle of the Motor.
VPTB-20 board has the provision to interface the 5V stepper motor and +12V DC motor through
the ULN2803A driver IC. P9 2-pin J801 connector has the option to give external supply voltage
to the driver IC and J13 jumper will choose the driver voltage is be the on-board +5V or be the
external voltage. Driver output lines for stepper motor are terminated in P11 5-pin RMC
connector and for DC motor lines are terminated in P7 2-pin J801 connector. But we cannot
execute the stepper motor and dc motor alone not in the same time.
CHAPTER – 7
LCD DISPLAY
Once mastered, the LCD is a practical way to display a variety of information using standard
ASCII and custom characters. However, these displays are not fast. Scrolling the display at half-
second intervals tests the practical limit for clarity.
LCD D0 D1 D2 D3 D4 D5 D6 D7 RS CS
FPGA Pin T10 M9 N9 P9 R9 T9 T8 P8 T10 M10
Voltage Compatibility
The character LCD is power by +5V. The FPGA I/O signals are powered by 3.3V.However, the
FPGA’s output levels are recognized as valid Low or High logic levels by the LCD. The LCD
controller accepts 5V TTL signal levels and the 3.3V LVC MOS outputs provided by the FPGA
meet the 5V TTL voltage level requirements.
The 390Ω series resistors on the data lines prevent over stressing on the FPGA and Strata Flash
I/O pins when the character LCD drives a High logic value. The character LCD drives the data
lines when LCD R/W is High. Most applications treat the LCD as a write only peripheral and
never read from the display and hence in this trainer the R/W pin is grounded by default.
Spartan 6 project card has one RTC (Real Time Clock) IC DS1340 in its onboard. It’s a 2-wire
8pin RTC IC, uses a low-cost 32.768 kHz crystal, it tracks time using several internal registers.
The clock/calendar automatically adjusts for months with fewer than 31 days, including
corrections for leap years. Each pin function and FPGA connections is given below.
0x00 register contains the time format seconds data, it have BCD ones (bit 0 to 3) and
tens (bit 4 to 6).
0x01 register have time format minutes data in the order of BCD ones (bit 0 to 3) and
tens (bit 4 to 6).
0x02 register have time format hour data, is situated as BCD ones (bit 0 to 3) and tens
(bit 4 to 5).
0x04 register for date, have BCD ones in bit 0 to 3 and tens in bit 4 to 5.
0x05 register for month, have BCD ones in bit 0 to 3 and tens in bit 4.
0x06 register for year, have BCD ones in bit 0 to 3 and tens in bit 4 to 7. Corrections
include for leap year also.
ADC & DAC
Spartan 6 Trainer Kit has one SPI-compatible; two channel Analog to Digital Converter (ADC)
by using AD122S101 IC. It is a single channel, 12 bit, low power, high speed, and single power
supply with 2.7V - 5.25V range, successive approximation, serial interface IC. And it is a 8 pin
IC.
1st pin (CS bar) is a chip select pin. When it is low then only the ADC conversion process
will start.
2nd pin (VA) is connected to +3.3V supply and bypassed with 0.1uF capacitor.
4th (IN2) and 5th (IN1) pin (Vin) is a analog input, it ranges from 0V to VA.
6th pin is a digital data input. Control Register is loaded through this pin on rising edges
of the SCLK pin.
7th pin (DOUT) is a serial digital output, at falling edge of the SCLK signal.
8th pin (SCLK) is a serial clock input. This controls the conversion and readout processes.
CS is chip select, which initiates conversions and frames the serial data transfers. SCLK
(serial clock) controls both the conversion process and the timing of serial data. DOUT is the
serial data output pin, where a conversion result is sent as a serial data stream, MSB first. Data to
be written to the ADC122S101's Control Register is placed at DIN, the serial data input pin. New
data is written to DIN with each conversion.
A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS.
Each frame must contain an integer multiple of 16 rising SCLK edges. The ADC output data
(DOUT) is in a high impedance state when CS is high and is active when CS is low. Thus, CS
acts as an output enable.
ADC Control Register and Bit Explanation
Input Channel Selection
Timing Diagram
External Input
Pot meter or other analog input signal is used to give input to ADC channels and the ADC will
support the voltage range from 0V to +3.3V. Connect the 1st pin of pot meter to the 5th pin of P12
connector, 1st pin to 6th pin of P6 and 2nd pin to 1st pin of P12 (ADC Channel 1). If we want to
give analog input to second channel of ADC, connect 2nd point of pot meter to 2nd pin of P12
connector. Download .bit file and rotate the pot meter and the corresponding digital output is
displayed in the 12 LEDs (L55 to L44).
On-Board Analog Input
On-board TP5 trimmer is used to give analog input to ADC CH1 or ADC CH2 by using J16
jumper. When we short J16 pin 1 and 2, the trim-pot output is connected to ADC CH1 and when
J16 pin 2 and 3 shorted, trim-pot output is connected to ADC CH2. Set the jumpers and
download the .bit file. The output will be displayed in 16 LEDs (L55 to L40).
Temperature Sensor Input
LM35 temperature is used in Spatan-6 Trainer Kit to measure the external environment
temperature. This sensor converts the temperature into corresponding voltage. Temperature
conversion is in ˚C (Centigrade). 1˚C will gives 10mV voltage. By using this relation, calibration
is made in program. Voltage output is given as an analog input to ADC CH1 by short the jumper
J19. At that time we should not give external analog input and on-board trimmer analog input to
ADC CH1. Download the .bit file, at normal condition room temperature is measured and that
voltage is given to ADC. When we apply external heat to the sensor, that corresponding
unknown temperature value is displayed in LCD in ˚C (Centigrade).
Spartan 6 Trainer Kit has one SPI-compatible, single channel Digital to Analog
Converter (DAC) by using DAC121S085 IC. It is a two channel, 12 bit, low power, high speed,
and power supply with the range of 2.7V - 5.25V, serial interface IC. And it is a 10 pin IC.
In this IC 1st pin (VA) is connected to +3.3V supply and bypassed with 0.1uF capacitor.
7th pin (Vrefin) is connected to +3.3V supply and bypassed with 0.1uF capacitor.
8th pin (DIN) is serial Data Input. Data is clocked into the 16-bit shift register on the
falling edges of SCLK after the fall of SYNC.
9th pin (SYNC bar) is frame synchronization input for the data input. When this pin goes
low, it enables the input shift register and data is transferred on the falling edges of SCLK.
10th pin (SCLK) is serial Clock Input. Data is clocked into the input shift register on the
falling edges of this pin.
The input shift register has sixteen bits. The first bit must be set to "0" and the second bit
is an address bit. The address bit determines whether the register data is for DAC A or DAC B.
This bit is followed by two bits that determine the mode of operation (writing to a DAC register
without updating the outputs of both DACs, writing to a DAC register and updating the outputs
of both DACs, writing to the register of both DACs and updating their outputs, or powering
down both outputs). The final twelve bits of the shift register are the data bits. The data format is
straight binary (MSB first, LSB last), with all 0's corresponding to an output of 0V and all 1's
corresponding to a full-scale output of VREFIN - 1 LSB. The contents of the serial input register
are transferred to the DAC register on the sixteenth falling edge of SCLK.
SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is updated on the 16th
SCLK falling edge. However, if SYNC is brought high before the 16th falling edge, the data
transfer to the shift register is aborted and the write sequence is invalid. Under this condition, the
DAC register is not updated and there is no change in the mode of operation or in the DAC
output voltages.
USB to UART
Spartan-6 Trainer Kit supports UART communication with PC using USB to UART Converter
Bridge (USB 2.0). FT232RL device is act as the USB to UART Bridge between Spartan-6 FPGA
and PC. Transmit (TXD) and Receive (RXD) lines are only used in this board. When connecting
the board USB to UART with PC, open Device Manager to know the COM port. We can choose
the baud rate for the program using the following formula,
Ex, Frequency 20MHz, Count Value 2083 and Baud Rate 9600
Spartan-6 Trainer Kit has On-Board USB to JTAG programmer section to download the
configuration file into the FPGA and PROM device and it has the USB provision to connect the
Spartan-6 Trainer Kit to PC USB port using USB cable. Thus we may not require the external
programmer to configure the device. JTAG lines from the device are converted to USB signals
and these USB signals are terminated in the P3 USB connector.
There are three 20-pin connectors are presented in Spartan-6 Trainer Kit and general purpose I/O
lines are terminated in these connectors to interface the external hardware peripherals with
Spartan-6 FPGA. We can give 3.3V level external signals to FPGA through these connectors and
can out 3.3V level signals from FPGA. Don’t give more than 3.3V level signals to FPGA
because it induces harmful effect to Spartan-6 device.
J14 3-pin jumper is used to select the supply voltage for P10 connector. When we short J14 pin-1
and pin-2, 3.3V is given to pin-1 of the P10 connector and short J14 pin-2 and pin-3, +5V is
connected. This gives the supply to the external hardware which is connected to P10 connector.
P6 20-pin Connector
J11 3-pin jumper is used to select the supply voltage for P6 connector. When we short J11 pin-1
and pin-2, 3.3V is given to pin-1 of the P6 connector and short J11 pin-2 and pin-3, +5V is
connected. This gives the supply to the external hardware which is connected to P6 connector.
J17 3-pin jumper is used to select the supply voltage for P13 connector. When we short J17 pin-1
and pin-2, 3.3V is given to pin-1 of the P13 connector and short J17 pin-2 and pin-3, +5V is
connected. This gives the supply to the external hardware which is connected to P13 connector.
P14 connector allows the restrictions of 20-pin connectors because we can in and out the +5V
logic level signals in P14 connector. For that voltage level translators (bidirectional) U15, U21
and U22 (SN74LVCC3245A) are used in Spartan-6 Trainer Kit. Totally 24 I/O lines are
terminated in this connector through three SN74LVCC3245A ICs. Voltage conversion from A
B (FPGA +3.3V to Connector +5V) and B A (Connector +5V to FPGA +3.3V) is
controlled by the DIR pin in level translator IC.
Connector Pin Signal Name IC IC Signal FPGA Pin
1 PA0 SPA0 J14
2 PA1 SPA1 J16
3 PA2 SPA2 H16
4 PA3 U15 SPA3 H15
5 PA4 SPA4 H14
6 PA5 SPA5 H13
7 PA6 SPA6 H11
8 PA7 SPA7 G16
PADIR L14
9 PB0 SPB0 B12
10 PB1 SPB1 A11
11 PB2 SPB2 C10
12 PB3 U21 SPB3 B10
13 PB4 SPB4 A10
14 PB5 SPB5 F9
15 PB6 SPB6 D9
16 PB7 SPB7 C9
PBDIR L13
17 PC0 SPC0 C15
18 PC1 SPC1 C13
19 PC2 SPC2 C11
20 PC3 U22 SPC3 B16
21 PC4 SPC4 B15
22 PC5 SPC5 B14
23 PC6 SPC6 A14
24 PC7 SPC7 A13
PCDIR C16
25 Ground Gnd
26 VCC +5V
Spartan-6 Trainer Kit has On-Board Traffic Light Controller section which reflects the original
TLC what we seen in our day to day life. This section includes three colors (Red, Green and
Yellow) controller LEDs for signal controlling and 8 pedestrian LEDs are also placed. Each road
has red, yellow and three green LEDs are placed to indicate right turning, left turning and
straight.
Road Color LED Signal Name FPGA Pin
Red L25 PB6 D9
Yellow L24 PB7 C9
Green L23 PC0 C15
Road1 Green L17 PC2 C11
Green L29 PC1 C13
Pedestrian L19 NOT PB0 B12
Pedestrian L31 NOT PB0 B12
Red L12 PA2 H16
Yellow L11 PA1 J16
Green L9 PA0 J14
Road2 Green L10 PA4 H14
Green L8 PA3 H15
Pedestrian L16 NOT PB1 A11
Pedestrian L14 NOT PB1 A11
Red L26 PC3 B16
Yellow L27 PC4 B15
Green L28 PC5 B14
Road3 Green L22 PC7 A13
Green L34 PC6 A13
Pedestrian L20 NOT PB2 C10
Pedestrian L33 NOT PB2 C10
Red L39 PA5 H13
Yellow L56 PA6 H11
Green L58 PA7 G16
Road4 Green L59 PB5 F9
Green L57 PB4 H14
Pedestrian L37 NOT PB3 B10
Pedestrian L35 NOT PB3 B10