stm32f091cc 956209 PDF
stm32f091cc 956209 PDF
stm32f091cc 956209 PDF
Features )%*$
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 ARM®-Cortex®-M0 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 14
3.5 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5.2 Power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.6 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.7 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.8 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.9 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.9.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 17
3.9.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 18
3.10 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.10.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.10.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.10.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.11 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.12 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.13 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.14 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.14.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.14.2 General-purpose timers (TIM2, 3, 14, 15, 16, 17) . . . . . . . . . . . . . . . . . 22
3.14.3 Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.14.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.14.5 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 54
6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 55
6.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.3.6 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.3.10 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
List of tables
List of figures
1 Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F091xB/xC microcontrollers.
This document should be read in conjunction with the STM32F0xxxx reference manual
(RM0091). The reference manual is available from the STMicroelectronics website
www.st.com.
For information on the ARM® Cortex®-M0 core, please refer to the Cortex®-M0 Technical
Reference Manual, available from the www.arm.com website.
2 Description
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3 Functional overview
3.2 Memories
The device has the following features:
• 32 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states and featuring embedded parity checking with exception generation for fail-critical
applications.
• The non-volatile memory is divided into two arrays:
– up to 256 Kbytes of embedded Flash memory for programs and data
– Option bytes
The option bytes are used to write-protect the memory (with 4 KB granularity) and/or
readout-protect the whole memory with the following options:
– Level 0: no readout protection
– Level 1: memory readout protection, the Flash memory cannot be read from or
written to if either debug features are connected or boot in RAM is selected
–
®
Level 2: chip readout protection, debug features (Cortex -M0 serial wire) and
boot in RAM selection disabled
threshold. The interrupt service routine can then generate a warning message and/or put
the MCU into a safe state. The PVD is enabled by software.
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
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Several prescalers allow the application to configure the frequency of the AHB and the APB
domains. The maximum frequency of the AHB and the APB domains is 48 MHz.
Additionally, also the internal RC 48 MHz oscillator can be selected for system clock or PLL
input source. This oscillator can be automatically fine-trimmed by the means of the CRS
peripheral using the external synchronization.
precise voltage of VREFINT is individually measured for each part by ST during production
test and stored in the system memory area. It is accessible in read-only mode.
Both comparators can wake up from STOP mode, generate interrupts and breaks for the
timers and can be also combined into a window comparator.
G1 3 3 3
G2 3 3 3
G3 3 3 2
G4 3 3 3
G5 3 3 3
G6 3 3 3
G7 3 0 0
G8 3 0 0
Number of capacitive
24 18 17
sensing channels
TIM2, TIM3
STM32F091xB/xC devices feature two synchronizable 4-channel general-purpose timers.
TIM2 is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TIM3 is based
on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. They feature 4 independent
channels each for input capture/output compare, PWM or one-pulse mode output. This
gives up to 12 input captures/output compares/PWMs on the largest packages.
The TIM2 and TIM3 general-purpose timers can work together or with the TIM1 advanced-
control timer via the Timer Link feature for synchronization or event chaining.
TIM2 and TIM3 both have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
Their counters can be frozen in debug mode.
TIM14
This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM14 features one single channel for input capture/output compare, PWM or one-pulse
mode output.
Its counter can be frozen in debug mode.
TIM15 has two independent channels, whereas TIM16 and TIM17 feature one single
channel for input capture/output compare, PWM or one-pulse mode output.
The TIM15, TIM16 and TIM17 timers can work together, and TIM15 can also operate
withTIM1 via the Timer Link feature for synchronization or event chaining.
TIM15 can be synchronized with TIM16 and TIM17.
TIM15, TIM16 and TIM17 have a complementary output with dead-time generation and
independent DMA request generation.
Their counters can be frozen in debug mode.
The RTC is an independent BCD timer/counter. Its main features are the following:
• calendar with subseconds, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format
• automatic correction for 28, 29 (leap year), 30, and 31 day of the month
• programmable alarm with wake up from Stop and Standby mode capability
• Periodic wakeup unit with programmable resolution and period.
• on-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize the RTC with a master clock
• digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal
inaccuracy
• Three anti-tamper detection pins with programmable filter. The MCU can be woken up
from Stop and Standby modes on tamper event detection
• timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be
woken up from Stop and Standby modes on timestamp event detection
• reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision
The RTC clock sources can be:
• a 32.768 kHz external crystal
• a resonator or oscillator
• the internal low-power RC oscillator (typical frequency of 40 kHz)
• the high-speed external clock divided by 32
In addition, I2C1 provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP
capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts
verifications and ALERT protocol management. I2C1 also has a clock domain independent
from the CPU clock, allowing the I2C1 to wake up the MCU from Stop mode on address
match.
The I2C peripherals can be served by the DMA controller.
Refer to Table 9 for the differences between I2C1 and I2C2.
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versions.
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Unless otherwise specified in brackets below the pin name, the pin function during and
Pin name
after reset is the same as the actual pin name
S Supply pin
Pin type I/O Input / output pin
FT 5 V-tolerant I/O
FTf 5 V-tolerant I/O, FM+ capable
I/O structure TTa 3.3 V-tolerant I/O directly connected to ADC
TC Standard 3.3 V I/O
RST Bidirectional reset pin with embedded weak pull-up resistor
Unless otherwise specified by a note, all I/Os are set as floating inputs during and after
Notes
reset.
Alternate
Functions selected through GPIOx_AFR registers
Pin functions
functions Additional
Functions directly selected/enabled through peripheral registers
functions
LQFP48/UFQFPN48
I/O structure
Pin type
Pin name
UFBGA100
Notes
WLCSP64
UFBGA64
LQFP100
LQFP64
(function upon
Additional
reset) Alternate functions
functions
LQFP48/UFQFPN48
I/O structure
Pin type
Pin name
UFBGA100
Notes
WLCSP64
UFBGA64
LQFP100
LQFP64
(function upon
Additional
reset) Alternate functions
functions
EVENTOUT,
J1 19 - - - - PF2 I/O FT USART7_TX, WKUP8
USART7_CK_RTS
K1 20 F1 12 G8 8 VSSA S - Analog ground
M1 21 H1 13 H8 9 VDDA S - Analog power supply
EVENTOUT,
L1 22 - - - - PF3 I/O FT USART7_RX,
USART6_CK_RTS
USART2_CTS,
RTC_ TAMP2,
TIM2_CH1_ETR,
WKUP1,
L2 23 G2 14 F7 10 PA0 I/O TTa TSC_G1_IO1,
ADC_IN0,
USART4_TX
COMP1_INM6
COMP1_OUT
USART2_RTS,
TIM2_CH2,
TIM15_CH1N, ADC_IN1,
M2 24 H2 15 F6 11 PA1 I/O TTa
TSC_G1_IO2, COMP1_INP
USART4_RX,
EVENTOUT
USART2_TX, TIM2_CH3,
ADC_IN2,
TIM15_CH1,
K3 25 F3 16 E5 12 PA2 I/O TTa WKUP4,
TSC_G1_IO3
COMP2_INM6
COMP2_OUT
USART2_RX,TIM2_CH4,
ADC_IN3,
L3 26 G3 17 H7 13 PA3 I/O TTa TIM15_CH2,
COMP2_INP
TSC_G1_IO4
D3 27 C2 18 G7 - VSS S - Ground
H3 28 D2 19 G6 - VDD S - Digital power supply
SPI1_NSS, I2S1_WS,
COMP1_INM4,
TIM14_CH1,
COMP2_INM4,
M3 29 H3 20 H6 14 PA4 I/O TTa TSC_G2_IO1,
ADC_IN4,
USART2_CK,
DAC_OUT1
USART6_TX
SPI1_SCK, I2S1_CK,
COMP1_INM5,
CEC,
COMP2_INM5,
K4 30 F4 21 F5 15 PA5 I/O TTa TIM2_CH1_ETR,
ADC_IN5,
TSC_G2_IO2,
DAC_OUT2
USART6_RX
LQFP48/UFQFPN48
I/O structure
Pin type
Pin name
UFBGA100
Notes
WLCSP64
UFBGA64
LQFP100
LQFP64
(function upon
Additional
reset) Alternate functions
functions
SPI1_MISO, I2S1_MCK,
TIM3_CH1, TIM1_BKIN,
TIM16_CH1,
L4 31 G4 22 G5 16 PA6 I/O TTa COMP1_OUT, ADC_IN6
TSC_G2_IO3,
EVENTOUT,
USART3_CTS
SPI1_MOSI, I2S1_SD,
TIM3_CH2, TIM14_CH1,
TIM1_CH1N, TIM17_CH1,
M4 32 H4 23 E4 17 PA7 I/O TTa ADC_IN7
COMP2_OUT,
TSC_G2_IO4,
EVENTOUT
K5 33 H5 24 H5 - PC4 I/O TTa EVENTOUT, USART3_TX ADC_IN14
TSC_G3_IO1, ADC_IN15,
L5 34 H6 25 F4 - PC5 I/O TTa
USART3_RX WKUP5
TIM3_CH3, TIM1_CH2N,
TSC_G3_IO2,
M5 35 F5 26 G4 18 PB0 I/O TTa ADC_IN8
EVENTOUT,
USART3_CK
TIM3_CH4,
USART3_RTS,
M6 36 G5 27 F3 19 PB1 I/O TTa ADC_IN9
TIM14_CH1, TIM1_CH3N,
TSC_G3_IO3
L6 37 G6 28 H4 20 PB2 I/O FT TSC_G3_IO4 -
TIM1_ETR,
M7 38 - - - - PE7 I/O FT -
USART5_CK_RTS
TIM1_CH1N,
L7 39 - - - - PE8 I/O FT -
USART4_TX
M8 40 - - - - PE9 I/O FT TIM1_CH1, USART4_RX -
TIM1_CH2N,
L8 41 - - - - PE10 I/O FT -
USART5_TX
M9 42 - - - - PE11 I/O FT TIM1_CH2, USART5_RX -
SPI1_NSS, I2S1_WS,
L9 43 - - - - PE12 I/O FT -
TIM1_CH3N
SPI1_SCK, I2S1_CK,
M10 44 - - - - PE13 I/O FT -
TIM1_CH3
LQFP48/UFQFPN48
I/O structure
Pin type
Pin name
UFBGA100
Notes
WLCSP64
UFBGA64
LQFP100
LQFP64
(function upon
Additional
reset) Alternate functions
functions
SPI1_MISO, I2S1_MCK,
M11 45 - - - - PE14 I/O FT -
TIM1_CH4
SPI1_MOSI, I2S1_SD,
M12 46 - - - - PE15 I/O FT -
TIM1_BKIN
SPI2_SCK, I2S2_CK,
I2C2_SCL,
L10 47 G7 29 G3 21 PB10 I/O FTf -
USART3_TX, CEC,
TSC_SYNC, TIM2_CH3
USART3_RX, TIM2_CH4,
EVENTOUT,
L11 48 H7 30 H3 22 PB11 I/O FTf -
TSC_G6_IO1,
I2C2_SDA
F12 49 D5 31 H2 23 VSS S - Ground
G12 50 E5 32 H1 24 VDD S - Digital power supply
TIM1_BKIN, TIM15_BKIN,
SPI2_NSS, I2S2_WS,
L12 51 H8 33 G2 25 PB12 I/O FT USART3_CK, -
TSC_G6_IO2,
EVENTOUT
SPI2_SCK, I2S2_CK,
I2C2_SCL,
K12 52 G8 34 F2 26 PB13 I/O FTf USART3_CTS, -
TIM1_CH1N,
TSC_G6_IO3
SPI2_MISO, I2S2_MCK,
I2C2_SDA,
K11 53 F8 35 G1 27 PB14 I/O FTf USART3_RTS, -
TIM1_CH2N, TIM15_CH1,
TSC_G6_IO4
SPI2_MOSI, I2S2_SD,
TIM1_CH3N, WKUP7,
K10 54 F7 36 F1 28 PB15 I/O FT
TIM15_CH1N, RTC_REFIN
TIM15_CH2
K9 55 - - - - PD8 I/O FT USART3_TX -
K8 56 - - - - PD9 I/O FT USART3_RX -
J12 57 - - - - PD10 I/O FT USART3_CK -
J11 58 - - - - PD11 I/O FT USART3_CTS -
LQFP48/UFQFPN48
I/O structure
Pin type
Pin name
UFBGA100
Notes
WLCSP64
UFBGA64
LQFP100
LQFP64
(function upon
Additional
reset) Alternate functions
functions
USART3_RTS,
J10 59 - - - - PD12 I/O FT TSC_G8_IO1, -
USART8_CK_RTS
TSC_G8_IO2,
H12 60 - - - - PD13 I/O FT -
USART8_TX
TSC_G8_IO3,
H11 61 - - - - PD14 I/O FT -
USART8_RX
TSC_G8_IO4,
H10 62 - - - - PD15 I/O FT CRS_SYNC, -
USART7_CK_RTS
(3)
E12 63 F6 37 E1 - PC6 I/O FT TIM3_CH1, USART7_TX -
E11 64 E7 38 D1 - PC7 I/O FT (3) TIM3_CH2, USART7_RX -
(3)
E10 65 E8 39 E2 - PC8 I/O FT TIM3_CH3, USART8_TX -
(3)
D12 66 D8 40 E3 - PC9 I/O FT TIM3_CH4, USART8_RX -
USART1_CK, TIM1_CH1,
D11 67 D7 41 D2 29 PA8 I/O FT (3)
EVENTOUT, MCO, -
CRS_SYNC
USART1_TX, TIM1_CH2,
D10 68 C7 42 C1 30 PA9 I/O FT (3)
TIM15_BKIN, MCO, -
TSC_G4_IO1, I2C1_SCL
USART1_RX, TIM1_CH3,
C12 69 C6 43 C2 31 PA10 I/O FT (3)
TIM17_BKIN, -
TSC_G4_IO2, I2C1_SDA
CAN_RX, USART1_CTS,
(3) TIM1_CH4, COMP1_OUT,
B12 70 C8 44 D3 32 PA11 I/O FT -
TSC_G4_IO3,
EVENTOUT, I2C2_SCL
CAN_TX, USART1_RTS,
(3) TIM1_ETR, COMP2_OUT,
A12 71 B8 45 B1 33 PA12 I/O FT -
TSC_G4_IO4,
EVENTOUT, I2C2_SDA
(3)
A11 72 A8 46 C3 34 PA13 I/O FT (4) IR_OUT, SWDIO -
LQFP48/UFQFPN48
I/O structure
Pin type
Pin name
UFBGA100
Notes
WLCSP64
UFBGA64
LQFP100
LQFP64
(function upon
Additional
reset) Alternate functions
functions
(3)
A10 76 A7 49 B3 37 PA14 I/O FT (4) USART2_TX, SWCLK -
SPI1_NSS, I2S1_WS,
USART2_RX,
(3)
A9 77 A6 50 A2 38 PA15 I/O FT USART4_RTS, -
TIM2_CH1_ETR,
EVENTOUT
(3) USART3_TX,
B11 78 B7 51 A3 - PC10 I/O FT -
USART4_TX
(3) USART3_RX,
C10 79 B6 52 C4 - PC11 I/O FT -
USART4_RX
USART3_CK,
B10 80 C5 53 B4 - PC12 I/O FT (3)
USART4_CK, -
USART5_TX
(3) USART3_RTS,
C8 83 B5 54 A4 - PD2 I/O FT -
TIM3_ETR, USART5_RX
SPI2_MISO, I2S2_MCK,
B8 84 - - - - PD3 I/O FT -
USART2_CTS
SPI2_MOSI, I2S2_SD,
B7 85 - - - - PD4 I/O FT -
USART2_RTS
A6 86 - - - - PD5 I/O FT USART2_TX -
B6 87 - - - - PD6 I/O FT USART2_RX -
A5 88 - - - - PD7 I/O FT USART2_CK -
SPI1_SCK, I2S1_CK,
A8 89 A5 55 D4 39 PB3 I/O FT TIM2_CH2, TSC_G5_IO1, -
EVENTOUT, USART5_TX
SPI1_MISO, I2S1_MCK,
TIM17_BKIN, TIM3_CH1,
A7 90 A4 56 D5 40 PB4 I/O FT -
TSC_G5_IO2,
EVENTOUT, USART5_RX
LQFP48/UFQFPN48
I/O structure
Pin type
Pin name
UFBGA100
Notes
WLCSP64
UFBGA64
LQFP100
LQFP64
(function upon
Additional
reset) Alternate functions
functions
SPI1_MOSI, I2S1_SD,
I2C1_SMBA,
C5 91 C4 57 C5 41 PB5 I/O FT TIM16_BKIN, WKUP6
TIM3_CH2,
USART5_CK_RTS
I2C1_SCL, USART1_TX,
B5 92 D3 58 A5 42 PB6 I/O FTf TIM16_CH1N, -
TSC_G5_I03
I2C1_SDA, USART1_RX,
USART4_CTS,
B4 93 C3 59 B5 43 PB7 I/O FTf -
TIM17_CH1N,
TSC_G5_IO4
Boot memory
A4 94 B4 60 C6 44 PF11-BOOT0 I/O FT -
selection
I2C1_SCL, CEC,
A3 95 B3 61 A6 45 PB8 I/O FTf TIM16_CH1, TSC_SYNC, -
CAN_RX
SPI2_NSS, I2S2_WS,
I2C1_SDA, IR_OUT,
B3 96 A3 62 B6 46 PB9 I/O FTf -
TIM17_CH1, EVENTOUT,
CAN_TX
C3 97 - - - - PE0 I/O FT EVENTOUT, TIM16_CH1 -
A2 98 - - - - PE1 I/O FT EVENTOUT, TIM17_CH1 -
D3 99 D4 63 A7 47 VSS S - Ground
C4 100 E4 64 A8 48 VDD S - Digital power supply
1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF.
- These GPIOs must not be used as current sources (e.g. to drive an LED).
2. After the first RTC domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content
of the RTC registers which are not reset by the system reset. For details on how to manage these GPIOs, refer to the RTC
domain and RTC register descriptions in the reference manual.
3. PC6, PC7, PC8, PC9, PA8, PA9, PA10, PA11, PA12, PA13, PF6, PA14, PA15, PC10, PC11, PC12, PD0, PD1 and PD2 I/Os
are supplied by VDDIO2
4. After reset, these pins are configured as SWDIO and SWCLK alternate functions, and the internal pull-up on the SWDIO pin
and the internal pull-down on the SWCLK pin are activated.
STM32F091xB STM32F091xC
STM32F091xB STM32F091xC
Table 16. Alternate functions selected through GPIOC_AFR registers for port C
Pin name AF0 AF1 AF2
Table 17. Alternate functions selected through GPIOD_AFR registers for port D
Pin name AF0 AF1 AF2
Table 18. Alternate functions selected through GPIOE_AFR registers for port E
Pin name AF0 AF1
Table 19. Alternate functions selected through GPIOF_AFR registers for port F
Pin
AF0 AF1 AF2
name
5 Memory mapping
To the difference of STM32F091xC memory map in Figure 10, the two bottom code memory
spaces of STM32F091xB end at 0x0001 FFFF and 0x0801 FFFF, respectively.
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Figure 11. Pin loading conditions Figure 12. Pin input voltage
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Caution: Each power supply pair (VDD/VSS, VDDA/VSSA etc.) must be decoupled with filtering ceramic
capacitors as shown above. These capacitors must be placed as close as possible to, or
below, the appropriate pins on the underside of the PCB to ensure the good functionality of
the device.
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ΣIVDD Total current into sum of all VDD power lines (source)(1) 120
(1)
ΣIVSS Total current out of sum of all VSS ground lines (sink) -120
(1)
IVDD(PIN) Maximum current into each VDD power pin (source) 100
IVSS(PIN) Maximum current out of each VSS ground pin (sink)(1) -100
Output current sunk by any I/O and control pin 25
IIO(PIN)
Output current source by any I/O and control pin -25
(2)
Total output current sunk by sum of all I/Os and control pins 80
ΣIIO(PIN) Total output current sourced by sum of all I/Os and control pins(2) -80 mA
Total output current sourced by sum of all I/Os supplied by VDDIO2 -40
Injected current on FT and FTf pins -5/+0(4)
IINJ(PIN)(3) Injected current on TC and RST pin ±5
Injected current on TTa pins(5) ±5
ΣIINJ(PIN) Total injected current (sum of all I/O and control pins)(6) ± 25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages.
3. A positive injection is induced by VIN > VDDIOx while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be
exceeded. Refer to Table 21: Voltage characteristics for the maximum allowed input voltage values.
4. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
value.
5. On these I/Os, a positive injection is induced by VIN > VDDA. Negative injection disturbs the analog performance of the
device. See note (2) below Table 59: ADC accuracy.
6. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).
VREFINT Internal reference voltage –40 °C < TA < +105 °C 1.2 1.23 1.25 V
ADC_IN17 buffer startup
tSTART - - - 10(1) µs
time
ADC sampling time when
tS_vrefint reading the internal - 4(1) - - µs
reference voltage
Internal reference voltage
∆VREFINT spread over the VDDA = 3 V - - 10(1) mV
temperature range
Table 29. Typical and maximum current consumption from VDD supply at VDD = 3.6 V
Parameter All peripherals enabled All peripherals disabled
Symbol
HSI48 48 MHz 26.9 29.5 30.3 30.6 14.7 16.1 16.3 16.4
48 MHz 26.7 29.2 30.1 30.3 14.6 16.0 16.2 16.2
code executing from Flash memory
HSE bypass,
Supply current in Run mode
HSE bypass, 8 MHz 4.8 5.3 5.5 5.9 3.0 3.2 3.3 3.5
PLL off 1 MHz 1.3 1.5 1.6 1.9 1.0 1.1 1.2 1.4
48 MHz 26.8 29.4 30.2 30.5 14.7 16.1 16.3 16.3
HSI clock,
32 MHz 18.1 20.5 20.9 21.2 10.2 10.9 11.0 11.1
PLL on
24 MHz 14.1 15.9 16.2 16.4 8.6 9.1 9.2 9.5
HSI clock,
8 MHz 4.9 5.4 5.6 5.9 3.1 3.2 3.4 3.5
PLL off
mA
HSI48 48 MHz 26.3 28.7 29.5 29.7 14.0 15.3 15.5 15.7
48 MHz 26.0 28.4 29.2 29.4 13.9 15.2 15.4 15.6
HSE bypass,
Supply current in Run mode,
PLL on
24 MHz 13.3 15.1 15.5 15.6 7.6 8.2 8.4 8.5
HSE bypass, 8 MHz 4.4 4.9 5.1 5.3 2.4 2.6 2.8 2.9
IDD PLL off 1 MHz 0.9 0.9 1.0 1.2 0.5 0.6 0.7 0.8
48 MHz 26.1 28.5 29.3 29.5 13.9 15.3 15.5 15.6
HSI clock,
32 MHz 17.5 19.6 20.0 20.3 9.7 10.4 10.5 10.6
PLL on
24 MHz 13.3 15.3 15.7 15.8 7.7 8.2 8.5 8.6
HSI clock,
8 MHz 4.6 5.0 5.2 5.4 2.5 2.7 2.9 3.0
PLL off
HSI48 48 MHz 17.0 18.7 19.1 19.4 3.2 3.5 3.6 3.7
48 MHz 16.9 18.5 19.0 19.3 3.1 3.5 3.5 3.6
HSE bypass,
Supply current in Sleep mode
HSE bypass, 8 MHz 2.9 3.2 3.4 3.7 0.8 0.9 0.9 1.0
PLL off 1 MHz 0.4 0.6 0.6 0.7 0.3 0.4 0.4 0.5 mA
1. Data based on characterization results, not tested in production unless otherwise specified.
Table 30. Typical and maximum current consumption from the VDDA supply
VDDA = 2.4 V VDDA = 3.6 V
Para-meter
HSI48 48 MHz 312 333 338 347 316 334 341 350
48 MHz 147 168 178 181 160 181 192 197
HSE
Supply
bypass, 32 MHz 101 119 125 127 109 127 135 138
current in
PLL on
Run or 24 MHz 80 96 98 100 87 101 106 109
Sleep
HSE 8 MHz 2.8 3.5 3.7 3.9 3.7 4.3 4.6 4.7
mode,
bypass,
IDDA code 1 MHz 2.7 3.2 3.5 3.8 3.3 3.9 4.4 4.7 µA
PLL off
executing
from 48 MHz 214 243 254 259 235 262 275 281
Flash HSI clock,
memory 32 MHz 166 193 203 204 185 207 216 220
PLL on
or RAM 24 MHz 144 171 177 178 161 180 187 190
HSI clock,
8 MHz 65 83 85 86 77 90 92 93
PLL off
1. Current consumption from the VDDA supply is independent of whether the digital peripherals are enabled or disabled, being
in Run or Sleep mode or executing from Flash memory or RAM. Furthermore, when the PLL is off, IDDA is independent from
the frequency.
2. Data based on characterization results, not tested in production unless otherwise specified.
Table 31. Typical and maximum consumption in Stop and Standby modes
Typ @VDD (VDD = VDDA) Max(1)
Sym- Para-
Conditions Unit
bol meter TA = TA = TA =
2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V
25 °C 85 °C 105 °C
Regulator in run
Supply mode, all 14.6 14.8 14.9 15.1 15.4 15.8 18 51 97
current in oscillators OFF
Stop Regulator in low-
mode power mode, all 3.3 3.4 3.6 3.8 4.1 4.4 11 53 106
IDD oscillators OFF
current in
Stop Regulator in
mode low-power
mode, all 1.9 2.0 2.2 2.3 2.4 2.6 3.8 4.2 4.6
oscillators
OFF µA
current in
Stop Regulator in
mode low-power
mode, all 1.2 1.2 1.3 1.3 1.4 1.4 - - -
oscillators
OFF
Table 32. Typical and maximum current consumption from the VBAT supply
Typ @ VBAT Max(1)
1.65 V
2.7 V
1.8 V
2.4 V
3.3 V
3.6 V
TA = TA = TA =
25 °C 85 °C 105 °C
Table 33. Typical current consumption, code executing from Flash memory,
running from HSE 8 MHz crystal
Typical consumption in Typical consumption in
Run mode Sleep mode
Symbol Parameter fHCLK Unit
Peripherals Peripherals Peripherals Peripherals
enabled disabled enabled disabled
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously (see
Table 35: Peripheral current consumption), the I/Os used by an application also contribute
to the current consumption. When an I/O pin switches, it uses the current from the I/O
supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load
(internal or external) connected to the pin:
I SW = V DDIOx × f SW × C
where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDDIOx is the I/O supply voltage
fSW is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = CINT + CEXT + CS
CS is the PCB board capacitance including the pad pin.
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
4 MHz 0.07
8 MHz 0.15
VDDIOx = 3.3 V
C =CINT 16 MHz 0.31
24 MHz 0.53
48 MHz 0.92
4 MHz 0.18
4 MHz 0.66
VDDIOx = 2.4 V
CEXT = 47 pF 8 MHz 1.43
C = CINT + CEXT+ CS 16 MHz 2.45
C = Cint
24 MHz 4.97
1. CS = 7 pF (estimated value).
BusMatrix(1) 3.1
CRC 2.0
DMA1 5.5
DMA2 5.1
Flash memory interface 15.4
GPIOA 5.5
GPIOB 5.4
AHB µA/MHz
GPIOC 3.2
GPIOD 3.1
GPIOE 4.0
GPIOF 2.5
SRAM 0.8
TSC 5.5
All AHB peripherals 61.0
Regulator in run
3.2 3.1 2.9 2.9 2.8 5
Wakeup from Stop mode
tWUSTOP
mode Regulator in low
7.0 5.8 5.2 4.9 4.6 9
power mode
µs
Wakeup from
tWUSTANDBY - 60.4 55.6 53.5 52 51 -
Standby mode
Wakeup from Sleep
tWUSLEEP - 4 SYSCLK cycles -
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For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 20 pF range (Typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 17). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
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Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
Figure 19. HSI oscillator accuracy characterization results for soldered parts
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TA = 25 °C -2.8 - 2.9 %
tsu(HSI48) HSI48 oscillator startup time - - - 6(2) µs
HSI48 oscillator power
IDDA(HSI48) - - 312 350(2) µA
consumption
1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.
3. Data based on characterization results, not tested in production.
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Software recommendations
The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter
• Unexpected reset
• Critical Data corruption (for example control registers)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
0.1 to 30 MHz 3
VDD = 3.6 V, TA = 25 °C,
LQFP100 package 30 to 130 MHz 23 dBµV
SEMI Peak level
compliant with 130 MHz to 1 GHz 15
IEC 61967-2
EMI Level 4 -
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
• A supply overvoltage is applied to each power supply pin.
• A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Weak pull-up
RPU equivalent resistor VIN = VSS 25 40 55 kΩ
(3)
Weak pull-down
RPD equivalent VIN = - VDDIOx 25 40 55 kΩ
resistor(3)
CIO I/O pin capacitance - - 5 - pF
1. Data based on design simulation only. Not tested in production.
2. The leakage could be higher than the maximum value, if negative current is injected on adjacent pins. Refer to Table 52:
I/O current injection susceptibility.
3. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
All I/Os are CMOS- and TTL-compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 22 for standard I/Os, and in Figure 23 for
5 V-tolerant I/Os. The following curves are design simulation results, not tested in
production.
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VOL Output low level voltage for an I/O pin CMOS port(2) - 0.4
|IIO| = 8 mA V
VOH Output high level voltage for an I/O pin VDDIOx ≥ 2.7 V VDDIOx–0.4 -
VOL Output low level voltage for an I/O pin TTL port(2) - 0.4
|IIO| = 8 mA V
VOH Output high level voltage for an I/O pin VDDIOx ≥ 2.7 V 2.4 -
VOL(3) Output low level voltage for an I/O pin |IIO| = 20 mA - 1.3
V
VOH(3) Output high level voltage for an I/O pin VDDIOx ≥ 2.7 V VDDIOx–1.3 -
VOL(3) Output low level voltage for an I/O pin |IIO| = 6 mA - 0.4
V
VOH(3) Output high level voltage for an I/O pin VDDIOx ≥ 2 V VDDIOx–0.4 -
VOL(4) Output low level voltage for an I/O pin - 0.4 V
|IIO| = 4 mA
VOH(4) Output high level voltage for an I/O pin VDDIOx–0.4 - V
|IIO| = 20 mA
Output low level voltage for an FTf I/O pin in - 0.4 V
VOLFm+(3) VDDIOx ≥ 2.7 V
Fm+ mode
|IIO| = 10 mA - 0.4 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 21:
Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ΣIIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. Data based on characterization results. Not tested in production.
4. Data based on characterization results. Not tested in production.
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 24 and
Table 55, respectively. Unless otherwise specified, the parameters given are derived from
tests performed under the ambient temperature and supply voltage conditions summarized
in Table 24: General operating conditions.
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fADC = 14 MHz,
- - 823 kHz
fTRIG(2) External trigger frequency 12-bit resolution
12-bit resolution - - 17 1/fADC
VAIN Conversion voltage range - 0 - VDDA V
See Equation 1 and
RAIN(2) External input impedance - - 50 kΩ
Table 58 for details
Sampling switch
RADC(2) - - - 1 kΩ
resistance
Internal sample and hold
CADC(2) - - - 8 pF
capacitor
fADC = 14 MHz 5.9 µs
tCAL(2)(3) Calibration time
- 83 1/fADC
1.5 ADC 1.5 ADC
ADC clock = HSI14 cycles + 2 - cycles + 3 -
fPCLK cycles fPCLK cycles
ADC_DR register ready
WLATENCY(2)(4) fPCLK
latency ADC clock = PCLK/2 - 4.5 -
cycle
fPCLK
ADC clock = PCLK/4 - 8.5 -
cycle
fADC = fPCLK/2 = 14 MHz 0.196 µs
fADC = fPCLK/2 5.5 1/fPCLK
tlatr(2) Trigger conversion latency fADC = fPCLK/4 = 12 MHz 0.219 µs
fADC = fPCLK/4 10.5 1/fPCLK
fADC = fHSI14 = 14 MHz 0.179 - 0.250 µs
ADC jitter on trigger
JitterADC fADC = fHSI14 - 1 - 1/fHSI14
conversion
fADC = 14 MHz 0.107 - 17.1 µs
tS(2) Sampling time
- 1.5 - 239.5 1/fADC
tSTAB(2) Stabilization time - 14 1/fADC
fADC = 14 MHz,
1 - 18 µs
Total conversion time 12-bit resolution
tCONV(2)
(including sampling time) 14 to 252 (tS for sampling +12.5 for
12-bit resolution 1/fADC
successive approximation)
1. During conversion of the sampled value (12.5 x ADC clock period), an additional consumption of 100 µA on IDDA and 60 µA
on IDD should be taken into account.
2. Guaranteed by design, not tested in production.
3. Specified value includes only ADC timing. It does not include the latency of the register access.
4. This parameter specify latency for transfer of the conversion result to the ADC_DR register. EOC flag is set at this time.
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-robust) analog input
pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog
input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject
negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.14 does not affect the ADC
accuracy.
3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges.
4. Data based on characterization results, not tested in production.
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1. Refer to Table 57: ADC characteristics for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
No hysteresis
- - 0 -
(COMPxHYST[1:0]=00)
High speed mode 3 13
Low hysteresis
8
(COMPxHYST[1:0]=01) All other power 5 10
modes
Vhys Comparator hysteresis High speed mode 7 26 mV
Medium hysteresis
15
(COMPxHYST[1:0]=10) All other power 9 19
modes
High speed mode 18 49
High hysteresis
31
(COMPxHYST[1:0]=11) All other power 19 40
modes
1. Data based on characterization results, not tested in production.
- - 1 - tTIMxCLK
tres(TIM) Timer resolution time
fTIMxCLK = 48 MHz - 20.8 - ns
Timer external clock - - fTIMxCLK/2 - MHz
fEXT frequency on CH1 to
CH4 fTIMxCLK = 48 MHz - 24 - MHz
/4 0 0.1 409.6
/8 1 0.2 819.2
/16 2 0.4 1638.4
/32 3 0.8 3276.8 ms
/64 4 1.6 6553.6
/128 5 3.2 13107.2
/256 6 or 7 6.4 26214.4
1. These timings are given for a 40 kHz clock but the microcontroller internal RC frequency can vary from 30
to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing
of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.
1 0 0.0853 5.4613
2 1 0.1706 10.9226
ms
4 2 0.3413 21.8453
8 3 0.6826 43.6906
SPI/I2S characteristics
Unless otherwise specified, the parameters given in Table 68 for SPI or in Table 69 for I2S
are derived from tests performed under the ambient temperature, fPCLKx frequency and
supply voltage conditions summarized in Table 24: General operating conditions.
Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S).
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1. Measurement points are done at CMOS levels: 0.3 × VDDIOx and 0.7 × VDDIOx.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
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7 Package information
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A4 - 0.320 - - 0.0126 -
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Pitch 0.5
Dpad 0.280 mm
0.370 mm typ. (depends on the solder mask
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Stencil opening 0.280 mm
Stencil thickness Between 0.100 mm and 0.125 mm
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
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1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
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b 0.170 0.220 0.270 0.0067 0.0087 0.0106
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D 15.800 16.000 16.200 0.6220 0.6299 0.6378
D1 13.800 14.000 14.200 0.5433 0.5512 0.5591
D3 - 12.000 - - 0.4724 -
E 15.800 16.000 16.200 0.6220 0.6299 0.6378
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Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
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Stencil opening 0.280 mm
Stencil thickness Between 0.100 mm and 0.125 mm
Pad trace width 0.100 mm
Device marking
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
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samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
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The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
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chain operations, are not indicated below.
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1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
Samples to run qualification activity.
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A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D - 12.000 - - 0.4724 -
D1 - 10.000 - - 0.3937 -
D3 - 7.500 - - 0.2953 -
E - 12.000 - - 0.4724 -
E1 - 10.000 - - 0.3937 -
E3 - 7.500 - - 0.2953 -
e - 0.500 - - 0.0197 -
K 0° 3.5° 7° 0° 3.5° 7°
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
ccc - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
DLF
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
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samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
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b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 8.800 9.000 9.200 0.3465 0.3543 0.3622
D1 6.800 7.000 7.200 0.2677 0.2756 0.2835
D3 - 5.500 - - 0.2165 -
E 8.800 9.000 9.200 0.3465 0.3543 0.3622
E1 6.800 7.000 7.200 0.2677 0.2756 0.2835
E3 - 5.500 - - 0.2165 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0° 3.5° 7° 0° 3.5° 7°
ccc - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
DLG
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
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samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
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The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
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usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
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8 Ordering information
For a list of available options (memory, package, and so on) or for further information on any
aspect of this device, please contact your nearest ST sales office.
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = General-purpose
Sub-family
091= STM32F091xx
Pin count
C = 48 pins
R = 64 pins
V = 100 pins
Package
H = UFBGA
T = LQFP
U = UFQFPN
Y = WLCSP
Temperature range
6 = –40 to 85 °C
7 = –40 to 105 °C
Options
xxx = code ID of programmed parts (includes packing type)
TR = tape and reel packing
blank = tray packing
9 Revision history
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
Authorized Distributor
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STM32F091CCT7 STM32F091VBT6 STM32F091CCU7 STM32F091RCH6 STM32F091VBT7 STM32F091VCH6
STM32F091CBT6 STM32F091CBU6 STM32F091RBT6 STM32F091VCH7 STM32F091RCT6TR STM32F091CCU6
STM32F091RCT7 STM32F091RCH7 STM32F091CCU6TR STM32F091VCT7 STM32F091CCT6J
STM32F091CBT6TR STM32F091RCT6J STM32F091VCT7TR STM32F091CCU7TR STM32F091RCH6TR
STM32F091RCY7TR STM32F091CBT7TR STM32F091CBT7