DLD Lab Manual 10 Labs (Unitrain) PDF
DLD Lab Manual 10 Labs (Unitrain) PDF
DLD Lab Manual 10 Labs (Unitrain) PDF
Eqipment detail
Technical data:
Operating voltage : + 5V DC
Function groups : 2x inverters (NOT)
2x AND gates 2x OR gates
3x NAND gates 3x NOR gates
1x XOR gate 1x EXNOR gate
1x sequence of gates with
AND, OR, NAND, NOR, EXOR gates
7 simulated faults
in the sequence of gates
ATTENTION
Due to the fault simulation, this card has
connections to the contacts of relays 3 and 4 of
the UniTr@in-I. For that reason no external
connection to the contacts of these two relays
is permitted. If necessary remove any existing
connections!
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Digital Logic Design Lab EE Department UET FSD campus
2. SO4201-8R JK flip-flops
Technical data:
Description of SO4201-8R
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Digital Logic Design Lab EE Department UET FSD campus
Operating voltage: + 5V
- 4 NAND gates
- 8 Inverters
- 2 simulated faults
Description of SO4201-9T:
ATTENTION: Due to the fault simulation, this card has connections to the
contacts of relays 1 and 2 of the UniTr@in-I. For that reason no external connection to
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the contacts of these two relays is permitted. If necessary remove any existing
connections!
Technical data:
Operating voltage: + 5V
Serial addition :
In practice, it is often unnecessary to provide a
separate adding circuit for each bit (parallel
processing), instead a shift register is used for
serial addition. For more detailed information
read the 4-bit adder
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Digital Logic Design Lab EE Department UET FSD campus
Parallel addition :
If a separate adder circuit is used for each bit, parallel addition takes place. There exist
standard parallel adder ICs. For more detailed information read the 4-bit adder
Fault simulation :
The card allows for 3 simulated faults to be activated individually.
BEWARE The simulated faults mean that the card uses the connections to
UniTr@in-I relays 1 and 2. Therefore, the card may not be connected to any external
circuitry using the contacts of these two relays. Any such connection should be
eliminated
Operating voltage: + 5V
The circuit board consists of an integrated synchronous binary counter (74 HC 191)
which counts up/down in 4-bit binary code. [ logic diagram of the IC ] In addition, there is
a 74HC00 IC for debouncing button S3 on the circuit board. The state of the counter is
indicated by 6 LEDs.
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Digital Logic Design Lab EE Department UET FSD campus
Technical data:
Operating voltage: + 5V
Disable
Enable
Dimensions: Eurocard 160 x 100 mm
Count down
The circuit board consists of an integrated synchronous binary counter (74 HC 191)
which counts up/down in 4-bit binary code. [ logic diagram of the IC ]
In addition, there is a 74HC00 IC for debouncing button S3 on the circuit board. The
state of the counter is indicated by 6 LEDs.
Button S3 is connected directly to the CP input (clock) and provides the clock pulse.
This allows a detailed investigation of the counter's response to falling and rising edges
of the clock pulse.
Switch S1 is connected to the CE input (count enable) and enables the clock input.
The current signal state can be stored when this switch is on.
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Digital Logic Design Lab EE Department UET FSD campus
Name
Reg. #
Marks
Lab 1
Objective:
Theory:
Binary logic deals with variables that take on two discrete values and with opdona hat assume
Logical meaning. The two values the variables assume may be called by Different names (true
and false, yes and no, etc.), but for our purpose , it is convenient to thiak in terms of bits and
assign the values 1 and 0. The binary logic introduced in this section is equivalent to an algebra
called Boolean algebra
Binary logic consists of binary variables and a set of logical operation. The variables are
designated by letters of the alphabet, such as A, B. C.x.y, i,etc., with each variable having
moaodonly two distinct possibie values: 1 and 0,Them are three bariclogicalaperafionr: AND.
OR and NOT
NOT (Negation)
The two symbols shown are used to represent the NOT function.
According to DIN, the second variation Q = ¬A is preferred.
The first variation Q = A is also permissible. It continues to be
used for reasons of clarity.
Exercise 1:
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Q0 I0
A Q=A
Exercise 2
Q0 I1 I0
A Z=A
1
Complete the equations:
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Z= ; Q= = =
AND
It should be noted that although the Boolean AND function bears certain
similarities to algebraic multiplication, there are also distinct differences.
Exercise 3:
Q1 Q0
I0
B A Q
0 0
0 1
1 0
1 1
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Exercise 4:
Construct the following experiments and note down the results. Describe in a few words the rules
that you discover.
Result: A · 0 =
Result: A·1=
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Result: A·A=
Result: A · A’ =
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OR
Exercise 5:
Experiment set-up
Q1 Q0
I0
B A Q
0 0
0 1
1 0
1 1
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Exercise 6:
Construct the following experiments and note down the results. Describe in a few words the rules
that you discover.
Result: A0=
Result: 1A=
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c) ORing A A (Tautology)
Result: AA=
Result: AA=
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Lab evaluation:
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Name
Reg. #
Marks
Lab 2
Objective:
AB=BA A B C = A (B C) = (A B) C
Distributive laws
A · (B C) = (A · B) (A · C)
A (B · C) = (A B) · (A C)
A · (A B) = A A·B = AB
A · (A B) = A · B A B =A·B
A (A · B) = A B
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Commutative laws
A·B=B·A
Exercise 1:
Experiment set-up
Table 1
Q1 Q0
I1 I0
B A Q2 Q1
0 0
0 1
1 0
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Digital Logic Design Lab EE Department UET FSD campus
1 1
↑ ↑
B·A A·B
A B=B A
Exercise 2:
Experiment set-up
Table 2
Q1 Q0
I1 I0
B A Q2 Q1
0 0
0 1
1 0
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1 1
↑ ↑
BA AB
Associative laws
A · B · C = A · (B · C) = (A · B) · C
Exercise 1:
Experiment set-up
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Digital Logic Design Lab EE Department UET FSD campus
Table 1 re re
Fig.1.1 Fig.1.2
Q2 Q1 Q0
I0 I0
C B A Q1 Q2
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
↑ ↑
A·(B·C) (A·B)·C
A B C = A (B C) = (A B) C
Exercise 2:
Experiment set-up
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Digital Logic Design Lab EE Department UET FSD campus
Table 2 re re
Fig.2.1 Fig.2.2
Q2 Q1 Q0
I0 I0
C B A Q1 Q2
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
↑ ↑
A(BC) (AB)C
Distributive laws
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A · (B C) = (A · B) (A · C)
Exercise 1:
Experiment set-up
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Table 1 re re
Fig.1.1 Fig.1.2
Q2 Q1 Q0
I0 I0
C B A Q1 Q2
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Q1 = A·(B C)
Q2 = (A·B) A·C)
Exercise 2:
Experiment set-up
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Digital Logic Design Lab EE Department UET FSD campus
Table 2 re re
Fig.2.1 Fig.2.2
Q2 Q1 Q0
I0 I0
C B A Q1 Q2
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Q1 = A (B · C)
Q2 = (A B) · A C)
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Digital Logic Design Lab EE Department UET FSD campus
Absorption
In the following exercises, we will specifically
investigate AND/OR/NOT sequences with two input
variables that can be simplified.
Exercise 1
Experiment set-up
Table 1
Q1 Q0
I0
B A Q
Karnaugh map 1
0 0 A A
B
0 1
B
1 0
1 1
Q = A (A · B) =
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Digital Logic Design Lab EE Department UET FSD campus
Exercise 2 A · (A B) = ?
Experiment set-up
Table 2
Q1 Q0
I0
B A Q
Karnaugh map 2
0 0 A A
B
0 1
B
1 0
1 1
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Digital Logic Design Lab EE Department UET FSD campus
Q = A · (A B) =
Exercise 3 A·(AB)=?
Experiment set-up
Table 3
Q1 Q0
I0
B A Q
Karnaugh map 3
0 0 A A
B
0 1
B
1 0
1 1
Q=A·(AB)=
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Digital Logic Design Lab EE Department UET FSD campus
Exercise 4 A(A·B)=?
Experiment set-up
Table 4
Q1 Q0
I0
B A Q
Karnaugh map 4
0 0 A A
B
0 1
B
1 0
1 1
+
Q = A (A · B) =
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Digital Logic Design Lab EE Department UET FSD campus
Lab Evaluation:
1. Write the commutative law in your own words. Is this law the same as the commutative law for
normal multiplication?
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
_____________________________________________________________________________
2. Write the associative law in your own words. Is this law the same as the associative law for
normal multiplication & normal addition?
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
3. Write the distributive law in your own words. Is this law the same as the distributive law in
normal algebra?
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________
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Digital Logic Design Lab EE Department UET FSD campus
Name
Reg. #
Marks
Lab 3
To understand NegatioN laws (De MorgaN's laws) aND ex-or and ex-nor
operation
Objective:
Negation of logic
Antivalence and Equivalence operation
These two experiments are intended to provide confirmation of two laws of De Morgan.
Experiment set-up
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Digital Logic Design Lab EE Department UET FSD campus
Q1= A · B Q2 = A B
In this experiment, both sides of the equation are experimentally reproduced and can be directly
compared with one another. Confirm the validity of the negation law from the table.
Table 1
Q1 Q0
I1 I0
B A Q2 Q1
0 0
0 1
1 0
1 1
↑ ↑
AB A·B
Experiment set-up
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Digital Logic Design Lab EE Department UET FSD campus
In this experiment, both sides of the equation are experimentally reproduced and can be directly
compared with one another.
Table 2
Q1 Q0
I1 I0
B A Q2 Q1
0 0
0 1
1 0
1 1
↑ ↑
A·B AB
BOOLEAN OPERATIONS
EXOR EXNOR
ANTIVALENCE EQUIVALENCE
EXOR (Antivalence)
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Exercise 1:
Experiment set-up
Table 1
Q1 Q0
I0
B A Q
0 0
0 1
1 0
1 1
EXOR
Exercise 2:
Experiment set-up
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Digital Logic Design Lab EE Department UET FSD campus
Table 2
Q1 Q0
I0
B A Q
0 0
0 1
1 0
1 1
↑
A·B A·B
Confirm from the values in Tables 1 and 2 that the EXOR function can be represented by the
function Q = A·B A·B.
EXNOR (Equivalence)
The symbol for EXNOR is that shown in the illustration. The operation is termed
"Exclusive NOR" or "Equivalence".
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Digital Logic Design Lab EE Department UET FSD campus
The logical function is given as Q = A·B A·B . This statement will be tested in the following
experiment.
Exercise 3:
Experiment set-up
Table 1
Q1 Q0
I0
B A Q
0 0
0 1
1 0
1 1
EXNOR
Exercise 4:
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Digital Logic Design Lab EE Department UET FSD campus
Experiment set-up
Table 2
Q1 Q0
I0
B A Q
0 0
0 1
1 0
1 1
↑
A·B A·B
Confirm from the values in Tables 1 and 2 that the EXNOR function can be represented by the
function Q = A·B A·B .
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Digital Logic Design Lab EE Department UET FSD campus
Lab evaluation:
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
(equality) gate?
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
3. Can you think of a way to achieve the same result using only three gates?
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
______________________________________________________________________________
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Digital Logic Design Lab EE Department UET FSD campus
Name
Reg. #
Marks
Lab 4
Objective:
Kar-naugh map
Minimizing the digital function.
Karnaugh maps
OR , + +
AND , · ALT+0183
Exercise 1:
Karnaugh map K1
B
A
1 0 0 1
0 0 0 0
]D
0 0 0 0
]C
1 0 0 1
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Digital Logic Design Lab EE Department UET FSD campus
Exercise 2:
Karnaugh map K2
B
A
0 1 1 1
1 1 1 1
]D
0 1 1 0
]C
0 1 1 0
Exercise 3:
Table 1
Q
C B A
0 0 0 0 0
0 0 1 0 Karnaugh
1
map K3
2 0 1 0 0 A
3 0 1 1 1 ]C
]B
4 1 0 0 0
5 1 0 1 1
6 1 1 0 0
7 1 1 1 1
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______________________________________________________________________________
______________________________________________________________________________
Sequence of gates
In this experiment, we investigate the sequence of gates and attempt to minimise the sequence.
Exercise 1:
Experiment set-up
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Digital Logic Design Lab EE Department UET FSD campus
Table 1
Q3 Q2 Q1 Q0 I0
I4 I3 I2 I1
D C B A Z1 Z2 Z3 Z4 Q
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
Copy the values of Q into the Karnaugh map (only the values Q=0 or Q=1 need to be copied; the
rest of the entries can just be filled in).
______________________________________________________________________________
______________________________________________________________________________
Karnaugh map 1
Output: Q
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Digital Logic Design Lab EE Department UET FSD campus
B 0 0 1 1
A 0 1 1 0
0 1
1 1
1 0
0 0
C D
______________________________________________________________________________
_____________________________________________________________
Exercise 2:
Table 2
D B A Q
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
Exercise 3
Enter the values for Z4 from Table 1 into Karnaugh map 2 and determine the minimised function
for Z4.
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Digital Logic Design Lab EE Department UET FSD campus
Karnaugh map 2
Output: Z4
B 0 0 1 1
A 0 1 1 0
8 9 11 10
0 1
12 13 15 14 Note:
1 1 The small numerals correspond to the line
4 5 7 6 numbers from Table 1<. They are intended to
1 0 make it clearer where everything belongs.
0 1 3 2
0 0
C D
______________________________________________________________________________
_____________________________________________________________
Enter the values for Z3 from Table 1 into Karnaugh map 2 and determine the minimised function
for Z3.
Karnaugh map 3
Output: Z3
B 0 0 1 1
A 0 1 1 0
8 9 11 10
0 1
12 13 15 14 Note:
1 1 The small numerals correspond to the line
4 5 7 6 numbers from Table 1. They are intended to
1 0 make it clearer where everything belongs.
0 1 3 2
0 0
C D
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Digital Logic Design Lab EE Department UET FSD campus
Name
Reg. #
Marks
Lab 5
Objective:
To understand Design and function of 1-bit half adder & 1-bit full adder
Parallel 4-bit adding circuit, Serial 4-bit adding circuit
Adding circuits
In arithmetic, we are familiar with the addition of decimal numbers from 0 to 9. A number must
be carried when the addition is greater than 10. This example shows the process of adding two 4-
digit decimal numbers.
+ 1
31 51 7 5 ← 2nd addend
← Carry
11035 ← Total
Binary numbers only contain the digits 0 und 1 and a one must be carried when the sum is
greater than 2.
Adding circuits are constructed to realise the rules of addition. They must be able to add and to
accommodate carrying. Addition can be implemented using an EXOR (exclusive or) operation,
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Digital Logic Design Lab EE Department UET FSD campus
while the carry is accomplished by an AND operation. The combination of these two elements
produces a half adder.
X
=1 S1
Y
X S1
Y C1
& C1
CO
A half adder can add two individual binary numbers but it does not take into account any carry
from a preceding stage. A binary adder with a third input for the carry from a previous stage is
termed a full adder.
The following truth table including the carry from a previous stage applies:
↓ ↓ ↓
S: Cn-1 C: Cn-1
Cn-1 Y X S Cn
Y Y
0 0 0 0 0 1 3 7 5 1 3 7 5
0 0 1 1 0 1 0 1 0 X 0 1 1 1 X
0 1 0 1 0 0 2 6 4 0 2 6 4
0 1 1 0 1 0 1 0 1 0 0 1 0
1 0 0 1 0
1 0 1 0 1 S=(X Y) Cn-1 C = Cn-1·( X Y ) + X·Y
1 1 0 0 1
1 1 1 1 1 S = S1 Cn-1 C = Cn-1·S1 + C1
↑ ↑
Total
Carry .
This is how a full adder can be implemented using 2 half adders and an OR gate.
Cn-1 U
U
X S2 S
X S1 V
=1 S
Y
=1
Y
X
X S C2
Y S & >1 C
Y = Cn
Cn-1 U C C1
CI CO Cn &
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Digital Logic Design Lab EE Department UET FSD campus
Half adder
This experiment studies the basic functionality of a 1-bit half adder. The 1-bit half adder has two
inputs and two outputs.
X S1
Y CO C1
Procedure
1. Connect the terminals on the card to those of the UniTr@in-I
according to the list of connections to the right
3 4
1
List of connections
2 74 HC 74
74 LS 245
74 HC 08
74 HC 86
74 HC 02
From To
74 HC 195
74 HC 273
3 4
Digital out 0 Terminal X
74 HC 195
74 HC 08
74 HC 245
Digital in 0 TerminalvS1
1 2
Digital in 1 Terminal C1
3. Set up the required bit patterns for X and Y and note the Q1 Q0 I1 I0
resulting outputs S1 and C1.
Derive the logical operations for the sum S1 and the carry C1 Y X C1 S1
S1 = 0 0
=
C1 = 0 1
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Digital Logic Design Lab EE Department UET FSD campus
1 0
(observe the nomenclature)
1 1
What do you conclude from the behaviour of the circuit?
5. Which of the following illustrations shows he correct set-up for a 1-bit half adder?
X X
= 1 S1
S1
Y Y
& C1
& C1
#1 #2
X Y
=1 C1
=1 S1
Y X
& S1
& C1
#3 #4
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Digital Logic Design Lab EE Department UET FSD campus
Full adder
This experiment studies the behaviour of a 1-bit full adder. The full adder extends the half adder
and has 3 inputs instead of the half adder's 2. The third input allows the circuit to take into
account a carry from a previous stage of addition.
X
X
S
Y S
Y
Cn-1 U C
CI CO Cn
Procedure
1. Connect the terminals on the card to those of the UniTr@in-I List of connections
according to the list of connections to the right
8 9
1 4
2 74 HC 74
From To
6
74 LS 245
7 4 HC 08
74 HC 86
7
3 5
74 HC 02
Digital out 0 Terminal X
7 4 HC 195
74 HC 273
4 5 6 7 8 9
74 HC 195
1 2 3
Digital in 0 Terminal S
Digital in 1 Terminal C
Digital in 3 Terminal C2
Digital in 4 Terminal S1
Digital in 5 Terminal C1
Jumper
V - S1
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Digital Logic Design Lab EE Department UET FSD campus
3. Set the required bit patterns for X , Y and U (representing the carry Cn-1) and note the
resulting outputs C1, S1, C2, S2, C and S.
X X
0 2 6 4 0 2 6 4
U Y X C1 S1 C2 S2 C S
0 0 0 0
C2 : U S2 : U
1 0 0 1 Y Y
1 3 7 5 1 3 7 5
2 0 1 0 X X
0 2 6 4 0 2 6 4
3 0 1 1
4 1 0 0
C: U S: U
5 1 0 1 Y Y
1 3 7 5 1 3 7 5
6 1 1 0 X X
0 2 6 4 0 2 6 4
7 1 1 1
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Digital Logic Design Lab EE Department UET FSD campus
Cn-1 U
U
X S2 S
X =1 S
S1 V
=1
Y
Y
C2
& >1 C
= Cn
C1
&
CI p21
1
A2
B21 CO C1
CI p22
2
A2
B22 CO C
2
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Digital Logic Design Lab EE Department UET FSD campus
Procedure
1. Connect the terminals on the card to the UniTr@in-I List of connections
according to the list of connections to the right.
74 HC 74
74 LS 245
From To
74 HC 08
74 HC 86
74 HC 02
74 HC 195
74 HC 273
9 11 13
74 HC 195
4
3 1
Digital out 1 A2
74 HC 08
74 HC 245 Terminal
2
1
8
74 HC 283
13
6
7
11
12 Digital out 2 Terminal A2 2
5 10
1 3 5 7
9
2 4 6 8
Digital out 3 Terminal A2 3
0
Digital out 4 Terminal B2
2
Digital out 6 Terminal B2
3
Digital out 7 Terminal B2
0
Digital in 0 Terminal p2
1
Digital in 1 Terminal p2
2
Digital in 2 Terminal p2
3
Digital in 3 Terminal p2
4
Digital in 4 Terminal p2
Digital 8 bit;
outputs Dec.
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Digital Logic Design Lab EE Department UET FSD campus
3. Set the suggested bit patterns for the two examples and enter the results in the tables.
Observe the note on reading values.
Example 1: Example 2:
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
B23 B22 B21 B20 A23 A22 A21 A20 B23 B22 B21 B20 A23 A22 A21 A20
24 23 22 21 20 → Dec. 24 23 22 21 20 → Dec.
A→ 0 1 0 1 → A→ 1 0 1 0 →
+B→ 0 1 0 1 →+ +B→ 1 1 1 0 →+
= pS → → = pS → →
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Digital Logic Design Lab EE Department UET FSD campus
This experiment studies the fundamental behaviour of a 4-bit serial adder. If only one full adder
is available, then addition can only be performed serially. This requires a circuit where the input
data are temporarily saved and input to the adder in sequence. Also, the carry resulting from each
intermediate addition needs to be saved for the subsequent addition stage. Finally, it is also
necessary to store the results of each intermediate addition so that the individual bit totals can be
combined to produce a parallel output once the last bit (MSB) has been added.
B
one number A.
: Shift register for
the bit pattern of
2 the second
CI CO ... number B.
B23 B22 B21 B20 0
C20 C23 : 1-bit full adder
C21 C22 : D-type flip-flop to
C22 FF C21 store the carry bit
C23 C20
4
Procedure
1. Connect the terminals on the card to the UniTr@in-I according to the list of connections
below.
List of connections
i
Digital out 0 Terminal A2 0 Digital in 0 Terminal s2
0
Terminal A2 Terminal X
1 1 0
Digital out 1 Terminal A2 Digital in 1 Terminal s2 Terminal s2 Terminal Y
0 4
Digital out 4 Terminal B2 Digital in 4 Terminal s2 Terminal C Terminal D
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Digital Logic Design Lab EE Department UET FSD campus
1
Digital out 5 Terminal B2 Interface S Terminal CLK
2
Digital out 6 Terminal B2 Jumper
3
Digital out 7 Terminal B2 V - S1
Output:
Advanced
8 bit; Hex.
digital
Input:
IO Display
8 bit; Dec
First, set the switch to the L position and generate a clock pulse.
For the subsequent steps, set the switch to S.
Use the DC source to produce further clock pulses.
Read the values of A2i from the LED on the card.
[ Alternatively, you could record the values using one
of the unoccupied digital inputs. ]
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Digital Logic Design Lab EE Department UET FSD campus
4 3 2 1 0
S / L Reset CLK s2 s2 s2 s2 s2 A2i
Parallel loading L 0 0
S 0
S 0
S 0
S 0 0
5. Press the Reset button again and repeat the experiment with the second bit pattern.
Parallel loading L 0 0
S 0
S 0
S 0
S 0 0
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Digital Logic Design Lab EE Department UET FSD campus
The illustration below reiterates the relationships to help you understand the tables you have
obtained. The bits s23.. s20 are shifted one place to the right along the shift register with each
clock pulse. The bit representing the sum S at input SD is shifted into the s23 bit on the next
pulse and the carry C is stored at s24.
1 0 B
0
A2
A
3
A2
S
What are the equivalent decimal numbers being added in this example.
6. Study the two tables you have generated with regard to the specified characteristics.
How many clock pulses are needed to produce the final result? Explain how you arrive at this
number.
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Digital Logic Design Lab EE Department UET FSD campus
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Digital Logic Design Lab EE Department UET FSD campus
Name
Reg. #
Marks
Lab 6
Objective:
Multiplexers
How is the number of data lines (N) related to the number of address lines (n)?
The following represents the logic table for the AND gates in the above illustration. Fill in the
table taking into account the inversion of the select bits A2 0 and A21)
0 1 2 3
D2 & D2 D2 D2
0 0 0
& 1 0
& 2 0
& 3
A2 Z2 A2 Z2 A2 Z2 A2 Z2
1 1 1 1
A2 A2 A2 A2
0 1 2 3
D2 0 A2 1 A2 0 Z2 D2 0 A2 1 A2 0 Z2 D20 A21 A20 Z2 D2 0 A2 1 A2 0 Z2
0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 1 0 0 1 0 0 1
0 1 0 0 1 0 0 1 0 0 1 0
0 1 1 0 1 1 0 1 1 0 1 1
1 0 0 1 0 0 1 0 0 1 0 0
1 0 1 1 0 1 1 0 1 1 0 1
1 1 0 1 1 0 1 1 0 1 1 0
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Digital Logic Design Lab EE Department UET FSD campus
1 1 1 1 1 1 1 1 1 1 1 1
How many input signals to the OR gate can simultaneously be at logic level "1"?
What is the purpose of the OR gate?
Multiplexer - Experiments
EN 7 MUX
EN
0 11
A2 0
10
A2
1 G_
0
9 7
2 2
A2
4
D20 0
3
D21 1
2 5
D22 2
Q
1
D23 3
15 6
D24 4 Q
14
D25 5
13
D26 6
12
D27 7
Procedure
1. Connect the terminals on the card with those of the UniTr@in-I List of connections
as shown in the list of connections to the right.
From To
0
Digital out 0 Terminal A2
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Digital Logic Design Lab EE Department UET FSD campus
1
Digital out 1 Terminal A2
1 5
2 2
3
Digital out 2 Terminal A2
74 HC 151
74 HC 238
4
5 Digital in 0 Terminal Q
74 HC 393
1 3
2
3. Set the input lines ( D20 to D27) to the logic levels given in the table (high level is
achieved by connecting to the 5V-socket of the Experimenter / open sockets are at low
level)
Set the suggested bit combinations for the address lines A20..A2 2 in sequence (go through
the BCD codes for 0 to 7) and enter the value of Q that emerges in each case.
0 1 2 3 4 5 6 7
0
A2 0 1 0 1 0 1 0 1
1
A2 0 0 1 1 0 0 1 1
2
A2 0 0 0 0 1 1 1 1
7 6 5 4 3 2 1 0
D2 D2 D2 D2 D2 D2 D2 D2 Q
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1
0 0 0 0 0 0 1 0
0 0 0 0 0 1 0 0
0 0 0 0 1 0 0 0
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Digital Logic Design Lab EE Department UET FSD campus
0 0 0 1 0 0 0 0
0 0 1 0 0 0 0 0
0 1 0 0 0 0 0 0
1 0 0 0 0 0 0 0
What happens?
Explain what this input does.
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Digital Logic Design Lab EE Department UET FSD campus
Demultiplexers
How can the design of the demultiplexer be derived from that of the multiplexer?
Is the addressing logic for the demultiplexer different from that of the multiplexer?
Demultiplexer - Experiments
0
B2 1 DX 15 0
0 0 Q2
2 14
B2 1 G0
_ 1 Q2 1
3 7 13
2
2 2 Q2 2
B2 12
3 Q2 3
11
4 Q2 4
E 4 10
& 5 Q2 5
5 9
EN 6 Q2 6
6 7
7 Q2 7
E
Symbol for the multiplexer component used here with its accessible ports.
Procedure
1. Connect the terminals on the card with those of the List of connections
UniTr@in-I as shown in the list of connections to the
right.
From To
1 4
0
2
5
Digital out 0 Terminal B2
6 8 10 12 3
74 HC 151 6
5 7 9 11 7
74 HC 238
8
1
4 9
10 Digital out 1 Terminal B2
11
12
74 HC 393
2
Digital out 2 Terminal B2
1 3
2
Experimenter 5V Terminal E
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Digital Logic Design Lab EE Department UET FSD campus
1
Digital in 1 Terminal Q2
2
Digital in 2 Terminal Q2
3
Digital in 3 Terminal Q2
4
Digital in 4 Terminal Q2
5
Digital in 5 Terminal Q2
6
Digital in 6 Terminal Q2
7
Digital in 7 Terminal Q2
3. Connect socket "E" to logical "1", (the 5V output of the Experimenter). Set the specified
bit patterns for the address lines B20..B22 in sequence (go through the BCD codes for 0 to
7) and enter the values of Q20 .. Q27 that emerge in each case.
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
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Digital Logic Design Lab EE Department UET FSD campus
4. Connect input "E" to logical "0" (one of the ground connections on the card). Repeat the
above experiment.
5. Now connect input "E" to 0V (logical "0") and repeat the above experiment.
Then connect "E" to the 5V socket (logical "1") and repeat the experiment again.
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Digital Logic Design Lab EE Department UET FSD campus
Name
Reg. #
Marks
Lab 7
Objective:
RS - flip-flop
Experiment set-up
Procedure
1. Connect an Experimenter to the UniTr@in-I Interface List of connections
and insert with the experiment card SO4201-9T.
From To
Then connect up the experiment card to the UniTr@in-
I Interface as shown in the illustration and as specified Terminal NAND
in the list of connections: Digital Out 1
E1
Terminal NAND
Digital Out 0
E4
Terminal NAND
Digital In 1
Q1
Terminal NAND
Digital In 0
Q2
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Digital Logic Design Lab EE Department UET FSD campus
been applied. 0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
d).
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Digital Logic Design Lab EE Department UET FSD campus
Expanded RS flip-flop
Experiment set-up
Procedure
1. Connect the experiment card to the sockets of the List of connections
UniTr@in-I as specified in the list of connections on
From To
the right.
Digital Out 1 Terminal NOT E1
Terminal NAND
Terminal NOT Q1
E1
Terminal NAND
Terminal NOT Q2
E4
Terminal NAND
Digital In 1
Q1
Terminal NAND
Digital In 0
Q2
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Digital Logic Design Lab EE Department UET FSD campus
Instruments menu
- Digital inputs and outputs Digital
see Table
outputs
applied. 0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
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Digital Logic Design Lab EE Department UET FSD campus
Experiment set-up
Procedure
1. Connect the experiment board to the sockets of the List of connections
UniTr@in-I as specified in the list of connections
From To
on the right.
Digital Out 1 Terminal NAND E5
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Digital Logic Design Lab EE Department UET FSD campus
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
d).
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Digital Logic Design Lab EE Department UET FSD campus
Latching :
Undefined :
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Digital Logic Design Lab EE Department UET FSD campus
Name
Reg. #
Marks
Lab 8
Objective:
Counters
Counters are circuits for continuous counting of electrical signals. Counting is generally
performed by adding and storing values. Counters are mainly built using JK flip-flops.
The simplest pulse counter is a JK master-slave flip-flop (termed only 'flip-flop' in the following)
whose inputs J and K are set to logical 1. The frequency applied to its C input is divided in the
ratio 2:1.
The counting states of several flip-flops connected together are determined as follows:
m = 2n
n = log2m
k=m-1
n Number of flip-flops
k maximum count
Counters with a large maximum count are not built using discrete components these days, as a
large number of integrated modules are now available for this purpose. However, discrete
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Digital Logic Design Lab EE Department UET FSD campus
counter circuits are still very suitable for promoting an understanding of the design of digital
circuits. The flip-flop inputs influence the outputs Q1 and Q1 as follows:
Counter types:
Asynchronous counters
The flip-flops of an asynchronous counter are controlled with different clock signals. Only the
first flip-flop receives the original clock signal. The Q output of every subsequent flip-flop
controls the clock input of the next flip-flop.
+
PULL-UP
This illustration shows the principal design of a JK master-slave flip-flop on the experiment card.
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Digital Logic Design Lab EE Department UET FSD campus
The delay times (roughly 20ns per gate) of the individual gates are added. This results in a total
delay time of 60ns caused by the gates alone. Parasitic capacitances further lengthen this lag
time. The delay times start causing interference at high clock frequencies, an effect that becomes
clearly identifiable at frequencies in excess of 1 MHz. As the UniTr@in-I does not cover this
frequency range though, the effect cannot be investigated here.
Asynchronous counters
Calculate the number of JK flips flops required to make a counter capable of counting 16 pulses.
=2 = log
n = log =
k=
k= =
, i.e. the counter can count up to decimal .
Experiment set-up
Q1 Q2 Q3 Q4
S Q1 S Q2 S Q3 S Q4
J1 Q J2 Q J3 Q J4 Q
1J 1J 1J 1J
C1 C1 C1 C1
K1
1K K2
1K K3
1K K4
1K
C Q Q Q Q
R R R R
Procedure
1. Connect the card to the UniTr@in-I as shown in the list List of connections
of connections on the right.
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Digital Logic Design Lab EE Department UET FSD campus
S1
J1 Q1 E1
DI 0 From To
(C) DO 0 C1 Q1
E2
K1 Q1
R1 DI 1
E3
S2
J2 Q2
E4
Q2
Interface S Terminal FF C1
C2
E5
K2 Q2 Q3
R2 E6
S3
J3
C3
Q3
E7
Q4 DI 2 Digital In 0 Terminal FF Q1
E8
K3 Q3
R3 E1 Q1
S4
J4
C4
Q4
E2
E3
Q2
Q3
DI 3
Digital In 1 Terminal FF Q2
E4 Q4
K4 Q4
E5 Q5
R4
E6 Q6
k l m n o
E7
E8
Q7
Q8
Digital In 2 Terminal FF Q3
p q r s t
0V 0V
Note: Inputs which are not connected (for example, J and K inputs) are set to a
high level by pull-up resistors
3. Start the function generator and observe the display of Binary Dec Oct Hex
the digital inputs. Switch the display format between
decimal (dec), octal (oct) and hexadecimal (hex) and 0000 D O H
fill out the adjacent table.
0001 D O H
4. What do you observe after the circuit has been
0010
started up? D O H
0011 D O H
0100 D O H
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Digital Logic Design Lab EE Department UET FSD campus
0101 D O H
0110 D O H
0111 D O H
1000 D O H
1001 D O H
1010 D O H
1011 D O H
1100 D O H
1101 D O H
1110 D O H
1111 D O H
Experiment set-up
1 Q1 Q2
S S
1J 2J
C1 C2
1K 2K
R R
C
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Digital Logic Design Lab EE Department UET FSD campus
0 0 0
1 0 1
2 1 0
3 1 1
Q1 n ⇒ J1 = ; K1 =
The simplified switching equation is:
Q2n+1
Q2 n+1 =
Q2n Q2 n
= ·Q2n + ·Q2n
Q1 n
Q1 n ⇒ J2 = ; K2 =
As a consequence:
Compare your results with the output circuit and comment on them.
Procedure
1. Connect the card to the UniTr@in-I as shown in the List of connections
list of connections on the right.
From To
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Digital Logic Design Lab EE Department UET FSD campus
DI 1
S1 Terminal FF
J1
C1
Q1 E1
Q1
Dig-Out 0
K1
R1
Q1
E2
E3
C1,C2
S2 Q2
E4 DI 0
J2 Q2
C2
K2
R2
Q2
E5
E6
Q3 Terminal FF Q1 Terminal FF J2
S3
E7
J3 Q3 Q4
C3 E8
(C) DO 0
K3
R3
Q3
E1 Q1
Terminal FF Q2 Terminal FF K2
S4 E2 Q2
J4 Q4 E3 Q3
C4
K4
R4
Q4
E4
E5
Q4
Q5 Digital In 0 Terminal FF Q2
E6 Q6
k l m n o
E7 Q7
E8 Q8
0V
p q r s t
0V
Digital In 1 Terminal FF Q1
SO4201-9T
Note: Inputs, which are not connected (for example, J and K inputs),
are set to a high level by pull-up resistors.
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Digital Logic Design Lab EE Department UET FSD campus
Name
Reg. #
Marks
Lab 9
Objective:
A control bit is to allow selection between the up and down counting modes.
The following table shows the bit patterns occurring during up and down counts:
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Digital Logic Design Lab EE Department UET FSD campus
Experiment set-up:
S 1
Q1 Q2
From the experiment set-up, determine the condition for clock input C2:
Accordingly:
C2 = · · ·
If S=1: C2 =
C2 = · + · If S=0: C2 =
Procedure
1. Connect the card to the UniTr@in-I as shown in the list List of connections
of connections on the right.
DO 0
S1
J1 Q1 E1
DI 0
From To
(C) S C1 Q1
E2
K1 Q1
R1
E3
S2
J2
C2
Q2
E4
Q2
DI 1
Interface S Terminal FF C1
E5
K2 Q2 Q3
R2 E6
S3
J3
C3
Q3
E7
E8
Q4 Digital In 0 Terminal FF Q1
K3 Q3
R3 E1 Q1
S4 E2 Q2
J4
C4
K4
Q4
Q4
E3
E4
Q3
Q4 Digital In 1 Terminal FF Q2
E5 Q5
R4
E6 Q6
k l m n o
E7 Q7
p q r s t
E8 Q8
Digital Out 0 Terminal NOT E1
0V 0V
SO4201-9T
Terminal NAND
Terminal NOT E1
E4
Click on the image for a schematic representation of the wiring
Terminal NAND
Terminal FF Q1
Note: Inputs which are not connected (for example, J and K inputs), E3
are set to a high level by pull-up resistors.
Terminal NAND
Terminal FF Q1
E2
Terminal NAND
Terminal NOT Q1
E1
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Digital Logic Design Lab EE Department UET FSD campus
Terminal NAND
Terminal FF C2
Q3
Settings
Amplitude:
50% at 1:1
Function
Frequency: 1Hz
generator
Logic
Power ON
3. Start the function generator and observe the display of the digital inputs. Switch S (DO0)
from 0 to 1.
S=0 S=1
⇔
4. What can you observe after the circuit has been started up?
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Digital Logic Design Lab EE Department UET FSD campus
The following truth table applies to a up/down counter with a maximum count of m=8:
C3 = · · + · ·
The condition for C2 is the same as the one for the counter described above.
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Digital Logic Design Lab EE Department UET FSD campus
This experiment is intended to investigate the operation of a synchronous up and down counter.
A synchronous counter is capable of binary up and down counting between 0 and 3. A control bit
is to allow selection between the up and down counting modes.
n = log =
; ; ;
In the following table, enter the values which occur in the up and down counting modes.
Table
0
Down
0
1 0 0
Up
1
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Digital Logic Design Lab EE Department UET FSD campus
Use the truth table to prepare the Karnaugh maps for each flip-flop.
Determine the problem functions and use them as a basis for ascertaining the input
functions of the required JK flip-flop.
Output: Q1n+1
Q2n 0 0 1 1
0 1 1 0 Q1n+1 =
S
0 4 6 2
0 =
1 5 7 3
·Q1n + ·Q1 n
1
⇒ J1 = ; K1 =
Q1 n
Output: Q2n+1
Q2n+1 =
Q2n 0 0 1 1
S 0 1 1 0 =
0 4 6 2 ·Q2n + ·Q2 n
0
1 5 7 3
1
⇒ J2 = ; K2 =
Q1 n Accordingly, J2 K2
Note:
The following relationship applies in Boolean algebra:
x·y+x·y =x·y+x·y
S 1
Q1 Q2
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Digital Logic Design Lab EE Department UET FSD campus
J2 K2
(Q1n S ) ( Q1n S )
(Q1n S ) ( Q1n S )
( Q1n S ) ( Q1n S )
A B ; A Q1n S ; B Q1n S
Procedure
1. Connect the card to the UniTr@in-I as shown in the list of List of connections
connections on the right.
S1
J1 Q1 E1
DI 0
From To
C1 Q1
E2
K1 Q1
R1
E3
S2 Q2
J2 Q2
E4
Terminal FF
(C) S
C2
K2 Q2
E5
DI 1
Interface S
R2
S3
E6
Q3
C1,C2
E7
J3 Q3 Q4
C3 E8
K3 Q3
DO 0
R3
S4
E1
E2
Q1
Q2
Digital In 0 Terminal FF Q1
J4 Q4 E3 Q3
C4 E4 Q4
K4 Q4
E5 Q5
R4
k l m n o
E6
E7
Q6
Q7
Digital In 1 Terminal FF Q2
E8 Q8
p q r s t
0V 0V
Terminal NOT
SO4201-9T
Digital Out 0
E1
Click on the image for a schematic representation of the wiring Terminal NOT Terminal NAND
E1 E4
Note: Inputs which are not connected (for example, J and K inputs)
are set to a high level by pull-up resistors
Terminal NAND
Terminal FF Q1
E3
Terminal NAND
Terminal FF Q1
E2
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Digital Logic Design Lab EE Department UET FSD campus
menu:
- Function generator Amplitude:
- Extended digital inputs and outputs 50% at 1:1
Function
Frequency: 1Hz
generator
Logic
Power ON
3. Start the function generator and observe the display of the digital inputs. Switch S (DO0)
from 0 to 1.
S=0 S=1
⇔
4. What can you observe after the circuit has been started up?
How do a synchronous counter and an asynchronous counter differ in terms of circuit design?
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Digital Logic Design Lab EE Department UET FSD campus
Asynchronous counter:
- Advantages:
- Disadvantages:
Synchronous counter:
- Advantages:
- Disadvantages:
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Digital Logic Design Lab EE Department UET FSD campus
Name
Reg. #
Marks
Lab 10
Objective:
REGISTERS
In terms of information processing Registers are miniature memory units for a modest number
of bits. Normally they serve for short-term storage of information. The simplest register is the D
flip-flop (Latch). An arrangement of more than one flip-flop in series, triggered synchronously
by one common clock signal, is termed a Shift Register. Shift registers can also be made of JK
flip-flops and as such can be used as counters in some special applications.
In actual practice only synchronous shift registers are used. The design of shift registers is based
on the procedures used in designing synchronous counters. Only the input functions for J and K
are determined. The input functions of the following flip-flops are the same as the previous
output variables.
In general, the signal input, processing and output carried out in shift registers are all based on
three basic principles
a. The serial input of data ( all signals enter into the shift register
sequentially and are transferred to the circuit's output bit by bit).
b. Parallel input of data ( all signals enter the shift register in parallel or
sequentially and reach the output simultaneously, in sequence ).
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Digital Logic Design Lab EE Department UET FSD campus
At the same time, all the flip-flops record the information with the same clock pulse edge and
simultaneously transfer to the next flip-flop the briefly stored information. This means that with
each triggering clock edge the stored data is transported one flip-flop further.
By checking the number of inputs and outputs, you can determine whether the shift register
operates in serial or parallel input/output mode.
In this experiment, we will set up and investigate one 4-bit shift register with serial input and
serial output.
Experiment set-up
Q4
E S Q1 S Q2 S Q3 S
1J 2J 3J 4J
C2 C3 C4
1 1K 2K 3K 4K
R R R R
C
Procedure
1. Connect the card to the UniTr@in-I as shown in the List of connections
list of connections on the right.
From To
S1 DI 3
(E) DO 0 J1 Q1 E1
C1
K1 Q1
E2
Q1
Digital Out 0 Terminal FF J1
R1
E3
S2 Q2
E4
J2 Q2
C2
K2 Q2
E5
Q3
DI 2
Digital Out 0 Terminal NOT E1
R2 E6
S3 DI 1
E7
J3 Q3 Q4
C3
K3
E8
Terminal FF
R3
Q3
E1 Q1 Digital Out 1
S4
J4 Q4
E2
E3
Q2
Q3
DI 0 C1,C2,C3,C4
C4 E4 Q4
K4 Q4
E5 Q5
R4
(C) DO 1 E6 Q6
k l m n o
E7 Q7 Terminal NOT Q1 Terminal FF K1
E8 Q8
p q r s t
0V 0V
SO4201-9T
Terminal FF Q1 Terminal FF J2
Terminal FF Q1 Terminal FF K2
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Digital Logic Design Lab EE Department UET FSD campus
Terminal FF Q2 Terminal FF J3
Click on the image to see a schematic representation of the wiring.
Terminal FF Q2 Terminal FF K3
Note: Unconnected inputs (e.g. J and K inputs) are
set to high level by pull-up resistors.
Terminal FF Q3 Terminal FF J4
Terminal FF Q3 Terminal FF K4
Digital In 0 Terminal FF Q4
Digital In 1 Terminal FF Q3
Digital In 2 Terminal FF Q2
Digital In 3 Terminal FF Q1
2. Enter into the table the states resulting when the Clock
binary code (1010) is read in sequentially for the Data
pulse Q1 Q2 Q3 Q4
decimal number 10 . E
C
1 0 1 0
0 0 1 0
1 0 1 0
0 0 1 0
0 0 1 0
0 0 1 0
4. How many pulses have to be applied to C in order to be able to read out serially the
binary combination for 10D at Q4 ?
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Digital Logic Design Lab EE Department UET FSD campus
In a circular shift register, a number sequence is continuously 'shifted through' so that the last
binary digit is shifted out of one end and replaced at the other. The state is then displayed.
Experiment set-up
Q1 Q2 Q3 Q4
S S S S
1J 2J 3J 4J
C1 C2 C3 C4
1K 2K 3K 4K
R R R R
C
Procedure
5. Modify the original circuit to create the newly List of connections
developed one.
S1
DISCONNECT
DI 3
J1 Q1 E1
C1 Q1
E2
K1 Q1
R1
S2
E3
E4
Q2 From To
J2 Q2
DI 2
C2
E5
K2 Q2 Q3
R2 E6
S3
J3 Q3
E7
Q4
DI 1
Digital Out 0 Terminal FF J1
C3 E8
K3 Q3
R3 E1 Q1
E2 Q2
S4
J4
C4
Q4 E3
E4
Q3
Q4
DI 0 Digital Out 0 Terminal NOT E1
K4 Q4
E5 Q5
R4
(C) DO 1 E6 Q6
k l m n o
E7 Q7
p q r s t
E8 Q8
Terminal NOT Q1 Terminal FF K1
0V 0V
SO4201-9T
RECONNECT
Click on the image to see the schematic representation of the wiring.
From To
Note: Unconnected inputs (e.g. J and K inputs) are
set to high level by pull-up resistors. Terminal FF Q4 Terminal FF J1
Terminal FF Q4 Terminal FF K1
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Digital Logic Design Lab EE Department UET FSD campus
Logic analyser
7. Using the S (Set) and R (Reset) buttons apply a random bit pattern (e.g. Q1=1, Q2=0,
Q3=0, Q4=0 or Q1=1, Q2=0, Q3=1, Q4=0 ).
to the inputs of the 4 flip-flops. Then start your measurement procedure and observe
the result. Change the bit pattern as desired and repeat the measurement. Document
the two patterns ascertained here.
Beware:
In order to avoid deleting the bit pattern, refrain from switching off the power.
Clock the bit sequence through the circular shift register.
In this experiment, the shift register used in the previous experiment will be used but with
parallel operation.
Experiment set-up
Q1 Q2 Q3
E S S S
1J 2J 3J
C2 C3
1 1K 2K 3K
R R R
C
Procedure
1. Connect the card to the UniTr@in-I as shown in the list List of connections
of connections on the right.
From To
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Digital Logic Design Lab EE Department UET FSD campus
S1 DI 2
Digital Out 0 Terminal NOT E1
(E) DO 0 J1 Q1 E1
C1 Q1
E2
K1 Q1
R1
E3
S2 Q2 Terminal FF
J2
C2
Q2
E4
DI 1 Digital Out 1
K2
R2
Q2
E5
E6
Q3 C1,C2,C3
S3 DI 0
E7
J3 Q3 Q4
C3 E8
(C) DO 1
K3
R3
Q3
E1 Q1
Terminal NOT Q1 Terminal FF K1
S4 E2 Q2
J4 Q4 E3 Q3
C4
K4
R4
Q4
E4
E5
Q4
Q5 Terminal FF Q1 Terminal FF J2
E6 Q6
k l m n o
E7 Q7
E8 Q8
0V
p q r s t
0V
Terminal FF Q1 Terminal FF K2
SO4201-9T
Terminal FF Q2 Terminal FF J3
Digital In 2 Terminal FF Q1
3. Start your measurement procedure and transfer the result into the results field.
Fill in the adjacent Table using the diagram.
Table 1.
after
Decim
cloc al
Q1 Q2 Q3
k numbe
#1 #2 #3 #4 #5 #6 #7 #8 #9 #10puls r
e
#1
#2
#3
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Digital Logic Design Lab EE Department UET FSD campus
#4
Table 2.
after
Decim
cloc al
Q1 Q2 Q3
k numbe
puls r
e
#1
#1 #2 #3 #4 #5 #6 #7 #8 #9 #10
#2
#3
#4
#5
Table 3.
#1 #2 #3 #4 #5 #6 #7 #8 #9 #10after Decim
al
Q1 Q2 Q3
cloc numbe
k r
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Digital Logic Design Lab EE Department UET FSD campus
puls
e
#1
#2
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6. Describe how the shift register works. How many clock pulses are needed until the
desired signal appears at the outputs?
97
Digital Logic Design Lab EE Department UET FSD campus
98