Gmid 5t Ota Mej BBL 20180320
Gmid 5t Ota Mej BBL 20180320
Gmid 5t Ota Mej BBL 20180320
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1 Abstract—The simple square-law MOSFET model fails to and intuition to make his design work. In addition to requiring 43
2 describe the behavior of short channel and moderate/weak significant design time and expensive simulation tools licenses, 44
3 inversion devices. The gm/ID methodology is a promising tech- this design methodology hinders the understanding of design 45
4 nique that addresses the square-law shortcomings and bridges
5 the gap between hand analysis and simulation. This paper trade-offs, the development of valuable designer intuition, and 46
6 describes a systematic procedure for the design of a single-stage the systematic porting of designs from one technology node 47
8 methodology. Both small signal and large signal specifications A promising methodology that addresses the previous lim- 49
9 are used to constrain the design process, which is graphically itations, and bridges the gap between hand analysis and 50
10 illustrated using trade-off charts. The presented design procedure
11 is automated using MATLAB, and an iterative procedure is used simulation is the gm /ID design methodology [4]–[9]. The 51
12 to take the OTA self-loading into consideration. Moreover, an basic idea of this methodology is to describe the transistor 52
13 automated optimization procedure is presented to maximize the behavior using a dataset generated from simulation sweeps 53
14 speed of a unity-gain buffer under current consumption, DC (or measurements) rather than inaccurate simple models. This 54
15 gain, and input capacitance constraints. The designed circuits dataset characterizes different normalized transistor parameters 55
16 are verified using Cadence Spectre and the 180 nm Predictive
17 Technology Model (PTM), where the simulation results are in and figures-of-merit vs the transconductance-to-current ratio 56
18 close agreement with hand analysis and automation results. (gm /ID ). The gm /ID is used as a primary design variable 57
21 tion; CMOS normalized measure of the channel inversion level for all 60
23 Analog IC design will always be there because we live in gm /ID dataset is one-time generated for a given technology, 64
24 an analog world. Analog-to-digital converters (ADCs) and and can be reused in the form of trade-off charts or lookup 65
25 digital-to-analog converter (DACs) will always be needed tables. The design process becomes a systematic procedure, 66
26 (together with their associated circuits such as amplifiers, where hand analysis expectations are in close agreement with 67
28 analog world and our digital electronic devices. It may be One of the early works that discussed the gm /ID method- 69
29 thought that CMOS analog design is an art that depends on lots ology was proposed by Silveira et al. in [4]. This pioneering 70
30 of experience and intuition. One reason that may support this work proposed using the gm /ID methodology for OTA design; 71
31 claim is that the simple square-law MOSFET model common however, several design variables were assumed without being 72
32 to most textbooks and university courses fails to describe the constrained by clear circuit specifications. In addition, the 73
33 behavior of short channel devices, as well as devices operated details of the optimization procedure used to select the gm /ID 74
34 in moderate and weak inversion (which are becoming increas- values and the transistor sizing were not explained. Moreover, 75
35 ingly popular in energy-efficient designs [1]–[3]) regardless of important circuit specifications such as input range, noise, and 76
36 their channel length. On the other hand, more accurate device common-mode rejection were not considered. Finally, it did 77
37 models are too complicated, and are not amenable to hand not consider the variation of the gm /ID characteristics with 78
38 analysis. In addition, there is no definite systematic recipe that channel length, since this variation was negligible for the 3 µm 79
39 the designer can follow to design an analog block, even if it technology used in the design. The gm /ID methodology was 80
40 is a fundamental block like an operational transconductance used to optimize a gain boosted cascode in [5]. However, 81
41 amplifier (OTA). As a result, the analog designer has to rely on similar to [4], it suffered from the same previously mentioned 82
42 lengthy multi-variable sweeps on simulation tools, experience, drawbacks. The optimization of a three-stage nested-Miller 83
Mostafa N. Sabry is with Si-Vision LLC, Cairo, Egypt design procedure aimed at optimizing both noise and settling 85
(email: [email protected]). Hesham Omran and time specifications. However, it neglected other circuit spec- 86
Mohamed Dessouky are with the Integrated Circuits Lab, Faculty
of Engineering, Ain Shams University, Cairo, Egypt (email: ifications, and assumed that the gm /ID values and channel 87
35 The target design example is a single-ended output five- The first step is to choose the type of the OTA input pair. 61
36 transistor OTA to be used as a unity-gain buffer to drive a Since the required input range (0.2 V − 1.1 V ) is close to the 62
37 large capacitive load. The design specifications are shown in ground rail, a PMOS input stage is necessary. The schematic 63
38 Table I. The available current consumption for the OTA is of the OTA is shown in Fig. 1. From the GBW and CL 64
39 20 µA. In addition, a 10 µA reference current is externally specifications the transconductance of the input pair can be 65
to the large output load (more about this point in Section II-F 68
10 1
L = 2 7m
L = 2 7m 200 L = 0.4 7m
10 1
ID/W (uA/um)
200
ID/W (uA/um)
gm/gds
150 L = 2 7m
200 X: 15
gm/gds
150
10 1
ID/W (uA/um)
X: 16 Y: 83.84
10 0 X: 16
100
gm/gds
Y: 88.62 150
100 Y: 0.437 X: 15
Y: 83.84 10 0
50 L = 2 7m
100
50 L = 2 7m L = 0.4 7m
L = 0.4 7m 0 10 0
50 L = 2 7m
0 10 -1 5 10 15 20 5
5 10 15 20 5 10 15 20 L = 0.4 7m
0 gm/ID (S/A)
gm/ID (S/A) 5 gm/ID (S/A) 10 15 20 5
0.8 (a) 0.3
(a) gm/ID (S/A)
X: 8.333
-0.5
Y: 0.67 0.25
0.7
0.8 0.3
-0.55 1 L = 0.4 7m
(V) (V)
VGS (V)
10 L = 2 7m -0.1
X: 8.333
0.2
Y: 0.67 X: 16 0.25
Vdsat Vdsat
-0.6 X: 16 0.6
10 1 Y: -0.09491L = 0.4 7m
Y: -0.5703 0.15
VGS (V)
ID/W (uA/um)
-0.65 L = 2 7m -0.15
L = 0.4 7m
0.2
200 0.5
0.6
X: 16 -0.7 0
L = 0.4 7m L = 2 7m 0.1
10 X: 16 0.15
Y: 88.62 -0.2
gm/gds
150 Y: 0.437
-0.75 X: 16 0.4
0.5 0.05
10 0 L = 2 7m 10 X: 16 0.1 5
Y: 88.62 5 15 20
100 Y: 0.437
-0.8 L = 2 7m -0.25 gm/ID (S/A)
5 10 15 20 5 0.410 15 20 0.05
L = 0.4 7m 5 10 15 20 5
50
-1 gm/ID (S/A) L = 2 7m gm/ID (S/A)
10 0.92
15 20 5 10 15
L = 0.4 7m
20 gm/ID (S/A)
0 gm/ID (S/A) -1
10
0.9 (b)
(r/s) (r/s)
5 10 15 20 5 10 15 20 0.92
10 10 (b) (S/A)
gm/ID 10 10 gm/ID (S/A) 0.9
0.89
gm/Cgg
L = 0.4 7m
.
gm/Cgg (r/s)
10 1 X: 16
.
X: 16 -0.55 X: 16
(V) (V)
10 9 L = 2 7m
gm/gds
-0.15
-0.6 L = 0.4 7m X: 16 0.86 X: 16 0.88
Vdsat (V)
Y: 83.84 0.86
100 Y: -0.5703 10 9 5 Y: -0.09491
ID/W (uA/um)
7m L = 0.4 7m 0.85 5 10 15 20
-0.65 -0.15
0 gm/ID (S/A)
ID/W (uA/um)
-0.2 L = 2107m
X: 16 8 50 L = 0.4 7m 0.84 L = 2 7m 0.86
10 0
10-0.7 X: 16
X:Y:
1688.62 5 10 15 Y: 16
0.437 20 7m5
L = 0.4-0.2 5
10 10
15 15
20 20 5
10 0 X:
Y: 88.62 -0.75
-0.25 0 gm/ID (S/A) gm/ID (S/A) gm/ID (S/A)
15 20 5 105 1510 Y: 0.437 15
20 20 5 10 15 20
-0.8 L = 2 7m gm/ID (S/A) -0.25
5 10 15
gm/ID (S/A)20 5 10 15
gm/ID (S/A)20
L = 0.4 7m L = 2 7m
10 -1 gm/ID (S/A) gm/ID (S/A) (c)
15 L = 0.4 7m 20 0.9 5 0.8
10 15 20 0.3
10 -1 X: 8.333
5 20 0.89 5 10 (c)
gm/ID (S/A) 15 20 0.9 Figure 3. NMOS
0.25 current mirror load (M3 and M4) design charts vs gm /ID
Y: 0.67
0.7
L = 0.4 7m with length as a parameter (L = 0.4µm : 0.2µm : 2µm): (a) intrinsic gain
10 gm/ID (S/A) L = 0.4 7m
Vdsat (V)
10
VGS (V)
0.88 0.89
(gm /gLds= ), 0.2VGS , and (c) current density (ID /W ).
0.4(b)
7m
0.6
(V) (r/s)
0.87 0.88
.
X: 16 0.15
-0.1 Y: 0.8571
gm/Cgg
0.87
.
X: 16 0.869 0.5 X: 16 X: 16
Y: -0.5703 -0.1
10 L = 2 7m Y: -0.09491 0.1 Y: 0.8571
X: 16 It is fair to assume that this requirement is split equally
Vdsat
X: 16 -0.15 0.86
Vdsat (V)
0.85 1
Y: -0.5703 0.4
L = 2 7m Y: -0.09491 0.05
7m -0.15
0.84 5 10 15 0.85 20 5 10 between M2 and M4, i.e., M2 and M4 have the same output
15 20 2
15 20 -0.25 10 15 20 L = 2 7m
m
10 8
gm/ID (S/A) 0.84 ds2 ds4 conductance (g
gm/ID (S/A) =g < 2 µS). Thus, the intrinsic gain of 3
gm/ID (S/A) 15
-0.2 5 10 20 5 10 15 20
the input pair is constrained by 4
-0.25 gm/ID (S/A) 0.92 gm/ID (S/A)
15 20 5 10 15 20
-0.25 gm/ID (S/A)
gm/Cgg (r/s)
5 20 5 10
10 15 20
10
(d) (S/A)
gm/ID
0.9 (gm /gds )1,2 ≥ 80 (5)
0.9
.
0.89
0.9
L = 0.4 7m 0.88
0.88
0.89 10 9 The channel length can be selected using the intrinsic gain vs 5
L = 0.4 7m gm /ID chart shown in Fig. 2a. This chart shows a fundamental 6
0.87
.
0.88 X: 16 0.86
5 10 Y: 0.8571 15 trade-off
20 between
5 gain and
10 speed, where15 higher gain
20 requires 7
0.86
0.87
.
X: 16
gm/ID (S/A) long channel length and large gm /ID , which both come
gm/ID (S/A) 8
Y: 0.8571
0.85
0.86 at the expense of speed. Selecting L1,2 ≈ 0.8 µm yields 9
L = 2 7m
0.84
0.85 (gm /gds )1,2 ≈ 87, which satisfies (5). 10
15 20 5 10 15 20
L = 2 7m
0.84 gm/ID (S/A) The channel width can be specified using the current den- 11
5 20 5 10 15 20
gm/ID (S/A)
sity (ID /W ) vs gm /ID chart shown in Fig. 2b. Using the 12
(e)
previously calculated values for (gm /ID )1,2 and L1,2 yields a 13
1 D. Design of the Current Mirror Load where γN and γP are the noise coefficients of NMOS and 40
2 From Section II-C, the condition on the output conductance PMOS devices, respectively [10]. Substituting from (13) in 41
3 of the NMOS current mirror load (M3 and M4) is given by (12), the RMS noise constraint can be written as 42
2 kT γef f
gds3,4 ≤ 2 µS (7) Vn,rms = < (50 µV rms)2 (15)
CL
4 Thus, the gds /ID ratio of the current mirror load is equal γef f < 3.02 (16)
5 to 0.2V −1 . This ratio is equivalent to the channel length
From the PMOS noise chart in Fig. 2e, γP ≈ 0.86. Thus, 43
6 modulation coefficient (λ) in the long-channel model. gds /ID
by substituting in (14) the constraint on M3 and M4 can be 44
7 strongly decreases with increasing L, and slightly increases
written as 45
8 with increasing gm /ID . Since the dependence of gds /ID on
9 gm /ID is rather weak, it can be initially ignored in order to γN gm3,4 ≤ 103 µS (17)
10 obtain an estimate for the channel length of M3 and M4. In In general, the value of γN is a function of gm /ID ; thus, (17) 46
11 order to use the intrinsic gain vs gm /ID chart, we assume an should be plotted on the NMOS noise chart to find the gm /ID 47
12 arbitrary but relatively large value for gm /ID , such that the that satisfies the constraint. However, the dependence of γN 48
13 actual gain is higher than the required specification, which is on gm /ID is fairly weak, and for L = 0.6 µm it is roughly 49
14 usually desirable. Assuming gm /ID = 15 yields gm = 150 µS constant at γN ≈ 0.89. Therefore, the constraint on the NMOS 50
15 and gm /gds ≥ 75. From the chart in Fig. 3a, the channel length current mirror load can be directly written as 51
16 that satisfies this requirement is L3,4 = 0.6 µm.
gm
17 The choice of the gm /ID of the current mirror load is con- ≤ 11.6 S/A (18)
18 strained by the input range and the RMS noise specifications. ID 3,4
19 Starting with the input range, the minimum input signal that The constraints in (10) and (18) shows the trade-off between 52
20 can be tolerated before driving the input pair out of saturation headroom and noise, where lower gm /ID for the current 53
21 is given and constrained by mirror load corresponds to lower total noise but smaller signal 54
Vin,min = 0.2 V ≥ − |VGS1,2 | + |Vdsat1,2 | + VGS3,4 (8) swing. As a compromise, we will proceed with (gm /ID )3,4 = 55
22 where Vdsat is the minimum drain-source voltage required to gin, and is lower than the assumed value (gm /ID = 15) 57
23 keep the transistor in saturation, and is equivalent to the over- used to obtain L. The width of M3 and M4 can be selected 58
24 drive voltage for a square-law device. |VGS1,2 | and |Vdsat1,2 | from the NMOS current density chart shown in Fig. 3c, where 59
25 can be extracted from the PMOS input pair VGS and Vdsat (ID /W )3,4 ≈ 6.7 µA/µm; thus, W3,4 ≈ 2 µm. 60
VGS3,4 ≤ 0.67 V (9) of the PMOS tail current source. The sizing of the tail current 63
29 By using the NMOS VGS chart in Fig. 3b, the constraint on the source is constrained by the CMRR and the input range 64
30 NMOS current mirror load due to the input range specification specifications. The CMRR is given by [10] 65
2
Vn,in (f ) =
4kT γef f √
< (17.7 nV / Hz)2 (13) 15 results in gm = 300 µS and gm /gds ? 115 (note that 72
37 where k is Boltzmann constant, T is the temperature in Kelvin, intrinsic gain chart shown in Fig. 4a, choosing L5,6 = 1.2 µm 74
38 and γef f is the effective noise coefficient of the OTA, which satisfies this requirement. 75
6 10 1 Table II
S80 7m OTA TRANSISTORS SIZING .
GBW (MHz)
UMMARY
L = OF
0.4 THE
CMRR (dB)
L = 2 7m
2001
ID/W (uA/um)
10 4 X: 15 606 X: 10
gm/gds
L = 0.4 7mY: 127.2 Transistor Width 80
Y: 73.56
gm /ID Length
Function
GBW (MHz)
CMRR (dB)
150
40 X: 14
ID/W (uA/um)
X: 15
2 10 04 60 X: 10
Y: 127.2 100 M1 and M2 20 16 0.8 µm
Y: 0.403 24 µm Input pair Y: 73.56
10 0
X: 14
LM3
= 2 and
7m M4 0210 0.6 µm 2 µm Current mirror load40
50 0 Y: 0.403
0 0.2 0.4 0.6 0.8 1 1.2 M5 1.4and M6 10 10 mirror20
0 3 6 9
L = 0.4 7m 14 1.2 µm1052 µm and 26 10µm Bias current
0 L = 2 7m Vin (V) 10 -1 0 Frequency (Hz) 0 0
5 10 15 20 5 10 0 0.2 0.415 0.6 0.820 1 1.2 1.4
L = 0.4 7m 2 10 1
10 -1 10
gm/ID (S/A) gm/ID (S/A) Vin (V) F
Gain (dB)
Vn(f) (nV/rtHz)
15 20 5 10 15 20 40
A) -0.5 (a)
gm/ID (S/A) -0.125 2 X: 5.012e+006
10
20 X: 10
(nV/rtHz)
Y: 16.98
X: 5.011e+006 Y: 33.52 40
L = 2 7m
0 Y: 12.19 0 X: 11.84
10 20 X: 10
Vdsat (V)
-0.6
(V) (V)
X: 10
Vn(f)Loop
Y: -0.13
-0.1
X: 11.84
-20 Y: 16.98
X: 5.011e+006 Y: 33.52
Y: -0.13 -0.13 Y: 12.19 0
VdsatVGS
0
10
-40 0
-0.7
-0.15 10
0L = 0.4 7m
10
3
10
6
10
9
10 10
3
10
6
10
9 -20
0.4 7m Frequency (Hz) 0
Frequency
3
(Hz)6 9
-40 0
-0.2 -0.135 10 10 10 10 10 1
-0.8 4 (a)
Phase (Degree)
Region
15 20 5 10 15 20
Phase (Degree)
A)
-100 gm/ID (S/A) 0.9 20
X: 0.14 X: 1.12
Region
X: 5.01e+006
10 10
0.9 (b) Y: -89.33 Y: 2 Y: 2
L = 0.4 7m
-100 2
gm/Cgg (r/s)
0.88 X: 0.14
1 -200 0
L = 0.4 7m 0 X: 5.01e+006
Y: 2
10
10 10
3
10
6
10
9 0 0.2 0.4 0.6Y: -89.33
0.8 1 1.2 1.4
.
0.88
10 9 L = 0.4 7m Vin (V)
Frequency (Hz) -200 0 0
ID/W (uA/um)
0.86
.
X: 15
10 10
3
10
6
10
9 0 0.2 0.4
Y: 127.2
0.86
10 0
X: 14 Frequency (Hz)
L = 2 7m
10 8 Y: 0.403 0.84
5 L = 2 10
7m 15 20 5 10 15 (b) 20
0.84 L = 2 7m
15 20 5 10gm/ID (S/A) 15 20 gm/IDresults
Figure 5. Simulation (S/A) of (a) loop gain and (b) phase vs frequency
A) L = 0.4 7m gm/ID (S/A) in unity gain buffer configuration. Open-loop DC gain, unity-gain frequency
10 -1 (ωu ), and phase at ωu are annotated.
15 20 5 10 15 20
) gm/ID (S/A)
-0.125 (c) model [12]. A testbench similar to the one described in [13] 15
Figure 4. PMOS tail current source (M5) design charts vs gm /ID with length is used. Fig. 5a shows the simulated loop gain in unity-gain 16
as a parameter (L = 0.4µm : 0.2µm : 2µm): X: 11.84 (a) intrinsic gain (gm /gds ),
buffer configuration using Spectre stability (stb) analysis. The
Vdsat (V)
17
(b) Vdsat (variation with L is negligible),Y:, and
-0.13(c) current density (ID /W ).
-0.13 DC gain is ≈ 33.5 dB and the GBW is ≈ 5 M Hz, where both 18
1 Since VGS1,2 ≈ 570 mV as calculated in Section II-D, the intrinsic capacitance has minor impact as it is much smaller 20
2 CMIR constraint can be written as than the large capacitive load. However, if the effect of self- 21
-0.135
15 20
loading is to be considered, the OTA internal capacitance can 22
|Vdsat5,6gm/ID (S/A)
| < 130 mV (24) be estimated from the MOSFET capacitance vs gm /ID charts. 23
)
3 From the PMOS Vdsat chart in Fig. 4b, the range of gm /ID Next, another design iteration is performed which takes both 24
0.9
4 that satisfies this requirement is intrinsic and extrinsic capacitances into consideration as will 25
L =
0.4 7m be shown in Section III. Since the OTA has a single dominant 26
0.88 gm
ID 5,6
? 11.84 (25) output pole, the phase margin specification is satisfied without 27
28
5
0.86 margin from operating the tail current source
To keep some The buffer input range can be verified by plotting the 29
6 at the edge of saturation, (gm /ID )5,6 = 14 is used, which is operating region of the input pair (M1,2) and the tail current 30
7 lower than0.84 L = 2 7m
the assumed value (gm /ID = 15) used to obtain source (M5) vs the input voltage. The meaning of the “region” 31
15
8
20 5 10
L. The selected gm /ID yields a current15density ≈ 0.4
20
µA/µm small signal parameter is as follows: “1” for triode, “2” 32
)
9
gm/ID (S/A)
as shown in the PMOS current density chart in Fig. 4c. for saturation, and “3” for subthreshold operation. The valid 33
10 Consequently, the channel widths of the bias circuit are given input range over which all transistors operate in saturation 34
13 Table II shows a summary of the OTA transistors sizing. The more meaningful indication of the CMIR can be obtained by 39
14 OTA was verified using Cadence Spectre and 180 nm PTM using a parametric sweep to plot the GBW vs the input signal 40
Loop
-20
6 9
-40 0 3 6 9 6
0 10 10 10 10 10
z) Frequency (Hz)
4 6
80
M1,2
GBW (MHz)
CMRR (dB)
Region 4 M5 60 X: 10
Y: 73.56
2 40
06 X: 0.14 2 X: 1.12
Y: 2 Y: 2 20
0 0 0 0
6 9 0 0 0.8
0.2 0.4 0.6 0.2 0.4 0.6 1.4
1 1.2 0.8 1 1.2 1.4 10 10
3
10
6
10
9
0 10
Vin (V) Vin (V) Frequency (Hz)
z)
2
10 (a)
6 40
Figure 8. Simulation result of OTA CMRR vs frequency.
80
X: 5.012e+006
20 X: 10
GBW (MHz)
CMRR (dB)
6
4
X: 10
Y: 16.98
X: 5.011e+006 60 Y: 33.52 Y: 0.000117
Y: 12.19 80 0 Table III
GBW (MHz)
CMRR (dB)
10 40 C OMPARISON OF REQUIRED SPECIFICATIONS AND ACHIEVED RESULTS .
4
2 60 X: 10 -20
20 Y: 73.56
40 -40
Specification Required Achieved
2 10
0 3
10 1.2 1.410
6 0 109 10
0
106
3
10 9
6 9
2010
0
0 0.2 0.4 0.6 0.8 1 20 10 0 OTA Current
10 3 Consumption
10 20 µA10 µA
Vin (V) Frequency (Hz) Frequency (Hz)
06 0 0 Frequency
GBW (Hz) 5 M Hz 5 M Hz
0 0.2 0.4 0.6 0.8 1 1.2 1.4 80
10
3
4 Margin10
10Phase
6
10
9
Phase (Degree)
2 70o 90o
GBW (MHz)
0Vin (V)
(dB)
10
Frequency (Hz) M1,2
Vn,in(f) (nV/rtHz)
4 6040
(dB)
32 dB
Open Loop DC gain
M533.5 dB
Region
2 (b) CMRR
10 Loop Gain 4020
2 Thermal Noise
Total Integrated 50 µV rms 48.6 µV rms
Loop Gain (dB)
X: 1000
Vn(f) (nV/rtHz)
2
Figure 6. Simulation results of-100 (a)Y:operating
16.98 region of input pair (M1,2) and40
20 0 X: 0.14 X: 1.12
X: 5.01e+006
tail current source (M5) vs buffer input voltage, and (b) variation of GBW vs Input Range
Y: 2 0.2 V − 1.1 V 0.14
X: 5.012e+006 V − 1.12 V
Y: 2
10 0 Y: -89.33 20 X: 10
0 X: 10
buffer input voltage. The region parameter 0
is “1” for triode, “2” for saturation, -20 Y: 33.52 Y: 0.000117
X: 5.011e+006 7010
dB 73.6 dB
0 Y: 16.98
0.2 0.4
-200
0.6 0.8 1 1.2 1.4 10 0 10 30CMRR 10 6 9
and “3” for subthreshold.
0
The CMIR is
Y: annotated.
12.19 0
10 10
0 (V)
Vin
10
3
10
6 -40
010
9 03 0.2(Hz)0.4 6
Frequency 0.6 0.8 1 1.2 1.4
10 0 10 3 10 6 10 9 -20 10 10 10 10 9
11
0 3 6 9 0 3 6 9
10 10 10 10 104 shows
20 10all target specifications
that 10 10
are successfully satisfied, 12
Phase (Degree)
0 X: 1000
Frequency
Y: 16.98
(Hz) Frequency (Hz)
0 3 which demonstrates the robustness
M1,2
of the gm /ID design 13
M5
Region
-500
10 4 methodology. 14
Phase (Degree)
-20 2
0
-100 M1,2
-40
M5 109
Region
-150 10 0 1
10 3 10 6 10 9 10 0 10 3 10 6
-100
-200 Frequency (Hz) 2 III. AUTOMATED D ESIGN P ROCEDURE U SING MATLAB
0 Frequency (Hz)
15
X: 5.01e+006 X:0.2
0.14 0.4 1 X: 1.12
10 0 10 3 10 6 10 9 0 0.6 0.8 1.2 1.4
showed a Y: -89.33
(a) flow using gm /ID 4 Section
Y: 2 II systematic
Y: 2 design 16
Vin (V)
Frequency (Hz)
(Degree)
10 10 10 10 18
(7Vrms)
2
-100 Frequency (Hz) X: 1e+09 and can be Vin
tedious(V) if repeated several times due to the 19
Vn,rmsPhase
40
-150 Y: 48.6
1 frequent changes in specifications during the initial phases of 20
-200 0
an IC design project. Second, in order to keep it tractable, 21
20
10 0 10 3 10 6 10 9 0 the 0.2
dataset
0.4 was
0.6 limited
0.8 by
1 choosing
1.2 1.4a relatively coarse step 22
Frequency (Hz) for channel lengthVin (V)and ignoring second order effects, e.g., 23
0
10
60
0
10 3
10 6
10 9
VDS dependence. Third, it cannot be directly applied to a 24
Vn,rms (7Vrms)
Vx
CGS1 CGS2 Start
Vin M1 M2 -
+ CGD2 Read
Vout design
CGD4 CDB2 specs
+ CDB4 CL
M3 M4
CLeff = CL
i=1
MaxNoIter = 10
reltol = 0.001
Figure 9. Simplified schematic for the analysis of the effective load capaci-
tance.
i++ > Yes Display
MaxNoIter results
1 where CLef f = CL + COT A . However, in order to cal-
2 culate COT A the sizing of the transistors must be known. No
3 Contrastingly, the sizing is itself the desired outcome of the Perform the End
4 design procedure. Such a dilemma can be resolved by solving systematic
design
5 the problem iteratively as will be shown in the following procedure
6 subsections.
Calculate COTA
7 A. Analysis of the Effective Load Capacitance
8 Before delving into automation, an analytical expression
9 must be derived for the effective load capacitance (CLef f ). Error < reltol
Yes Display
results
10 The equivalent circuit for calculating CLef f of the OTA in
11 unity gain buffer configuration is shown in Fig. 9. The output No
12 resistance and the drain capacitance of the tail current source
End
13 (M5) are ignored to simplify the analysis. The drain-bulk CLeff = CL + COTA
14 capacitance of M2 and M4 (CDB2 and CDB4 ) directly add
15 to CL . The gate-drain capacitance of M4 (CGD4 ) has its gate
Figure 10. Simplified flow chart for the iterative design procedure to take
16 terminal at a low impedance node (diode-connected M3); thus, the effective load capacitance into account. As an example, maximum no. of
17 approximately, it directly adds to CL as well. However, the iterations is set to 10 and the relative tolerance is set to 0.1%.
18 gate-source capacitance of M2 (CGS2 ) is floating between
19 Vout and Vx ; thus, its contribution at Vout must be analyzed.
20 Assuming a test source Vt is applied at Vout , the gain from is calculated using (26). Simulations show that (32) slightly 31
21 Vt to Vx can be calculated using Gm Rout method underestimates CLef f , especially for large CL , as will be 32
22 where M1 has a low impedance at its drain terminal. Thus, the closed loop AC simulation rather than stability analysis. 40
25 Alternatively, (30) can be derived by looking from Vout while operating point and noise parameters are stored as lookup 44
26 Vin is deactivated. It can be noted that CGS2 and CGS1 appear tables (LUTs) in the form of MATLAB matrices. A lookup 45
28 Vout . The effective load capacitance can now be written as The systematic design procedure is embedded in an iterative 47
29 The above analysis was verified using AC simulations, iterative loop: ’MaxNoIter’ defines the maximum number of 52
30 where the GBW is measured from simulations, then CLef f iterations to avoid going into an infinite loop, and ’reltol’ 53
8
Figure 11. Normalized progress of COT A vs the iteration index for different
values of CL .
negligible, and the two curves will slowly approach each other. 30
33
-10 such a case can result in more than 50% error, and the iterative 37
Figure 12. Percent error in achieved GBW as extracted from AC simulations MATLAB 40
vs CL .
The design procedure explained in Section II then auto- 41
1 defines the required relative tolerance. The loop performs the of specifications (constraints). However, optimizing real-life 43
2 sizing procedure, then calculates COT A from the LUTs based designs usually involve one or more variables that need to be 44
3 on the sizing results. The relative error is then calculated to maximized or minimized given a set of constraints. In this sec- 45
4 compare the new CLef f with the value of CLef f used in the tion we will give an example of such an optimization scenario 46
5 current iteration as follows within the framework presented in the previous sections. 47
CL + COT A
Error = − 1 (33) A. Optimization Problem 48
CLef f
The design example presented in this paper deals with 49
6 Convergence is achieved if the error is less than the required
a unity-gain buffer that drives a large capacitive load, e.g., 50
7 relative tolerance (0.1% in Fig. 10). The sizing results are then
probing a sensitive signal in a mixed-signal design to an 51
8 displayed to the user.
external test-pad. Consequently, the buffer should introduce 52
10 The automated iterative procedure was used to design the maximum input capacitance at low frequency is required to 55
11 OTA for different values of CL . Fig. 11 shows the variation of be less than 10 f F . The set of specifications is similar to the 56
12 COT A vs the index of iteration at different loading conditions. one given in Table I except for the GBW. The optimization 57
13 It is clear that the value of COT A converges very quickly, scenario presented in this section considers the case of max- 58
14 and the required tolerance is achieved in few iterations. The imizing the OTA GBW under a given current consumption, 59
15 designed OTAs were simulated at different values of CL in input capacitance, and DC gain specifications. Maximizing the 60
16 order to verify the automated procedure. For each value of GBW for a given current means that gm /ID must be maxi- 61
17 CL two OTA versions were simulated. The first version used mized. However, increasing gm /ID means that the transistors 62
18 transistor sizing from single design iteration (i.e., COT A = 0), are biased towards subthreshold operation, where they will 63
19 while the second version used the iterative procedure to obtain have low current driving capability, i.e., low current density 64
20 a better estimate for COT A . Fig. 12 shows that for single (ID /W ). Consequently, for a given bias current, W will 65
21 iteration the percent error at CL = 0.5 pF is ≈ 10%. On the increase, which will result in increased capacitive loading on 66
22 contrary, the iterative procedure gives a less than 1% error. The the stage preceding the buffer. On the other hand, increasing 67
23 residual error for the iterative case is due to the approximate gm /ID increases the intrinsic gain of the transistors. Since the 68
24 nature of the analytical expression in (32) which was used gain spec is fixed, this means that a lower L can be used to 69
25 to estimate COT A in the program. The negative error shows satisfy the gain spec, which may lead to a lower W and lower 70
26 that CLef f is slightly underestimated, especially at relatively Cin . The overall variation of Cin depends on how these two 71
27 large CL . A more elaborate expression, or an expression fitted opposite effects interact together. These constraints will limit 72
28 from simulations, can be used to reduce the error. Fig. 12 also the maximum gm /ID that can be used, and consequently the 73
29 shows that as CL increases, the contribution of COT A becomes maximum GBW that can be achieved. 74
9
Vx Start
CGS1
Vy gm/ID = 5:0.1:20
M4 CL Perform element-wise vector Given gm/ID, L, and W:
operations Find CGS and CGD vectors
1/gm3 M3
Given Avdc, CGS and CGD:
Given gm/ID and ID:
Find Cin vector using (40)
Find gm vector
Figure 13. Simplified schematic for the analysis of the buffer input capaci- Search the Cin vector for the
Given gm and Avdc:
tance. max gm/ID that meets the
Find gds vector
Cin spec
18 Due to the unity-gain feedback action Vout is related to Vin mitigated by the OTA gain as given by (42). 31
gm3
1
created from 5 to 20 with 0.1 step resulting in 151 total 36
Vx = − Vy + Vin 1 − (37) design points. This vector reasonably covers the expected 37
gm2 Avdc
design space, and can be thought as equivalent to the x- 38
21 Writing KCL equation at Vy yields axis in the graphical procedure presented in Section II. The 39
gm3 Vy + gds1 (Vy − Vx ) + gm1 (Vin − Vx ) = 0 (38) previous section described an automated iterative procedure 40
22 where M1 has Vgs = Vin − Vx . Substituting from (37) in (38) On the other hand, the optimization procedure described in this 42
gm1
23 and noting that Avdc = 2g ds1
, it can be shown that Vy is section is applied to all design points simultaneously using 43
24 approximately given by element-wise vector operations. For every gm /ID value, the 44
25 Substituting from (39) in (37) yields gm /ID will yield a different gm and a different gds . A plot of 48
2 2 20
L
40
Cin (fF)
L (7m)
Y: 9.896
Y: 9.896
Y: 32.64
10 5
0 -20
X: 3.95e+06
0 5 0 -20 0 Y: 0.0003543 -40
5 10 15 20 10 0 10 3 10 6 10 0
0 gm/ID (S/A) -40 Frequency (Hz)
10 0 10 3 10 6 10 0 10 3 10 6 10 9
20
(a) (a)
Frequency (Hz) 30
Frequency (Hz) 2
40
(fF)
Cin (fF)
L (7m)
(dB)
15 Y: 32.64 X: 12.8
10 X: 1000
X: 10
Cin
20 01.5 20 Y: 8.929
Cin (fF)
Cin (fF)
Y: 9.896
L (7m)
Loop Gain
X: 12.8 Y: 32.64
10 X: 3.95e+06 1
5 10
Y: 8.929 -20 0 Y: 1.371e-05
10 1 X: 3.95e+06
0 5 -40 -200 0.5
Y: 0.0003543
3 5 6 10
10 0 10 3
10 6
10 0 10 10 10 9 15 20 5
0 0
Frequency (Hz) 0.5 -40
Frequency (Hz) gm/ID (S/A)
5 10 0
10 15 10 3 20 10 6 5 10 0
10 10 3
15 10 6
20 10 9
30 gm/ID (S/A) Frequency (Hz) 2 gm/ID (S/A) Frequency (Hz)
2
(b) (b)
ID/W (7A/7m)
30 2
Figure 15.20Intermediate results of the MATLAB optimization program: (a) Figure 16. Simulation results of (a) buffer input capacitance vs frequency
Cin (fF)
L (7m)
Channel length and current density selected based on DC gain spec vs gm /ID
X: 12.8 1 and (b) loop-gain vs frequency. Cin at low frequency,
1 open-loop DC gain,
and (b) input capacitance vs 20 gm /ID . Y:The input capacitance meeting the 1.5frequency (ω ) are annotated.
Cin (fF)
0
gm/ID (S/A) A higher GBW gm/IDcan
0.5 (S/A)be obtained by revisiting the assumption 23
5 10 15 20 5 10 15
Specification Required gm/ID
Achieved made after (4) and assigning a larger value for gds220compared 24
(S/A) gm/ID (S/A)
to gds4 . The achieved results are summarized in Table V. 25
OTA Current Consumption 20 µA 20 µA
Input Capacitance 10 f F 9.9 f F
Open Loop DC gain 32 dB 32.6 dB V. C ONCLUSION 26
1 yield a continuous channel length curve, rather than the 0.2µm graphically illustrated using the gm /ID design methodology. 29
2 step that was used in the graphical procedure. The decrease in The proposed systematic procedure was automated using 30
3 L vs gm /ID may misleadingly indicate that the capacitance MATLAB, which enabled tackling iterative and optimization 31
4 will decrease. However, the decay in current density is faster problems. Analytical expressions were derived for the OTA 32
5 as shown in Fig. 15a, leading to an overall increase in channel self-loading and input capacitances. The derived expressions 33
6 width and input capacitance. were further verified and employed in the automation pro- 34
7 At every combination of gm /ID and L the program cal- grams. The performance of the designed OTAs was verified 35
8 culates the corresponding ID /W and W , extracts the capaci- using Cadence Spectre, and simulation results meet all the 36
9 tances from the LUTs, then Cin is calculated using (42). The design requirements with acceptable accuracy. The proposed 37
10 plot of Cin vs gm /ID is shown in Fig. 15b. The program procedure can be similarly applied to other OTA topologies. It 38
11 takes 10% margin below the Cin design spec to account for is worth noting that the work presented in this paper assumes 39
12 the approximations done in (42). For the specifications given that the circuit architecture is known beforehand. A promising 40
13 in this example, a (gm /ID )1,2 = 12.8 is chosen. The selected future extension to this work is to build a more sophisticated 41
14 gm /ID is then used to complete the design procedure similar automation procedure that selects (or synthesizes) the circuit 42
15 to the previous sections. architecture based on the given specifications, possibly with 43
niques [15]–[17]. 45
16 D. Results and Discussion
17 The buffer input capacitance was simulated using AC anal-
18 ysis. The simulation results are shown in Fig. 16a, where ACKNOWLEDGMENT 46
19 Cin ≈ 9.9 f F achieving the required spec. The input capac-
20 itance increases with frequency as the OTA gain falls. The The authors would like to thank Omar A. Abu-El-ela for 47
21 loop-gain simulation is also shown in Fig. 16b. The DC gain useful hints and discussions. 48
11
1 R EFERENCES
2 [1] R. Dreslinski, M. Wieckowski, D. Blaauw, D. Sylvester, T. Mudge, Near-
3 threshold computing: Reclaiming Moore’s law through energy efficient
4 integrated circuits, Proceedings of the IEEE 98 (2) (2010) 253–266.
5 doi:10.1109/JPROC.2009.2034764.
6 [2] A. Ragheb, H. Kim, Ultra-low power OTA based on bias recy-
7 cling and subthreshold operation with phase margin enhancement,
8 Microelectronics Journal 60 (Supplement C) (2017) 94 – 101.
9 doi:https://doi.org/10.1016/j.mejo.2016.12.007.
10 [3] H. Omran, A. Alhoshany, H. Alahmadi, K. N. Salama, A 33fJ/Step
11 SAR capacitance-to-digital converter using a chain of inverter-based
12 amplifiers, IEEE Transactions on Circuits and Systems I: Regular Papers
13 64 (2) (2017) 310–321. doi:10.1109/TCSI.2016.2608905.
14 [4] F. Silveira, D. Flandre, P. G. A. Jespers, A gm/ID based methodology for
15 the design of CMOS analog circuits and its application to the synthesis
16 of a silicon-on-insulator micropower OTA, IEEE Journal of Solid-State
17 Circuits 31 (9) (1996) 1314–1319. doi:10.1109/4.535416.
18 [5] D. Flandre, A. Viviani, J. P. Eggermont, B. Gentinne, P. G. A. Jespers,
19 Improved synthesis of gain-boosted regulated-cascode CMOS stages
20 using symbolic analysis and gm/ID methodology, IEEE Journal of Solid-
21 State Circuits 32 (7) (1997) 1006–1012. doi:10.1109/4.597291.
22 [6] P. Jespers, The gm/ID Methodology, a sizing tool for low-voltage analog
23 CMOS Circuits: The semi-empirical and compact model approaches,
24 Springer Science & Business Media, 2010.
25 [7] T. Konishi, K. Inazu, J. G. Lee, M. Natsui, S. Masui, B. Murmann,
26 Design optimization of high-speed and low-power operational transcon-
27 ductance amplifier using gm/ID lookup table methodology, IEICE trans-
28 actions on electronics 94 (3) (2011) 334–345.
29 [8] S. Seth, B. Murmann, Settling time and noise optimization of a three-
30 stage operational transconductance amplifier, IEEE Transactions on
31 Circuits and Systems I: Regular Papers 60 (5) (2013) 1168–1174.
32 doi:10.1109/TCSI.2013.2244325.
33 [9] P. Jespers, B. Murmann, Systematic Design of Analog CMOS Circuits
34 Using Pre-Computed Lookup Tables, Cambridge University Press, 2017.
35 [10] B. Razavi, Design of analog CMOS integrated circuits, 2nd Edition,
36 McGraw-Hill Education, 2017.
37 [11] S. Oh, Y. Lee, J. Wang, Z. Foo, Y. Kim, W. Jung, Z. Li, D. Blaauw,
38 D. Sylvester, A dual-slope capacitance-to-digital converter integrated
39 in an implantable pressure-sensing system, Solid-State Circuits, IEEE
40 Journal of 50 (7) (2015) 1581–1591. doi:10.1109/JSSC.2015.2435736.
41 [12] Predictive technology model (PTM), Nanoscale Integration and Model-
42 ing (NIMO) Group, Arizona State University.
43 URL http://ptm.asu.edu/
44 [13] K. Kundert, A test bench for differential circuits, Available from
45 www.designers-guide.org.
46 [14] B. Murmann, Gm/ID Starter Kit.
47 URL https://web.stanford.edu/ murmann/gmid
48 [15] A. S. Elwakil, B. J. Maundy, Single transistor active filters: What is pos-
49 sible and what is not, IEEE Transactions on Circuits and Systems I: Reg-
50 ular Papers 61 (9) (2014) 2517–2524. doi:10.1109/TCSI.2014.2332249.
51 [16] B. J. Maundy, A. Elwakil, A. Al-Ali, L. Belostotski, Synthesis and anal-
52 ysis of fully differential filters using two port networks, in: 2017 IEEE
53 60th International Midwest Symposium on Circuits and Systems (MWS-
54 CAS), 2017, pp. 1105–1108. doi:10.1109/MWSCAS.2017.8053121.
55 [17] A. Montagne, SLiCAP: Symbolic Linear Circuit Analysis Program.
56 URL https://www.analog-electronics.eu/slicap