Mrinmay Dutta Bengaluru - Bangalore 9.10 Yrs
Mrinmay Dutta Bengaluru - Bangalore 9.10 Yrs
Mrinmay Dutta Bengaluru - Bangalore 9.10 Yrs
[email protected]
https://www.linkedin.com/in/mrinmaydutta
Objective
Obtain a technical leadership position in an organization that will utilize my 10 years of experience in VLSI domain with
proficiency in team building, mentoring, strategic thinking, problem solving, computer architecture, micro-architecture, logic
design, circuit/physical design, high speed design convergence, power optimization for mutual growth and success.
Experience
RTL TEAM LEAD INTEL CORPORATION [ 2016 + ]
Leading a Front End team of 10 members, responsible for delivering complete RTL design and validation of Execution cluster
of world most complicated IP ‘Intel Big Core IP’ over multiple project including big architectural changes and/or technology
node changes. Member of Intel strategic group ‘Machine Learning Center of Excellence (MLCoE)’ and driving multiple Machine
Learning features across geographical location of Intel Corporation.
Responsibilities
Responsible for delivering entire Front End (RTL Present ‘bill of cost’, ROI, execution planning, risk and
design and validation) solution in Execution cluster mitigation plan of each feature to project manager and get
throughout production cycle of Intel Microprocessor. approval.
Motivate and inspire team with mission and vision of Work with team to break feature implementation into
the organization. Encourage innovation, risk-taking, smaller task, and understand dependency at each stage.
constant improvement and arrange/deliver necessary Task planning and tracking using HSD-ES.
training to improve technical expertise of the team. Resource allocation, stakeholder management and resolve
Collaborate with Arch team on Path Finding (PF) and dependency/conflict to enable team to delivery on time.
High-level Architectural Specification (HAS) Weekly sync meeting with team members and other
development. stakeholders and roll up progress, new issues, Bug trend,
Features assignment, Tech Readiness (TR) work group coverage, Test Pass Rate. Discuss top-down direction, new
formation, planning and tracking to meet PF timeline. methodology/MoW and evaluate implication.
Perform Micro-Architecture Specification (MAS) and Perform code reviews of complex and risky features. Drive
validation Plan review. Features implementation and Cluster Bug Board and ECO Control Board.
integration staging planning. Work with Intel strategical group to bring innovation on next
generation technology.
Achievement
Excel in Quality: Team able to deliver very high quality of RTL code and pre-silicon validation. No Post Silicon bug found
in my cluster over the projects led by me.
Outperform in Schedule: Team pull-in due date for most of the deliverables over last year.
Award: Received “Intel India Divisional Award from Intel India GM” for excellent contribution in Machine Learning.
Education
M. TECH Electronics Design and Technology [2007 – 2009]
Department of Electronic Systems Engineering INDIAN INSTITUTE OF SCIENCE, BANGALORE
GPA: 6.4/8
B. E. Electronics and Telecommunication Engineering [ 2003 – 2007 ]
Department of Electronics and Telecomm INDIAN INSTITUTE OF ENGINEERING SCIENCE AND TECHNOLOGY, SHIBPUR
Aggregate: 83.4%
Publication
Construction and Maintenance of Energy Aware Virtual Backbone Tree in WSN, 13th National Conf. on Communication,
pp 58-62, 2007
Timing Aware Routing for Structured Data Path (SDP) Designs in DTTC 2012, Intel Internal conference
File US patent on Deep Learning/Machine Learning (2018 March) – Intel approved, external approval in progress.